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Prepare for V5.3.1 release.

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This commit is contained in:
Richard Barry 2009-06-21 19:20:26 +00:00
parent fe1295fd25
commit f1d6aa1a06
440 changed files with 7276 additions and 408 deletions
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2
Demo/CORTEX_AT91SAM3U256_IAR/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_AT91SAM3U256_IAR/ParTest/ParTest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_AT91SAM3U256_IAR/lcd_message.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_AT91SAM3U256_IAR/main.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_AT91SAM3U256_IAR/serial/serial.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_GCC/Demo1/main.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_GCC/Demo2/main.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_GCC/main.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_KEIL/Demo1/main.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_KEIL/Demo2/main.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_KEIL/main.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_Rowley/Demo1/main.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_Rowley/Demo2/main.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S102_Rowley/Demo3/main.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S316_IAR/commstest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S316_IAR/commstest.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S316_IAR/main.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S811_GCC/main.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S811_IAR/main.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3S811_KEIL/main.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/IntQueueTimer.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/IntQueueTimer.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/Makefile
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@ -1,5 +1,5 @@
#/*
# FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
# FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
#
# This file is part of the FreeRTOS.org distribution.
#

2
Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/ParTest/ParTest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/main.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/timertest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uIP_Task.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_IAR_Keil/IntQueueTimer.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_IAR_Keil/IntQueueTimer.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_IAR_Keil/ParTest/ParTest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_IAR_Keil/main.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uIP_Task.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LPC1766_GCC_RedSuite/FreeRTOSConfig.h
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LPC1766_GCC_RedSuite/LED.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LPC1766_GCC_RedSuite/LED.h
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LPC1766_GCC_RedSuite/Makefile
View file

@ -1,5 +1,5 @@
#/*
# FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
# FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
#
# This file is part of the FreeRTOS.org distribution.
#

2
Demo/CORTEX_LPC1766_GCC_RedSuite/main.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_LPC1766_GCC_RedSuite/webserver/uIP_Task.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_IAR/FreeRTOSConfig.h
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_IAR/ParTest/ParTest.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_IAR/main.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_IAR/serial/serial.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_IAR/timertest.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_Keil/FreeRTOSConfig.h
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_Keil/ParTest/ParTest.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

31
Demo/CORTEX_STM32F103_Keil/RTOSDemo.Opt
View file

@ -11,25 +11,25 @@
DaveTm { 0,0,0,0,0,0,0,0 }
Target (Target 1), 0x0004 // Tools: 'ARM-ADS'
GRPOPT 1,(System),0,0,0
GRPOPT 1,(System),1,0,0
GRPOPT 2,(Demo Files),0,0,0
GRPOPT 3,(FreeRTOS files),0,0,0
OPTFFF 1,1,2,0,0,0,0,0,<.\STM32F10x.s><STM32F10x.s>
OPTFFF 1,2,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\lcd.c><lcd.c>
OPTFFF 1,3,2,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\cortexm3_macro_rvds.s><cortexm3_macro_rvds.s>
OPTFFF 1,4,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_usart.c><stm32f10x_usart.c>
OPTFFF 1,5,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_gpio.c><stm32f10x_gpio.c>
OPTFFF 1,6,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_lib.c><stm32f10x_lib.c>
OPTFFF 1,7,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_nvic.c><stm32f10x_nvic.c>
OPTFFF 1,8,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_rcc.c><stm32f10x_rcc.c>
OPTFFF 1,9,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_spi.c><stm32f10x_spi.c>
OPTFFF 1,10,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_systick.c><stm32f10x_systick.c>
OPTFFF 1,11,1,0,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_tim.c><stm32f10x_tim.c>
OPTFFF 1,2,1,234881024,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\lcd.c><lcd.c>
OPTFFF 1,3,2,704643072,0,0,0,0,<..\Common\drivers\ST\STM32F10xFWLib\src\cortexm3_macro_rvds.s><cortexm3_macro_rvds.s>
OPTFFF 1,4,1,0,0,0,0,0,<.\STM32F10xFWLib\src\stm32f10x_usart.c><stm32f10x_usart.c>
OPTFFF 1,5,1,0,0,0,0,0,<.\STM32F10xFWLib\src\stm32f10x_gpio.c><stm32f10x_gpio.c>
OPTFFF 1,6,1,0,0,0,0,0,<.\STM32F10xFWLib\src\stm32f10x_lib.c><stm32f10x_lib.c>
OPTFFF 1,7,1,0,0,0,0,0,<.\STM32F10xFWLib\src\stm32f10x_nvic.c><stm32f10x_nvic.c>
OPTFFF 1,8,1,0,0,0,0,0,<.\STM32F10xFWLib\src\stm32f10x_rcc.c><stm32f10x_rcc.c>
OPTFFF 1,9,1,0,0,0,0,0,<.\STM32F10xFWLib\src\stm32f10x_spi.c><stm32f10x_spi.c>
OPTFFF 1,10,1,0,0,0,0,0,<.\STM32F10xFWLib\src\stm32f10x_systick.c><stm32f10x_systick.c>
OPTFFF 1,11,1,0,0,0,0,0,<.\STM32F10xFWLib\src\stm32f10x_tim.c><stm32f10x_tim.c>
OPTFFF 2,12,1,285212672,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c>
OPTFFF 2,13,1,0,0,0,0,0,<.\serial\serial.c><serial.c>
OPTFFF 2,14,1,0,0,0,0,0,<.\timertest.c><timertest.c>
OPTFFF 2,15,1,117440512,0,0,0,0,<.\main.c><main.c>
OPTFFF 2,15,1,2,0,179,199,0,<.\main.c><main.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,132,0,0,0,132,0,0,0,55,4,0,0,197,1,0,0 }
OPTFFF 2,16,1,0,0,0,0,0,<.\spi_flash.c><spi_flash.c>
OPTFFF 2,17,1,0,0,0,0,0,<..\Common\Minimal\semtest.c><semtest.c>
OPTFFF 2,18,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c><BlockQ.c>
@ -57,15 +57,14 @@ TARGOPT 1, (Target 1)
OPTFL 1,0,1
OPTAX 255
OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103VB)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103VB)
OPTDBG 48126,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
OPTDBG 42998,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0))
OPTKEY 0,(DLGUARM)((105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0))
OPTKEY 0,(DLGDARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0))
OPTKEY 0,(ARMDBGFLAGS)(-T0)
OPTKEY 0,(JLTAgdi)(-O1038 -J1 -Y1000 -Z1 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)
OPTKEY 0,(UL2CM3)(-UU0226F8E -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06410041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP7 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)
OPTBB 0,0,237,1,134228048,0,0,0,0,1,<serial.c>()()
OPTDF 0x82
OPTKEY 0,(UL2CM3)(-UU0605F6E -O47 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06410041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP7 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)
OPTDF 0x86
OPTLE <>
OPTLC <>
EndOpt

22
Demo/CORTEX_STM32F103_Keil/RTOSDemo.Uv2
View file

@ -10,14 +10,14 @@ Group (FreeRTOS files)
File 1,2,<.\STM32F10x.s><STM32F10x.s>
File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\lcd.c><lcd.c>
File 1,2,<..\Common\drivers\ST\STM32F10xFWLib\src\cortexm3_macro_rvds.s><cortexm3_macro_rvds.s>
File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_usart.c><stm32f10x_usart.c>
File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_gpio.c><stm32f10x_gpio.c>
File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_lib.c><stm32f10x_lib.c>
File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_nvic.c><stm32f10x_nvic.c>
File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_rcc.c><stm32f10x_rcc.c>
File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_spi.c><stm32f10x_spi.c>
File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_systick.c><stm32f10x_systick.c>
File 1,1,<..\Common\drivers\ST\STM32F10xFWLib\src\stm32f10x_tim.c><stm32f10x_tim.c>
File 1,1,<.\STM32F10xFWLib\src\stm32f10x_usart.c><stm32f10x_usart.c>
File 1,1,<.\STM32F10xFWLib\src\stm32f10x_gpio.c><stm32f10x_gpio.c>
File 1,1,<.\STM32F10xFWLib\src\stm32f10x_lib.c><stm32f10x_lib.c>
File 1,1,<.\STM32F10xFWLib\src\stm32f10x_nvic.c><stm32f10x_nvic.c>
File 1,1,<.\STM32F10xFWLib\src\stm32f10x_rcc.c><stm32f10x_rcc.c>
File 1,1,<.\STM32F10xFWLib\src\stm32f10x_spi.c><stm32f10x_spi.c>
File 1,1,<.\STM32F10xFWLib\src\stm32f10x_systick.c><stm32f10x_systick.c>
File 1,1,<.\STM32F10xFWLib\src\stm32f10x_tim.c><stm32f10x_tim.c>
File 2,1,<.\ParTest\ParTest.c><ParTest.c>
File 2,1,<.\serial\serial.c><serial.c>
File 2,1,<.\timertest.c><timertest.c>
@ -85,7 +85,7 @@ Options 1,0,0 // Target 'Target 1'
ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ACPUTYP ("Cortex-M3")
RVDEV ()
ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSTFLGA { 0,12,0,18,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSIRAM { 0,0,0,0,32,0,80,0,0 }
OCMADSIROM { 1,0,0,0,8,0,0,2,0 }
@ -96,7 +96,7 @@ Options 1,0,0 // Target 'Target 1'
ADSCMISC ()
ADSCDEFN (RVDS_ARMCM3_LM3S102)
ADSCUDEF ()
ADSCINCD (..\CORTEX_STM32F103_Keil;..\Common\include;..\..\Source\include;..\Common\drivers\ST\STM32F10xFWLib\inc)
ADSCINCD (..\CORTEX_STM32F103_Keil;..\Common\include;..\..\Source\include;.\STM32F10xFWLib\inc)
ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSAMISC ()
ADSADEFN ()
@ -121,7 +121,7 @@ Options 1,0,0 // Target 'Target 1'
ADSLDIF ()
ADSLDDW ()
OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103VB)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103VB)
OPTDBG 48126,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
OPTDBG 42998,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
FLASH1 { 9,0,0,0,1,0,0,0,1,16,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (BIN\UL2CM3.DLL)
FLASH3 ("" ())

177
Demo/CORTEX_STM32F103_Keil/RTOSDemo.plg
View file

@ -3,7 +3,180 @@
<pre>
<h1>µVision3 Build Log</h1>
<h2>Project:</h2>
C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\CORTEX_STM32F103_Keil\RTOSDemo.uv2
Project File Date: 05/21/2008
C:\E\temp\rc\4\FreeRTOSV5.3.1\Demo\CORTEX_STM32F103_Keil\RTOSDemo.uv2
Project File Date: 06/21/2009
<h2>Output:</h2>
Build target 'Target 1'
assembling STM32F10x.s...
compiling lcd.c...
assembling cortexm3_macro_rvds.s...
compiling stm32f10x_usart.c...
compiling stm32f10x_gpio.c...
compiling stm32f10x_lib.c...
compiling stm32f10x_nvic.c...
compiling stm32f10x_rcc.c...
compiling stm32f10x_spi.c...
compiling stm32f10x_systick.c...
compiling stm32f10x_tim.c...
compiling ParTest.c...
compiling serial.c...
compiling timertest.c...
compiling main.c...
compiling spi_flash.c...
compiling semtest.c...
compiling BlockQ.c...
compiling blocktim.c...
compiling comtest.c...
compiling death.c...
compiling flash.c...
compiling integer.c...
compiling PollQ.c...
compiling tasks.c...
compiling list.c...
compiling queue.c...
compiling port.c...
compiling heap_2.c...
linking...
Program Size: Code=22904 RO-data=14540 RW-data=256 ZI-data=18488
"RTOSDemo.axf" - 0 Error(s), 0 Warning(s).
Load "C:\\E\\temp\\rc\\4\\FreeRTOSV5.3.1\\Demo\\CORTEX_STM32F103_Keil\\RTOSDemo.AXF"
Erase Done.
Programming Done.
Verify OK.
Clean started: Project: 'RTOSDemo'
deleting intermediate output files for target 'Target 1'
Build target 'Target 1'
assembling STM32F10x.s...
compiling lcd.c...
assembling cortexm3_macro_rvds.s...
compiling stm32f10x_usart.c...
compiling stm32f10x_gpio.c...
compiling stm32f10x_lib.c...
compiling stm32f10x_nvic.c...
compiling stm32f10x_rcc.c...
compiling stm32f10x_spi.c...
compiling stm32f10x_systick.c...
compiling stm32f10x_tim.c...
compiling ParTest.c...
compiling serial.c...
compiling timertest.c...
compiling main.c...
compiling spi_flash.c...
compiling semtest.c...
compiling BlockQ.c...
compiling blocktim.c...
compiling comtest.c...
compiling death.c...
compiling flash.c...
compiling integer.c...
compiling PollQ.c...
compiling tasks.c...
compiling list.c...
compiling queue.c...
compiling port.c...
compiling heap_2.c...
linking...
Program Size: Code=22904 RO-data=14540 RW-data=256 ZI-data=18488
"RTOSDemo.axf" - 0 Error(s), 0 Warning(s).
Load "C:\\E\\temp\\rc\\4\\FreeRTOSV5.3.1\\Demo\\CORTEX_STM32F103_Keil\\RTOSDemo.AXF"
Erase Done.
Programming Done.
Verify OK.
Load "C:\\E\\temp\\rc\\4\\FreeRTOSV5.3.1\\Demo\\CORTEX_STM32F103_Keil\\RTOSDemo.AXF"
Erase Done.
Programming Done.
Verify OK.
Build target 'Target 1'
linking...
Program Size: Code=22904 RO-data=14540 RW-data=256 ZI-data=18488
"RTOSDemo.axf" - 0 Error(s), 0 Warning(s).
Load "C:\\E\\temp\\rc\\4\\FreeRTOSV5.3.1\\Demo\\CORTEX_STM32F103_Keil\\RTOSDemo.AXF"
Erase Done.
Programming Done.
Verify OK.
Build target 'Target 1'
assembling STM32F10x.s...
compiling lcd.c...
assembling cortexm3_macro_rvds.s...
compiling stm32f10x_usart.c...
compiling stm32f10x_gpio.c...
compiling stm32f10x_lib.c...
compiling stm32f10x_nvic.c...
compiling stm32f10x_rcc.c...
compiling stm32f10x_spi.c...
compiling stm32f10x_systick.c...
compiling stm32f10x_tim.c...
compiling ParTest.c...
compiling serial.c...
compiling timertest.c...
compiling main.c...
compiling spi_flash.c...
compiling semtest.c...
compiling BlockQ.c...
compiling blocktim.c...
compiling comtest.c...
compiling death.c...
compiling flash.c...
compiling integer.c...
compiling PollQ.c...
compiling tasks.c...
compiling list.c...
compiling queue.c...
compiling port.c...
compiling heap_2.c...
linking...
Program Size: Code=22904 RO-data=14540 RW-data=256 ZI-data=18488
"RTOSDemo.axf" - 0 Error(s), 0 Warning(s).
Load "C:\\E\\temp\\rc\\4\\FreeRTOSV5.3.1\\Demo\\CORTEX_STM32F103_Keil\\RTOSDemo.AXF"
Erase Done.
Programming Done.
Verify OK.
Build target 'Target 1'
assembling STM32F10x.s...
linking...
Program Size: Code=22908 RO-data=14540 RW-data=256 ZI-data=18496
"RTOSDemo.axf" - 0 Error(s), 0 Warning(s).
Load "C:\\E\\temp\\rc\\4\\FreeRTOSV5.3.1\\Demo\\CORTEX_STM32F103_Keil\\RTOSDemo.AXF"
Erase Done.
Programming Done.
Verify OK.
Build target 'Target 1'
assembling STM32F10x.s...
compiling lcd.c...
assembling cortexm3_macro_rvds.s...
compiling stm32f10x_usart.c...
compiling stm32f10x_gpio.c...
compiling stm32f10x_lib.c...
compiling stm32f10x_nvic.c...
compiling stm32f10x_rcc.c...
compiling stm32f10x_spi.c...
compiling stm32f10x_systick.c...
compiling stm32f10x_tim.c...
compiling ParTest.c...
compiling serial.c...
compiling timertest.c...
compiling main.c...
compiling spi_flash.c...
compiling semtest.c...
compiling BlockQ.c...
compiling blocktim.c...
compiling comtest.c...
compiling death.c...
compiling flash.c...
compiling integer.c...
compiling PollQ.c...
compiling tasks.c...
compiling list.c...
compiling queue.c...
compiling port.c...
compiling heap_2.c...
linking...
Program Size: Code=20174 RO-data=14530 RW-data=248 ZI-data=18152
"RTOSDemo.axf" - 0 Error(s), 0 Warning(s).
Load "C:\\E\\temp\\rc\\4\\FreeRTOSV5.3.1\\Demo\\CORTEX_STM32F103_Keil\\RTOSDemo.AXF"
Erase Done.
Programming Done.
Verify OK.
Clean started: Project: 'RTOSDemo'
deleting intermediate output files for target 'Target 1'

2
Demo/CORTEX_STM32F103_Keil/main.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_Keil/serial/serial.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_Keil/timertest.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_Primer_GCC/FreeRTOSConfig.h
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_Primer_GCC/ParTest/ParTest.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_Primer_GCC/bitmap.h
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F103_Primer_GCC/timertest.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F107_GCC_Rowley/FreeRTOSConfig.h
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F107_GCC_Rowley/FreeRTOSConfig.h.scsc
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F107_GCC_Rowley/ParTest/ParTest.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F107_GCC_Rowley/main.c
View file

@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F107_GCC_Rowley/scsc.tmp
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F107_GCC_Rowley/timertest.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F107_GCC_Rowley/webserver/emac.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F107_GCC_Rowley/webserver/emac.c.scsc
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F107_GCC_Rowley/webserver/emac.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F107_GCC_Rowley/webserver/emac.h.scsc
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/CORTEX_STM32F107_GCC_Rowley/webserver/uIP_Task.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.

0
Demo/ColdFire_MCF51CN128_CodeWarrior/CFV1_BDM_P&E_Multilink_CyclonePro.hwc Normal file
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74
Demo/ColdFire_MCF51CN128_CodeWarrior/CFV1_BDM_P&E_Multilink_CyclonePro.ini Normal file
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@ -0,0 +1,74 @@
[Environment Variables]
GENPATH={Project}Sources;{Compiler}lib\cfv1c\device\src;{Compiler}lib\cfv1c\device\include;{Compiler}lib\cfv1c\device\asm_include;{Compiler}\ColdFire_Support\Runtime\Runtime_ColdFire\Source;{Compiler}ColdFire_Support\Runtime\(Runtime_Common)\MWRuntime;{Compiler}ColdFire_Support\Runtime\(Runtime_Common);{Compiler}ColdFire_Support\msl\MSL_C\MSL_ColdFire\Src;{Compiler}ColdFire_Support\msl\MSL_C\MSL_ColdFire\Lib;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common\Src;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common_Embedded\Src;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common_Embedded\Math\Double_precision;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common_Embedded\Math\Single_precision;{Compiler}ColdFire_Support\msl\MSL_C++\MSL_ColdFire\Lib;{Compiler}ColdFire_Support\msl\MSL_C++\MSL_Common\Src;{Compiler}ColdFire_Support\msl\MSL_C++\MSL_Precompiled_Headers\Src;{Compiler}ColdFire_Support\msl\MSL_Extras\MSL_Common\Src
LIBPATH={Compiler}lib\cfv1c\device\include;{Compiler}ColdFire_Support\msl\MSL_C\MSL_ColdFire\Include;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common\Include;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common_Embedded\Include;{Compiler}ColdFire_Support\msl\MSL_C++\MSL_ColdFire\Include;{Compiler}ColdFire_Support\msl\MSL_C++\MSL_Common\Include;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common_Embedded\Math\Include;{Compiler}ColdFire_Support\msl\MSL_Extras\MSL_Common\Include;{Compiler}ColdFire_Support\msl\MSL_Extras\MSL_Common\Include\sys;
OBJPATH={Project}bin
TEXTPATH={Project}bin
ABSPATH={Project}bin
[HI-WAVE]
Target=CFICDCYCLMULT
CPU=ColdFire
Layout=C_layout.hwl
LoadDialogOptions=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main"
MainFrame=2,3,-1,-1,-1,-1,132,132,1182,881
TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806
AEFWarningDialog=FALSE
[CFICDCYCLMULT]
COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL
HOST_IO_SUPPORT=0
[CFMultilinkCyclonePro_GDI_SETTINGS]
MCUID=0x700A
CMDFILE0=CMDFILE STARTUP ON ".\cmd\CFV1_BDM_P&E_Multilink_CyclonePro_startup.cmd"
CMDFILE1=CMDFILE RESET ON ".\cmd\CFV1_BDM_P&E_Multilink_CyclonePro_reset.cmd"
CMDFILE2=CMDFILE PRELOAD ON ".\cmd\CFV1_BDM_P&E_Multilink_CyclonePro_preload.cmd"
CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\CFV1_BDM_P&E_Multilink_CyclonePro_postload.cmd"
CMDFILE4=CMDFILE VPPON ON "vppon.cmd"
CMDFILE5=CMDFILE VPPOFF ON "vppoff.cmd"
DBG0=DBG GENERAL DISARM_ON PROTECT_OFF ANALYZE_ON STEPATRUN_ON
DBG1=DBG PREDEFINED SELECT 0
CF_V1_DBG_TRIGGER_A=RangeAllowed:0 AccessSizeCompareAllowed:0 DataCompareAllowed:0 Disabled:0 AccessSize:4 Range:0 OutsideRange:0 DataToCompare:0 DataToCompareSize:0 DataToCompareMode:-1 EnableMask: 0 TriggerMask:0
CF_V1_DBG_TRIGGER_B=RangeAllowed:0 AccessSizeCompareAllowed:0 DataCompareAllowed:0 Disabled:0 AccessSize:4 Range:0 OutsideRange:0 DataToCompare:0 DataToCompareSize:0 DataToCompareMode:-1 EnableMask: 0 TriggerMask:0
CF_V1_DBG_TRIGGER_C=RangeAllowed:1 AccessSizeCompareAllowed:1 DataCompareAllowed:0 Disabled:0 AccessSize:4 Range:0 OutsideRange:0 DataToCompare:0 DataToCompareSize:0 DataToCompareMode:-1 EnableMask: 0 TriggerMask:0
DBG2=
NV_PARAMETER_FILE=C:\devtools\Freescale\CodeWarrior for Microcontrollers V6.2\prog\FPP\mcu700A.fpp
NV_SAVE_WSP=0
NV_AUTO_ID=1
[STARTUP]
CPUTARGETTYPE=0
check_and_fix_if_secure_enable_flag=1
trim_reference_target_newvalue=3125000
trim_reference_target_override=0
IO_DELAY_SET=0
USE_CYCLONEPRO_RELAYS=1
CyclonePro_poweroffonexit=0
CyclonePro_currentvoltage=255
CyclonePro_PowerDownDelay=250
CyclonePro_PowerUpDelay=250
IO_DELAY_CNT=14
PCI_DELAY=0
RESET_DELAY=0
PORT=21
interface_selection=0
SHOWDIALOG=0
[PORT]
IP=

27
Demo/ColdFire_MCF51CN128_CodeWarrior/CFV1_Full_Chip_Simulator.ini Normal file
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[Environment Variables]
GENPATH={Project}Sources;{Compiler}lib\cfv1c\device\src;{Compiler}lib\cfv1c\device\include;{Compiler}lib\cfv1c\device\asm_include;{Compiler}\ColdFire_Support\Runtime\Runtime_ColdFire\Source;{Compiler}ColdFire_Support\Runtime\(Runtime_Common)\MWRuntime;{Compiler}ColdFire_Support\Runtime\(Runtime_Common);{Compiler}ColdFire_Support\msl\MSL_C\MSL_ColdFire\Src;{Compiler}ColdFire_Support\msl\MSL_C\MSL_ColdFire\Lib;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common\Src;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common_Embedded\Src;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common_Embedded\Math\Double_precision;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common_Embedded\Math\Single_precision;{Compiler}ColdFire_Support\msl\MSL_C++\MSL_ColdFire\Lib;{Compiler}ColdFire_Support\msl\MSL_C++\MSL_Common\Src;{Compiler}ColdFire_Support\msl\MSL_C++\MSL_Precompiled_Headers\Src;{Compiler}ColdFire_Support\msl\MSL_Extras\MSL_Common\Src
LIBPATH={Compiler}lib\cfv1c\device\include;{Compiler}ColdFire_Support\msl\MSL_C\MSL_ColdFire\Include;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common\Include;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common_Embedded\Include;{Compiler}ColdFire_Support\msl\MSL_C++\MSL_ColdFire\Include;{Compiler}ColdFire_Support\msl\MSL_C++\MSL_Common\Include;{Compiler}ColdFire_Support\msl\MSL_C\MSL_Common_Embedded\Math\Include;{Compiler}ColdFire_Support\msl\MSL_Extras\MSL_Common\Include;{Compiler}ColdFire_Support\msl\MSL_Extras\MSL_Common\Include\sys;
OBJPATH={Project}bin
TEXTPATH={Project}bin
ABSPATH={Project}bin
[HI-WAVE]
Target=sim
Layout=C_layout.hwl
LoadDialogOptions=RUNANDSTOPAFTERLOAD="main"
CPU=ColdFire
MainFrame=2,3,-1,-1,-1,-1,22,23,1072,771
TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806
[Simulator]
CMDFILE0=CMDFILE STARTUP ON ".\cmd\CFV1_Full_Chip_Simulator_startup.cmd"
[Simulator COLDFIRE]
CMDFILE0=CMDFILE RESET ON ".\cmd\CFV1_Full_Chip_Simulator_reset.cmd"
CMDFILE1=CMDFILE PRELOAD ON ".\cmd\CFV1_Full_Chip_Simulator_preload.cmd"
CMDFILE2=CMDFILE POSTLOAD ON ".\cmd\CFV1_Full_Chip_Simulator_postload.cmd"
CMDFILE3=CMDFILE SETCPU ON ".\cmd\CFV1_Full_Chip_Simulator_setcpu.cmd"
FCS=ColdFire V1 SAMPLE
HOST_IO_SUPPORT=1

14
Demo/ColdFire_MCF51CN128_CodeWarrior/C_Layout.hwl Normal file
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OPEN source 0 0 60 99
Source < attributes TOOLTIP on,TOOLTIP_FORMAT signed,TOOLTIP_MODE details,FREEZE off,MARKS off
OPEN assembly 60 0 40 31
Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,FORMAT Auto,FREEZE off,TOPPC 0x410
OPEN register 60 31 40 25
Register < attributes FORMAT AUTO,COMPLEMENT None
OPEN data 60 56 40 22
Data < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,SORT NotSort,UPDATERATE 10,NAMEWIDTH 16
OPEN Command 60 77 40 23
Command < attributes CACHESIZE 1000
bckcolor 50331647
font 'Courier New' 9 BLACK
AUTOSIZE on
ACTIVATE "Register" "Assembly" "Data" "Source" "Command"

BIN
Demo/ColdFire_MCF51CN128_CodeWarrior/Default.mem Normal file
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BIN
Demo/ColdFire_MCF51CN128_CodeWarrior/RTOSDemo.mcp Normal file
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692
Demo/ColdFire_MCF51CN128_CodeWarrior/Sources/FEC.c Normal file
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/*
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License (version 2) as published
by the Free Software Foundation and modified by the FreeRTOS exception.
FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
A special exception to the GPL is included to allow you to distribute a
combined work that includes FreeRTOS.org without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details.
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
1 tab == 4 spaces!
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "semphr.h"
#include "task.h"
/* Demo includes. */
#include "FEC.h"
#include "fecbd.h"
#include "mii.h"
#include "eth_phy.h"
#include "eth.h"
/* uIP includes. */
#include "uip.h"
#include "uip_arp.h"
/*-----------------------------------------------------------*/
/* FEC hardware specifics. */
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
#define MCF_FEC_RDAR_R_DES_ACTIVE ( 0x1000000 )
#define MCF_FEC_TDAR_X_DES_ACTIVE ( 0x1000000 )
/* PHY hardware specifics. */
#define PHY_STATUS ( 16 )
#define PHY_DUPLEX_STATUS ( 4 )
/* Delay between polling the PHY to see if a link has been established. */
#define fecLINK_DELAY ( 500 / portTICK_RATE_MS )
/* Very short delay to use when waiting for the Tx to finish with a buffer if
we run out of Rx buffers. */
#define fecMINIMAL_DELAY ( 3 / portTICK_RATE_MS )
/* Don't block to wait for a buffer more than this many times. */
#define uipBUFFER_WAIT_ATTEMPTS ( 30 )
/* The Tx re-uses the Rx buffers and only has one descriptor. */
#define fecNUM_TX_DESCRIPTORS ( 1 )
/* The total number of buffers available, which should be greater than the
number of Rx descriptors. */
#define fecNUM_BUFFERS ( configNUM_FEC_RX_DESCRIPTORS + 2 )
/*-----------------------------------------------------------*/
/*
* Return an unused buffer to the pool of free buffers.
*/
static void prvReturnBuffer( unsigned char *pucBuffer );
/*
* Find and return the next buffer that is not in use by anything else.
*/
static unsigned char *prvGetFreeBuffer( void );
/*-----------------------------------------------------------*/
/* The semaphore used to wake the uIP task when data arrives. */
xSemaphoreHandle xFECSemaphore = NULL;
/* The buffer used by the uIP stack. In this case the pointer is used to
point to one of the Rx buffers to avoid having to copy the Rx buffer into
the uIP buffer. */
unsigned char *uip_buf;
/* The DMA descriptors. These are char arrays to allow us to align them
correctly. */
static unsigned char xFECTxDescriptors_unaligned[ ( fecNUM_TX_DESCRIPTORS * sizeof( FECBD ) ) + 16 ];
static unsigned char xFECRxDescriptors_unaligned[ ( configNUM_FEC_RX_DESCRIPTORS * sizeof( FECBD ) ) + 16 ];
static FECBD *pxFECTxDescriptor;
static FECBD *xFECRxDescriptors;
/* The DMA buffer. This is a char arrays to allow it to be aligned correctly. */
static unsigned char ucFECRxBuffers[ ( fecNUM_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ];
/* Index to the next descriptor to be inspected for received data. */
static unsigned long ulNextRxDescriptor = 0;
/* Contains the start address of each Rx buffer, after it has been correctly
aligned. */
static unsigned char *pucAlignedBufferStartAddresses[ fecNUM_BUFFERS ] = { 0 };
/* Each ucBufferInUse index corresponds to a position in the same index in the
pucAlignedBufferStartAddresses array. If the index contains a 1 then the
buffer within pucAlignedBufferStartAddresses is in use, if it contains a 0 then
the buffer is free. */
static unsigned char ucBufferInUse[ fecNUM_BUFFERS ] = { 0 };
/*-----------------------------------------------------------*/
/********************************************************************/
/*
* Write a value to a PHY's MII register.
*
* Parameters:
* ch FEC channel
* phy_addr Address of the PHY.
* reg_addr Address of the register in the PHY.
* data Data to be written to the PHY register.
*
* Return Values:
* 0 on failure
* 1 on success.
*
* Please refer to your PHY manual for registers and their meanings.
* mii_write() polls for the FEC's MII interrupt event and clears it.
* If after a suitable amount of time the event isn't triggered, a
* value of 0 is returned.
*/
static int fec_mii_write( int phy_addr, int reg_addr, int data )
{
int timeout;
unsigned long eimr;
/* Clear the MII interrupt bit */
EIR = EIR_MII;
/* Mask the MII interrupt */
eimr = EIMR;
EIMR &= ~EIMR_MII;
/* Write to the MII Management Frame Register to kick-off the MII write */
MMFR = ( unsigned long ) ( FEC_MMFR_ST_01 | FEC_MMFR_OP_WRITE | FEC_MMFR_PA(phy_addr) | FEC_MMFR_RA(reg_addr) | FEC_MMFR_TA_10 | FEC_MMFR_DATA( data ) );
/* Poll for the MII interrupt (interrupt should be masked) */
for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
{
if( EIR & EIR_MII)
{
break;
}
}
if( timeout == FEC_MII_TIMEOUT )
{
return 0;
}
/* Clear the MII interrupt bit */
EIR = EIR_MII;
/* Restore the EIMR */
EIMR = eimr;
return 1;
}
/********************************************************************/
/*
* Read a value from a PHY's MII register.
*
* Parameters:
* ch FEC channel
* phy_addr Address of the PHY.
* reg_addr Address of the register in the PHY.
* data Pointer to storage for the Data to be read
* from the PHY register (passed by reference)
*
* Return Values:
* 0 on failure
* 1 on success.
*
* Please refer to your PHY manual for registers and their meanings.
* mii_read() polls for the FEC's MII interrupt event and clears it.
* If after a suitable amount of time the event isn't triggered, a
* value of 0 is returned.
*/
static int fec_mii_read( int phy_addr, int reg_addr, unsigned short* data )
{
int timeout;
unsigned long eimr;
/* Clear the MII interrupt bit */
EIR = 0xffffffff;
/* Mask the MII interrupt */
eimr = EIMR;
EIMR &= ~EIMR_MII;
/* Write to the MII Management Frame Register to kick-off the MII read */
MMFR = ( unsigned long ) ( FEC_MMFR_ST_01 | FEC_MMFR_OP_READ | FEC_MMFR_PA(phy_addr) | FEC_MMFR_RA(reg_addr) | FEC_MMFR_TA_10 );
/* Poll for the MII interrupt (interrupt should be masked) */
for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
{
if (EIR)
{
break;
}
}
if(timeout == FEC_MII_TIMEOUT)
{
return 0;
}
/* Clear the MII interrupt bit */
EIR = EIR_MII;
/* Restore the EIMR */
EIMR = eimr;
*data = (unsigned short)(MMFR & 0x0000FFFF);
return 1;
}
/********************************************************************/
/*
* Generate the hash table settings for the given address
*
* Parameters:
* addr 48-bit (6 byte) Address to generate the hash for
*
* Return Value:
* The 6 most significant bits of the 32-bit CRC result
*/
static unsigned char fec_hash_address( const unsigned char* addr )
{
unsigned long crc;
unsigned char byte;
int i, j;
crc = 0xFFFFFFFF;
for(i=0; i<6; ++i)
{
byte = addr[i];
for(j=0; j<8; ++j)
{
if((byte & 0x01)^(crc & 0x01))
{
crc >>= 1;
crc = crc ^ 0xEDB88320;
}
else
{
crc >>= 1;
}
byte >>= 1;
}
}
return (unsigned char)(crc >> 26);
}
/********************************************************************/
/*
* Set the Physical (Hardware) Address and the Individual Address
* Hash in the selected FEC
*
* Parameters:
* ch FEC channel
* pa Physical (Hardware) Address for the selected FEC
*/
static void fec_set_address( const unsigned char *pa )
{
unsigned char crc;
/*
* Set the Physical Address
*/
PALR = (unsigned long)((pa[0]<<24) | (pa[1]<<16) | (pa[2]<<8) | pa[3]);
PAUR = (unsigned long)((pa[4]<<24) | (pa[5]<<16));
/*
* Calculate and set the hash for given Physical Address
* in the Individual Address Hash registers
*/
crc = fec_hash_address(pa);
if(crc >= 32)
{
IAUR |= (unsigned long)(1 << (crc - 32));
}
else
{
IALR |= (unsigned long)(1 << crc);
}
}
/*-----------------------------------------------------------*/
static void prvInitialiseFECBuffers( void )
{
unsigned portBASE_TYPE ux;
unsigned char *pcBufPointer;
/* Set the pointer to a correctly aligned address. */
pcBufPointer = &( xFECTxDescriptors_unaligned[ 0 ] );
while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
{
pcBufPointer++;
}
pxFECTxDescriptor = ( FECBD * ) pcBufPointer;
/* Likewise the pointer to the Rx descriptor. */
pcBufPointer = &( xFECRxDescriptors_unaligned[ 0 ] );
while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
{
pcBufPointer++;
}
xFECRxDescriptors = ( FECBD * ) pcBufPointer;
/* There is no Tx buffer as the Rx buffer is reused. */
pxFECTxDescriptor->length = 0;
pxFECTxDescriptor->status = 0;
/* Align the Rx buffers. */
pcBufPointer = &( ucFECRxBuffers[ 0 ] );
while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
{
pcBufPointer++;
}
/* Then fill in the Rx descriptors. */
for( ux = 0; ux < configNUM_FEC_RX_DESCRIPTORS; ux++ )
{
xFECRxDescriptors[ ux ].status = RX_BD_E;
xFECRxDescriptors[ ux ].length = configFEC_BUFFER_SIZE;
xFECRxDescriptors[ ux ].data = pcBufPointer;
/* Note the start address of the buffer now that it is correctly
aligned. */
pucAlignedBufferStartAddresses[ ux ] = pcBufPointer;
/* The buffer is in use by the descriptor. */
ucBufferInUse[ ux ] = pdTRUE;
pcBufPointer += configFEC_BUFFER_SIZE;
}
/* Note the start address of the last buffer as one more buffer is
allocated than there are Rx descriptors. */
pucAlignedBufferStartAddresses[ ux ] = pcBufPointer;
/* Set uip_buf to point to the last buffer. */
uip_buf = pcBufPointer;
ucBufferInUse[ ux ] = pdTRUE;
/* Set the wrap bit in the last descriptors to form a ring. */
xFECRxDescriptors[ configNUM_FEC_RX_DESCRIPTORS - 1 ].status |= RX_BD_W;
/* We start with descriptor 0. */
ulNextRxDescriptor = 0;
}
/*-----------------------------------------------------------*/
void vInitFEC( void )
{
unsigned short usData;
struct uip_eth_addr xAddr;
const unsigned char ucMACAddress[6] =
{
configMAC_0, configMAC_1,configMAC_2,configMAC_3,configMAC_4,configMAC_5
};
prvInitialiseFECBuffers();
/* Create the semaphore used to wake the uIP task when data arrives. */
vSemaphoreCreateBinary( xFECSemaphore );
/* Set the MAC address within the stack. */
for( usData = 0; usData < 6; usData++ )
{
xAddr.addr[ usData ] = ucMACAddress[ usData ];
}
uip_setethaddr( xAddr );
/* Set the Reset bit and clear the Enable bit */
ECR_RESET = 1;
/* Enable the clock. */
SCGC4 |= SCGC4_FEC_MASK;
/* Wait at least 8 clock cycles */
for( usData = 0; usData < 10; usData++ )
{
asm( "NOP" );
}
/* Set MII speed to 2.5MHz. */
MSCR = MCF_FEC_MSCR_MII_SPEED( ( ( configCPU_CLOCK_HZ / 1000000 ) / 5 ) + 1 );
/*
* Make sure the external interface signals are enabled
*/
PTCPF2_C0 = 1;
PTCPF2_C1 = 1;
PTCPF2_C2 = 1;
PTAPF1 = 0x55;
PTAPF2 = 0x55;
PTBPF1 = 0x55;
PTBPF2 = 0x55;
/* Set all pins to full drive with no filter. */
PTADS = 0x06;
PTAIFE = 0x06;
PTBDS = 0xf4;
PTBIFE = 0xf4;
PTCDS = 0;
PTCIFE = 0;
/* Can we talk to the PHY? */
do
{
vTaskDelay( fecLINK_DELAY );
usData = 0xffff;
fec_mii_read( configPHY_ADDRESS, PHY_PHYIDR1, &usData );
} while( usData == 0xffff );
/* Start auto negotiate. */
fec_mii_write( configPHY_ADDRESS, PHY_BMCR, ( PHY_BMCR_AN_RESTART | PHY_BMCR_AN_ENABLE ) );
/* Wait for auto negotiate to complete. */
do
{
vTaskDelay( fecLINK_DELAY );
fec_mii_read( configPHY_ADDRESS, PHY_BMSR, &usData );
} while( !( usData & PHY_BMSR_AN_COMPLETE ) );
/* When we get here we have a link - find out what has been negotiated. */
usData = 0;
fec_mii_read( configPHY_ADDRESS, PHY_STATUS, &usData );
/* Setup half or full duplex. */
if( usData & PHY_DUPLEX_STATUS )
{
RCR &= (unsigned long)~RCR_DRT;
TCR |= TCR_FDEN;
}
else
{
RCR |= RCR_DRT;
TCR &= (unsigned long)~TCR_FDEN;
}
/* Clear the Individual and Group Address Hash registers */
IALR = 0;
IAUR = 0;
GALR = 0;
GAUR = 0;
/* Set the Physical Address for the selected FEC */
fec_set_address( ucMACAddress );
/* Set Rx Buffer Size */
EMRBR = (unsigned short) configFEC_BUFFER_SIZE;
/* Point to the start of the circular Rx buffer descriptor queue */
ERDSR = ( volatile unsigned long ) &( xFECRxDescriptors[ 0 ] );
/* Point to the start of the circular Tx buffer descriptor queue */
ETSDR = ( volatile unsigned long ) pxFECTxDescriptor;
/* Clear all FEC interrupt events */
EIR = ( unsigned long ) -1;
/* Various mode/status setup. */
RCR = 0;
RCR_MAX_FL = configFEC_BUFFER_SIZE;
RCR_MII_MODE = 1;
#if( configUSE_PROMISCUOUS_MODE == 1 )
{
RCR |= RCR_PROM;
}
#endif
/* Enable interrupts. */
EIMR = EIR_TXF_MASK | EIMR_RXF_MASK | EIMR_RXB_MASK | EIMR_UN_MASK | EIMR_RL_MASK | EIMR_LC_MASK | EIMR_BABT_MASK | EIMR_BABR_MASK | EIMR_HBERR_MASK;
/* Enable the MAC itself. */
ECR = ECR_ETHER_EN_MASK;
/* Indicate that there have been empty receive buffers produced */
RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
}
/*-----------------------------------------------------------*/
unsigned long ulFECRx( void )
{
unsigned long ulLen = 0UL;
/* Is a buffer ready? */
if( ( xFECRxDescriptors[ ulNextRxDescriptor ].status & RX_BD_E ) == 0 )
{
/* uip_buf is about to be set to a new buffer, so return the buffer it
is already pointing to. */
prvReturnBuffer( uip_buf );
/* Obtain the size of the packet and put it into the "len" variable. */
ulLen = xFECRxDescriptors[ ulNextRxDescriptor ].length;
uip_buf = xFECRxDescriptors[ ulNextRxDescriptor ].data;
/* The buffer that this descriptor was using is now in use by the
TCP/IP stack, so allocate it a new buffer. */
xFECRxDescriptors[ ulNextRxDescriptor ].data = prvGetFreeBuffer();
/* Doing this here could cause corruption! */
xFECRxDescriptors[ ulNextRxDescriptor ].status |= RX_BD_E;
portENTER_CRITICAL();
{
ulNextRxDescriptor++;
if( ulNextRxDescriptor >= configNUM_FEC_RX_DESCRIPTORS )
{
ulNextRxDescriptor = 0;
}
}
portEXIT_CRITICAL();
/* Tell the DMA a new buffer is available. */
RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
}
return ulLen;
}
/*-----------------------------------------------------------*/
void vFECTx( void )
{
/* When we get here the Tx descriptor should show as having completed. */
while( pxFECTxDescriptor->status & TX_BD_R )
{
vTaskDelay( fecMINIMAL_DELAY );
}
portENTER_CRITICAL();
{
/* To maintain the zero copy implementation, point the Tx descriptor
to the data from the Rx buffer. */
pxFECTxDescriptor->data = uip_buf;
/* Setup the buffer descriptor for transmission */
pxFECTxDescriptor->length = uip_len;
/* NB this assumes only one Tx descriptor! */
pxFECTxDescriptor->status = ( TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_W );
}
portEXIT_CRITICAL();
/* Continue the Tx DMA task (in case it was waiting for a new TxBD) */
TDAR = MCF_FEC_TDAR_X_DES_ACTIVE;
/* uip_buf is being used by the Tx descriptor. Allocate a new buffer to
uip_buf. */
uip_buf = prvGetFreeBuffer();
}
/*-----------------------------------------------------------*/
static void prvReturnBuffer( unsigned char *pucBuffer )
{
unsigned long ul;
/* Mark a buffer as free for use. */
for( ul = 0; ul < fecNUM_BUFFERS; ul++ )
{
if( pucAlignedBufferStartAddresses[ ul ] == pucBuffer )
{
ucBufferInUse[ ul ] = pdFALSE;
break;
}
}
}
/*-----------------------------------------------------------*/
static unsigned char *prvGetFreeBuffer( void )
{
portBASE_TYPE x;
unsigned char *pucReturn = NULL;
unsigned long ulAttempts = 0;
while( pucReturn == NULL )
{
/* Look through the buffers to find one that is not in use by
anything else. */
for( x = 0; x < fecNUM_BUFFERS; x++ )
{
if( ucBufferInUse[ x ] == pdFALSE )
{
ucBufferInUse[ x ] = pdTRUE;
pucReturn = pucAlignedBufferStartAddresses[ x ];
break;
}
}
/* Was a buffer found? */
if( pucReturn == NULL )
{
ulAttempts++;
if( ulAttempts >= uipBUFFER_WAIT_ATTEMPTS )
{
break;
}
/* Wait then look again. */
vTaskDelay( fecMINIMAL_DELAY );
}
}
return pucReturn;
}
/*-----------------------------------------------------------*/
void interrupt 86 vFECISRHandler( void )
{
unsigned long ulEvent;
portBASE_TYPE xHighPriorityTaskWoken = pdFALSE;
/* Determine the cause of the interrupt. */
ulEvent = EIR & EIMR;
EIR = ulEvent;
if( ulEvent & EIR_RXF_MASK )
{
/* A packet has been received. Wake the handler task in case it is
blocked. */
xSemaphoreGiveFromISR( xFECSemaphore, &xHighPriorityTaskWoken );
}
if( ulEvent & EIR_TXF_MASK )
{
/* The Tx has completed. Mark the buffer it was using as free again. */
prvReturnBuffer( pxFECTxDescriptor->data );
pxFECTxDescriptor->data = NULL;
}
if (ulEvent & ( EIR_UN_MASK | EIR_RL_MASK | EIR_LC_MASK | EIR_EBERR_MASK | EIR_BABT_MASK | EIR_BABR_MASK | EIR_HBERR_MASK ) )
{
/* Sledge hammer error handling. */
prvInitialiseFECBuffers();
RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
}
portEND_SWITCHING_ISR( xHighPriorityTaskWoken );
}

46
Demo/ColdFire_MCF51CN128_CodeWarrior/Sources/FEC.h Normal file
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@ -0,0 +1,46 @@
/*
FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#ifndef INC_FEC_H
#define INC_FEC_H
/* Configure the FEC peripheral, IO and descriptors. */
void vInitFEC( void );
/* Receive any data into the uip_buf array. */
unsigned portLONG ulFECRx( void );
/* Transmit the uip_buf array. */
void vFECTx( void );
#endif

157
Demo/ColdFire_MCF51CN128_CodeWarrior/Sources/FreeRTOSConfig.h Normal file
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/*
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License (version 2) as published
by the Free Software Foundation and modified by the FreeRTOS exception.
**NOTE** The exception to the GPL is included to allow you to distribute a
combined work that includes FreeRTOS.org without being obliged to provide
the source code for any proprietary components. Alternative commercial
license and support terms are also available upon request. See the
licensing section of http://www.FreeRTOS.org for full details.
FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
1 tab == 4 spaces!
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* CodeWarrior often thinks it knows better than you which files you want to
build - and changes the port.c and portasm.S files included in the project from
the ColdFire V1 versions to the x86 versions. If you get lots of errors output
when either file is compiled then delete the files from the project and then
add back in the port.c and portasm.S files that are located in the
FreeRTOS\Source\portable\GCC\ColdFire_V1 directory. Remove the line below
before compiling. */
//#error Read the comment above this line, then delete this error statement!
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <hidef.h>
#include "derivative.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( 50000000UL )
#define configTICK_RATE_HZ ( ( portTickType ) 100 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 13 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 12 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 0
#define configUSE_MUTEXES 1
#define configCHECK_FOR_STACK_OVERFLOW 1
#define configGENERATE_RUN_TIME_STATS 0
#define configUSE_RECURSIVE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 0
#define configUSE_COUNTING_SEMAPHORES 0
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
/* It is not advisable to change these values on a Coldfire V1 core. */
#define configKERNEL_INTERRUPT_PRIORITY 1
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 7
/* Ethernet configuration. */
#define configMAC_0 0x00
#define configMAC_1 0x04
#define configMAC_2 0x9F
#define configMAC_3 0x00
#define configMAC_4 0xAB
#define configMAC_5 0x2B
#define configIP_ADDR0 192
#define configIP_ADDR1 168
#define configIP_ADDR2 0
#define configIP_ADDR3 222
#define configGW_ADDR0 192
#define configGW_ADDR1 168
#define configGW_ADDR2 0
#define configGW_ADDR3 3
#define configNET_MASK0 255
#define configNET_MASK1 255
#define configNET_MASK2 255
#define configNET_MASK3 0
#define configNUM_FEC_RX_DESCRIPTORS 2
#define configFEC_BUFFER_SIZE 1520 /* Should be multiple of 16. */
#define configUSE_PROMISCUOUS_MODE 0
#define configETHERNET_INPUT_TASK_STACK_SIZE ( 320 )
#define configETHERNET_INPUT_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configPHY_ADDRESS 1
#if ( configFEC_BUFFER_SIZE & 0x0F ) != 0
#error configFEC_BUFFER_SIZE must be a multiple of 16.
#endif
#endif /* FREERTOS_CONFIG_H */

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