Commit graph

475 commits

Author SHA1 Message Date
Pascal Reich
e5987bbdb2
Remove Unused Code and Preprocessor Directives in RP2040 Port (#1324)
* Remove redundant code and preprocessor directives

* Remove more redundant code and directives
2025-10-08 18:06:45 +05:30
Ths.quiniou
a1f6e1f64f
fix[RL78 Port] incorrect register image for pvParameters in FAR model (#1316) (#1317)
In the RL78 FAR data model, pxPortInitialiseStack() did not initialize
the register image for the task parameter (pvParameters) correctly.
A:DE registers were saved with dummy values instead of the actual pointer.

Effect: on first context restore the function prologue read a corrupted
parameter. NEAR builds were not affected.

This patch aligns the FAR path with the calling convention and compiler
version:
 - IAR V2: pass pvParameters via registers → DE = low 16 bits, A = high 8
 - IAR V1 (fallback): keep legacy stack write
Also keeps the original stack-frame layout and updates the comment to
reflect that pointer sizes depend on __DATA_MODEL__.

Result: tasks in FAR receive the correct parameter at entry; NEAR remains
unchanged.

Co-authored-by: Thomas Quiniou <tquiniou@fdi-access.com>
2025-10-06 18:37:11 +05:30
Ahmed Ismail
a8ae21c88e
armv8-r: Add Arm Cortex-R82 non-MPU port (#1289)
The goal of this commit is to add the GCC/ARMClang non-MPU
port variant for ARM Cortex-R82 processor which is
ARMv8-R AArch64 based.
The work done is inspired by the GCC ARM_AARCH64 FreeRTOS port.

This port has the following features:
* Uses single security state (non TrustZone).
* Supports SMP (Symmetric multi-processing).
* Doesn't support Hypervisor (EL2).
* Doesn't support neither PMSA (MPU) nor VMSA (MMU).

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
2025-09-29 20:10:22 +05:30
mathiasgredal
3d44975181
RP2040: Fix use of deprecated volatile semantics for C++20 (#1318) (#1319)
Co-authored-by: Mathias Gredal <matg@universal-robots.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2025-09-17 12:44:14 +05:30
razrbro
692c4b070f
Fix: avoid set but unused variable warning in pxPortInitialiseStack (#1320) 2025-09-17 11:19:04 +05:30
Ahmed Ismail
44ae6cf61a
cortex-M ports: Clarify hardware-saved exception frame size variable (#1314)
* cortex-M ports: Clarify hardware-saved exception frame size variable

- Rename ulStackFrameSize to ulHardwareSavedExceptionFrameSize to
reflect the hardware-saved exception frame (8 or 26 words based
on FPU/lazy stacking).
- Add comments explaining standard vs extended frames.
- Apply across Cortex-M ports.
- No functional change, improves readability.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* kernel-checker-script: Modify Arm copyright header regex

Arm's copyright header regex is modified with the following:

* Accept both single year copyright headers (e.g., "2024")
and year range copyright headers (e.g., "2024-2025").

* Accept both single-line copyright header and also
multi-line header.

* Add the escape backslash to accept only literal dot
not any character.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

---------

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-09-09 14:25:42 +08:00
Kim Lindberg Schwaner
ccabdec2f8
Fix risk of Win32 timer setup call getting ignored (#1311)
If a user configures the configASSERT macro to expand to nothing,
a call to the Win32 API SetWaitableTimer() doesn't get compiled.

This can happen if, for example, configASSERT(x) set defined as
assert(x) (from assert.h) which expands to nothing when NDEBUG is
set (common for "release" builds).
2025-08-15 11:09:28 -07:00
DuYicheng
386c1bca66
Change the macro from portMAX_DELAY to SIZE_MAX in order to initialize size_t-type variable correctly (#1310) 2025-08-15 12:37:23 +05:30
Ahmed Ismail
43947413b9
event-groups: Fix multiple definitions (#1307)
This commit does the following:
* Remove xEventGroupClearBitsFromISR and
xEventGroupSetBitsFromISR functions direct mapping
to xTimerPendFunctionCallFromISR in case the trace
facility is feature not set. This should match the
current implementation in which the application calling
xEventGroupClearBitsFromISR
without defining the trace macros
(i.e. traceENTER_xEventGroupClearBitsFromISR is
a blank function in this case) will end up calling
xTimerPendFunctionCallFromISR function directly.
This enhances the readability of the code by not
guarding the xEventGroup<Set/Clear>BitsFromISR
functions' declaration and definition based on
the trace facility macro (i.e. configUSE_TRACE_FACILITY).

* Refactor the guarding macros for MPU_xEventGroupClearBitsFromISR
and MPU_xEventGroupSetBitsFromISR functions to match the
change above.

The current implementation leads to redefinition warnings
as `event_groups.h`redefines xEventGroupClearBitsFromISR
and xEventGroupSetBitsFromISR based on
`configUSE_TRACE_FACILITY' after they have been defined based
on configUSE_MPU_WRAPPERS_V1 in `mpu_wrappers.h`. The
implemented changes should resolve these warnings.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
2025-08-14 10:40:59 -07:00
Dennis Lambe Jr.
c91ee8d724
Fix CMake build for GCC_ARM_CRx_MPU (#1308) (#1309)
Add GCC_ARM_CRX_MPU to the set of FREERTOS_PORT patterns that trigger
adding mpu_wrappers.c and mpu_wrappers_v2.c to freertos_kernel_port
target_sources.
2025-08-14 10:35:53 +05:30
creiter64
e9440d4079
Move windows headers to port.c (#1302)
* [MSVC-MingW] Move windows headers to port.c

This prevents the inclusion of windows.h. into all header files using
FreeRTOS.h and thus defining several macros conflicting with common
definitions.

* [MSVC-MingW] Include correct header for compiler intrinsics

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2025-08-05 19:11:54 +08:00
Dennis Lambe Jr.
c5bec0e4b2
LLVM assembler compatibility for ARM_CRx_MPU (#1303)
GNU as makes unrecognized sections loadable and writable by default, but
LLVM's assembler requires specifying flags explicitly. Without them, the
linker generates "has non-ABS relocation" errors when trying to link the
resulting object files.
2025-08-05 16:02:03 +05:30
Gaurav-Aggarwal-AWS
32e581636f
Delete thread key on process exit (#1297)
Previously, the shared thread key was deleted in xPortStartScheduler
after scheduler was ended. This created a race condition where
prvThreadKeyDestructor (responsible for freeing thread-specific heap
memory) would not be called if xPortStartScheduler deleted the key
before the last task deletion, as destructors are not invoked after key
deletion (see https://github.com/walac/glibc/blob/master/nptl/pthread_create.c#L145-L150).

Move thread key deletion to process exit to ensure all thread-specific
memory is properly freed.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-07-24 11:07:27 +05:30
Florian La Roche
48a4939c9f
Fix compiler warning (#1291)
- In list.h fix a typo in comments.
- In portable/ThirdParty/GCC/Posix/port.c fix compiler warning about
  "gcc -Wwrite-strings".

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2025-07-09 11:16:00 +05:30
Rahul Kar
62bd622ffc
Update download locations to outside repository content (#1280)
Update curl command to download in a non user accessible folder
2025-06-05 23:23:47 +05:30
Simon Brizard
2615dcde13
fix[IAR/RL78 Port] Compilation fails on portasm.s file (#1278)
The indentation on ASM macro is not authorized by IAR compiler
2025-05-12 21:20:46 +05:30
Florian La Roche
d03233f209
fix warnings from "gcc -Wconversion" (#1271)
fix warnings from "gcc -Wconversion"

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
2025-04-28 09:51:58 +05:30
Mario Luzeiro
4ee6a1f22f
MPLAB PIC32MZ-EF - Adds an assert to catch register overflow (#1265) (#1267)
Add an assert to catch register overflow (#1265)
2025-04-25 17:05:15 +05:30
arctic-alpaca
03db672b8f
Fix race in POSIX port vPortEndScheduler (#1262)
* Fix race in POSIX port `vPortEndScheduler`

The `vPortEndScheduler` checks whether it's a FreeRTOS thread after signalling the scheduler thread to stop. This creates a race between the check and the destruction of the thread key. By moving the signal to the scheduler thread after the check, the race is prevented.

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-04-03 14:32:44 +05:30
Jonathan Cubides
0030d609a4
Add support for Vector context save support on RISC-V (#1260)
port: riscv: Add vector context save support
2025-03-27 15:22:22 +05:30
ErickReyesR
b9aa064591
FreeRTOS MPU: Remove MPU region number check (#1261)
FreeRTOS MPU: Remove MPU region number check

This change removes the assertion and runtime check that enforces
matching between configTOTAL_MPU_REGIONS and physical MPU
regions,. This allows applications running on devices with 16 MPU
regions to manage 8 MPU regions while leaving the remaining 8
for the kernel.

Signed-off-by: Erick Reyes <erickreyes@google.com>
2025-03-19 15:01:22 +05:30
Gaurav-Aggarwal-AWS
dacce186cf
Use UBaseType_t for ullMachineTimerCompareRegisterBase (#1258)
Use architecture-dependent UBaseType_t instead of fixed type for
ullMachineTimerCompareRegisterBase. This type is defined to uint32_t or
uint64_t based on XLEN, resolving warnings on 32-bit platforms.

Reported by landretk@ on the PR FreeRTOS/FreeRTOS-Kernel#1176.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-03-17 16:41:11 +05:30
Saiiijchan
64fd9291ef
RISC-V: refine fpu reg context offset (#1257)
RISC-V: refine fpu reg context offset

pxCode and mstatus stored at index 0 and 1 are based on XLEN.
Therefore, the correct formula to calculate the FPU register index
should be ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ).

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
2025-03-13 21:10:51 +05:30
Saiiijchan
bb47bc02f2
RISC-V: refine fpu offset according to portFPU_REG_SIZE (#1256)
Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
Co-authored-by: wangfei_chen <wangfei_chen@realsil.com.cn>
2025-03-13 11:22:38 +05:30
Jonathan Cubides
4d9cd906d3
RISCV Add FPU context save (#1250)
* port: riscv: Split the number of registers and the size of the context

* port: riscv: Create some macros for the FPU context

* port: riscv: Add a couple of macros that store fpu context

* port: riscv: Update the stack init function to include the fpu context size

* port: riscv: Add a chip_specific_extensions file that includes the F extension

* Update dictionary to include some risc-v instructions

* port: riscv: Fix a few typos

* port: riscv: Apply @aggarg's sugestions
2025-03-06 10:34:48 -08:00
Gaurav-Aggarwal-AWS
df0aa5a815
Disable stack overflow check for MPU ports (#1231)
Disable stack overflow check for MPU ports

Stack overflow check is not straight forward to implement for MPU ports
because of the following reasons:
1. The context is stroed in TCB and as a result, pxTopOfStack member
   points to the context location in TCB.
2. System calls are executed on a separate privileged only stack.

It is still okay because an MPU region is used to protect task stack
which means task stack overflow will trigger an MPU fault.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-02-24 21:54:15 +05:30
Bhoomika R S
1a1ae36f9a
Update instruction to suppress SIGUSR1 in Posix with LLDB debugger (#1248) 2025-02-13 15:03:23 +05:30
John Boiles
15ec8b8995
POSIX Simulator: Assert if vPortYield called from a non-FreeRTOS thread (#1247) 2025-02-13 10:44:22 +05:30
Bhoomika R S
51a1598e4e
Add instruction to suppress SIGUSR1 in Posix with LLDB debugger (#1245)
While using the macOS default LLDB debugger, a call to vTaskEndScheduler results in an unhandled SIGUSR1 (aka SIGRESUME) when restoring the scheduler thread's signals with pthread_sigmask. This crashes the program.

Added instructions in portable/ThirdParty/GCC/Posix/port.c to suppress SIGUSR1 to prevent LLDB debugger interference when exiting xPortStartScheduler

Thanks to: @johnboiles for pointing it out in #1224
2025-02-12 14:57:03 +05:30
Graham Sanderson
a470b2d375
RP2040: update FreeRTOS_Kernel_import.cmake to match the newer version in Community-Supported-Ports (#1243)
- The newer version looks in Community-Supported-Ports too

Co-authored-by: graham sanderson <graham.sanderson@raspeberryi.com>
2025-02-10 11:02:36 +05:30
Jakub Tymejczyk
d10ee46811
Fix GCC/Posix port compilation on FreeBSD (#1239) (#1240)
On FreeBSD pthread_once_t is a struct and cast is required.
Otherwise there's compilation error:
../../mocks/freertos/port.c:261:23: error: expected expression
    hSigSetupThread = PTHREAD_ONCE_INIT;
                      ^
PTHREAD_ONCE_INIT is defined as: { PTHREAD_NEEDS_INIT, NULL } on FreeBSD

Co-authored-by: Jakub Tymejczyk <jakub.tymejczyk@enigma.com.pl>
2025-02-07 06:51:34 +05:30
Rahul Kar
ae0a5913c8
Call key creation before checking if a thread is FreeRTOS (#1238) 2025-02-06 14:41:19 +05:30
Ben Nicholls
0f7edaff73
Reinstate "Fix inaccurate ticks in windows port" (#1198)
Reinstates PR https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/142 that was reverted in https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/143

Co-authored-by: Ben Nicholls <benn@smartbadge.com.au>
2025-02-04 11:03:44 +05:30
Gaurav-Aggarwal-AWS
ad4e723829
Mark mutex as robust to prevent deadlocks (#1233)
Mark mutex as robust to prevent deadlocks

Prevent application hangs that occur when a thread dies while holding a
mutex, particularly during vTaskEndScheduler or exit calls. This is
achieved by setting the PTHREAD_MUTEX_ROBUST attribute on the mutex.

Fixes:
- GitHub issue: FreeRTOS/FreeRTOS-Kernel#1217
- Forum thread: freertos.org/t/22287

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-01-29 07:27:30 +05:30
Cavin McKinley
b421abc7c3
Update Community-Supported-Ports submod to fix RP2350 port - FreeRTOS-Kernel#1220 (#1232)
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2025-01-25 15:08:49 +05:30
Gaurav-Aggarwal-AWS
11d0caa614
Fix the context array size for MPU ports (#1230)
Fix the context array size for MPU ports

Ensure the saved context location falls within the reserved context area
rather than overlapping with the next MPU_SETTINGS structure member.

This never caused a problem because actual read/write operations
start from one word before the saved context location.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-01-25 13:34:03 +05:30
John Boiles
2b35979a1a
POSIX Simulator: Handle pthreads not created by FreeRTOS differently (#1223) 2025-01-24 16:56:59 -08:00
Marouen Ghodhbane
72bb476bf3 portable: aarch64_sre: Add support for vApplicationFPUSafeIRQHandler
The application writer needs to name their IRQ handler as:
1. vApplicationIRQHandler if the IRQ handler does not use FPU registers.
2. vApplicationFPUSafeIRQHandler is the IRQ handler uses FPU registers.

When the application uses vApplicationFPUSafeIRQHandler, a default
implementation of vApplicationIRQHandler is used which stores FPU
registers and then calls vApplicationFPUSafeIRQHandler.

Note that recent versions of GCC may use FP/SIMD registers to optimize 16-bytes
copy and especially when using va_start()/va_arg() functions (e.g printing some thing
in IRQ handlers may trigger usage of FPU registers)

This implementation is heavily inspired by both the ARM_CA9 port and the ARM_CRx_No_GIC
port done in [1]

[1] https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/1113

Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
2025-01-22 17:00:50 -08:00
Marouen Ghodhbane
630cfb5b79 portable: aarch64_sre: add the configuration and status registers to the fpu saved context
FPSR and FPCR are two 64-bits registers where only the lower 32 bits are defined.
Save them when doing context switch with FPU context saving enabled.

Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
2025-01-22 17:00:50 -08:00
Marouen Ghodhbane
ff0989e46b portable: aarch64_sre: add configUSE_TASK_FPU_SUPPORT support
This is a direct backport of upstream commit [1] for aarch64 (legacy operation port)
done under [2]
The same code can be applied on the aarch SRE port to be able to enable FPU context
saving on all tasks context switch to mitigate GCC optimization to use SIMD registers
for copy.

[1] "55eceb22: Add configUSE_TASK_FPU_SUPPORT to AARCH64 port (#1048)"
[2] https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/1048

Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
2025-01-22 17:00:50 -08:00
kzorer
1b8f5965d3
Add xQueueCreateSetStatic method for static allocation of Queue Sets (#1228)
Add xQueueCreateSetStatic method for static allocation of Queue Sets

This commit introduces the xQueueCreateSetStatic function, which allows for the static allocation of Queue Sets in FreeRTOS when both configUSE_QUEUE_SETS and configSUPPORT_STATIC_ALLOCATION are enabled.
2025-01-22 14:53:35 +05:30
John Boiles
a58579681c
POSIX Simulator: Remove unused __APPLE__ mach_vm.h include (#1225)
Remove unused __APPLE__ mach_vm.h include
2025-01-21 14:20:16 +05:30
Ahmed Ismail
78e0cc778a
ARMv8.1-M: Add task dedicated PAC key support (#1195)
armv8.1-m: Add task dedicated PAC key

To harden the security, each task is assigned a dedicated PAC key, so that attackers needs to guess the all the tasks' PAC keys right to exploit the system using Return Oriented Programming.

The kernel is now updated to support the following:
* A PAC key set with a random number generated and is saved in the task's context when a task is created.
* As part of scheduling, the task's PAC key is stored/restored to/from the task's context when a task is unscheduled/scheduled from/to run.

stack-overflow-check: Introduce portGET_CURRENT_TOP_OF_STACK macro

When MPU wrapper v2 is used, the task's context is stored in TCB and `pxTopOfStack`` member of TCB points to the context location in TCB. We, therefore, need to read PSP to find the task's current top of stack.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
2025-01-14 10:50:52 +05:30
creiter64
c38427eea4
Fix function parameter shadowing global variable. (#1221)
The function vApplicationFPUSafeIRQHandler gets the value of ICCIAR as
parameter, but a constant containing the address of ICCIAR was also
defined. Fix the name of the constant to align it with what it actually
holds.
2025-01-13 14:48:10 -08:00
iotah
3a7b3082cf
Update community supported ports submodulees (#1218)
Signed-off-by: Hua Zheng <hua.zheng@embeddedboys.com>
Co-authored-by: Hua Zheng <hua.zheng@embeddedboys.com>
2025-01-06 11:05:53 +05:30
Felix van Oost
f05244a8d5
Pass core ID to port lock macros (#1212)
Pass core ID to task/ISR lock functions
2024-12-30 14:28:49 +05:30
Felix van Oost
31dd1e39cb
Pass core ID to critical nesting count macros (#1206)
* Pass core ID to CRITICAL_NESTING_COUNT macros

* Match existing data type for xCoreID

* Get core ID when interrupts are disabled

* Implement get core ID with interrupt disabled

* Get core ID inline within vTaskSuspendAll() to resolve compiler warning

* Fix formatting check

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Ching-Hsin,Lee <chinglee@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2024-12-19 14:20:43 +05:30
Saiiijchan
e169442c29
Refine VFP context for Coretex-A9 (#1209)
s0–s15 (d0–d7, q0–q3) and d16–d31 (q8–q15) are caller save
register

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
Co-authored-by: wangfei_chen <wangfei_chen@realsil.com.cn>
2024-12-17 17:25:20 +05:30
wwhheerree
3ddfffda04
Regression Bug Fix: Fix Incorrect Return of MSVC-MingW portYIELD_FROM_ISR (#1207)
There is a regression issue introduced in
    cfc268814a.
    This PR was intended to update MIT licensed header from v9 to v10.
    But it accidentally changed "portYIELD_FROM_ISR( x )" in MSVC-MingW/portmacro.h.
    It caused "portYIELD_FROM_ISR( x )" does not return correct value to "prvProcessSimulatedInterrupts".
2024-12-16 18:48:54 +05:30
Rahul Kar
b58005a4da
Add macro guard configUSE_MPU_WRAPPERS_V1 to remove definition missing warning. (#1208)
Add macro guard to removed definition missing warning
2024-12-16 18:26:43 +05:30