8 commits

Author	SHA1	Message	Date
Richard Barry	d55e7e77a2	Update version number to 8.1.2 after moving the defaulting of configUSE_PORT_OPTIMISED_TASK_SELECTION into individual port layers so it does not affect ports that do not support the definition.	2014-09-02 22:39:54 +00:00
Richard Barry	a60ce58731	Update version number to 8.1.1 for patch release that re-enables mutexes to be given from an interrupt.	2014-08-29 19:14:23 +00:00
Richard Barry	d33a14b5fb	***IMMINENT RELEASE NOTICE*** ... Update version numbers ready for FreeRTOS V8.1.0 release in about 10 days.	2014-08-16 20:19:40 +00:00
Richard Barry	162448f06b	General maintenance - changing comments and correcting spellings only.	2014-08-04 07:57:18 +00:00
Richard Barry	47f895cb34	Cortex-A5 IAR port: ... - Removed SAMA5 specifics from the port layer, and instead call a generic ISR callback as per Cortex-A9 ports.	2014-08-03 19:15:30 +00:00
Richard Barry	b2e739495a	Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.: ... - Slight improvement to the save context macro. - Remove some #warning remarks. - Enable interrupts before calling the ISR handler rather than in the ISR handler.	2014-08-03 18:37:58 +00:00
Richard Barry	3a3d061cc5	Continue working on the GIC-less Cortex-A5 port for IAR: ... - Add in the assert when a task attempts to exit its implementing function without deleting itself. - Remove obsolete code from the context switch asm code (obsoleted by the fact that there is no mask register). - Attempt to make code more generic by using definitions for additional register addresses.	2014-07-29 21:31:04 +00:00
Richard Barry	8ad9b75810	Rename ARM_CAx_No_GIC ARM_CA5_No_GIC and add FreeRTOSConfig setting to specify the number of registers in the FPU unit.	2014-07-12 20:39:22 +00:00