10 commits

Author	SHA1	Message	Date
Richard Barry	dc99300fa9	First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.	2018-11-24 20:59:07 +00:00
Richard Barry	8cef339aec	Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.	2018-11-19 06:01:29 +00:00
Richard Barry	baee711cb6	Continue work on Risc V port.	2018-11-06 02:04:28 +00:00
Richard Barry	e3dc5e934b	RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet.	2018-09-27 17:25:17 +00:00
Richard Barry	32f35e9130	RISC-V: ... Added code to setup the timer interrupt - not tested yet. Added the taskYIELD() implementation - so far just checked it generates an interrupt.	2018-09-12 16:33:05 +00:00
Richard Barry	b11eb3a59c	RISC-V work in progress: ... + Initialise task stack. + Successfully jump to start of first task.	2018-09-10 20:50:05 +00:00
Richard Barry	3a1631fda3	Update copyright date ready for tagging V10.1.0.	2018-08-22 23:23:03 +00:00
Richard Barry	fb9de58f56	Update version numbers in preparation for a new release.	2018-08-21 19:50:48 +00:00
Richard Barry	f6cbf20019	Update RISC-V project to used official port stubs in place of third party port.	2018-07-07 21:54:41 +00:00
Richard Barry	3bfc32d444	Add stubs for official RISC-V RV32 port.	2018-07-07 21:47:31 +00:00