4 commits

Author	SHA1	Message	Date
Richard Barry	b2b1b09ea5	Fix bug in core_cm3.c atomic macros. ... Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.	2019-02-16 01:08:38 +00:00
Richard Barry	fb73829148	Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState(). ... Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task. Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.	2019-02-08 01:18:08 +00:00
Richard Barry	80df5cd517	Update the pin mux setup on the Vega board demo to enable the LED.	2018-12-31 20:14:34 +00:00
Richard Barry	11d9c440b8	Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason). ... Add a project for the Vega board's RI5CY core.	2018-12-31 18:19:52 +00:00