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Author SHA1 Message Date
Yuhui.Zheng 99e796eb01 Removing unnecessary ThirdParty ports -- Wiced_CY and nrf52840-dk. 
For projects depending on either of these two ports, please update your projects according to below:
Wiced_CY -- Use GCC/ARM_CRx_No_GIC instead. 
nrf52840-dk -- Use GCC/ARM_CM7/r0p1 instead. Please note that, kernel port shall only take dependency on MCU core, not MCU peripherals. (Please take out RTC related from kernel port.) For low power feature (tickless) in FreeRTOS, please follow this page https://www.freertos.org/low-power-ARM-cortex-rtos.html. In case ARM_CM7/rop1 is missing any feature, reach out to us.
 2020-01-30 19:45:03 +00:00
Richard Barry 0d54d1c4dc Correct an err in queue.c introduced when previously updating behaviour when queue sets are used in combination with queue overwrites. 2020-01-29 19:52:38 +00:00
Richard Barry 2415dc26b0 Introduce the portSOFTWARE_BARRIER macro which thus far is only used by the Win32 demo to hold execution up in case a simulated interrupt is executing simultaneously. That should never happen as all threads should execute on the same core, but we have had numerous reports that this and other Win32 port changes we have made fixed these issues - although we have not been able to replicate them ourselves. 2020-01-23 23:49:24 +00:00
Gaurav Aggarwal e058a65b16 Updates to CM3_MPU GCC port 
- System calls are now only allowed from kernel code. This change can be turned on
  or off using configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY.
- MPU is disabled before reprogramming it and enabled afterwards to be compliant
  with ARM recommendations.
 2020-01-23 01:50:25 +00:00
Richard Barry 42a0eaafdc Ensure both one-shot and auto-reload are written consistently with a hyphen in comments. 2020-01-16 04:25:29 +00:00
Richard Barry 9456992c1f Added uxTimerGetReloadMode() API function. 2020-01-16 04:10:18 +00:00
Yuhui.Zheng 0d95aca202 Introduce a port for T-HEAD CK802. A simple demo for T-HEAD CB2201 is also included. 2020-01-10 07:53:14 +00:00
Richard Barry 066e2bc7d2 Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the IAR RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old. 2020-01-09 02:23:51 +00:00
Richard Barry fbb23055cd Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the GCC RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old. 2020-01-07 01:14:36 +00:00
Richard Barry eaf9318df8 Add Source/portable/ARMClang file that directs users to the GCC port if they which to use the ARMClang compiler. 2020-01-04 00:14:18 +00:00
Richard Barry 881958514b If tickless idle mode is in use then ensure prvResetNextTaskUnblockTime() is called after a task is unblocked due to a bit being set in an event group. This allows the MCU to re-enter sleep mode at the earliest possible time (rather than waiting until the timeout that would occur had the task not being unblocked be the event group) and matches a similar change made for queues and derivative objects (semaphores, etc.) some time ago. 2020-01-03 22:50:31 +00:00
Richard Barry 9e86cb95a7 Add xPortIsInsideInterrupt() to the IAR ARMv7-M ports. 2020-01-03 01:17:29 +00:00
Richard Barry be3561ed53 Added xTaskAbortDelayFromISR() and ulTaskNotifyValueClear() API functions. 
Added tests for xTaskAbortDelayFromISR() into Demo/Common/Minimal/AbortDelay.c.
Added tests for ulTaskNotifyValueClear() into Demo/Common/Minimal/TaskNotify.c.
 2020-01-02 18:55:20 +00:00
Richard Barry 62b413627a Minor updates to comment block for xTaskCheckForTimeOut(). 2020-01-01 22:24:44 +00:00
Gaurav Aggarwal 474182ab39 Make vSetupTimerInterrupt weak in the RVDS M4 MPU port to give the 
application writer a chance to override this function. This gives
the application write ability to use a different timer.
 2020-01-01 00:04:10 +00:00
Gaurav Aggarwal 22dd9a55ab Update documentation of xTaskCheckForTimeOut function to reflect the 
intended use of this API.
 2019-12-31 20:49:07 +00:00
Richard Barry 3203c5cc85 Previously the STM32F0518 compiler setting was changed to enable the use of the __weak attribute - however changing the port layer to use #pragma weak in place of __weak means the compiler setting change is not required and removes the risk of introducing incompatibilities - so this check in reverts the compiler settings change. 2019-12-30 22:24:58 +00:00
Richard Barry e292c67933 Replace the static prvSetupTimerInterrupt() function in the Cortex-M port layers that still used it (other than MPU ports so far) with a weakly defined function call vPortSetupTimerInterrupt() - which allows application writers to override the function with one that uses a different clock. 2019-12-30 21:16:09 +00:00
Richard Barry e23d638afd Correct use of xStreamBufferRead() to xStreamBufferReceive() in code comments - no source code changes. 2019-12-30 20:00:49 +00:00
Richard Barry c72df2f98d Tidy up comments only. 2019-12-27 21:22:07 +00:00
Gaurav Aggarwal cef6548e8b Updates to CM4_MPU RCDS port 
- System calls are now only allowed from kernel code. This change can be turned on
  or off using configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY.
- MPU is disabled before reprogramming it and enabled afterwards to be compliant
  with ARM recommendations.
 2019-12-24 22:45:32 +00:00
Richard Barry 05adf564f6 Add readme into the third party RISC-V port that points to the directories that contains the official ports. 2019-12-24 17:24:23 +00:00
Gaurav Aggarwal 96b6746364 Updates to CM4_MPU IAR port 
- System calls are now only allowed from kernel code. This change can be turned on
  or off using configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY.
- MPU is disabled before reprogramming it and enabled afterwards to be compliant
  with ARM recommendations.
 2019-12-21 00:02:31 +00:00
Gaurav Aggarwal 47d8ac6ac6 Updates to CM4_MPU GCC port 
- System calls are now only allowed from kernel code. This change can be turned on
  or off using configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY.
- MPU is disabled before reprogramming it and enabled afterwards to be compliant
  with ARM recommendations.
 2019-12-20 02:05:44 +00:00
Yuhui.Zheng 9c0e3fe9f1 Cortex M0 GCC/IAR/Keil ports -- tickless support. 
The default portMISSED_COUNTS_FACTOR is set to 45 cycles. User could override this value, if a more accurate count is available.
 2019-12-18 09:55:08 +00:00
Yuhui.Zheng 3cde02a046 RVDS/Keil weak linkage for vPortSetupTimerInterrupt() -- CM4F, CM3 
Test steps are documented in this PR https://github.com/aws/amazon-freertos/pull/1141.
 2019-12-18 02:08:06 +00:00
Gaurav Aggarwal 66ce9f7d72 Move warning suppression for IAR compiler to portmacro.h for v8M ports 
IAR produces some warnings which can not be fixed in the source code because
then other compilers start generating warnings. We suppressed those warnings
in the project file before. This change moves the warning suppression from
project files to portmacro.h.
 2019-12-07 01:23:17 +00:00
Richard Barry 9491af1fd7 Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to overwrite items in two queues that are part of the same set. 
Minor queue optimisations.
 2019-12-03 01:50:07 +00:00
Richard Barry 46e5937529 Remove guards against __ARMCC_VERSION version numbers that were previously used to avoid compiler warnings in some GCC ARM Cortex ports. 2019-11-21 22:35:21 +00:00
Richard Barry 07622ed3ee Remove driver files that generate compiler warnings from the RISC-V_Renode_Emulator_SoftConsole project. 
Update RISC-V ports so the interrupt stack is set to a known value before the scheduler is started if the interrupt stack is statically defined rather than re-using the main.c() stack.
 2019-11-18 17:23:14 +00:00
Richard Barry 16639d2d63 Update to the latest atomic.h. 
Improve commenting in RISC-V GCC port.
Fix IAR RISC-V port so the first task starts with interrupts enabled.
Add references to third party page ref using newlib with FreeRTOS into the tasks.c file in each place newlib is referenced.
Move the position of the traceTASK_DELETE() trace macro in case of use with a memory allocator that writes over freed memory even when inside a critical section.
Efficiency improvement:  Make sure xTaskIncrementTick() does not return pdTRUE when the scheduler is locked.  This just prevents an unnecessary yield interrupt (unnecessary as it is ignored) when xYieldPending happens to be pdTRUE.
 2019-11-18 16:28:03 +00:00
Richard Barry 61a003088d Update RISK-V GCC port to ensure the first task starts with interrupts enabled - previously its interrupts were only enabled after it yielded for the first time. 2019-10-21 04:16:32 +00:00
Richard Barry d435a7b62d Move the call to traceTASK_DELETE() to before port portPRE_TASK_DELETE_HOOK() as in the Windows port portPRE_TASK_DELETE_HOOK() never returns. 2019-10-15 22:14:40 +00:00
Richard Barry dbac79045c Formatting changes only. 2019-10-10 17:56:10 +00:00
Richard Barry fd118f1888 Minor formatting change in comment only. 2019-10-07 18:56:33 +00:00
Yuhui.Zheng eb5c60c60b Update FreeRTOS.h with the version in GitHub. This is also to test submodule. 2019-09-24 22:29:35 +00:00
Yuhui.Zheng 0fe36e497d Nordic port. Notes for Richard -- the work items we discussed about for nrf52840-dk and Wiced_CY still remain. The only reason for this commit is we want to test out submodule. 2019-09-24 22:26:36 +00:00
Yuhui.Zheng 35bc9d7938 Revert 2728. Not because the files are still needed, but because we want to test out submodule. 
Before further updating project files in GitHub, keeping an additional copy.
 2019-09-24 22:19:54 +00:00
Yuhui.Zheng f001126ea8 Wiced_CY port is not needed anymore. Use GCC/ARM_CRx_No_GIC instead. 2019-09-24 20:56:55 +00:00
Yuhui.Zheng 9052882500 Adding tickless hooks to GCC/ARM_CRx_No_GIC port. 2019-09-24 20:07:40 +00:00
Richard Barry 80c1cb5de1 Correct code comments that referred to taskYIELD_FROM_ISR to portYIELD_FROM_ISR. 
Update RV32 port to use 16 byte-alignment all the time (only strictly necessary when using FLOP instructions).
 2019-09-24 16:06:21 +00:00
Yuhui.Zheng c217b68d38 sync from github to svn: this version of atomic.h does not have compiler specific symbols. compiler specific optimization is to be merged in each port/<compiler>/<arch> directory. 2019-09-23 16:51:03 +00:00
Yuhui.Zheng 6f958bbf80 sync from github to svn: Xtensa GCC as-is. 2019-09-20 22:09:21 +00:00
Yuhui.Zheng 1c5fcc7f05 sync from github to svn: Wiced_CY for AFR Cypress ports. 2019-09-20 20:52:30 +00:00
Yuhui.Zheng 74df636c78 sync from github to svn: documentation for RISC-V. This may be a temporary parking location. 2019-09-20 20:47:29 +00:00
Yuhui.Zheng cc0aee651e sync from github to svn: Renasas/RX100 #pragma _VECT() 2019-09-20 20:41:32 +00:00
Richard Barry da3d370ff7 RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores. 2019-09-04 15:46:45 +00:00
Richard Barry 96bad0f6c3 Minor bug fix in NTPDemo.c -> use of FREERTOS_INVALID_SOCKET in place of NULL. 
Update trace recorder code to account for uxPendedTicks renaming to xPendedTicks.
 2019-09-04 00:13:17 +00:00
Richard Barry ab41d89285 Add IAR RISC-V port to SVN - a work in progress. 2019-09-03 01:39:29 +00:00
Richard Barry 973a4f9869 Correct alignment of stack top in RISC-V port when configISR_STACK_SIZE_WORDS is defined to a non zero value. 2019-08-27 15:57:45 +00:00