Commit graph

242 commits

Author SHA1 Message Date
Richard Barry 8dadb6b87c Final V8.2.1 release ready for tagging:
+ Added MSP432 (ARM Cortex-M4F MSP430!) demos for IAR, Keil and CCS.
+ Renamed directory containing demo for STM32F7 ARM Cortex-M7.
+ Renamed directory containing demo for SAMV71 ARM Cortex-M7.
+ Introduced xTaskNotifyAndQuery().
2015-03-24 15:24:49 +00:00
Richard Barry 693d0520bc Update version number ready for V8.2.1 release. 2015-03-21 21:03:42 +00:00
Richard Barry 63b3c773d5 Kernel changes:
Exclude the entire croutine.c file when configUSE_CO_ROUTINES is 0.

New ports:
Added Cortex-M7 IAR and Keil port layers that include a minor errata workaround r0p1 Cortex-M7 devices.
Added Cortex-M4F port layer for CCS.

New demo applications:
Added demo application for STM32F7.
Added demo application for SAMv71.
2015-03-21 14:01:43 +00:00
Richard Barry 2bf93bf925 Minor updates relating to formatting and comments only. 2015-03-20 15:43:20 +00:00
Richard Barry 3012d9b94d Work-in-progress check in of MicroBlaze Kintex7 demo. 2015-03-10 15:58:19 +00:00
Richard Barry 96e72413f7 Kernel code:
+ Added mtCOVERAGE_TEST_DELAY() macro to facilitate getting better code coverage during testing.
+ Update prvNotifyQueueSetContainer() so it does not call xTaskRemoveFromEventList() if it is called from an interrupt, and the queue is locked.

Demo apps:
Added QueueSetPolling.c/h demo/test functions.
2015-03-04 17:45:18 +00:00
Richard Barry 7d169cef52 Correct typeo that broke the Win32 port. 2015-02-17 14:28:10 +00:00
Richard Barry 86b09bfeb9 Kernel updates:
+ Added vTimerSetTimerID() to compliment vTimerGetTimerID().  Now the timer ID can be used as timer local storage.
+ Updated comments and added some additional assert() calls.

Win32 port:
+ Some changes to allow easier 64-bit builds

PIC24/dsPIC port:
+ Added NOP after disable interrupt instruction.
2015-02-11 15:41:30 +00:00
Richard Barry dfdc319518 Kernel updates:
- Add user configurable thread local storage array, with get/set access function.
2015-01-26 17:40:35 +00:00
Richard Barry 501a531d46 Update version number in preparation for official V8.2.0 release. 2015-01-16 13:20:28 +00:00
Richard Barry c37b2ca39b Demo app changes:
Add a "query heap" command to the standard sample CLI commands.
Remove casting from configMAX_PRIORITIES setting in Win32 simulator demos as it was preventing a clean build. 

Source code changes.
General tidy up and addition of assert points.
2015-01-15 21:37:32 +00:00
Richard Barry 271393b7d9 Release candidate - this will be tagged as FreeRTOS V8.2.0rc1 and a zip file provided.
Minor lint changes.
2014-12-24 09:40:58 +00:00
Richard Barry 6741592026 Update version numbers in preparation for V8.2.0 release candidate 1. 2014-12-21 19:09:18 +00:00
Richard Barry fd02010886 Kernel changes:
+ Made xTaskNotifyGiveFromISR() its own function, rather than a macro that calls xTaskNotifyFromISR() (minor performance improvement).
+ GCC and Keil Cortex-M4F ports now use vPortRaiseBASEPRI() in place of ulPortRaiseBASEPRI() where the return value is not required (minor performance improvement).

Demo changes:
Change the [very basic] FreeRTOS+UDP SAM4E driver to use task notifications rather than a semaphore (execution time now 55% what it was in FreeRTOS V8.1.2!).
Robustness improvements to IntQueue.c standard demo task.h.
Added the latest standard demo tasks, reg test tasks and int q  tasks to the SAM4E demo.
2014-12-21 10:26:36 +00:00
Richard Barry 2de32c0141 Kernel changes:
+ Do not attempt to free the stack of a deleted task if the stack was statically allocated.
+ Introduce configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES - which optionally writes known values into the list and list item data structures in order to assist with the detection of memory corruptions.

Microblase port:  
+Change occurrences of #if XPAR_MICROBLAZE_0_USE_FPU == 1 to 	#if XPAR_MICROBLAZE_0_USE_FPU != 0 as the value can also be 2 or 3.

Demo app modifications:
+ Update Zynq project to use the 2014.4 tools and add in tests for the new task notification feature.
+ Update SAM4S project to include tests for the new task notification feature.
2014-12-19 16:27:56 +00:00
Richard Barry f407b70dcc + Update demos that use FreeRTOS+Trace to work with the latest trace recorder library.
+ Fix a few compiler warnings.
+ Add TickType_t specific critical sections so critical sections are not used when accessing the tick count in cases where the access is atomic (32-bit tick count, 32-bit architecture).
2014-12-18 11:02:15 +00:00
Richard Barry 85fb1cc024 + New feature added: Task notifications.
+ Optimise Cortex-M4F ports by inlining some critical section macros.
+ Original ports used a #define to set the path to portmacro.h - that method has been obsolete for years and now all the old definitions have been moved into a separate header files called deprecated_definitions.h.
+ Cortex-M port now check the active vector bits against 0xff when determining if a function is called from an interrupt - previously only a subset of the bits (0x1f) were checked.
+ Add in new standard demo/test files TaskNotify.c/h and include the files in the simulator demos.
+ Update trace recorder code, and some demos to use the new version (more to do).
+ Introduce uxTaskPriorityGetFromISR().
+ Minor typo corrections.
+ Update MingW simulator demo to match the MSVC simulator demo.
2014-12-15 14:13:03 +00:00
Richard Barry ca22607d14 Core kernel code:
Allow the stats formatting functions to be built in without stdio.h being included inside tasks.c.

Kernel port code:
- Slight change to the Cortex-A GIC-less port to move all non portable code to the application level.

SAMA5D4 demo project:
- Update the Atmel provided library to V1.1.
- Create a DDR build configuration.
- Ensure interrupts are all edge sensitive.
- Update the regtest code to use all 32 flop registers.
2014-10-15 21:01:31 +00:00
Richard Barry 9e66637bec Core kernel files:
+ Change how queues are allocated and deleted so only one pvPortMalloc() or vPortFree() is required in place of the previous 2.
+ Where the TCB is allocated in relation to the stack is now dependent on the stack growth direction.  The stack will not grow into the TCB.
+ Introduce the configAPPLICATION_ALLOCATED_HEAP constant to allow the application to provide the array used by heap_4.c as its heap.  This allows the application writer to use qualifiers on the array to, for example, force the memory into faster RAM.

Demo application:
+ Add demo for SAMA5D4 using IAR.
2014-10-08 20:31:14 +00:00
Richard Barry 3b0854bf96 Core kernel code:
+ Introduce xSemaphoreGenericGiveFromISR() as an optimisation when giving semaphores and mutexes from an interrupt.

Demo applications:
+ Update IntSemTest.c to provide more code coverage in xSemaphoreGenericGiveFromISR().
+ Ensure the MMU is turned on in the RZ IAR demo.  It was already on in the RZ ARM demo.
2014-09-16 14:54:32 +00:00
Richard Barry d55e7e77a2 Update version number to 8.1.2 after moving the defaulting of configUSE_PORT_OPTIMISED_TASK_SELECTION into individual port layers so it does not affect ports that do not support the definition. 2014-09-02 22:39:54 +00:00
Richard Barry 99229b597b Correct potential compiler warning when configUSE_MUTEXES is set to 0.
Add comments.
2014-08-30 20:18:18 +00:00
Richard Barry a60ce58731 Update version number to 8.1.1 for patch release that re-enables mutexes to be given from an interrupt. 2014-08-29 19:14:23 +00:00
Richard Barry ff5d3512b3 Core kernel code:
- Re-introduce the ability to give a mutex from an ISR.

Common demo code:
- Add additional tests into the GenQTest files for priority inheritance and using a mutex from an ISR.
2014-08-29 13:53:58 +00:00
Richard Barry 7d49c2190c Minor edits prior to tagging V8.1.0. 2014-08-26 16:23:09 +00:00
Richard Barry d33a14b5fb ***IMMINENT RELEASE NOTICE***
Update version numbers ready for FreeRTOS V8.1.0 release in about 10 days.
2014-08-16 20:19:40 +00:00
Richard Barry 52e687086c Demo application related:
+ Update the RZ IAR project so it targets the RZ RSK rather than custom hardware.
+ Update the RZ ARM/DS-5 project so it targets the RZ RSK rather than custom hardware.
+ Updated RX64M demos to use the new iodefine.h naming.

Cortex-A9 port related:
+ Update IAR, ARM and GCC Cortex-A9 port layers to include a 'task exit error' function which is called if a task attempts to incorrectly exit its implementing function.
+ Moved the instruction which switches into system mode out of the restore context macro, as it is only needed when starting the first task.

Core kernel files related:
+ Ensure there are no references to the mutexes held count when mutexes are excluded from the build.
2014-08-16 14:29:39 +00:00
Richard Barry 162448f06b General maintenance - changing comments and correcting spellings only. 2014-08-04 07:57:18 +00:00
Richard Barry 47f895cb34 Cortex-A5 IAR port:
- Removed SAMA5 specifics from the port layer, and instead call a generic ISR callback as per Cortex-A9 ports.
2014-08-03 19:15:30 +00:00
Richard Barry b2e739495a Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.:
- Slight improvement to the save context macro.
- Remove some #warning remarks.
- Enable interrupts before calling the ISR handler rather than in the ISR handler.
2014-08-03 18:37:58 +00:00
Richard Barry 3a3d061cc5 Continue working on the GIC-less Cortex-A5 port for IAR:
- Add in the assert when a task attempts to exit its implementing function without deleting itself.
- Remove obsolete code from the context switch asm code (obsoleted by the fact that there is no mask register).
- Attempt to make code more generic by using definitions for additional register addresses.
2014-07-29 21:31:04 +00:00
Richard Barry 8ad9b75810 Rename ARM_CAx_No_GIC ARM_CA5_No_GIC and add FreeRTOSConfig setting to specify the number of registers in the FPU unit. 2014-07-12 20:39:22 +00:00
Richard Barry f4a1a7d577 Add new port layer for Cortex-A devices without the means to mask interrupt priorities. 2014-07-12 19:21:04 +00:00
Richard Barry 8aa5fa3459 Make the parameters to vPortDefineHeapRegions() const.
Add additional asserts to the Keil CM3 and CM4F ports (other CM3/4 ports already updated).
Add the additional yield necessitated by the mutex held count to the case when configUSE_QUEUE_SETS is 0.
2014-07-04 13:17:21 +00:00
Richard Barry d96dc2adb0 Simply some of the alignment calculations in heap_4.c to match those used in heap_5.c.
Remove some apparently obsolete code from xTaskPriorityDisinherit() (a task cannot be both blocked and giving bac a mutex at the same time].
Update the new "mutex held count" increment and decrement functions to allow mutexes to be created before the scheduler is started.
2014-07-03 14:44:37 +00:00
Richard Barry b0ba273489 Check in the portable.h version required to use heap_5.c. 2014-07-02 10:20:35 +00:00
Richard Barry 4b26dc0614 Check in the new memory allocator that allows the heap to span multiple blocks. 2014-07-02 10:19:49 +00:00
Richard Barry 42b1688a30 Implementation of mutex held counting in tasks.c - needs optimisation before release. 2014-06-16 12:55:50 +00:00
Richard Barry 583b144bc3 Default the definition of portASSERT_IF_IN_ISR() to nothing if it is not defined.
Helper updates to allow a count of the number of mutexes held to be added.
Updates to the CCS Cortex-R4 implementation necessitated by a change in compiler semantics.
Update PIC32MX and MZ ports to assert if a non ISR safe function is called from an ISR.
2014-06-16 12:51:35 +00:00
Richard Barry b4659d8872 Add code to assert() if non ISR safe API function is called from ISR in Tasking CM4F ports - plus fix bug where the max syscall interrupt priority was used incorrectly in the Tasking CM4F port. 2014-06-15 09:24:08 +00:00
Richard Barry 113220628f Add code to assert() if non ISR safe API function is called from ISR in IAR and GCC CM3 and CM4F ports - Keil and tasking to follow. 2014-06-14 13:56:25 +00:00
Richard Barry 4723209074 Simplify the assert that checks if a non-ISR safe function is called from an ISR in the GCC Cortex-A9 port. 2014-06-13 14:08:28 +00:00
Richard Barry 8426eba8e7 Added portASSERT_IF_IN_INTERRUPT() macro to the GCC Cortex A9 port layer. 2014-06-12 16:28:56 +00:00
Richard Barry 9efb5c8b2f Check in RL78 GCC port layer now it has been verified with the fixed compiler. 2014-06-05 12:42:49 +00:00
Richard Barry 1130a53ec8 Reverse order of projdefs.h and FreeRTOSConfig.h includes in FreeRTOS.h to allow addition of pdMS_TO_TICKS() macro.
Update RXv2 GCC port to match RXv2 Renesas port.
2014-06-04 09:17:14 +00:00
Richard Barry b215310e63 Add some missing volatiles to __asm statements in the CA9 GCC port. 2014-05-19 13:14:02 +00:00
Richard Barry 0bb794301a Update version number ready for release. 2014-04-24 14:26:36 +00:00
Richard Barry 911e82a909 Add xQueueGetMutexHolder() to MPU functions. 2014-04-24 12:29:40 +00:00
Richard Barry f25503977e Event Groups: Convert the 'clear bits from ISR' function into a pended function to fix reentrancy issue.
Event Groups: Ensure the 'wait bits' and 'sync' functions don't return values that still contain some internal control bits.
2014-04-23 15:23:54 +00:00
Richard Barry 6af9b013eb Ensure xNewLib_reent is reclaimed when a task is deleted. 2014-04-09 09:07:19 +00:00