8 commits

Author	SHA1	Message	Date
Richard Barry	65f7a2dc19	Update RISC-V port to use a separate interrupt stack.	2018-12-04 01:23:41 +00:00
Richard Barry	e85ea96f78	Some efficiency improvements in Risc-V port.	2018-11-28 19:35:40 +00:00
Richard Barry	dc99300fa9	First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.	2018-11-24 20:59:07 +00:00
Richard Barry	db64297487	Provide each Risc V task with an initial mstatus register value.	2018-11-20 20:12:35 +00:00
Richard Barry	8cef339aec	Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.	2018-11-19 06:01:29 +00:00
Richard Barry	baee711cb6	Continue work on Risc V port.	2018-11-06 02:04:28 +00:00
Richard Barry	e3dc5e934b	RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet.	2018-09-27 17:25:17 +00:00
Richard Barry	2bcb1ab02b	Add trap handler to RISC-V port so there is no dependency on third party code.	2018-09-23 03:52:23 +00:00