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Author SHA1 Message Date
Kody Stribrny
54d4eeaa26
Add Vectored Interrupt Support To SiFive RISC-V Demo (#871) 
Update SiFive IAR demo to support vectored interrupts. This is a near copy of https://github.com/FreeRTOS/FreeRTOS/pull/797.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
 2022-11-09 10:34:04 -08:00
Gaurav-Aggarwal-AWS
c984275953
Update the SiFive HiFive IAR project (#804) 
Update the SiFive HiFive IAR project

1. Update to the latest toolchain.
2. Add the prints needed by CI.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
 2022-03-11 16:26:31 -08:00
Richard Barry
d2914041f8 Update the GCC and IAR SiFive HiFive rev-b demos to use the new configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS constants in place of the deprecated configCLINT_BASE_ADDRESS constant. 
Update the IAR RISC-V HiFive demo to use the latest IAR Embedded Workbench version.
 2020-01-09 02:28:45 +00:00
Richard Barry
0a29d350b1 Renamed RISC-V_RV32_SiFive_HiFive1_IAR directory to RISC-V_RV32_SiFive_HiFive1-RevB_IAR as it targets the RevB hardware. 2020-01-01 22:38:23 +00:00
Renamed from FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_IAR/RTOSDemo.ewp (Browse further)