Jonathan Cubides
0fc228dc9b
port: riscv: Add a couple of macros that store fpu context
2025-03-06 10:52:48 +01:00
Jonathan Cubides
214b8092f2
port: riscv: Create some macros for the FPU context
2025-03-06 10:52:48 +01:00
Jonathan Cubides
f38a54b42a
port: riscv: Split the number of registers and the size of the context
2025-03-06 10:52:48 +01:00
Soren Ptak
839ccb719b
Use Regex for Copyright Year in Header Check ( #1002 )
2024-02-26 09:26:42 -08:00
Soren Ptak
5fb9b50da8
CI-CD Updates ( #768 )
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* Use new version of CI-CD Actions
* Use cSpell spell check, and use ubuntu-20.04 for formatting check
* Format and spell check all files in the portable directory
* Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /*
* Use checkout@v3 instead of checkout@v2 on all jobs
---------
2023-09-05 14:24:04 -07:00
Jakub Lužný
d91cd6fd05
RISC-V: Add support for RV32E extension in GCC port ( #543 )
...
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
2022-08-30 16:49:37 -07:00
Gaurav-Aggarwal-AWS
9efca75d1e
Riscv re-factoring ( #444 )
...
* Refactor RISCV port
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Changes to make re-factoring work on ESP32-C3
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Remove alignment and place handlers in separate sections
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Correct section names
This is needed so that the assemblers correctly recognizes functions.
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Move mtvec programming to the application
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Refactor mtimer udpate code
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Move critical nesting to port layer
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Respect configTASK_RETURN_ADDRESS
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Formatting changes
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-01-26 17:55:01 -08:00
