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port: riscv: Add a couple of macros that store fpu context
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Jonathan Cubides
parent
214b8092f2
commit
0fc228dc9b
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@ -97,6 +97,97 @@
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.extern pxCriticalNesting
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/*-----------------------------------------------------------*/
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.macro portcontexSAVE_FPU_CONTEXT_INTERNAL
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/* Check if the FPU has been used, if it has not, skip the context save */
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srl t1, t0, MSTATUS_FS_USED_OFFSET
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andi t1, t1, 1
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beqz t1, 1f /* The FPU has not been used (FS either initial or clean), skip context save */
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/* Store the fp registers */
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store_f f0, portFPUREG_OFFSET(0)( sp )
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store_f f1, portFPUREG_OFFSET(1)( sp )
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store_f f2, portFPUREG_OFFSET(2)( sp )
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store_f f3, portFPUREG_OFFSET(3)( sp )
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store_f f4, portFPUREG_OFFSET(4)( sp )
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store_f f5, portFPUREG_OFFSET(5)( sp )
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store_f f6, portFPUREG_OFFSET(6)( sp )
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store_f f7, portFPUREG_OFFSET(7)( sp )
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store_f f8, portFPUREG_OFFSET(8)( sp )
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store_f f9, portFPUREG_OFFSET(9)( sp )
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store_f f10, portFPUREG_OFFSET(10)( sp )
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store_f f11, portFPUREG_OFFSET(11)( sp )
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store_f f12, portFPUREG_OFFSET(12)( sp )
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store_f f13, portFPUREG_OFFSET(13)( sp )
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store_f f14, portFPUREG_OFFSET(14)( sp )
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store_f f15, portFPUREG_OFFSET(15)( sp )
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store_f f16, portFPUREG_OFFSET(16)( sp )
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store_f f17, portFPUREG_OFFSET(17)( sp )
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store_f f18, portFPUREG_OFFSET(18)( sp )
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store_f f19, portFPUREG_OFFSET(19)( sp )
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store_f f20, portFPUREG_OFFSET(20)( sp )
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store_f f21, portFPUREG_OFFSET(21)( sp )
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store_f f22, portFPUREG_OFFSET(22)( sp )
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store_f f23, portFPUREG_OFFSET(23)( sp )
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store_f f24, portFPUREG_OFFSET(24)( sp )
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store_f f25, portFPUREG_OFFSET(25)( sp )
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store_f f26, portFPUREG_OFFSET(26)( sp )
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store_f f27, portFPUREG_OFFSET(27)( sp )
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store_f f28, portFPUREG_OFFSET(28)( sp )
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store_f f29, portFPUREG_OFFSET(29)( sp )
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store_f f30, portFPUREG_OFFSET(30)( sp )
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store_f f31, portFPUREG_OFFSET(31)( sp )
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csrr t0, fcsr
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store_x t0, portFPUREG_OFFSET(32)( sp )
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/* Mark the FPU as clean */
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li t1, ~MSTATUS_FS_MASK
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and t0, t0, t1
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li t1, MSTATUS_FS_CLEAN
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or t0, t0, t1
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csrw mstatus, t0
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1:
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.endm
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/*-----------------------------------------------------------*/
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.macro portasmRESTORE_FPU_CONTEXT_INTERNAL
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/* Restore fp registers from context */
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load_f f0, portFPUREG_OFFSET(0)( sp )
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load_f f1, portFPUREG_OFFSET(0)( sp )
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load_f f1, portFPUREG_OFFSET(1)( sp )
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load_f f2, portFPUREG_OFFSET(2)( sp )
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load_f f3, portFPUREG_OFFSET(3)( sp )
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load_f f4, portFPUREG_OFFSET(4)( sp )
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load_f f5, portFPUREG_OFFSET(5)( sp )
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load_f f6, portFPUREG_OFFSET(6)( sp )
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load_f f7, portFPUREG_OFFSET(7)( sp )
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load_f f8, portFPUREG_OFFSET(8)( sp )
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load_f f9, portFPUREG_OFFSET(9)( sp )
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load_f f10, portFPUREG_OFFSET(10)( sp )
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load_f f11, portFPUREG_OFFSET(11)( sp )
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load_f f12, portFPUREG_OFFSET(12)( sp )
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load_f f13, portFPUREG_OFFSET(13)( sp )
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load_f f14, portFPUREG_OFFSET(14)( sp )
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load_f f15, portFPUREG_OFFSET(15)( sp )
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load_f f16, portFPUREG_OFFSET(16)( sp )
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load_f f17, portFPUREG_OFFSET(17)( sp )
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load_f f18, portFPUREG_OFFSET(18)( sp )
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load_f f19, portFPUREG_OFFSET(19)( sp )
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load_f f20, portFPUREG_OFFSET(20)( sp )
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load_f f21, portFPUREG_OFFSET(21)( sp )
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load_f f22, portFPUREG_OFFSET(22)( sp )
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load_f f23, portFPUREG_OFFSET(23)( sp )
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load_f f24, portFPUREG_OFFSET(24)( sp )
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load_f f25, portFPUREG_OFFSET(25)( sp )
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load_f f26, portFPUREG_OFFSET(26)( sp )
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load_f f27, portFPUREG_OFFSET(27)( sp )
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load_f f28, portFPUREG_OFFSET(28)( sp )
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load_f f29, portFPUREG_OFFSET(29)( sp )
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load_f f30, portFPUREG_OFFSET(30)( sp )
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load_f f31, portFPUREG_OFFSET(31)( sp )
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load_x t0, portFPUREG_OFFSET(32)( sp )
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csrw fcsr, t0
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1:
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.endm
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/*-----------------------------------------------------------*/
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.macro portcontextSAVE_CONTEXT_INTERNAL
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addi sp, sp, -portCONTEXT_SIZE
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store_x x1, 1 * portWORD_SIZE( sp )
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@ -136,6 +227,9 @@ store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the criti
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csrr t0, mstatus /* Required for MPIE bit. */
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store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
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#ifdef portasmSTORE_FPU_CONTEXT
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portcontexSAVE_FPU_CONTEXT_INTERNAL
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#endif /* ifdef portasmSTORE_FPU_CONTEXT */
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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@ -176,6 +270,10 @@ csrw mepc, t0
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/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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portasmRESTORE_ADDITIONAL_REGISTERS
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#ifdef portasmSTORE_FPU_CONTEXT
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portasmRESTORE_FPU_CONTEXT_INTERNAL
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#endif /* ifdef portasmSTORE_FPU_CONTEXT */
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/* Load mstatus with the interrupt enable bits used by the task. */
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load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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