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Regenerate the EthernetLite hardware (MicroBlaze) in an attempt to get Rx working.

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This commit is contained in:
Richard Barry 2011-07-27 12:08:38 +00:00
parent 1019db5850
commit fab6050ab8
11 changed files with 17198 additions and 12 deletions
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Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.bit Normal file
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<!DOCTYPE html PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/SVG/DTD/svg10.dtd">
<HTML>
<HEAD>
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
<TITLE>XPS Project Report</TITLE>
</HEAD>
<HEAD><TITLE>XPS Project Report</TITLE></HEAD>
<FRAMESET COLS="20%,80%" BORDER="0" FRAMESPACING="0">
<FRAME SRC="system_toc.html" MARGINWIDTH="0" MARINHEIGHT="0" FRAMEBORDER="NO" BORDER="NO" NAME="system_toc" SCROLLING="YES">
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Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm Normal file
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// BMM LOC annotation file.
//
// Release 13.1 - Data2MEM O.40d, build 1.9 Aug 19, 2010
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0', ID 100, memory map.
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0' address space 'microblaze_0_bram_block_combined' 0x00000000:0x00001FFF (8 KBytes).
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_SPACE microblaze_0_bram_block_combined RAMB16 [0x00000000:0x00001FFF]
BUS_BLOCK
microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_0 [31:24] INPUT = microblaze_0_bram_block_combined_0.mem PLACED = X1Y30;
microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_1 [23:16] INPUT = microblaze_0_bram_block_combined_1.mem PLACED = X1Y32;
microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_2 [15:8] INPUT = microblaze_0_bram_block_combined_2.mem PLACED = X0Y30;
microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_3 [7:0] INPUT = microblaze_0_bram_block_combined_3.mem PLACED = X0Y32;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

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<HTML>
<HEAD>
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
<TITLE>Table of Contents</TITLE>
<BASE target="system_main">
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<BODY class="main_body"><TABLE BGCOLOR="#FFFFFF" WIDTH="200" COLS="1" cellspacing="0" cellpadding="0" border="0"><TD COLSPAN="1" VALIGN="Top">
<A HREF="system_main.html#ANCHOR_OVERVIEW" style="text-decoration:none"><SPAN style="color:#000000; font: bold 16px Verdana Arial,Helvetica,sans-serif">Overview</SPAN></A><BR><A HREF="system_main.html#ANCHOR_BLOCKDIAGRAM" style="text-decoration:none"><SPAN style="color:#000000; font: bold 16px Verdana Arial,Helvetica,sans-serif">Block Diagram</SPAN></A><BR><A HREF="system_main.html#ANCHOR_EXTERNALPORTS" style="text-decoration:none"><SPAN style="color:#000000; font: bold 16px Verdana Arial,Helvetica,sans-serif">External Ports</SPAN></A><BR><DIV class="trigger" onClick="showBranch('Processors'); swapBranchImg('BranchImg_Processors');">
<IMG src="imgs/IMG_openBranch.png" border="0" id="BranchImg_Processors"><SPAN style="color:#000000; font: bold 16px Verdana ArialHelvetica,sans-serif"> Processor</SPAN>
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<SPAN class="branch" id="Processors"><A HREF="system_main.html#ANCHOR_microblaze_0" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   microblaze_0</SPAN></A><BR></SPAN><DIV class="trigger" onClick="showBranch('Debuggers'); swapBranchImg('BranchImg_Debuggers');">
<IMG src="imgs/IMG_openBranch.png" border="0" id="BranchImg_Debuggers"><SPAN style="color:#000000; font: bold 16px Verdana ArialHelvetica,sans-serif"> Debuggers</SPAN>
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<SPAN class="branch" id="Interrupt_Cntlrs"><A HREF="system_main.html#ANCHOR_microblaze_0_intc" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   microblaze_0_intc</SPAN></A><BR></SPAN><DIV class="trigger" onClick="showBranch('Busses'); swapBranchImg('BranchImg_Busses');">
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<SPAN class="branch" id="Busses"><A HREF="system_main.html#ANCHOR_axi4_0" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   axi4_0</SPAN></A><BR><A HREF="system_main.html#ANCHOR_axi4lite_0" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   axi4lite_0</SPAN></A><BR><A HREF="system_main.html#ANCHOR_microblaze_0_dlmb" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   microblaze_0_dlmb</SPAN></A><BR><A HREF="system_main.html#ANCHOR_microblaze_0_ilmb" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   microblaze_0_ilmb</SPAN></A><BR></SPAN><DIV class="trigger" onClick="showBranch('Memory'); swapBranchImg('BranchImg_Memory');">
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</DIV>
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<SPAN class="branch" id="Peripherals"><A HREF="system_main.html#ANCHOR_Ethernet_Lite" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   Ethernet_Lite</SPAN></A><BR><A HREF="system_main.html#ANCHOR_LEDs_4Bits" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   LEDs_4Bits</SPAN></A><BR><A HREF="system_main.html#ANCHOR_Push_Buttons_4Bits" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   Push_Buttons_4Bits</SPAN></A><BR><A HREF="system_main.html#ANCHOR_RS232_Uart_1" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   RS232_Uart_1</SPAN></A><BR><A HREF="system_main.html#ANCHOR_axi_timer_0" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   axi_timer_0</SPAN></A><BR></SPAN><DIV class="trigger" onClick="showBranch('IP'); swapBranchImg('BranchImg_Ips');">
<IMG src="imgs/IMG_openBranch.png" border="0" id="BranchImg_Ips"><SPAN style="color:#000000; font: bold 16px Verdana Arial,Helvetica,sans-serif"> IP</SPAN>
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<SPAN class="branch" id="IP"><A HREF="system_main.html#ANCHOR_clock_generator_0" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   clock_generator_0</SPAN></A><BR><A HREF="system_main.html#ANCHOR_proc_sys_reset_0" style="text-decoration:none"><SPAN style="color:#AA0017; font: italic 14px Verdana Arial,Helvetica,sans-serif">   proc_sys_reset_0</SPAN></A><BR></SPAN><A HREF="system_main.html#ANCHOR_TIMINGINFO" style="text-decoration:none"><SPAN style="color:#000000; font: bold 16px Verdana Arial,Helvetica,sans-serif">Timing Information</SPAN></A><BR>
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Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs
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@ -23,10 +23,10 @@
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_SYS_RST_PRESENT</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 228</arg>
</msg>
<msg type="info" file="EDK" num="740" delta="new" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_i_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it.
<msg type="info" file="EDK" num="740" delta="old" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_i_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it.
</msg>
<msg type="info" file="EDK" num="740" delta="new" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_d_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it.
<msg type="info" file="EDK" num="740" delta="old" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_d_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it.
</msg>
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_ethernetlite</arg>, INSTANCE: <arg fmt="%s" index="2">Ethernet_Lite</arg> - <arg fmt="%s" index="3">This design requires design constraints to guarantee performance.
@ -133,7 +133,7 @@ The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethe
<msg type="info" file="EDK" num="0" delta="new" >The following instances are synthesized with <arg fmt="%s" index="1">XST</arg>. The MPD option IMP_NETLIST=TRUE indicates that a NGC file is to be produced using <arg fmt="%s" index="2">XST</arg> synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
</msg>
<msg type="info" file="EDK" num="3509" delta="new" >NCF files should not be modified as they will be regenerated.
<msg type="info" file="EDK" num="3509" delta="old" >NCF files should not be modified as they will be regenerated.
If any constraint needs to be overridden, this should be done by modifying the data/<arg fmt="%s" index="1">system</arg>.ucf file.
</msg>

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Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport
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<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2011-06-17T21:48:17</DateModified>
<DateModified>2011-07-27T11:10:44</DateModified>
<ModuleName>system</ModuleName>
<SummaryTimeStamp>2011-06-17T21:48:16</SummaryTimeStamp>
<SummaryTimeStamp>2011-07-27T11:10:42</SummaryTimeStamp>
<SavedFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport</SavedFilePath>
<FilterFile>filter.filter</FilterFile>
<SavedFilterFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise</SavedFilterFilePath>

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Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml
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<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Fri Jun 17 21:48:16 2011">
<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Wed Jul 27 11:10:40 2011">
<SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp" SPEEDGRADE="-3"/>

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Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui
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@ -15,9 +15,10 @@
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
<SET ID="RS232_Uart_1" IS_EXPANDED="TRUE"/>
<SET ID="Ethernet_Lite" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS>
<VARIABLE ID="RS232_Uart_1"/>
<VARIABLE ID="Ethernet_Lite"/>
</SELECTIONS>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
@ -36,7 +37,7 @@
<VARIABLE ID="LEDs_4Bits" ROW_INDEX="12"/>
<VARIABLE ID="Push_Buttons_4Bits" ROW_INDEX="13"/>
<VARIABLE ID="MCB_DDR3" ROW_INDEX="8"/>
<VARIABLE ID="Ethernet_Lite" ROW_INDEX="11"/>
<VARIABLE ID="Ethernet_Lite" IS_EXPANDED="TRUE" ROW_INDEX="11"/>
<VARIABLE ID="axi_timer_0" ROW_INDEX="14"/>
<VARIABLE ID="microblaze_0_intc" ROW_INDEX="10"/>
</SEQUENCES>
@ -84,7 +85,7 @@
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
<HEADERS HSCROLL="0" VSCROLL="0">
<HEADERS HSCROLL="0" VSCROLL="144">
<VARIABLE COL_INDEX="0" COL_WIDTH="217" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="652" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
@ -100,11 +101,17 @@
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
<SET ID="microblaze_0" IS_EXPANDED="TRUE"/>
<SET ID="RS232_Uart_1" IS_EXPANDED="TRUE"/>
<SET ID="Push_Buttons_4Bits" IS_EXPANDED="TRUE"/>
<SET ID="Ethernet_Lite" IS_EXPANDED="TRUE">
<SET ID="ethernet_0" IS_EXPANDED="TRUE"/>
</SET>
<SET ID="microblaze_0_intc" IS_EXPANDED="TRUE">
<SET ID="S_AXI" IS_EXPANDED="TRUE"/>
</SET>
<STATUS>
<SELECTIONS/>
<SELECTIONS>
<VARIABLE ID="PHY_MDIO_I" INSTANCE="Ethernet_Lite" PARENT="ethernet_0"/>
</SELECTIONS>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="ExternalPorts" ROW_INDEX="0"/>
@ -121,9 +128,9 @@
<VARIABLE ID="debug_module" ROW_INDEX="10"/>
<VARIABLE ID="RS232_Uart_1" IS_EXPANDED="TRUE" ROW_INDEX="16"/>
<VARIABLE ID="LEDs_4Bits" ROW_INDEX="13"/>
<VARIABLE ID="Push_Buttons_4Bits" ROW_INDEX="14"/>
<VARIABLE ID="Push_Buttons_4Bits" IS_EXPANDED="TRUE" ROW_INDEX="14"/>
<VARIABLE ID="MCB_DDR3" ROW_INDEX="9"/>
<VARIABLE ID="Ethernet_Lite" ROW_INDEX="12"/>
<VARIABLE ID="Ethernet_Lite" IS_EXPANDED="TRUE" ROW_INDEX="12"/>
<VARIABLE ID="axi_timer_0" ROW_INDEX="15"/>
<VARIABLE ID="microblaze_0_intc" IS_EXPANDED="TRUE" ROW_INDEX="11"/>
</SEQUENCES>