XPS Project Report

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.bit b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.bit new file mode 100644 index 000000000..be3fae52c Binary files /dev/null and b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.bit differ diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.html new file mode 100644 index 000000000..1dda8a75f --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.html @@ -0,0 +1,12 @@ + + + + +XPS Project Report + +XPS Project Report + + + + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.xml b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.xml new file mode 100644 index 000000000..ec302a4fa --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system.xml @@ -0,0 +1,6258 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Interconnect + AXI4 Memory-Mapped Interconnect + + + + + + + Family + + + Base Family + + + Number of Slave Slots + + + Number of Master Slots + + + AXI ID Widgth + + + AXI Address Widgth + + + AXI Data Maximum Width + + + Slave AXI Data Width + + + Master AXI Data Width + + + Interconnect Crossbar Data Width + + + AXI Protocol + + + Master AXI Protocol + + + Master AXI Base Address + + + Master AXI High Address + + + Slave AXI Base ID + + + Slave AXI Thread ID Width + + + Slave AXI Is Interconnect + + + Slave AXI ACLK Ratio + + + Slvave AXI Is ACLK ASYNC + + + Master AXI ACLK Ratio + + + Master AXI Is ACLK ASYNC + + + Interconnect Crossbar ACLK Frequency Ratio + + + Slave AXI Supports Write + + + Slave AXI Supports Read + + + Master AXI Supports Write + + + Master AXI Supports Read + + + Propagate USER Signals + + + AWUSER Signal Width + + + ARUSER Signal Width + + + WUSER Signal Width + + + RUSER Signal Width + + + BUSER Signal Width + + + AXI Connectivity + + + Slave AXI Single Thread + + + Master AXI Supports Reordering + + + Master generates narrow bursts + + + Slave accepts narrow bursts + + + Slave AXI Write Acceptance + + + Slave AXI Read Acceptance + + + Master AXI Write Issuing + + + Master AXI Read Issuing + + + Slave AXI ARB Priority + + + Master AXI Secure + + + Master AXI Write FIFO Depth + + + Slave AXI Write FIFO Type + + + Slave AXI Write FIFO Delay + + + Slave AXI Read FIFO Depth + + + Slave AXI Read FIFO Type + + + Slave AXI Read FIFO Delay + + + Master AXI Write FIFO Depth + + + Master AXI Write FIFO Type + + + Master AXI Write FIFO Delay + + + Master AXI Read FIFO Depth + + + Master AXI Read FIFO Type + + + Master AXI Read FIFO Delay + + + Slave AXI AW Register + + + Slave AXI AR Register + + + Slave AXI W Register + + + Slave AXI R Register + + + Slave AXI B Register + + + Master AXI AW Register + + + Master AXI AR Register + + + Master AXI W Register + + + Master AXI R Register + + + Master AXI B Register + + + C_INTERCONNECT_R_REGISTER + + + Interconnect Architecture + + + Use Diagnostic Slave Port + + + Generate Interrupts + + + Check for transaction errors (DECERR) + + + Slave AXI CTRL Protocol + + + Slave AXI CTRL Address Width + + + Slave AXI CTRL Data Width + + + Diagnostic Slave Port Base Address + + + Diagnostic Slave Port High Address + + + Simulation debug + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Interconnect + AXI4 Memory-Mapped Interconnect + + + + + + + Family + + + Base Family + + + Number of Slave Slots + + + Number of Master Slots + + + AXI ID Widgth + + + AXI Address Widgth + + + AXI Data Maximum Width + + + Slave AXI Data Width + + + Master AXI Data Width + + + Interconnect Crossbar Data Width + + + AXI Protocol + + + Master AXI Protocol + + + Master AXI Base Address + + + Master AXI High Address + + + Slave AXI Base ID + + + Slave AXI Thread ID Width + + + Slave AXI Is Interconnect + + + Slave AXI ACLK Ratio + + + Slvave AXI Is ACLK ASYNC + + + Master AXI ACLK Ratio + + + Master AXI Is ACLK ASYNC + + + Interconnect Crossbar ACLK Frequency Ratio + + + Slave AXI Supports Write + + + Slave AXI Supports Read + + + Master AXI Supports Write + + + Master AXI Supports Read + + + Propagate USER Signals + + + AWUSER Signal Width + + + ARUSER Signal Width + + + WUSER Signal Width + + + RUSER Signal Width + + + BUSER Signal Width + + + AXI Connectivity + + + Slave AXI Single Thread + + + Master AXI Supports Reordering + + + Master generates narrow bursts + + + Slave accepts narrow bursts + + + Slave AXI Write Acceptance + + + Slave AXI Read Acceptance + + + Master AXI Write Issuing + + + Master AXI Read Issuing + + + Slave AXI ARB Priority + + + Master AXI Secure + + + Master AXI Write FIFO Depth + + + Slave AXI Write FIFO Type + + + Slave AXI Write FIFO Delay + + + Slave AXI Read FIFO Depth + + + Slave AXI Read FIFO Type + + + Slave AXI Read FIFO Delay + + + Master AXI Write FIFO Depth + + + Master AXI Write FIFO Type + + + Master AXI Write FIFO Delay + + + Master AXI Read FIFO Depth + + + Master AXI Read FIFO Type + + + Master AXI Read FIFO Delay + + + Slave AXI AW Register + + + Slave AXI AR Register + + + Slave AXI W Register + + + Slave AXI R Register + + + Slave AXI B Register + + + Master AXI AW Register + + + Master AXI AR Register + + + Master AXI W Register + + + Master AXI R Register + + + Master AXI B Register + + + C_INTERCONNECT_R_REGISTER + + + Interconnect Architecture + + + Use Diagnostic Slave Port + + + Generate Interrupts + + + Check for transaction errors (DECERR) + + + Slave AXI CTRL Protocol + + + Slave AXI CTRL Address Width + + + Slave AXI CTRL Data Width + + + Diagnostic Slave Port Base Address + + + Diagnostic Slave Port High Address + + + Simulation debug + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + MicroBlaze + The MicroBlaze 32 bit soft processor + + + + + + + + + + + + + Enable Fault Tolerance Support + + + + + Select implementation to optimize area (with lower instruction throughput) + + + + Select Bus Interfaces + + + Select Stream Interfaces + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Enable Additional Machine Status Register Instructions + + + Enable Pattern Comparator + + + Enable Barrel Shifter + + + Enable Integer Divider + + + Enable Integer Multiplier + + + Enable Floating Point Unit + + + Enable Unaligned Data Exception + + + Enable Illegal Instruction Exception + + + Enable Instruction-side AXI Exception + + + Enable Data-side AXI Exception + + + Enable Instruction-side PLB Exception + + + Enable Data-side PLB Exception + + + Enable Integer Divide Exception + + + Enable Floating Point Unit Exceptions + + + Enable Stream Exception + + + <qt>Enable stack protection</qt> + + + Specifies Processor Version Register + + + Specify USER1 Bits in Processor Version Register + + + Specify USER2 Bits in Processor Version Registers + + + Enable MicroBlaze Debug Module Interface + + + Number of PC Breakpoints + + + Number of Read Address Watchpoints + + + Number of Write Address Watchpoints + + + Sense Interrupt on Edge vs. Level + + + Sense Interrupt on Rising vs. Falling Edge + + + Specify Reset Value for Select MSR Bits + + + <qt>Generate Illegal Instruction Exception for NULL Instruction</qt> + + + Number of Stream Links + + + + Enable Additional Stream Instructions + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + I-Cache Base Address + + + I-Cache High Address + + + Enable Instruction Cache + + + Enable I-Cache Writes + + + + Size of the I-Cache in Bytes + + + + Instruction Cache Line Length + + + Use Cache Links for All I-Cache Memory Accesses + + + + Number of I-Cache Victims + + + Number of I-Cache Streams + + + Use Distributed RAM for I-Cache Tags + + + + + + + + + + + + + + + + + + + + D-Cache Base Address + + + D-Cache High Address + + + Enable Data Cache + + + Enable D-Cache Writes + + + + Size of D-Cache in Bytes + + + + Data Cache Line Length + + + Use Cache Links for All D-Cache Memory Accesses + + + + Enable Write-back Storage Policy + + + Number of D-Cache Victims + + + Use Distributed RAM for D-Cache Tags + + + + + + + + + + + + + + + + + + + + + + Memory Management + + + Data Shadow Translation Look-Aside Buffer Size + + + Instruction Shadow Translation Look-Aside Buffer Size + + + Enable Access to Memory Management Special Registers + + + Number of Memory Protection Zones + + + Privileged Instructions + + + + + + Enable Branch Target Cache + + + Branch Target Cache Size + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Local Memory Bus (LMB) 1.0 + 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' + + + + + + + Number of Bus Slaves + + + LMB Address Bus Width + + + LMB Data Bus Width + + + Active High External Reset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Local Memory Bus (LMB) 1.0 + 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' + + + + + + + Number of Bus Slaves + + + LMB Address Bus Width + + + LMB Data Bus Width + + + Active High External Reset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMB BRAM Controller + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + + + + + LMB BRAM Base Address + + + LMB BRAM High Address + + + + LMB Address Decode Mask + + + LMB Address Bus Width + + + LMB Data Bus Width + + + Error Correction Code + + + Select Interconnect + + + Fault Inject Registers + + + Correctable Error First Failing Register + + + Uncorrectable Error First Failing Register + + + ECC Status and Control Register + + + ECC On/Off Register + + + ECC On/Off Reset Value + + + Correctable Error Counter Register Width + + + Write Access setting + + + Base Address for PLB Interface + + + High Address for PLB Interface + + + PLB Address Bus Width + + + PLB Data Bus Width + + + PLB Slave Uses P2P Topology + + + Master ID Bus Width of PLB + + + Number of PLB Masters + + + PLB Slave is Capable of Bursts + + + Native Data Bus Width of PLB Slave + + + Frequency of PLB Slave + + + S_AXI_CTRL Clock Frequency + + + S_AXI_CTRL Base Address + + + S_AXI_CTRL High Address + + + S_AXI_CTRL Address Width + + + S_AXI_CTRL Data Width + + + S_AXI_CTRL Protocol + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMB BRAM Controller + Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus + + + + + + + LMB BRAM Base Address + + + LMB BRAM High Address + + + + LMB Address Decode Mask + + + LMB Address Bus Width + + + LMB Data Bus Width + + + Error Correction Code + + + Select Interconnect + + + Fault Inject Registers + + + Correctable Error First Failing Register + + + Uncorrectable Error First Failing Register + + + ECC Status and Control Register + + + ECC On/Off Register + + + ECC On/Off Reset Value + + + Correctable Error Counter Register Width + + + Write Access setting + + + Base Address for PLB Interface + + + High Address for PLB Interface + + + PLB Address Bus Width + + + PLB Data Bus Width + + + PLB Slave Uses P2P Topology + + + Master ID Bus Width of PLB + + + Number of PLB Masters + + + PLB Slave is Capable of Bursts + + + Native Data Bus Width of PLB Slave + + + Frequency of PLB Slave + + + S_AXI_CTRL Clock Frequency + + + S_AXI_CTRL Base Address + + + S_AXI_CTRL High Address + + + S_AXI_CTRL Address Width + + + S_AXI_CTRL Data Width + + + S_AXI_CTRL Protocol + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Block RAM (BRAM) Block + The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. + + + + + + + Size of BRAM(s) in Bytes + + + Data Width of Port A and B + + + Address Width of Port A and B + + + Number of Byte Write Enables + + + Device Family + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Processor System Reset Module + Reset management module + + + + + + + Device Subfamily + + + Number of Clocks Before Input Change is Recognized On The External Reset Input + + + Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input + + + External Reset Active High + + + Auxiliary Reset Active High + + + Number of Bus Structure Reset Registered Outputs + + + Number of Peripheral Reset Registered Outputs + + + Number of Active Low Interconnect Reset Registered Outputs + + + Number of Active Low Peripheral Reset Registered Outputs + + + Device Family + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Clock Generator + Clock generator for processor system. + + + + + + + Family + + + Device + + + Package + + + Speed Grade + + + Input Clock Frequency (Hz) + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Varaible Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Varaible Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase + + + Required Frequency (Hz) + + + Clock Deskew + + + Required Frequency (Hz) + + + Required Phase + + + Required Group + + + Buffered + + + Variable Phase Shift + + + + Clock Primitive Feedback Buffer + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + MicroBlaze Debug Module (MDM) + Debug module for MicroBlaze Soft Processor. + + + + + + + Device Family + + + Specifies the JTAG user-defined register used + + + Specifies the Bus Interface for the JTAG UART + + + Base Address + + + High Address + + + PLB Address Bus Width + + + PLB Data Bus Width + + + PLB Slave Uses P2P Topology + + + Master ID Bus Width of PLB + + + Number of PLB Masters + + + Native Data Bus Width of PLB Slave + + + PLB Slave is Capable of Bursts + + + Number of MicroBlaze debug ports + + + Enable JTAG UART + + + AXI Address Width + + + AXI Data Width + + + AXI4LITE protocal + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI UART (Lite) + Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI. + + + + + + + Device Family + + + AXI Clock Frequency + + + AXI Base Address + + + AXI High Address + + + AXI Address Width + + + AXI Data Width + + + UART Lite Baud Rate + Baud Rate + + + Number of Data Bits in a Serial Frame + Data Bits + + + Use Parity + + + Parity Type + + + AXI4LITE protocol + + + + + + + + + + Serial Data Out + + + Serial Data In + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI General Purpose IO + General Purpose Input/Output (GPIO) core for the AXI bus. + + + + + + + Device Family + + + AXI Base Address + + + AXI High Address + + + AXI Address Width + + + AXI Data Width + + + GPIO Data Channel Width + GPIO Data Width + + + GPIO2 Data Channel Width + + + Channel 1 is Input Only + + + Channel 2 is Input Only + + + GPIO Supports Interrupts + + + Channel 1 Data Out Default Value + + + Channel 1 Tri-state Default Value + + + Enable Channel 2 + + + Channel 2 Data Out Default Value + + + Channel 2 Tri-state Default Value + + + AXI4LITE protocol + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GPIO1 Data IO + + + GPIO2 Data IO + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI General Purpose IO + General Purpose Input/Output (GPIO) core for the AXI bus. + + + + + + + Device Family + + + AXI Base Address + + + AXI High Address + + + AXI Address Width + + + AXI Data Width + + + GPIO Data Channel Width + GPIO Data Width + + + GPIO2 Data Channel Width + + + Channel 1 is Input Only + + + Channel 2 is Input Only + + + GPIO Supports Interrupts + + + Channel 1 Data Out Default Value + + + Channel 1 Tri-state Default Value + + + Enable Channel 2 + + + Channel 2 Data Out Default Value + + + Channel 2 Tri-state Default Value + + + AXI4LITE protocol + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GPIO1 Data IO + + + GPIO2 Data IO + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI S6 Memory Controller(DDR/DDR2/DDR3) + Spartan-6 memory controller + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI 10/100 Ethernet MAC Lite + 'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation' + + + + + + + AXI protocol selection + + + Device Family + + + Ethernetlite Base Address + + + Ethernetlite High Address + + + AXI System Clock Period + + + AXI Interface Addresses Width + + + AXI Interface Data Width + + + Width of ID Bus on AXI4 + + + Include MII Management Module + + + Include Global Buffers for PHY clocks + + + Include Internal Loopback + + + Duplex Mode + + + Include Second Transmitter Buffer + + + Include Second Receiver Buffer + + + Include PHY I/O Constraints + + + Interconnect write acceptance + + + Interconnect read acceptance + + + Support Narrow Burst on AXI4 + + + + + + + + + + Ethernet PHY Management Data + + + Ethernet PHY Management Clock + + + Ethernet Transmit Data Output + + + Ethernet Transmit Enable + + + Ethernet Transmit Clock Input + + + Ethernet Collision Input + + + Ethernet Receive Data Input + + + Ethernet Receive Error Input + + + Ethernet Receive Clock Input + + + Ethernet Carrier Sense Input + + + Ethernet Receive Data Valid + + + Ethernet PHY Reset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Timer/Counter + Timer counter with AXI interface + + + + + + + AXI4LITE protocol + + + Device Family + + + The Width of Counter in Timer + Count Width + + + Only One Timer is present + + + TRIG0 Active Level + + + TRIG1 Active Level + + + GEN0 Active Level + + + GEN1 Active Level + + + AXI Base Address + + + AXI High Address + + + AXI Address Width + + + AXI Data Width + + + + + + + + + + + + Capture Trig 0 + + + Capture Trig 1 + + + Generate Out 0 + + + Generate Out 1 + + + Pulse Width Modulation 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Interrupt Controller + intc core attached to the AXI + + + + + + + Device Family + + + AXI Base Address + + + AXI High Address + + + AXI Address Width + + + AXI Data Width + + + Number of Interrupt Inputs + + + Type of Interrupt for Each Input + + + Type of Each Edge Senstive Interrupt + + + Type of Each Level Sensitive Interrupt + + + Support IPR + + + Support SIE + + + Support CIE + + + Support IVR + + + IRQ Output Use Level + + + The Sense of IRQ Output + + + AXI4LITE protocol + + + + + + + + + + Interrupt Request Output + + + + + + + + + + Interrupt Inputs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm new file mode 100644 index 000000000..ca5622cf7 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm @@ -0,0 +1,32 @@ +// BMM LOC annotation file. +// +// Release 13.1 - Data2MEM O.40d, build 1.9 Aug 19, 2010 +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. + + +/////////////////////////////////////////////////////////////////////////////// +// +// Processor 'microblaze_0', ID 100, memory map. +// +/////////////////////////////////////////////////////////////////////////////// + +ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100 + + + /////////////////////////////////////////////////////////////////////////////// + // + // Processor 'microblaze_0' address space 'microblaze_0_bram_block_combined' 0x00000000:0x00001FFF (8 KBytes). + // + /////////////////////////////////////////////////////////////////////////////// + + ADDRESS_SPACE microblaze_0_bram_block_combined RAMB16 [0x00000000:0x00001FFF] + BUS_BLOCK + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_0 [31:24] INPUT = microblaze_0_bram_block_combined_0.mem PLACED = X1Y30; + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_1 [23:16] INPUT = microblaze_0_bram_block_combined_1.mem PLACED = X1Y32; + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_2 [15:8] INPUT = microblaze_0_bram_block_combined_2.mem PLACED = X0Y30; + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_3 [7:0] INPUT = microblaze_0_bram_block_combined_3.mem PLACED = X0Y32; + END_BUS_BLOCK; + END_ADDRESS_SPACE; + +END_ADDRESS_MAP; + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html new file mode 100644 index 000000000..0864e1f1c --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html @@ -0,0 +1,5397 @@ + + + + +XPS Project Report + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Printable Version

+

Overview

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Resources Used
1	MicroBlaze
2	AXI Interconnect
2	Local Memory Bus (LMB) 1.0
1	Block RAM (BRAM) Block
2	LMB BRAM Controller
1	AXI S6 Memory Controller(DDR/DDR2/DDR3)
1	Processor System Reset Module
1	Clock Generator
1	MicroBlaze Debug Module (MDM)
1	AXI UART (Lite)
2	AXI General Purpose IO
1	AXI 10/100 Ethernet MAC Lite
1	AXI Timer/Counter
1	AXI Interrupt Controller

+ + + + + + + + + + + + + + +

Specifics
Generated	Wed Jul 27 11:49:42 2011
EDK Version	13.1
Device Family	spartan6
Device	xc6slx45tfgg484-3

+

+
+ + +

Block Diagram	TOP

+

BlockDiagram

+

+ + + +

External Ports	TOP

+
+ + + + + + +

+ These are the external ports defined in the MHS file. +

+Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK)
INTR  indicates Interrupt ports,(SIGIS = INTR)
RESET  indicates Reset ports, (SIGIS = RST)
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

#	NAME		DIR	[LSB:MSB]	SIG		ATTRIBUTES
+SHARED +	RESET		I	1	RESET		RESET
+Ethernet_Lite +	Ethernet_Lite_COL		I	1	Ethernet_Lite_COL
+Ethernet_Lite +	Ethernet_Lite_CRS		I	1	Ethernet_Lite_CRS
+Ethernet_Lite +	Ethernet_Lite_RXD		I	0:3	Ethernet_Lite_RXD
+Ethernet_Lite +	Ethernet_Lite_RX_CLK		I	1	Ethernet_Lite_RX_CLK
+Ethernet_Lite +	Ethernet_Lite_RX_DV		I	1	Ethernet_Lite_RX_DV
+Ethernet_Lite +	Ethernet_Lite_RX_ER		I	1	Ethernet_Lite_RX_ER
+Ethernet_Lite +	Ethernet_Lite_TX_CLK		I	1	Ethernet_Lite_TX_CLK
+Ethernet_Lite +	Ethernet_Lite_MDIO		IO	1	Ethernet_Lite_MDIO
+Ethernet_Lite +	Ethernet_Lite_MDC		O	1	Ethernet_Lite_MDC
+Ethernet_Lite +	Ethernet_Lite_PHY_RST_N		O	1	Ethernet_Lite_PHY_RST_N
+Ethernet_Lite +	Ethernet_Lite_TXD		O	0:3	Ethernet_Lite_TXD
+Ethernet_Lite +	Ethernet_Lite_TX_EN		O	1	Ethernet_Lite_TX_EN
+LEDs_4Bits +	LEDs_4Bits_TRI_O		O	3:0	LEDs_4Bits_TRI_O
+MCB_DDR3 +	mcbx_dram_dq		IO	0:15	mcbx_dram_dq
+MCB_DDR3 +	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
+MCB_DDR3 +	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
+MCB_DDR3 +	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
+MCB_DDR3 +	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
+MCB_DDR3 +	rzq		IO	1	rzq
+MCB_DDR3 +	zio		IO	1	zio
+MCB_DDR3 +	mcbx_dram_addr		O	0:12	mcbx_dram_addr
+MCB_DDR3 +	mcbx_dram_ba		O	0:2	mcbx_dram_ba
+MCB_DDR3 +	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
+MCB_DDR3 +	mcbx_dram_cke		O	1	mcbx_dram_cke
+MCB_DDR3 +	mcbx_dram_clk		O	1	mcbx_dram_clk
+MCB_DDR3 +	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
+MCB_DDR3 +	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
+MCB_DDR3 +	mcbx_dram_ldm		O	1	mcbx_dram_ldm
+MCB_DDR3 +	mcbx_dram_odt		O	1	mcbx_dram_odt
+MCB_DDR3 +	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
+MCB_DDR3 +	mcbx_dram_udm		O	1	mcbx_dram_udm
+MCB_DDR3 +	mcbx_dram_we_n		O	1	mcbx_dram_we_n
+Push_Buttons_4Bits +	Push_Buttons_4Bits_TRI_I		I	0:3	Push_Buttons_4Bits_TRI_I
+RS232_Uart_1 +	RS232_Uart_1_sin		I	1	RS232_Uart_1_sin
+RS232_Uart_1 +	RS232_Uart_1_sout		O	1	RS232_Uart_1_sout
+clock_generator_0 +	CLK_N		I	1	CLK		CLK
+clock_generator_0 +	CLK_P		I	1	CLK		CLK

+

+

+ + +

Processors	TOP

+
+ + +

+ + + + + + + + + +

+microblaze_0 + MicroBlaze
The MicroBlaze 32 bit soft processor

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
microblaze	8.10.a	IP

+

+

microblaze_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	MB_RESET		I	1	proc_sys_reset_0_MB_Reset
1	CLK		I	1	clk_100_0000MHzPLL0
2	INTERRUPT		I	1	microblaze_0_interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
M_AXI_DP	MASTER	AXI	axi4lite_0			7 Peripherals.
M_AXI_DC	MASTER	AXI	axi4_0			MCB_DDR3
M_AXI_IC	MASTER	AXI	axi4_0			MCB_DDR3
DLMB	MASTER	LMB	microblaze_0_dlmb			microblaze_0_d_bram_ctrl
ILMB	MASTER	LMB	microblaze_0_ilmb			microblaze_0_i_bram_ctrl
DEBUG	TARGET	XIL_MBDEBUG3	microblaze_0_debug			debug_module

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_SCO	0
C_FREQ	0
C_DATA_SIZE	32
C_DYNAMIC_BUS_SIZING	1
C_FAMILY	virtex5
C_INSTANCE	microblaze
C_FAULT_TOLERANT	0
C_ECC_USE_CE_EXCEPTION	0
C_ENDIANNESS	0
C_AREA_OPTIMIZED	0
C_OPTIMIZATION	0
C_INTERCONNECT	2
C_STREAM_INTERCONNECT	0
C_DPLB_DWIDTH	32
C_DPLB_NATIVE_DWIDTH	32
C_DPLB_BURST_EN	0
C_DPLB_P2P	0
C_IPLB_DWIDTH	32
C_IPLB_NATIVE_DWIDTH	32
C_IPLB_BURST_EN	0
C_IPLB_P2P	0
C_M_AXI_DP_SUPPORTS_THREADS	0
C_M_AXI_DP_THREAD_ID_WIDTH	1
C_M_AXI_DP_SUPPORTS_READ	1
C_M_AXI_DP_SUPPORTS_WRITE	1
C_M_AXI_DP_SUPPORTS_NARROW_BURST	0
C_M_AXI_DP_DATA_WIDTH	32
C_M_AXI_DP_ADDR_WIDTH	32
C_M_AXI_DP_PROTOCOL	AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS	0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING	1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING	1
C_M_AXI_IP_SUPPORTS_THREADS	0
C_M_AXI_IP_THREAD_ID_WIDTH	1
C_M_AXI_IP_SUPPORTS_READ	1
C_M_AXI_IP_SUPPORTS_WRITE	0
C_M_AXI_IP_SUPPORTS_NARROW_BURST	0
C_M_AXI_IP_DATA_WIDTH	32
C_M_AXI_IP_ADDR_WIDTH	32
C_M_AXI_IP_PROTOCOL	AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING	1
C_D_AXI	0
C_D_PLB	0
C_D_LMB	1
C_I_AXI	0
C_I_PLB	0
C_I_LMB	1
C_USE_MSR_INSTR	1
C_USE_PCMP_INSTR	1
C_USE_BARREL	1
C_USE_DIV	1
C_USE_HW_MUL	1
C_USE_FPU	1
C_UNALIGNED_EXCEPTIONS	1
C_ILL_OPCODE_EXCEPTION	1
C_M_AXI_I_BUS_EXCEPTION	1
C_M_AXI_D_BUS_EXCEPTION	1
C_IPLB_BUS_EXCEPTION	0
C_DPLB_BUS_EXCEPTION	0
C_DIV_ZERO_EXCEPTION	1
C_FPU_EXCEPTION	1
C_FSL_EXCEPTION	0
C_USE_STACK_PROTECTION	0
C_PVR	0
C_PVR_USER1	0x00
C_PVR_USER2	0x00000000
C_DEBUG_ENABLED	1
C_NUMBER_OF_PC_BRK	7
C_NUMBER_OF_RD_ADDR_BRK	2
C_NUMBER_OF_WR_ADDR_BRK	2
C_INTERRUPT_IS_EDGE	0
C_EDGE_IS_POSITIVE	1
C_RESET_MSR	0x00000000
C_OPCODE_0x0_ILLEGAL	1
C_FSL_LINKS	0
C_FSL_DATA_SIZE	32
C_USE_EXTENDED_FSL_INSTR	0
C_M0_AXIS_PROTOCOL	GENERIC
C_S0_AXIS_PROTOCOL	GENERIC
C_M1_AXIS_PROTOCOL	GENERIC
C_S1_AXIS_PROTOCOL	GENERIC
C_M2_AXIS_PROTOCOL	GENERIC
C_S2_AXIS_PROTOCOL	GENERIC
C_M3_AXIS_PROTOCOL	GENERIC
C_S3_AXIS_PROTOCOL	GENERIC
C_M4_AXIS_PROTOCOL	GENERIC
C_S4_AXIS_PROTOCOL	GENERIC
C_M5_AXIS_PROTOCOL	GENERIC
C_S5_AXIS_PROTOCOL	GENERIC
C_M6_AXIS_PROTOCOL	GENERIC
C_S6_AXIS_PROTOCOL	GENERIC
C_M7_AXIS_PROTOCOL	GENERIC
C_S7_AXIS_PROTOCOL	GENERIC
C_M8_AXIS_PROTOCOL	GENERIC
C_S8_AXIS_PROTOCOL	GENERIC
C_M9_AXIS_PROTOCOL	GENERIC
C_S9_AXIS_PROTOCOL	GENERIC
C_M10_AXIS_PROTOCOL	GENERIC
C_S10_AXIS_PROTOCOL	GENERIC
C_M11_AXIS_PROTOCOL	GENERIC
C_S11_AXIS_PROTOCOL	GENERIC
C_M12_AXIS_PROTOCOL	GENERIC
C_S12_AXIS_PROTOCOL	GENERIC
C_M13_AXIS_PROTOCOL	GENERIC
C_S13_AXIS_PROTOCOL	GENERIC
C_M14_AXIS_PROTOCOL	GENERIC
C_S14_AXIS_PROTOCOL	GENERIC
C_M15_AXIS_PROTOCOL	GENERIC
C_S15_AXIS_PROTOCOL	GENERIC
C_M0_AXIS_DATA_WIDTH	32
C_S0_AXIS_DATA_WIDTH	32
C_M1_AXIS_DATA_WIDTH	32
C_S1_AXIS_DATA_WIDTH	32
C_M2_AXIS_DATA_WIDTH	32
C_S2_AXIS_DATA_WIDTH	32

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_M3_AXIS_DATA_WIDTH	32
C_S3_AXIS_DATA_WIDTH	32
C_M4_AXIS_DATA_WIDTH	32
C_S4_AXIS_DATA_WIDTH	32
C_M5_AXIS_DATA_WIDTH	32
C_S5_AXIS_DATA_WIDTH	32
C_M6_AXIS_DATA_WIDTH	32
C_S6_AXIS_DATA_WIDTH	32
C_M7_AXIS_DATA_WIDTH	32
C_S7_AXIS_DATA_WIDTH	32
C_M8_AXIS_DATA_WIDTH	32
C_S8_AXIS_DATA_WIDTH	32
C_M9_AXIS_DATA_WIDTH	32
C_S9_AXIS_DATA_WIDTH	32
C_M10_AXIS_DATA_WIDTH	32
C_S10_AXIS_DATA_WIDTH	32
C_M11_AXIS_DATA_WIDTH	32
C_S11_AXIS_DATA_WIDTH	32
C_M12_AXIS_DATA_WIDTH	32
C_S12_AXIS_DATA_WIDTH	32
C_M13_AXIS_DATA_WIDTH	32
C_S13_AXIS_DATA_WIDTH	32
C_M14_AXIS_DATA_WIDTH	32
C_S14_AXIS_DATA_WIDTH	32
C_M15_AXIS_DATA_WIDTH	32
C_S15_AXIS_DATA_WIDTH	32
C_ICACHE_BASEADDR	0xC0000000
C_ICACHE_HIGHADDR	0xC7FFFFFF
C_USE_ICACHE	1
C_ALLOW_ICACHE_WR	1
C_ADDR_TAG_BITS	17
C_CACHE_BYTE_SIZE	16384
C_ICACHE_USE_FSL	1
C_ICACHE_LINE_LEN	4
C_ICACHE_ALWAYS_USED	1
C_ICACHE_INTERFACE	0
C_ICACHE_VICTIMS	0
C_ICACHE_STREAMS	0
C_ICACHE_FORCE_TAG_LUTRAM	0
C_ICACHE_DATA_WIDTH	0
C_M_AXI_IC_SUPPORTS_THREADS	0
C_M_AXI_IC_THREAD_ID_WIDTH	1
C_M_AXI_IC_SUPPORTS_READ	1
C_M_AXI_IC_SUPPORTS_WRITE	0
C_M_AXI_IC_SUPPORTS_NARROW_BURST	0
C_M_AXI_IC_DATA_WIDTH	32
C_M_AXI_IC_ADDR_WIDTH	32
C_M_AXI_IC_PROTOCOL	AXI4
C_M_AXI_IC_USER_VALUE	0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_IC_AWUSER_WIDTH	5
C_M_AXI_IC_ARUSER_WIDTH	5
C_M_AXI_IC_WUSER_WIDTH	1
C_M_AXI_IC_RUSER_WIDTH	1
C_M_AXI_IC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING	2
C_DCACHE_BASEADDR	0xC0000000
C_DCACHE_HIGHADDR	0xC7FFFFFF
C_USE_DCACHE	1
C_ALLOW_DCACHE_WR	1
C_DCACHE_ADDR_TAG	17
C_DCACHE_BYTE_SIZE	16384
C_DCACHE_USE_FSL	1
C_DCACHE_LINE_LEN	4
C_DCACHE_ALWAYS_USED	1
C_DCACHE_INTERFACE	0
C_DCACHE_USE_WRITEBACK	0
C_DCACHE_VICTIMS	0
C_DCACHE_FORCE_TAG_LUTRAM	0
C_DCACHE_DATA_WIDTH	0
C_M_AXI_DC_SUPPORTS_THREADS	0
C_M_AXI_DC_THREAD_ID_WIDTH	1
C_M_AXI_DC_SUPPORTS_READ	1
C_M_AXI_DC_SUPPORTS_WRITE	1
C_M_AXI_DC_SUPPORTS_NARROW_BURST	0
C_M_AXI_DC_DATA_WIDTH	32
C_M_AXI_DC_ADDR_WIDTH	32
C_M_AXI_DC_PROTOCOL	AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS	0
C_M_AXI_DC_USER_VALUE	0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_DC_AWUSER_WIDTH	5
C_M_AXI_DC_ARUSER_WIDTH	5
C_M_AXI_DC_WUSER_WIDTH	1
C_M_AXI_DC_RUSER_WIDTH	1
C_M_AXI_DC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING	2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING	32
C_USE_MMU	0
C_MMU_DTLB_SIZE	4
C_MMU_ITLB_SIZE	2
C_MMU_TLB_ACCESS	3
C_MMU_ZONES	16
C_MMU_PRIVILEGED_INSTR	0
C_USE_INTERRUPT	0
C_USE_EXT_BRK	0
C_USE_EXT_NM_BRK	0
C_USE_BRANCH_TARGET_CACHE	0
C_BRANCH_TARGET_CACHE_SIZE	0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DC_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DP_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_R_REGISTER	1
C_INTERCONNECT_M_AXI_DP_B_REGISTER	1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DC_R_REGISTER	1
C_INTERCONNECT_M_AXI_DC_B_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_IC_W_REGISTER	1
C_INTERCONNECT_M_AXI_IC_R_REGISTER	1
C_INTERCONNECT_M_AXI_IC_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Debuggers	TOP

+
+ + +

+ + + + + + + + + +

+debug_module + MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
mdm	2.00.b	IP

+

+

debug_module IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Debug_SYS_Rst		O	1	proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
MBDEBUG_0	INITIATOR	XIL_MBDEBUG3	microblaze_0_debug			microblaze_0
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_JTAG_CHAIN	2
C_INTERCONNECT	2
C_BASEADDR	0x74800000
C_HIGHADDR	0x7480FFFF
C_SPLB_AWIDTH	32
C_SPLB_DWIDTH	32
C_SPLB_P2P	0
C_SPLB_MID_WIDTH	3
C_SPLB_NUM_MASTERS	8
C_SPLB_NATIVE_DWIDTH	32

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_SPLB_SUPPORT_BURSTS	0
C_MB_DBG_PORTS	1
C_USE_UART	1
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Interrupt Controllers	TOP

+
+ + +

+ + + + + + + + + +

+microblaze_0_intc + AXI Interrupt Controller
intc core attached to the AXI

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_intc	1.01.a	IP

+

+

microblaze_0_intc IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	IRQ		O	1	microblaze_0_interrupt
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	INTR		I	1	Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.
+Interrupt Priorities
Priority	SIG			MODULE
0	Push_Buttons_4Bits_IP2INTC_Irpt			Push_Buttons_4Bits
1	Ethernet_Lite_IP2INTC_Irpt			Ethernet_Lite
2	axi_timer_0_Interrupt			axi_timer_0
3	RS232_Uart_1_Interrupt			RS232_Uart_1

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x41200000
C_HIGHADDR	0x4120FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_NUM_INTR_INPUTS	2
C_KIND_OF_INTR	0xFFFFFFFF
C_KIND_OF_EDGE	0xFFFFFFFF
C_KIND_OF_LVL	0xFFFFFFFF
C_HAS_IPR	1
C_HAS_SIE	1

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_HAS_CIE	1
C_HAS_IVR	1
C_IRQ_IS_LEVEL	1
C_IRQ_ACTIVE	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Busses	TOP

+
+ + + + + + + + +

+ + + + + + + + + +

+axi4_0 + AXI Interconnect
AXI4 Memory-Mapped Interconnect

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

+

+

axi4_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	interconnect_aclk		I	1	clk_100_0000MHzPLL0
1	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DC
microblaze_0					MASTER	M_AXI_IC
MCB_DDR3					SLAVE	S0_AXI

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	1
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+axi4lite_0 + AXI Interconnect
AXI4 Memory-Mapped Interconnect

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

+

+

axi4lite_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
1	INTERCONNECT_ACLK		I	1	clk_50_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DP
debug_module					SLAVE	S_AXI
RS232_Uart_1					SLAVE	S_AXI
LEDs_4Bits					SLAVE	S_AXI
Push_Buttons_4Bits					SLAVE	S_AXI
Ethernet_Lite					SLAVE	S_AXI
axi_timer_0					SLAVE	S_AXI
microblaze_0_intc					SLAVE	S_AXI

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	0
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+microblaze_0_dlmb + Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

+

+

microblaze_0_dlmb IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	DLMB
microblaze_0_d_bram_ctrl					SLAVE	SLMB

+

+

+ + + + + + + + + + + + + + + + + + + + +

Parameters
+ + These are the current parameter settings for this module. + + Parameters marked with + yellow + indicate parameters set by the user. + + Parameters marked with + blue + indicate parameters set by the system. + +
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+microblaze_0_ilmb + Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

+

+

microblaze_0_ilmb IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	ILMB
microblaze_0_i_bram_ctrl					SLAVE	SLMB

+

+

+ + + + + + + + + + + + + + + + + + + + +

Parameters
+ + These are the current parameter settings for this module. + + Parameters marked with + yellow + indicate parameters set by the user. + + Parameters marked with + blue + indicate parameters set by the system. + +
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Memorys	TOP

+
+ + +

+ + + + + + + + + +

+microblaze_0_bram_block + Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
bram_block	1.00.a	IP

+

+

microblaze_0_bram_block IP Image

+ + + + + + + + + + + + + + + + + + + + + +

Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
PORTA	TARGET	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_i_bram_ctrl
PORTB	TARGET	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_d_bram_ctrl

+

+

+ + + + + + + + + + + + + + + + + + + + + + + +

Parameters
+ + These are the current parameter settings for this module. + + Parameters marked with + yellow + indicate parameters set by the user. + + Parameters marked with + blue + indicate parameters set by the system. + +
Name		Value
C_MEMSIZE		2048
C_PORT_DWIDTH		32
C_PORT_AWIDTH		32
C_NUM_WE		4
C_FAMILY		virtex2

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Memory Controllers	TOP

+
+ + + + + + +

+ + + + + + + + + +

+MCB_DDR3 + AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_s6_ddrx	1.02.a	IP

+

+

MCB_DDR3 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	mcbx_dram_clk		O	1	mcbx_dram_clk
1	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
2	mcbx_dram_cke		O	1	mcbx_dram_cke
3	mcbx_dram_odt		O	1	mcbx_dram_odt
4	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
5	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
6	mcbx_dram_we_n		O	1	mcbx_dram_we_n
7	mcbx_dram_udm		O	1	mcbx_dram_udm
8	mcbx_dram_ldm		O	1	mcbx_dram_ldm
9	mcbx_dram_ba		O	1	mcbx_dram_ba
10	mcbx_dram_addr		O	1	mcbx_dram_addr
11	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
12	mcbx_dram_dq		IO	1	mcbx_dram_dq
13	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
14	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
15	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
16	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
17	rzq		IO	1	rzq
18	zio		IO	1	zio
19	s0_axi_aclk		I	1	clk_100_0000MHzPLL0
20	ui_clk		I	1	clk_100_0000MHzPLL0
21	sysclk_2x		I	1	clk_600_0000MHzPLL0_nobuf
22	sysclk_2x_180		I	1	clk_600_0000MHz180PLL0_nobuf
23	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
24	PLL_LOCK		I	1	proc_sys_reset_0_Dcm_locked
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S0_AXI	SLAVE	AXI	axi4_0			microblaze_0

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_MCB_LOC	MEMC3
C_MCB_RZQ_LOC	K7
C_MCB_ZIO_LOC	R7
C_MCB_PERFORMANCE	STANDARD
C_BYPASS_CORE_UCF	0
C_S0_AXI_BASEADDR	0xC0000000
C_S0_AXI_HIGHADDR	0xC7FFFFFF
C_S1_AXI_BASEADDR	0xFFFFFFFF
C_S1_AXI_HIGHADDR	0x00000000
C_S2_AXI_BASEADDR	0xFFFFFFFF
C_S2_AXI_HIGHADDR	0x00000000
C_S3_AXI_BASEADDR	0xFFFFFFFF
C_S3_AXI_HIGHADDR	0x00000000
C_S4_AXI_BASEADDR	0xFFFFFFFF
C_S4_AXI_HIGHADDR	0x00000000
C_S5_AXI_BASEADDR	0xFFFFFFFF
C_S5_AXI_HIGHADDR	0x00000000
C_MEM_TYPE	DDR3
C_MEM_PARTNO	MT41J64M16XX-187E
C_MEM_BASEPARTNO	NOT_SET
C_NUM_DQ_PINS	16
C_MEM_ADDR_WIDTH	13
C_MEM_BANKADDR_WIDTH	3
C_MEM_NUM_COL_BITS	10
C_MEM_TRAS	-1
C_MEM_TRCD	-1
C_MEM_TREFI	-1
C_MEM_TRFC	-1
C_MEM_TRP	-1
C_MEM_TWR	-1
C_MEM_TRTP	-1
C_MEM_TWTR	-1
C_PORT_CONFIG	B32_B32_B32_B32
C_SKIP_IN_TERM_CAL	0
C_SKIP_IN_TERM_CAL_VALUE	NONE
C_MEMCLK_PERIOD	0
C_MEM_ADDR_ORDER	ROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT	512
C_MEM_CAS_LATENCY	6
C_SIMULATION	FALSE
C_MEM_DDR1_2_ODS	FULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR2_RTT	150OHMS
C_MEM_DDR2_DIFF_DQS_EN	YES
C_MEM_DDR2_3_PA_SR	FULL
C_MEM_DDR2_3_HIGH_TEMP_SR	NORMAL
C_MEM_DDR3_CAS_WR_LATENCY	5
C_MEM_DDR3_CAS_LATENCY	6
C_MEM_DDR3_ODS	DIV6
C_MEM_DDR3_RTT	DIV4
C_MEM_DDR3_AUTO_SR	ENABLED
C_MEM_MOBILE_PA_SR	FULL
C_MEM_MDDR_ODS	FULL
C_ARB_ALGORITHM	0
C_ARB_NUM_TIME_SLOTS	12
C_ARB_TIME_SLOT_0	0b000000000001010011
C_ARB_TIME_SLOT_1	0b000000001010011000
C_ARB_TIME_SLOT_2	0b000000010011000001
C_ARB_TIME_SLOT_3	0b000000011000001010
C_ARB_TIME_SLOT_4	0b000000000001010011
C_ARB_TIME_SLOT_5	0b000000001010011000
C_ARB_TIME_SLOT_6	0b000000010011000001
C_ARB_TIME_SLOT_7	0b000000011000001010
C_ARB_TIME_SLOT_8	0b000000000001010011
C_ARB_TIME_SLOT_9	0b000000001010011000
C_ARB_TIME_SLOT_10	0b000000010011000001
C_ARB_TIME_SLOT_11	0b000000011000001010
C_S0_AXI_ENABLE	1
C_S0_AXI_PROTOCOL	AXI4
C_S0_AXI_ID_WIDTH	4
C_S0_AXI_ADDR_WIDTH	32
C_S0_AXI_DATA_WIDTH	32
C_S0_AXI_SUPPORTS_READ	1
C_S0_AXI_SUPPORTS_WRITE	1
C_S0_AXI_SUPPORTS_NARROW_BURST	1
C_S0_AXI_REG_EN0	0x00000
C_S0_AXI_REG_EN1	0x01000
C_S0_AXI_STRICT_COHERENCY	1
C_S0_AXI_ENABLE_AP	0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE	4
C_S1_AXI_ENABLE	0
C_S1_AXI_PROTOCOL	AXI4
C_S1_AXI_ID_WIDTH	4
C_S1_AXI_ADDR_WIDTH	32
C_S1_AXI_DATA_WIDTH	32
C_S1_AXI_SUPPORTS_READ	1
C_S1_AXI_SUPPORTS_WRITE	1
C_S1_AXI_SUPPORTS_NARROW_BURST	1
C_S1_AXI_REG_EN0	0x00000
C_S1_AXI_REG_EN1	0x01000
C_S1_AXI_STRICT_COHERENCY	1
C_S1_AXI_ENABLE_AP	0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE	4
C_S2_AXI_ENABLE	0
C_S2_AXI_PROTOCOL	AXI4
C_S2_AXI_ID_WIDTH	4
C_S2_AXI_ADDR_WIDTH	32
C_S2_AXI_DATA_WIDTH	32
C_S2_AXI_SUPPORTS_READ	1
C_S2_AXI_SUPPORTS_WRITE	1
C_S2_AXI_SUPPORTS_NARROW_BURST	1
C_S2_AXI_REG_EN0	0x00000
C_S2_AXI_REG_EN1	0x01000
C_S2_AXI_STRICT_COHERENCY	1
C_S2_AXI_ENABLE_AP	0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE	4
C_S3_AXI_ENABLE	0
C_S3_AXI_PROTOCOL	AXI4
C_S3_AXI_ID_WIDTH	4
C_S3_AXI_ADDR_WIDTH	32
C_S3_AXI_DATA_WIDTH	32
C_S3_AXI_SUPPORTS_READ	1
C_S3_AXI_SUPPORTS_WRITE	1
C_S3_AXI_SUPPORTS_NARROW_BURST	1
C_S3_AXI_REG_EN0	0x00000
C_S3_AXI_REG_EN1	0x01000
C_S3_AXI_STRICT_COHERENCY	1
C_S3_AXI_ENABLE_AP	0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE	4
C_S4_AXI_ENABLE	0
C_S4_AXI_PROTOCOL	AXI4
C_S4_AXI_ID_WIDTH	4
C_S4_AXI_ADDR_WIDTH	32
C_S4_AXI_DATA_WIDTH	32
C_S4_AXI_SUPPORTS_READ	1
C_S4_AXI_SUPPORTS_WRITE	1
C_S4_AXI_SUPPORTS_NARROW_BURST	1
C_S4_AXI_REG_EN0	0x00000
C_S4_AXI_REG_EN1	0x01000
C_S4_AXI_STRICT_COHERENCY	1
C_S4_AXI_ENABLE_AP	0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE	4
C_S5_AXI_ENABLE	0
C_S5_AXI_PROTOCOL	AXI4
C_S5_AXI_ID_WIDTH	4
C_S5_AXI_ADDR_WIDTH	32
C_S5_AXI_DATA_WIDTH	32
C_S5_AXI_SUPPORTS_READ	1
C_S5_AXI_SUPPORTS_WRITE	1
C_S5_AXI_SUPPORTS_NARROW_BURST	1
C_S5_AXI_REG_EN0	0x00000
C_S5_AXI_REG_EN1	0x01000
C_S5_AXI_STRICT_COHERENCY	1
C_S5_AXI_ENABLE_AP	0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE	4
C_MCB_USE_EXTERNAL_BUFPLL	0
C_SYS_RST_PRESENT	0
C_INTERCONNECT_S0_AXI_MASTERS	microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC
C_INTERCONNECT_S0_AXI_AW_REGISTER	1
C_INTERCONNECT_S0_AXI_AR_REGISTER	1
C_INTERCONNECT_S0_AXI_W_REGISTER	1
C_INTERCONNECT_S0_AXI_R_REGISTER	1
C_INTERCONNECT_S0_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+microblaze_0_d_bram_ctrl + LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

+

+

microblaze_0_d_bram_ctrl IP Image

+ + + + + + + + + + + + + + + + + + + + + +

Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_dlmb			microblaze_0

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+microblaze_0_i_bram_ctrl + LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

+

+

microblaze_0_i_bram_ctrl IP Image

+ + + + + + + + + + + + + + + + + + + + + +

Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_ilmb			microblaze_0

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Peripherals	TOP

+
+ + + + + + + + + + +

+ + + + + + + + + +

+Ethernet_Lite + AXI 10/100 Ethernet MAC Lite
'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_ethernetlite	1.00.a	IP

+

+

Ethernet_Lite IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	PHY_MDIO		IO	1	Ethernet_Lite_MDIO
1	PHY_MDC		O	1	Ethernet_Lite_MDC
2	PHY_tx_data		O	1	Ethernet_Lite_TXD
3	PHY_tx_en		O	1	Ethernet_Lite_TX_EN
4	PHY_tx_clk		I	1	Ethernet_Lite_TX_CLK
5	PHY_col		I	1	Ethernet_Lite_COL
6	PHY_rx_data		I	1	Ethernet_Lite_RXD
7	PHY_rx_er		I	1	Ethernet_Lite_RX_ER
8	PHY_rx_clk		I	1	Ethernet_Lite_RX_CLK
9	PHY_crs		I	1	Ethernet_Lite_CRS
10	PHY_dv		I	1	Ethernet_Lite_RX_DV
11	PHY_rst_n		O	1	Ethernet_Lite_PHY_RST_N
12	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
13	IP2INTC_Irpt		O	1	Ethernet_Lite_IP2INTC_Irpt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_FAMILY	virtex6
C_BASEADDR	0x40E00000
C_HIGHADDR	0x40E0FFFF
C_S_AXI_ACLK_PERIOD_PS	10000
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_ID_WIDTH	1
C_INCLUDE_MDIO	1
C_INCLUDE_GLOBAL_BUFFERS	0
C_INCLUDE_INTERNAL_LOOPBACK	0
C_DUPLEX	1

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_TX_PING_PONG	1
C_RX_PING_PONG	1
C_INCLUDE_PHY_CONSTRAINTS	1
C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE	1
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE	1
C_S_AXI_SUPPORTS_NARROW_BURST	0
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+LEDs_4Bits + AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

+

+

LEDs_4Bits IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_O		O	1	LEDs_4Bits_TRI_O
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40020000
C_HIGHADDR	0x4002FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	0
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	0
C_DOUT_DEFAULT	0x00000000

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+Push_Buttons_4Bits + AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

+

+

Push_Buttons_4Bits IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_I		I	1	Push_Buttons_4Bits_TRI_I
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	IP2INTC_Irpt		O	1	Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40000000
C_HIGHADDR	0x4000FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	1
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	1
C_DOUT_DEFAULT	0x00000000

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+RS232_Uart_1 + AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_uartlite	1.01.a	IP

+

+

RS232_Uart_1 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	TX		O	1	RS232_Uart_1_sout
1	RX		I	1	RS232_Uart_1_sin
2	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
3	Interrupt		O	1	RS232_Uart_1_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_S_AXI_ACLK_FREQ_HZ	100000000
C_BASEADDR	0x40600000
C_HIGHADDR	0x4060FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_BAUDRATE	115200
C_DATA_BITS	8

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_USE_PARITY	0
C_ODD_PARITY	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+axi_timer_0 + AXI Timer/Counter
Timer counter with AXI interface

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_timer	1.01.a	IP

+

+

axi_timer_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Interrupt		O	1	axi_timer_0_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_FAMILY	virtex6
C_COUNT_WIDTH	32
C_ONE_TIMER_ONLY	0
C_TRIG0_ASSERT	1
C_TRIG1_ASSERT	1
C_GEN0_ASSERT	1
C_GEN1_ASSERT	1
C_BASEADDR	0x41C00000

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_HIGHADDR	0x41C0FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

IP	TOP

+
+ + + + +

+ + + + + + + + + +

+clock_generator_0 + Clock Generator
Clock generator for processor system.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
clock_generator	4.01.a	IP

+

+

clock_generator_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	RST		I	1	RESET
1	CLKIN		I	1	CLK
2	CLKOUT2		O	1	clk_100_0000MHzPLL0
3	CLKOUT3		O	1	clk_50_0000MHzPLL0
4	CLKOUT0		O	1	clk_600_0000MHzPLL0_nobuf
5	CLKOUT1		O	1	clk_600_0000MHz180PLL0_nobuf
6	LOCKED		O	1	proc_sys_reset_0_Dcm_locked

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_DEVICE	NOT_SET
C_PACKAGE	NOT_SET
C_SPEEDGRADE	NOT_SET
C_CLKIN_FREQ	200000000
C_CLKOUT0_FREQ	600000000
C_CLKOUT0_PHASE	0
C_CLKOUT0_GROUP	PLL0
C_CLKOUT0_BUF	FALSE
C_CLKOUT0_VARIABLE_PHASE	FALSE
C_CLKOUT1_FREQ	600000000
C_CLKOUT1_PHASE	180
C_CLKOUT1_GROUP	PLL0
C_CLKOUT1_BUF	FALSE
C_CLKOUT1_VARIABLE_PHASE	FALSE
C_CLKOUT2_FREQ	100000000
C_CLKOUT2_PHASE	0
C_CLKOUT2_GROUP	PLL0
C_CLKOUT2_BUF	TRUE
C_CLKOUT2_VARIABLE_PHASE	FALSE
C_CLKOUT3_FREQ	50000000
C_CLKOUT3_PHASE	0
C_CLKOUT3_GROUP	PLL0
C_CLKOUT3_BUF	TRUE
C_CLKOUT3_VARIABLE_PHASE	FALSE
C_CLKOUT4_FREQ	0
C_CLKOUT4_PHASE	0
C_CLKOUT4_GROUP	NONE
C_CLKOUT4_BUF	TRUE
C_CLKOUT4_VARIABLE_PHASE	FALSE
C_CLKOUT5_FREQ	0
C_CLKOUT5_PHASE	0
C_CLKOUT5_GROUP	NONE
C_CLKOUT5_BUF	TRUE
C_CLKOUT5_VARIABLE_PHASE	FALSE
C_CLKOUT6_FREQ	0
C_CLKOUT6_PHASE	0
C_CLKOUT6_GROUP	NONE
C_CLKOUT6_BUF	TRUE
C_CLKOUT6_VARIABLE_PHASE	FALSE
C_CLKOUT7_FREQ	0
C_CLKOUT7_PHASE	0
C_CLKOUT7_GROUP	NONE
C_CLKOUT7_BUF	TRUE
C_CLKOUT7_VARIABLE_PHASE	FALSE
C_CLKOUT8_FREQ	0
C_CLKOUT8_PHASE	0
C_CLKOUT8_GROUP	NONE

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_CLKOUT8_BUF	TRUE
C_CLKOUT8_VARIABLE_PHASE	FALSE
C_CLKOUT9_FREQ	0
C_CLKOUT9_PHASE	0
C_CLKOUT9_GROUP	NONE
C_CLKOUT9_BUF	TRUE
C_CLKOUT9_VARIABLE_PHASE	FALSE
C_CLKOUT10_FREQ	0
C_CLKOUT10_PHASE	0
C_CLKOUT10_GROUP	NONE
C_CLKOUT10_BUF	TRUE
C_CLKOUT10_VARIABLE_PHASE	FALSE
C_CLKOUT11_FREQ	0
C_CLKOUT11_PHASE	0
C_CLKOUT11_GROUP	NONE
C_CLKOUT11_BUF	TRUE
C_CLKOUT11_VARIABLE_PHASE	FALSE
C_CLKOUT12_FREQ	0
C_CLKOUT12_PHASE	0
C_CLKOUT12_GROUP	NONE
C_CLKOUT12_BUF	TRUE
C_CLKOUT12_VARIABLE_PHASE	FALSE
C_CLKOUT13_FREQ	0
C_CLKOUT13_PHASE	0
C_CLKOUT13_GROUP	NONE
C_CLKOUT13_BUF	TRUE
C_CLKOUT13_VARIABLE_PHASE	FALSE
C_CLKOUT14_FREQ	0
C_CLKOUT14_PHASE	0
C_CLKOUT14_GROUP	NONE
C_CLKOUT14_BUF	TRUE
C_CLKOUT14_VARIABLE_PHASE	FALSE
C_CLKOUT15_FREQ	0
C_CLKOUT15_PHASE	0
C_CLKOUT15_GROUP	NONE
C_CLKOUT15_BUF	TRUE
C_CLKOUT15_VARIABLE_PHASE	FALSE
C_CLKFBIN_FREQ	0
C_CLKFBIN_DESKEW	NONE
C_CLKFBOUT_FREQ	0
C_CLKFBOUT_PHASE	0
C_CLKFBOUT_GROUP	NONE
C_CLKFBOUT_BUF	TRUE
C_PSDONE_GROUP	NONE
C_EXT_RESET_HIGH	1
C_CLK_PRIMITIVE_FEEDBACK_BUF	FALSE
C_CLK_GEN	UPDATE

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+proc_sys_reset_0 + Processor System Reset Module
Reset management module

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
proc_sys_reset	3.00.a	IP

+

+

proc_sys_reset_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	Ext_Reset_In		I	1	RESET
1	MB_Reset		O	1	proc_sys_reset_0_MB_Reset
2	Slowest_sync_clk		I	1	clk_50_0000MHzPLL0
3	Interconnect_aresetn		O	1	proc_sys_reset_0_Interconnect_aresetn
4	Dcm_locked		I	1	proc_sys_reset_0_Dcm_locked
5	MB_Debug_Sys_Rst		I	1	proc_sys_reset_0_MB_Debug_Sys_Rst
6	BUS_STRUCT_RESET		O	1	proc_sys_reset_0_BUS_STRUCT_RESET

+

+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Parameters
+ + These are the current parameter settings for this module. + + Parameters marked with + yellow + indicate parameters set by the user. + + Parameters marked with + blue + indicate parameters set by the system. + +
Name		Value
C_SUBFAMILY		lx
C_EXT_RST_WIDTH		4
C_AUX_RST_WIDTH		4
C_EXT_RESET_HIGH		1
C_AUX_RESET_HIGH		1
C_NUM_BUS_RST		1
C_NUM_PERP_RST		1
C_NUM_INTERCONNECT_ARESETN		1
C_NUM_PERP_ARESETN		1
C_FAMILY		virtex5

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Timing Information	TOP

+

+ + + +

Post Synthesis Clock Limits
+ No clocks could be identified in the design. Run platgen to generate synthesis information. +

+

+ diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html new file mode 100644 index 000000000..01df645af --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html @@ -0,0 +1,5407 @@ + + + + +XPS Project Report + + + + + + + +

TABLE OF CONTENTS

+
Overview
Block Diagram
External Ports
Processor
   microblaze_0
Debuggers
   debug_module
Interrupt Controllers
   microblaze_0_intc
Busses
   axi4_0
   axi4lite_0
   microblaze_0_dlmb
   microblaze_0_ilmb
Memory
   microblaze_0_bram_block
Memory Controllers
   MCB_DDR3
   microblaze_0_d_bram_ctrl
   microblaze_0_i_bram_ctrl
Peripherals
   Ethernet_Lite
   LEDs_4Bits
   Push_Buttons_4Bits
   RS232_Uart_1
   axi_timer_0
IP
   clock_generator_0
   proc_sys_reset_0
Timing Information +

+ + + + + + + + + + + + + + + + + + + + + + + + +

+ + + +

Overview	TOC

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Resources Used
1	MicroBlaze
2	AXI Interconnect
2	Local Memory Bus (LMB) 1.0
1	Block RAM (BRAM) Block
2	LMB BRAM Controller
1	AXI S6 Memory Controller(DDR/DDR2/DDR3)
1	Processor System Reset Module
1	Clock Generator
1	MicroBlaze Debug Module (MDM)
1	AXI UART (Lite)
2	AXI General Purpose IO
1	AXI 10/100 Ethernet MAC Lite
1	AXI Timer/Counter
1	AXI Interrupt Controller

+ + + + + + + + + + + + + + +

Specifics
Generated	Wed Jul 27 11:49:42 2011
EDK Version	13.1
Device Family	spartan6
Device	xc6slx45tfgg484-3

+

+
+ + +

Block Diagram	TOC

+

BlockDiagram

+

+ + + +

External Ports	TOC

+
+ + + + + + +

+ These are the external ports defined in the MHS file. +

+Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK)
INTR  indicates Interrupt ports,(SIGIS = INTR)
RESET  indicates Reset ports, (SIGIS = RST)
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

#	NAME		DIR	[LSB:MSB]	SIG		ATTRIBUTES
+SHARED +	RESET		I	1	RESET		RESET
+Ethernet_Lite +	Ethernet_Lite_COL		I	1	Ethernet_Lite_COL
+Ethernet_Lite +	Ethernet_Lite_CRS		I	1	Ethernet_Lite_CRS
+Ethernet_Lite +	Ethernet_Lite_RXD		I	0:3	Ethernet_Lite_RXD
+Ethernet_Lite +	Ethernet_Lite_RX_CLK		I	1	Ethernet_Lite_RX_CLK
+Ethernet_Lite +	Ethernet_Lite_RX_DV		I	1	Ethernet_Lite_RX_DV
+Ethernet_Lite +	Ethernet_Lite_RX_ER		I	1	Ethernet_Lite_RX_ER
+Ethernet_Lite +	Ethernet_Lite_TX_CLK		I	1	Ethernet_Lite_TX_CLK
+Ethernet_Lite +	Ethernet_Lite_MDIO		IO	1	Ethernet_Lite_MDIO
+Ethernet_Lite +	Ethernet_Lite_MDC		O	1	Ethernet_Lite_MDC
+Ethernet_Lite +	Ethernet_Lite_PHY_RST_N		O	1	Ethernet_Lite_PHY_RST_N
+Ethernet_Lite +	Ethernet_Lite_TXD		O	0:3	Ethernet_Lite_TXD
+Ethernet_Lite +	Ethernet_Lite_TX_EN		O	1	Ethernet_Lite_TX_EN
+LEDs_4Bits +	LEDs_4Bits_TRI_O		O	3:0	LEDs_4Bits_TRI_O
+MCB_DDR3 +	mcbx_dram_dq		IO	0:15	mcbx_dram_dq
+MCB_DDR3 +	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
+MCB_DDR3 +	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
+MCB_DDR3 +	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
+MCB_DDR3 +	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
+MCB_DDR3 +	rzq		IO	1	rzq
+MCB_DDR3 +	zio		IO	1	zio
+MCB_DDR3 +	mcbx_dram_addr		O	0:12	mcbx_dram_addr
+MCB_DDR3 +	mcbx_dram_ba		O	0:2	mcbx_dram_ba
+MCB_DDR3 +	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
+MCB_DDR3 +	mcbx_dram_cke		O	1	mcbx_dram_cke
+MCB_DDR3 +	mcbx_dram_clk		O	1	mcbx_dram_clk
+MCB_DDR3 +	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
+MCB_DDR3 +	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
+MCB_DDR3 +	mcbx_dram_ldm		O	1	mcbx_dram_ldm
+MCB_DDR3 +	mcbx_dram_odt		O	1	mcbx_dram_odt
+MCB_DDR3 +	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
+MCB_DDR3 +	mcbx_dram_udm		O	1	mcbx_dram_udm
+MCB_DDR3 +	mcbx_dram_we_n		O	1	mcbx_dram_we_n
+Push_Buttons_4Bits +	Push_Buttons_4Bits_TRI_I		I	0:3	Push_Buttons_4Bits_TRI_I
+RS232_Uart_1 +	RS232_Uart_1_sin		I	1	RS232_Uart_1_sin
+RS232_Uart_1 +	RS232_Uart_1_sout		O	1	RS232_Uart_1_sout
+clock_generator_0 +	CLK_N		I	1	CLK		CLK
+clock_generator_0 +	CLK_P		I	1	CLK		CLK

+

+

+ + +

Processors	TOC

+
+ + +

+ + + + + + + + + +

+microblaze_0 + MicroBlaze
The MicroBlaze 32 bit soft processor

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
microblaze	8.10.a	IP

+

+

microblaze_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	MB_RESET		I	1	proc_sys_reset_0_MB_Reset
1	CLK		I	1	clk_100_0000MHzPLL0
2	INTERRUPT		I	1	microblaze_0_interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
M_AXI_DP	MASTER	AXI	axi4lite_0			7 Peripherals.
M_AXI_DC	MASTER	AXI	axi4_0			MCB_DDR3
M_AXI_IC	MASTER	AXI	axi4_0			MCB_DDR3
DLMB	MASTER	LMB	microblaze_0_dlmb			microblaze_0_d_bram_ctrl
ILMB	MASTER	LMB	microblaze_0_ilmb			microblaze_0_i_bram_ctrl
DEBUG	TARGET	XIL_MBDEBUG3	microblaze_0_debug			debug_module

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_SCO	0
C_FREQ	0
C_DATA_SIZE	32
C_DYNAMIC_BUS_SIZING	1
C_FAMILY	virtex5
C_INSTANCE	microblaze
C_FAULT_TOLERANT	0
C_ECC_USE_CE_EXCEPTION	0
C_ENDIANNESS	0
C_AREA_OPTIMIZED	0
C_OPTIMIZATION	0
C_INTERCONNECT	2
C_STREAM_INTERCONNECT	0
C_DPLB_DWIDTH	32
C_DPLB_NATIVE_DWIDTH	32
C_DPLB_BURST_EN	0
C_DPLB_P2P	0
C_IPLB_DWIDTH	32
C_IPLB_NATIVE_DWIDTH	32
C_IPLB_BURST_EN	0
C_IPLB_P2P	0
C_M_AXI_DP_SUPPORTS_THREADS	0
C_M_AXI_DP_THREAD_ID_WIDTH	1
C_M_AXI_DP_SUPPORTS_READ	1
C_M_AXI_DP_SUPPORTS_WRITE	1
C_M_AXI_DP_SUPPORTS_NARROW_BURST	0
C_M_AXI_DP_DATA_WIDTH	32
C_M_AXI_DP_ADDR_WIDTH	32
C_M_AXI_DP_PROTOCOL	AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS	0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING	1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING	1
C_M_AXI_IP_SUPPORTS_THREADS	0
C_M_AXI_IP_THREAD_ID_WIDTH	1
C_M_AXI_IP_SUPPORTS_READ	1
C_M_AXI_IP_SUPPORTS_WRITE	0
C_M_AXI_IP_SUPPORTS_NARROW_BURST	0
C_M_AXI_IP_DATA_WIDTH	32
C_M_AXI_IP_ADDR_WIDTH	32
C_M_AXI_IP_PROTOCOL	AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING	1
C_D_AXI	0
C_D_PLB	0
C_D_LMB	1
C_I_AXI	0
C_I_PLB	0
C_I_LMB	1
C_USE_MSR_INSTR	1
C_USE_PCMP_INSTR	1
C_USE_BARREL	1
C_USE_DIV	1
C_USE_HW_MUL	1
C_USE_FPU	1
C_UNALIGNED_EXCEPTIONS	1
C_ILL_OPCODE_EXCEPTION	1
C_M_AXI_I_BUS_EXCEPTION	1
C_M_AXI_D_BUS_EXCEPTION	1
C_IPLB_BUS_EXCEPTION	0
C_DPLB_BUS_EXCEPTION	0
C_DIV_ZERO_EXCEPTION	1
C_FPU_EXCEPTION	1
C_FSL_EXCEPTION	0
C_USE_STACK_PROTECTION	0
C_PVR	0
C_PVR_USER1	0x00
C_PVR_USER2	0x00000000
C_DEBUG_ENABLED	1
C_NUMBER_OF_PC_BRK	7
C_NUMBER_OF_RD_ADDR_BRK	2
C_NUMBER_OF_WR_ADDR_BRK	2
C_INTERRUPT_IS_EDGE	0
C_EDGE_IS_POSITIVE	1
C_RESET_MSR	0x00000000
C_OPCODE_0x0_ILLEGAL	1
C_FSL_LINKS	0
C_FSL_DATA_SIZE	32
C_USE_EXTENDED_FSL_INSTR	0
C_M0_AXIS_PROTOCOL	GENERIC
C_S0_AXIS_PROTOCOL	GENERIC
C_M1_AXIS_PROTOCOL	GENERIC
C_S1_AXIS_PROTOCOL	GENERIC
C_M2_AXIS_PROTOCOL	GENERIC
C_S2_AXIS_PROTOCOL	GENERIC
C_M3_AXIS_PROTOCOL	GENERIC
C_S3_AXIS_PROTOCOL	GENERIC
C_M4_AXIS_PROTOCOL	GENERIC
C_S4_AXIS_PROTOCOL	GENERIC
C_M5_AXIS_PROTOCOL	GENERIC
C_S5_AXIS_PROTOCOL	GENERIC
C_M6_AXIS_PROTOCOL	GENERIC
C_S6_AXIS_PROTOCOL	GENERIC
C_M7_AXIS_PROTOCOL	GENERIC
C_S7_AXIS_PROTOCOL	GENERIC
C_M8_AXIS_PROTOCOL	GENERIC
C_S8_AXIS_PROTOCOL	GENERIC
C_M9_AXIS_PROTOCOL	GENERIC
C_S9_AXIS_PROTOCOL	GENERIC
C_M10_AXIS_PROTOCOL	GENERIC
C_S10_AXIS_PROTOCOL	GENERIC
C_M11_AXIS_PROTOCOL	GENERIC
C_S11_AXIS_PROTOCOL	GENERIC
C_M12_AXIS_PROTOCOL	GENERIC
C_S12_AXIS_PROTOCOL	GENERIC
C_M13_AXIS_PROTOCOL	GENERIC
C_S13_AXIS_PROTOCOL	GENERIC
C_M14_AXIS_PROTOCOL	GENERIC
C_S14_AXIS_PROTOCOL	GENERIC
C_M15_AXIS_PROTOCOL	GENERIC
C_S15_AXIS_PROTOCOL	GENERIC
C_M0_AXIS_DATA_WIDTH	32
C_S0_AXIS_DATA_WIDTH	32
C_M1_AXIS_DATA_WIDTH	32
C_S1_AXIS_DATA_WIDTH	32
C_M2_AXIS_DATA_WIDTH	32
C_S2_AXIS_DATA_WIDTH	32

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_M3_AXIS_DATA_WIDTH	32
C_S3_AXIS_DATA_WIDTH	32
C_M4_AXIS_DATA_WIDTH	32
C_S4_AXIS_DATA_WIDTH	32
C_M5_AXIS_DATA_WIDTH	32
C_S5_AXIS_DATA_WIDTH	32
C_M6_AXIS_DATA_WIDTH	32
C_S6_AXIS_DATA_WIDTH	32
C_M7_AXIS_DATA_WIDTH	32
C_S7_AXIS_DATA_WIDTH	32
C_M8_AXIS_DATA_WIDTH	32
C_S8_AXIS_DATA_WIDTH	32
C_M9_AXIS_DATA_WIDTH	32
C_S9_AXIS_DATA_WIDTH	32
C_M10_AXIS_DATA_WIDTH	32
C_S10_AXIS_DATA_WIDTH	32
C_M11_AXIS_DATA_WIDTH	32
C_S11_AXIS_DATA_WIDTH	32
C_M12_AXIS_DATA_WIDTH	32
C_S12_AXIS_DATA_WIDTH	32
C_M13_AXIS_DATA_WIDTH	32
C_S13_AXIS_DATA_WIDTH	32
C_M14_AXIS_DATA_WIDTH	32
C_S14_AXIS_DATA_WIDTH	32
C_M15_AXIS_DATA_WIDTH	32
C_S15_AXIS_DATA_WIDTH	32
C_ICACHE_BASEADDR	0xC0000000
C_ICACHE_HIGHADDR	0xC7FFFFFF
C_USE_ICACHE	1
C_ALLOW_ICACHE_WR	1
C_ADDR_TAG_BITS	17
C_CACHE_BYTE_SIZE	16384
C_ICACHE_USE_FSL	1
C_ICACHE_LINE_LEN	4
C_ICACHE_ALWAYS_USED	1
C_ICACHE_INTERFACE	0
C_ICACHE_VICTIMS	0
C_ICACHE_STREAMS	0
C_ICACHE_FORCE_TAG_LUTRAM	0
C_ICACHE_DATA_WIDTH	0
C_M_AXI_IC_SUPPORTS_THREADS	0
C_M_AXI_IC_THREAD_ID_WIDTH	1
C_M_AXI_IC_SUPPORTS_READ	1
C_M_AXI_IC_SUPPORTS_WRITE	0
C_M_AXI_IC_SUPPORTS_NARROW_BURST	0
C_M_AXI_IC_DATA_WIDTH	32
C_M_AXI_IC_ADDR_WIDTH	32
C_M_AXI_IC_PROTOCOL	AXI4
C_M_AXI_IC_USER_VALUE	0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_IC_AWUSER_WIDTH	5
C_M_AXI_IC_ARUSER_WIDTH	5
C_M_AXI_IC_WUSER_WIDTH	1
C_M_AXI_IC_RUSER_WIDTH	1
C_M_AXI_IC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING	2
C_DCACHE_BASEADDR	0xC0000000
C_DCACHE_HIGHADDR	0xC7FFFFFF
C_USE_DCACHE	1
C_ALLOW_DCACHE_WR	1
C_DCACHE_ADDR_TAG	17
C_DCACHE_BYTE_SIZE	16384
C_DCACHE_USE_FSL	1
C_DCACHE_LINE_LEN	4
C_DCACHE_ALWAYS_USED	1
C_DCACHE_INTERFACE	0
C_DCACHE_USE_WRITEBACK	0
C_DCACHE_VICTIMS	0
C_DCACHE_FORCE_TAG_LUTRAM	0
C_DCACHE_DATA_WIDTH	0
C_M_AXI_DC_SUPPORTS_THREADS	0
C_M_AXI_DC_THREAD_ID_WIDTH	1
C_M_AXI_DC_SUPPORTS_READ	1
C_M_AXI_DC_SUPPORTS_WRITE	1
C_M_AXI_DC_SUPPORTS_NARROW_BURST	0
C_M_AXI_DC_DATA_WIDTH	32
C_M_AXI_DC_ADDR_WIDTH	32
C_M_AXI_DC_PROTOCOL	AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS	0
C_M_AXI_DC_USER_VALUE	0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_DC_AWUSER_WIDTH	5
C_M_AXI_DC_ARUSER_WIDTH	5
C_M_AXI_DC_WUSER_WIDTH	1
C_M_AXI_DC_RUSER_WIDTH	1
C_M_AXI_DC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING	2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING	32
C_USE_MMU	0
C_MMU_DTLB_SIZE	4
C_MMU_ITLB_SIZE	2
C_MMU_TLB_ACCESS	3
C_MMU_ZONES	16
C_MMU_PRIVILEGED_INSTR	0
C_USE_INTERRUPT	0
C_USE_EXT_BRK	0
C_USE_EXT_NM_BRK	0
C_USE_BRANCH_TARGET_CACHE	0
C_BRANCH_TARGET_CACHE_SIZE	0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DC_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DP_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_R_REGISTER	1
C_INTERCONNECT_M_AXI_DP_B_REGISTER	1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DC_R_REGISTER	1
C_INTERCONNECT_M_AXI_DC_B_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_IC_W_REGISTER	1
C_INTERCONNECT_M_AXI_IC_R_REGISTER	1
C_INTERCONNECT_M_AXI_IC_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Debuggers	TOC

+
+ + +

+ + + + + + + + + +

+debug_module + MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
mdm	2.00.b	IP

+

+

debug_module IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Debug_SYS_Rst		O	1	proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
MBDEBUG_0	INITIATOR	XIL_MBDEBUG3	microblaze_0_debug			microblaze_0
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_JTAG_CHAIN	2
C_INTERCONNECT	2
C_BASEADDR	0x74800000
C_HIGHADDR	0x7480FFFF
C_SPLB_AWIDTH	32
C_SPLB_DWIDTH	32
C_SPLB_P2P	0
C_SPLB_MID_WIDTH	3
C_SPLB_NUM_MASTERS	8
C_SPLB_NATIVE_DWIDTH	32

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_SPLB_SUPPORT_BURSTS	0
C_MB_DBG_PORTS	1
C_USE_UART	1
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Interrupt Controllers	TOC

+
+ + +

+ + + + + + + + + +

+microblaze_0_intc + AXI Interrupt Controller
intc core attached to the AXI

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_intc	1.01.a	IP

+

+

microblaze_0_intc IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	IRQ		O	1	microblaze_0_interrupt
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	INTR		I	1	Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.
+Interrupt Priorities
Priority	SIG			MODULE
0	Push_Buttons_4Bits_IP2INTC_Irpt			Push_Buttons_4Bits
1	Ethernet_Lite_IP2INTC_Irpt			Ethernet_Lite
2	axi_timer_0_Interrupt			axi_timer_0
3	RS232_Uart_1_Interrupt			RS232_Uart_1

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x41200000
C_HIGHADDR	0x4120FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_NUM_INTR_INPUTS	2
C_KIND_OF_INTR	0xFFFFFFFF
C_KIND_OF_EDGE	0xFFFFFFFF
C_KIND_OF_LVL	0xFFFFFFFF
C_HAS_IPR	1
C_HAS_SIE	1

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_HAS_CIE	1
C_HAS_IVR	1
C_IRQ_IS_LEVEL	1
C_IRQ_ACTIVE	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Busses	TOC

+
+ + + + + + + + +

+ + + + + + + + + +

+axi4_0 + AXI Interconnect
AXI4 Memory-Mapped Interconnect

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

+

+

axi4_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	interconnect_aclk		I	1	clk_100_0000MHzPLL0
1	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DC
microblaze_0					MASTER	M_AXI_IC
MCB_DDR3					SLAVE	S0_AXI

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	1
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+axi4lite_0 + AXI Interconnect
AXI4 Memory-Mapped Interconnect

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

+

+

axi4lite_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
1	INTERCONNECT_ACLK		I	1	clk_50_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DP
debug_module					SLAVE	S_AXI
RS232_Uart_1					SLAVE	S_AXI
LEDs_4Bits					SLAVE	S_AXI
Push_Buttons_4Bits					SLAVE	S_AXI
Ethernet_Lite					SLAVE	S_AXI
axi_timer_0					SLAVE	S_AXI
microblaze_0_intc					SLAVE	S_AXI

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	0
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+microblaze_0_dlmb + Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

+

+

microblaze_0_dlmb IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	DLMB
microblaze_0_d_bram_ctrl					SLAVE	SLMB

+

+

+ + + + + + + + + + + + + + + + + + + + +

Parameters
+ + These are the current parameter settings for this module. + + Parameters marked with + yellow + indicate parameters set by the user. + + Parameters marked with + blue + indicate parameters set by the system. + +
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+microblaze_0_ilmb + Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

+

+

microblaze_0_ilmb IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	ILMB
microblaze_0_i_bram_ctrl					SLAVE	SLMB

+

+

+ + + + + + + + + + + + + + + + + + + + +

Parameters
+ + These are the current parameter settings for this module. + + Parameters marked with + yellow + indicate parameters set by the user. + + Parameters marked with + blue + indicate parameters set by the system. + +
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Memorys	TOC

+
+ + +

+ + + + + + + + + +

+microblaze_0_bram_block + Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
bram_block	1.00.a	IP

+

+

microblaze_0_bram_block IP Image

+ + + + + + + + + + + + + + + + + + + + + +

Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
PORTA	TARGET	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_i_bram_ctrl
PORTB	TARGET	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_d_bram_ctrl

+

+

+ + + + + + + + + + + + + + + + + + + + + + + +

Parameters
+ + These are the current parameter settings for this module. + + Parameters marked with + yellow + indicate parameters set by the user. + + Parameters marked with + blue + indicate parameters set by the system. + +
Name		Value
C_MEMSIZE		2048
C_PORT_DWIDTH		32
C_PORT_AWIDTH		32
C_NUM_WE		4
C_FAMILY		virtex2

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Memory Controllers	TOC

+
+ + + + + + +

+ + + + + + + + + +

+MCB_DDR3 + AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_s6_ddrx	1.02.a	IP

+

+

MCB_DDR3 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	mcbx_dram_clk		O	1	mcbx_dram_clk
1	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
2	mcbx_dram_cke		O	1	mcbx_dram_cke
3	mcbx_dram_odt		O	1	mcbx_dram_odt
4	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
5	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
6	mcbx_dram_we_n		O	1	mcbx_dram_we_n
7	mcbx_dram_udm		O	1	mcbx_dram_udm
8	mcbx_dram_ldm		O	1	mcbx_dram_ldm
9	mcbx_dram_ba		O	1	mcbx_dram_ba
10	mcbx_dram_addr		O	1	mcbx_dram_addr
11	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
12	mcbx_dram_dq		IO	1	mcbx_dram_dq
13	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
14	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
15	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
16	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
17	rzq		IO	1	rzq
18	zio		IO	1	zio
19	s0_axi_aclk		I	1	clk_100_0000MHzPLL0
20	ui_clk		I	1	clk_100_0000MHzPLL0
21	sysclk_2x		I	1	clk_600_0000MHzPLL0_nobuf
22	sysclk_2x_180		I	1	clk_600_0000MHz180PLL0_nobuf
23	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
24	PLL_LOCK		I	1	proc_sys_reset_0_Dcm_locked
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S0_AXI	SLAVE	AXI	axi4_0			microblaze_0

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_MCB_LOC	MEMC3
C_MCB_RZQ_LOC	K7
C_MCB_ZIO_LOC	R7
C_MCB_PERFORMANCE	STANDARD
C_BYPASS_CORE_UCF	0
C_S0_AXI_BASEADDR	0xC0000000
C_S0_AXI_HIGHADDR	0xC7FFFFFF
C_S1_AXI_BASEADDR	0xFFFFFFFF
C_S1_AXI_HIGHADDR	0x00000000
C_S2_AXI_BASEADDR	0xFFFFFFFF
C_S2_AXI_HIGHADDR	0x00000000
C_S3_AXI_BASEADDR	0xFFFFFFFF
C_S3_AXI_HIGHADDR	0x00000000
C_S4_AXI_BASEADDR	0xFFFFFFFF
C_S4_AXI_HIGHADDR	0x00000000
C_S5_AXI_BASEADDR	0xFFFFFFFF
C_S5_AXI_HIGHADDR	0x00000000
C_MEM_TYPE	DDR3
C_MEM_PARTNO	MT41J64M16XX-187E
C_MEM_BASEPARTNO	NOT_SET
C_NUM_DQ_PINS	16
C_MEM_ADDR_WIDTH	13
C_MEM_BANKADDR_WIDTH	3
C_MEM_NUM_COL_BITS	10
C_MEM_TRAS	-1
C_MEM_TRCD	-1
C_MEM_TREFI	-1
C_MEM_TRFC	-1
C_MEM_TRP	-1
C_MEM_TWR	-1
C_MEM_TRTP	-1
C_MEM_TWTR	-1
C_PORT_CONFIG	B32_B32_B32_B32
C_SKIP_IN_TERM_CAL	0
C_SKIP_IN_TERM_CAL_VALUE	NONE
C_MEMCLK_PERIOD	0
C_MEM_ADDR_ORDER	ROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT	512
C_MEM_CAS_LATENCY	6
C_SIMULATION	FALSE
C_MEM_DDR1_2_ODS	FULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR2_RTT	150OHMS
C_MEM_DDR2_DIFF_DQS_EN	YES
C_MEM_DDR2_3_PA_SR	FULL
C_MEM_DDR2_3_HIGH_TEMP_SR	NORMAL
C_MEM_DDR3_CAS_WR_LATENCY	5
C_MEM_DDR3_CAS_LATENCY	6
C_MEM_DDR3_ODS	DIV6
C_MEM_DDR3_RTT	DIV4
C_MEM_DDR3_AUTO_SR	ENABLED
C_MEM_MOBILE_PA_SR	FULL
C_MEM_MDDR_ODS	FULL
C_ARB_ALGORITHM	0
C_ARB_NUM_TIME_SLOTS	12
C_ARB_TIME_SLOT_0	0b000000000001010011
C_ARB_TIME_SLOT_1	0b000000001010011000
C_ARB_TIME_SLOT_2	0b000000010011000001
C_ARB_TIME_SLOT_3	0b000000011000001010
C_ARB_TIME_SLOT_4	0b000000000001010011
C_ARB_TIME_SLOT_5	0b000000001010011000
C_ARB_TIME_SLOT_6	0b000000010011000001
C_ARB_TIME_SLOT_7	0b000000011000001010
C_ARB_TIME_SLOT_8	0b000000000001010011
C_ARB_TIME_SLOT_9	0b000000001010011000
C_ARB_TIME_SLOT_10	0b000000010011000001
C_ARB_TIME_SLOT_11	0b000000011000001010
C_S0_AXI_ENABLE	1
C_S0_AXI_PROTOCOL	AXI4
C_S0_AXI_ID_WIDTH	4
C_S0_AXI_ADDR_WIDTH	32
C_S0_AXI_DATA_WIDTH	32
C_S0_AXI_SUPPORTS_READ	1
C_S0_AXI_SUPPORTS_WRITE	1
C_S0_AXI_SUPPORTS_NARROW_BURST	1
C_S0_AXI_REG_EN0	0x00000
C_S0_AXI_REG_EN1	0x01000
C_S0_AXI_STRICT_COHERENCY	1
C_S0_AXI_ENABLE_AP	0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE	4
C_S1_AXI_ENABLE	0
C_S1_AXI_PROTOCOL	AXI4
C_S1_AXI_ID_WIDTH	4
C_S1_AXI_ADDR_WIDTH	32
C_S1_AXI_DATA_WIDTH	32
C_S1_AXI_SUPPORTS_READ	1
C_S1_AXI_SUPPORTS_WRITE	1
C_S1_AXI_SUPPORTS_NARROW_BURST	1
C_S1_AXI_REG_EN0	0x00000
C_S1_AXI_REG_EN1	0x01000
C_S1_AXI_STRICT_COHERENCY	1
C_S1_AXI_ENABLE_AP	0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE	4
C_S2_AXI_ENABLE	0
C_S2_AXI_PROTOCOL	AXI4
C_S2_AXI_ID_WIDTH	4
C_S2_AXI_ADDR_WIDTH	32
C_S2_AXI_DATA_WIDTH	32
C_S2_AXI_SUPPORTS_READ	1
C_S2_AXI_SUPPORTS_WRITE	1
C_S2_AXI_SUPPORTS_NARROW_BURST	1
C_S2_AXI_REG_EN0	0x00000
C_S2_AXI_REG_EN1	0x01000
C_S2_AXI_STRICT_COHERENCY	1
C_S2_AXI_ENABLE_AP	0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE	4
C_S3_AXI_ENABLE	0
C_S3_AXI_PROTOCOL	AXI4
C_S3_AXI_ID_WIDTH	4
C_S3_AXI_ADDR_WIDTH	32
C_S3_AXI_DATA_WIDTH	32
C_S3_AXI_SUPPORTS_READ	1
C_S3_AXI_SUPPORTS_WRITE	1
C_S3_AXI_SUPPORTS_NARROW_BURST	1
C_S3_AXI_REG_EN0	0x00000
C_S3_AXI_REG_EN1	0x01000
C_S3_AXI_STRICT_COHERENCY	1
C_S3_AXI_ENABLE_AP	0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE	4
C_S4_AXI_ENABLE	0
C_S4_AXI_PROTOCOL	AXI4
C_S4_AXI_ID_WIDTH	4
C_S4_AXI_ADDR_WIDTH	32
C_S4_AXI_DATA_WIDTH	32
C_S4_AXI_SUPPORTS_READ	1
C_S4_AXI_SUPPORTS_WRITE	1
C_S4_AXI_SUPPORTS_NARROW_BURST	1
C_S4_AXI_REG_EN0	0x00000
C_S4_AXI_REG_EN1	0x01000
C_S4_AXI_STRICT_COHERENCY	1
C_S4_AXI_ENABLE_AP	0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE	4
C_S5_AXI_ENABLE	0
C_S5_AXI_PROTOCOL	AXI4
C_S5_AXI_ID_WIDTH	4
C_S5_AXI_ADDR_WIDTH	32
C_S5_AXI_DATA_WIDTH	32
C_S5_AXI_SUPPORTS_READ	1
C_S5_AXI_SUPPORTS_WRITE	1
C_S5_AXI_SUPPORTS_NARROW_BURST	1
C_S5_AXI_REG_EN0	0x00000
C_S5_AXI_REG_EN1	0x01000
C_S5_AXI_STRICT_COHERENCY	1
C_S5_AXI_ENABLE_AP	0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE	4
C_MCB_USE_EXTERNAL_BUFPLL	0
C_SYS_RST_PRESENT	0
C_INTERCONNECT_S0_AXI_MASTERS	microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC
C_INTERCONNECT_S0_AXI_AW_REGISTER	1
C_INTERCONNECT_S0_AXI_AR_REGISTER	1
C_INTERCONNECT_S0_AXI_W_REGISTER	1
C_INTERCONNECT_S0_AXI_R_REGISTER	1
C_INTERCONNECT_S0_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+microblaze_0_d_bram_ctrl + LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

+

+

microblaze_0_d_bram_ctrl IP Image

+ + + + + + + + + + + + + + + + + + + + + +

Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_dlmb			microblaze_0

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+microblaze_0_i_bram_ctrl + LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

+

+

microblaze_0_i_bram_ctrl IP Image

+ + + + + + + + + + + + + + + + + + + + + +

Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_ilmb			microblaze_0

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Peripherals	TOC

+
+ + + + + + + + + + +

+ + + + + + + + + +

+Ethernet_Lite + AXI 10/100 Ethernet MAC Lite
'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_ethernetlite	1.00.a	IP

+

+

Ethernet_Lite IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	PHY_MDIO		IO	1	Ethernet_Lite_MDIO
1	PHY_MDC		O	1	Ethernet_Lite_MDC
2	PHY_tx_data		O	1	Ethernet_Lite_TXD
3	PHY_tx_en		O	1	Ethernet_Lite_TX_EN
4	PHY_tx_clk		I	1	Ethernet_Lite_TX_CLK
5	PHY_col		I	1	Ethernet_Lite_COL
6	PHY_rx_data		I	1	Ethernet_Lite_RXD
7	PHY_rx_er		I	1	Ethernet_Lite_RX_ER
8	PHY_rx_clk		I	1	Ethernet_Lite_RX_CLK
9	PHY_crs		I	1	Ethernet_Lite_CRS
10	PHY_dv		I	1	Ethernet_Lite_RX_DV
11	PHY_rst_n		O	1	Ethernet_Lite_PHY_RST_N
12	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
13	IP2INTC_Irpt		O	1	Ethernet_Lite_IP2INTC_Irpt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_FAMILY	virtex6
C_BASEADDR	0x40E00000
C_HIGHADDR	0x40E0FFFF
C_S_AXI_ACLK_PERIOD_PS	10000
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_ID_WIDTH	1
C_INCLUDE_MDIO	1
C_INCLUDE_GLOBAL_BUFFERS	0
C_INCLUDE_INTERNAL_LOOPBACK	0
C_DUPLEX	1

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_TX_PING_PONG	1
C_RX_PING_PONG	1
C_INCLUDE_PHY_CONSTRAINTS	1
C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE	1
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE	1
C_S_AXI_SUPPORTS_NARROW_BURST	0
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+LEDs_4Bits + AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

+

+

LEDs_4Bits IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_O		O	1	LEDs_4Bits_TRI_O
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40020000
C_HIGHADDR	0x4002FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	0
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	0
C_DOUT_DEFAULT	0x00000000

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+Push_Buttons_4Bits + AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

+

+

Push_Buttons_4Bits IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_I		I	1	Push_Buttons_4Bits_TRI_I
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	IP2INTC_Irpt		O	1	Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40000000
C_HIGHADDR	0x4000FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	1
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	1
C_DOUT_DEFAULT	0x00000000

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+RS232_Uart_1 + AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_uartlite	1.01.a	IP

+

+

RS232_Uart_1 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	TX		O	1	RS232_Uart_1_sout
1	RX		I	1	RS232_Uart_1_sin
2	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
3	Interrupt		O	1	RS232_Uart_1_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_S_AXI_ACLK_FREQ_HZ	100000000
C_BASEADDR	0x40600000
C_HIGHADDR	0x4060FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_BAUDRATE	115200
C_DATA_BITS	8

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_USE_PARITY	0
C_ODD_PARITY	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+axi_timer_0 + AXI Timer/Counter
Timer counter with AXI interface

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
axi_timer	1.01.a	IP

+

+

axi_timer_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Interrupt		O	1	axi_timer_0_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			7 Peripherals.

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_FAMILY	virtex6
C_COUNT_WIDTH	32
C_ONE_TIMER_ONLY	0
C_TRIG0_ASSERT	1
C_TRIG1_ASSERT	1
C_GEN0_ASSERT	1
C_GEN1_ASSERT	1
C_BASEADDR	0x41C00000

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_HIGHADDR	0x41C0FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

IP	TOC

+
+ + + + +

+ + + + + + + + + +

+clock_generator_0 + Clock Generator
Clock generator for processor system.

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
clock_generator	4.01.a	IP

+

+

clock_generator_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	RST		I	1	RESET
1	CLKIN		I	1	CLK
2	CLKOUT2		O	1	clk_100_0000MHzPLL0
3	CLKOUT3		O	1	clk_50_0000MHzPLL0
4	CLKOUT0		O	1	clk_600_0000MHzPLL0_nobuf
5	CLKOUT1		O	1	clk_600_0000MHz180PLL0_nobuf
6	LOCKED		O	1	proc_sys_reset_0_Dcm_locked

+

+

+ + + + + + + +

Parameters

+ + These are the current parameter settings for this module. +

+ Parameters marked with + yellow + indicate parameters set by the user. +
+ Parameters marked with + blue + indicate parameters set by the system. + +

+ + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_FAMILY	virtex6
C_DEVICE	NOT_SET
C_PACKAGE	NOT_SET
C_SPEEDGRADE	NOT_SET
C_CLKIN_FREQ	200000000
C_CLKOUT0_FREQ	600000000
C_CLKOUT0_PHASE	0
C_CLKOUT0_GROUP	PLL0
C_CLKOUT0_BUF	FALSE
C_CLKOUT0_VARIABLE_PHASE	FALSE
C_CLKOUT1_FREQ	600000000
C_CLKOUT1_PHASE	180
C_CLKOUT1_GROUP	PLL0
C_CLKOUT1_BUF	FALSE
C_CLKOUT1_VARIABLE_PHASE	FALSE
C_CLKOUT2_FREQ	100000000
C_CLKOUT2_PHASE	0
C_CLKOUT2_GROUP	PLL0
C_CLKOUT2_BUF	TRUE
C_CLKOUT2_VARIABLE_PHASE	FALSE
C_CLKOUT3_FREQ	50000000
C_CLKOUT3_PHASE	0
C_CLKOUT3_GROUP	PLL0
C_CLKOUT3_BUF	TRUE
C_CLKOUT3_VARIABLE_PHASE	FALSE
C_CLKOUT4_FREQ	0
C_CLKOUT4_PHASE	0
C_CLKOUT4_GROUP	NONE
C_CLKOUT4_BUF	TRUE
C_CLKOUT4_VARIABLE_PHASE	FALSE
C_CLKOUT5_FREQ	0
C_CLKOUT5_PHASE	0
C_CLKOUT5_GROUP	NONE
C_CLKOUT5_BUF	TRUE
C_CLKOUT5_VARIABLE_PHASE	FALSE
C_CLKOUT6_FREQ	0
C_CLKOUT6_PHASE	0
C_CLKOUT6_GROUP	NONE
C_CLKOUT6_BUF	TRUE
C_CLKOUT6_VARIABLE_PHASE	FALSE
C_CLKOUT7_FREQ	0
C_CLKOUT7_PHASE	0
C_CLKOUT7_GROUP	NONE
C_CLKOUT7_BUF	TRUE
C_CLKOUT7_VARIABLE_PHASE	FALSE
C_CLKOUT8_FREQ	0
C_CLKOUT8_PHASE	0
C_CLKOUT8_GROUP	NONE

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Value
C_CLKOUT8_BUF	TRUE
C_CLKOUT8_VARIABLE_PHASE	FALSE
C_CLKOUT9_FREQ	0
C_CLKOUT9_PHASE	0
C_CLKOUT9_GROUP	NONE
C_CLKOUT9_BUF	TRUE
C_CLKOUT9_VARIABLE_PHASE	FALSE
C_CLKOUT10_FREQ	0
C_CLKOUT10_PHASE	0
C_CLKOUT10_GROUP	NONE
C_CLKOUT10_BUF	TRUE
C_CLKOUT10_VARIABLE_PHASE	FALSE
C_CLKOUT11_FREQ	0
C_CLKOUT11_PHASE	0
C_CLKOUT11_GROUP	NONE
C_CLKOUT11_BUF	TRUE
C_CLKOUT11_VARIABLE_PHASE	FALSE
C_CLKOUT12_FREQ	0
C_CLKOUT12_PHASE	0
C_CLKOUT12_GROUP	NONE
C_CLKOUT12_BUF	TRUE
C_CLKOUT12_VARIABLE_PHASE	FALSE
C_CLKOUT13_FREQ	0
C_CLKOUT13_PHASE	0
C_CLKOUT13_GROUP	NONE
C_CLKOUT13_BUF	TRUE
C_CLKOUT13_VARIABLE_PHASE	FALSE
C_CLKOUT14_FREQ	0
C_CLKOUT14_PHASE	0
C_CLKOUT14_GROUP	NONE
C_CLKOUT14_BUF	TRUE
C_CLKOUT14_VARIABLE_PHASE	FALSE
C_CLKOUT15_FREQ	0
C_CLKOUT15_PHASE	0
C_CLKOUT15_GROUP	NONE
C_CLKOUT15_BUF	TRUE
C_CLKOUT15_VARIABLE_PHASE	FALSE
C_CLKFBIN_FREQ	0
C_CLKFBIN_DESKEW	NONE
C_CLKFBOUT_FREQ	0
C_CLKFBOUT_PHASE	0
C_CLKFBOUT_GROUP	NONE
C_CLKFBOUT_BUF	TRUE
C_PSDONE_GROUP	NONE
C_EXT_RESET_HIGH	1
C_CLK_PRIMITIVE_FEEDBACK_BUF	FALSE
C_CLK_GEN	UPDATE

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+ + + + + + + + + +

+proc_sys_reset_0 + Processor System Reset Module
Reset management module

+

+ + + + + + + + + + +

IP Specs
Core	Version	Documentation
proc_sys_reset	3.00.a	IP

+

+

proc_sys_reset_0 IP Image

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

PORT LIST
These are the ports listed in the MHS file. + + Please refer to the IP documentation for complete information about module ports. +
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	Ext_Reset_In		I	1	RESET
1	MB_Reset		O	1	proc_sys_reset_0_MB_Reset
2	Slowest_sync_clk		I	1	clk_50_0000MHzPLL0
3	Interconnect_aresetn		O	1	proc_sys_reset_0_Interconnect_aresetn
4	Dcm_locked		I	1	proc_sys_reset_0_Dcm_locked
5	MB_Debug_Sys_Rst		I	1	proc_sys_reset_0_MB_Debug_Sys_Rst
6	BUS_STRUCT_RESET		O	1	proc_sys_reset_0_BUS_STRUCT_RESET

+

+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Parameters
+ + These are the current parameter settings for this module. + + Parameters marked with + yellow + indicate parameters set by the user. + + Parameters marked with + blue + indicate parameters set by the system. + +
Name		Value
C_SUBFAMILY		lx
C_EXT_RST_WIDTH		4
C_AUX_RST_WIDTH		4
C_EXT_RESET_HIGH		1
C_AUX_RESET_HIGH		1
C_NUM_BUS_RST		1
C_NUM_PERP_RST		1
C_NUM_INTERCONNECT_ARESETN		1
C_NUM_PERP_ARESETN		1
C_FAMILY		virtex5

+ + + + +

Post Synthesis Device Utilization
+ Device utilization information is not available for this IP. Run platgen to generate synthesis information. +

+

+

+

+

+

+ + +

Timing Information	TOC

+

+ + + +

Post Synthesis Clock Limits
+ No clocks could be identified in the design. Run platgen to generate synthesis information. +

+

+ + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html new file mode 100644 index 000000000..25287d5b0 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html @@ -0,0 +1,73 @@ + + + + +Table of Contents + + + + +

+Overview
Block Diagram
External Ports

+

Processor +

+

Debuggers +

+

Interrupt Controllers +

+ microblaze_0_intc

+

Busses +

+   axi4_0
   axi4lite_0
   microblaze_0_dlmb
   microblaze_0_ilmb

+

Memory +

+ microblaze_0_bram_block

+

Memory Controllers +

+   MCB_DDR3
   microblaze_0_d_bram_ctrl
   microblaze_0_i_bram_ctrl

+

Peripherals +

+   Ethernet_Lite
   LEDs_4Bits
   Push_Buttons_4Bits
   RS232_Uart_1
   axi_timer_0

+

IP +

+ clock_generator_0
proc_sys_reset_0
Timing Information
+

+ diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs index 3105fb7e2..59d19ccf9 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs @@ -23,10 +23,10 @@ IPNAME: axi_s6_ddrx, INSTANCE:MCB_DDR3 - tcl is overriding PARAMETER C_SYS_RST_PRESENT value to 1 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 228 -Cannot determine the input clock associated with port : microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this core and cores connected to it. +Cannot determine the input clock associated with port : microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this core and cores connected to it. -Cannot determine the input clock associated with port : microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this core and cores connected to it. +Cannot determine the input clock associated with port : microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this core and cores connected to it. IPNAME: axi_ethernetlite, INSTANCE: Ethernet_Lite - This design requires design constraints to guarantee performance. @@ -133,7 +133,7 @@ The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethe The following instances are synthesized with XST. The MPD option IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. -NCF files should not be modified as they will be regenerated. +NCF files should not be modified as they will be regenerated. If any constraint needs to be overridden, this should be done by modifying the data/system.ucf file. diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport index f1f6a0636..43e1cbae9 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport @@ -1,9 +1,9 @@

- 2011-06-17T21:48:17 + 2011-07-27T11:10:44 system - 2011-06-17T21:48:16 + 2011-07-27T11:10:42 C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport filter.filter C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml index f52b5f466..e3420a63b 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml @@ -1,4 +1,4 @@ - + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui index 73ae4b861..5738fe4d1 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui @@ -15,9 +15,10 @@ + - + @@ -36,7 +37,7 @@ - + @@ -84,7 +85,7 @@ - + @@ -100,11 +101,17 @@ + + + + - + + + @@ -121,9 +128,9 @@ - + - +