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Regenerate the EthernetLite hardware (MicroBlaze) in an attempt to get Rx working.

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Richard Barry 2011-07-27 12:08:38 +00:00
parent 1019db5850
commit fab6050ab8
11 changed files with 17198 additions and 12 deletions
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6
Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs
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@ -23,10 +23,10 @@
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_SYS_RST_PRESENT</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 228</arg>
</msg>
<msg type="info" file="EDK" num="740" delta="new" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_i_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it.
<msg type="info" file="EDK" num="740" delta="old" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_i_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it.
</msg>
<msg type="info" file="EDK" num="740" delta="new" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_d_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it.
<msg type="info" file="EDK" num="740" delta="old" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_d_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it.
</msg>
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_ethernetlite</arg>, INSTANCE: <arg fmt="%s" index="2">Ethernet_Lite</arg> - <arg fmt="%s" index="3">This design requires design constraints to guarantee performance.
@ -133,7 +133,7 @@ The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethe
<msg type="info" file="EDK" num="0" delta="new" >The following instances are synthesized with <arg fmt="%s" index="1">XST</arg>. The MPD option IMP_NETLIST=TRUE indicates that a NGC file is to be produced using <arg fmt="%s" index="2">XST</arg> synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
</msg>
<msg type="info" file="EDK" num="3509" delta="new" >NCF files should not be modified as they will be regenerated.
<msg type="info" file="EDK" num="3509" delta="old" >NCF files should not be modified as they will be regenerated.
If any constraint needs to be overridden, this should be done by modifying the data/<arg fmt="%s" index="1">system</arg>.ucf file.
</msg>

4
Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport
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@ -1,9 +1,9 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2011-06-17T21:48:17</DateModified>
<DateModified>2011-07-27T11:10:44</DateModified>
<ModuleName>system</ModuleName>
<SummaryTimeStamp>2011-06-17T21:48:16</SummaryTimeStamp>
<SummaryTimeStamp>2011-07-27T11:10:42</SummaryTimeStamp>
<SavedFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport</SavedFilePath>
<FilterFile>filter.filter</FilterFile>
<SavedFilterFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise</SavedFilterFilePath>