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rtos: Add explanatory comment for portFPU_REG_OFFSET in RISC-V port

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Explain that the initial (2 * portWORD_SIZE) offset reserves space for the
fcsr register and maintains proper memory and ABI stack alignment for both
RV32 and RV64 architectures.
This commit is contained in:
wanghengZzz 2026-07-30 14:18:00 +08:00
parent 4269c69a16
commit f006492046
1 changed files with 7 additions and 0 deletions
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7
portable/GCC/RISC-V/portContext.h
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@ -91,6 +91,13 @@
#define portFPU_REG_SIZE ( __riscv_flen / 8 )
#define portFPU_REG_COUNT 33 /* 32 Floating point registers plus one CSR. */
/*
* Reserve space at the beginning of the FPU context block for:
* 1. The FCSR (Floating-Point Control and Status Register).
* 2. Padding to ensure proper memory/stack alignment (8-byte alignment for
* RV32D, and 16-byte stack alignment mandated by the RISC-V ABI for RV64).
*/
#define portFPU_REG_OFFSET( regIndex ) ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) )
#define portFPU_CONTEXT_SIZE ( portFPU_REG_SIZE * portFPU_REG_COUNT )
#else