diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h
index 0869a82b6..eb3bed2fe 100644
--- a/portable/GCC/RISC-V/portContext.h
+++ b/portable/GCC/RISC-V/portContext.h
@@ -91,6 +91,13 @@
 
         #define portFPU_REG_SIZE                ( __riscv_flen / 8 )
         #define portFPU_REG_COUNT               33 /* 32 Floating point registers plus one CSR. */
+
+        /*
+         * Reserve space at the beginning of the FPU context block for:
+         * 1. The FCSR (Floating-Point Control and Status Register).
+         * 2. Padding to ensure proper memory/stack alignment (8-byte alignment for
+         *    RV32D, and 16-byte stack alignment mandated by the RISC-V ABI for RV64).
+         */
         #define portFPU_REG_OFFSET( regIndex )  ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) )
         #define portFPU_CONTEXT_SIZE            ( portFPU_REG_SIZE * portFPU_REG_COUNT )
     #else