made a copy

20080212/Source/portable/GCC/ARM7_AT91FR40008/port.c

@@ -0,0 +1,249 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Atmel AT91R40008
+ * port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware specific definitions. */
+#include "AT91R40008.h"
+#include "pio.h"
+#include "aic.h"
+#include "tc.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( portSTACK_TYPE ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( portSTACK_TYPE ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( portSTACK_TYPE ) 0 )
+#define portTICK_PRIORITY_6				( 6 )
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+portSTACK_TYPE *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
+
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the tick timer to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+volatile unsigned portLONG ulDummy;
+
+	/* Enable clock to the tick timer... */
+	AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
+
+	/* Stop the tick timer... */
+	portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
+
+	/* Start with tick timer interrupts disabled... */
+	portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
+
+	/* Clear any pending tick timer interrupts... */
+	ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
+
+	/* Store interrupt handler function address in tick timer vector register...
+	The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if configUSE_PREEMPTION == 1
+	{
+		extern void ( vPreemptiveTick )( void );
+		AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vPreemptiveTick;
+	}
+	#else  // else use cooperative scheduler
+	{
+		extern void ( vNonPreemptiveTick )( void );
+		AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vNonPreemptiveTick;
+	}
+	#endif
+
+	/* Tick timer interrupt level-sensitive, priority 6... */
+	AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
+
+	/* Enable the tick timer interrupt...
+
+	First at timer level */
+	portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
+
+	/* Then at the AIC level. */
+	AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
+
+	/* Calculate timer compare value to achieve the desired tick rate... */
+	if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
+	{
+		/* The tick rate is fast enough for us to use the faster timer input
+		clock (main clock / 2). */
+		portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
+		portTIMER_REG_BASE_PTR->TC_RC  = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
+	}
+	else
+	{
+		/* We must use a slower timer input clock (main clock / 8) because the
+		tick rate is too slow for the faster input clock. */
+		portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
+		portTIMER_REG_BASE_PTR->TC_RC  = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
+	}
+
+	/* Start tick timer... */
+	portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
+}
+/*-----------------------------------------------------------*/
+

20080212/Source/portable/GCC/ARM7_AT91FR40008/portISR.c

@@ -0,0 +1,246 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V3.2.4
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle interrupts. */
+#define portCLEAR_AIC_INTERRUPT		( ( unsigned portLONG ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( unsigned portLONG ) 0 )
+volatile unsigned portLONG ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/* 
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task 
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return 
+	address, but an SWI ISR does not.  Add the offset manually so the same 
+	ISR return code can be used in both cases. */
+	asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();	
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to 
+	simply increment the system tick. */
+	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+	void vNonPreemptiveTick( void )
+	{		
+	static volatile unsigned portLONG ulDummy;
+
+		/* Clear tick timer interrupt indication. */
+		ulDummy = portTIMER_REG_BASE_PTR->TC_SR;  
+
+		vTaskIncrementTick();
+
+		/* Acknowledge the interrupt at AIC level... */
+		AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
+	}
+
+#else  /* else preemption is turned on */
+
+	/* The preemptive scheduler is defined as "naked" as the full context is
+	saved on entry as part of the context switch. */
+	void vPreemptiveTick( void ) __attribute__((naked));
+	void vPreemptiveTick( void )
+	{
+		/* Save the context of the interrupted task. */
+		portSAVE_CONTEXT();	
+
+		/* WARNING - Do not use local (stack) variables here.  Use globals
+					 if you must! */
+		static volatile unsigned portLONG ulDummy;
+
+		/* Clear tick timer interrupt indication. */
+		ulDummy = portTIMER_REG_BASE_PTR->TC_SR;  
+
+		/* Increment the RTOS tick count, then look for the highest priority 
+		task that is ready to run. */
+		vTaskIncrementTick();
+		vTaskSwitchContext();
+
+		/* Acknowledge the interrupt at AIC level... */
+		AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
+
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT();
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+			
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	asm volatile ( 
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().				*/
+			asm volatile ( 
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
+

20080212/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h

@@ -0,0 +1,266 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+	Changes from V3.2.3
+	
+	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+	Changes from V3.2.4
+
+	+ Removed the use of the %0 parameter within the assembler macros and 
+	  replaced them with hard coded registers.  This will ensure the
+	  assembler does not select the link register as the temp register as
+	  was occasionally happening previously.
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+
+	Changes from V4.5.0
+
+	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+	  and replaced them with portYIELD_FROM_ISR() macro.  Application code 
+	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+	  macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned portLONG
+#define portBASE_TYPE	long
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/	
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+#define portBYTE_ALIGNMENT			4
+#define portYIELD()					asm volatile ( "SWI" )
+#define portNOP()					asm volatile ( "NOP" )
+
+/*
+ * These define the timer to use for generating the tick interrupt.
+ * They are put in this file so they can be shared between "port.c"
+ * and "portisr.c".
+ */
+#define portTIMER_REG_BASE_PTR		AT91C_BASE_TC0
+#define portTIMER_CLK_ENABLE_BIT	AT91C_PS_TC0
+#define portTIMER_AIC_CHANNEL		( ( unsigned portLONG ) 4 )
+/*-----------------------------------------------------------*/	
+
+/* Task utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile unsigned portLONG ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	asm volatile (														\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile unsigned portLONG ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	asm volatile (														\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+
+/* Critical section handling. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in 
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not 
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+	
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+			
+	#define portENABLE_INTERRUPTS()												\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+
+/*-----------------------------------------------------------*/	
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

20080212/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c

@@ -0,0 +1,51 @@
+//* ----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name           : lib_AT91SAM7X256.h
+//* Object              : AT91SAM7X256 inlined functions
+//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+//*
+//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
+//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
+//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
+//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
+//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
+//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
+//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+
+#include "AT91SAM7X256.h"
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+

20080212/Source/portable/GCC/ARM7_AT91SAM7S/port.c

@@ -0,0 +1,232 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V2.5.2
+		
+	+ ulCriticalNesting is now saved as part of the task context, as is 
+	  therefore added to the initial task stack during pxPortInitialiseStack.
+*/
+
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Processor constants. */
+#include "AT91SAM7X256.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( portSTACK_TYPE ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( portSTACK_TYPE ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( portSTACK_TYPE ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER			( ( unsigned portCHAR ) 0x01 )
+#define portPRESCALE_VALUE			0x00
+#define portINTERRUPT_ON_MATCH		( ( unsigned portLONG ) 0x01 )
+#define portRESET_COUNT_ON_MATCH	( ( unsigned portLONG ) 0x02 )
+
+/* Constants required to setup the PIT. */
+#define portPIT_CLOCK_DIVISOR			( ( unsigned portLONG ) 16 )
+#define portPIT_COUNTER_VALUE			( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS )
+
+#define portINT_LEVEL_SENSITIVE  0
+#define portPIT_ENABLE      	( ( unsigned portSHORT ) 0x1 << 24 )
+#define portPIT_INT_ENABLE     	( ( unsigned portSHORT ) 0x1 << 25 )
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+portSTACK_TYPE *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
+
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+AT91PS_PITC pxPIT = AT91C_BASE_PITC;
+
+	/* Setup the AIC for PIT interrupts.  The interrupt routine chosen depends
+	on whether the preemptive or cooperative scheduler is being used. */
+	#if configUSE_PREEMPTION == 0
+
+		extern void ( vNonPreemptiveTick ) ( void );
+		AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );
+
+	#else
+		
+		extern void ( vPreemptiveTick )( void );
+		AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );
+
+	#endif
+
+	/* Configure the PIT period. */
+	pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
+
+	/* Enable the interrupt.  Global interrupts are disables at this point so 
+	this is safe. */
+    AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
+}
+/*-----------------------------------------------------------*/
+
+
+

20080212/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c

@@ -0,0 +1,241 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V3.2.4
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "AT91SAM7X256.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( unsigned portCHAR ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( unsigned portLONG ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( unsigned portLONG ) 0 )
+volatile unsigned portLONG ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/* 
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task 
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return 
+	address, but an SWI ISR does not.  Add the offset manually so the same 
+	ISR return code can be used in both cases. */
+	asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();	
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to 
+	simply increment the system tick. */
+	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+	void vNonPreemptiveTick( void )
+	{		
+		unsigned portLONG ulDummy;
+		
+		/* Increment the tick count - which may wake some tasks but as the
+		preemptive scheduler is not being used any woken task is not given
+		processor time no matter what its priority. */
+		vTaskIncrementTick();
+		
+		/* Clear the PIT interrupt. */
+		ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+		
+		/* End the interrupt in the AIC. */
+		AT91C_BASE_AIC->AIC_EOICR = ulDummy;
+	}
+
+#else
+
+	/* The preemptive scheduler is defined as "naked" as the full context is
+	saved on entry as part of the context switch. */
+	void vPreemptiveTick( void ) __attribute__((naked));
+	void vPreemptiveTick( void )
+	{
+		/* Save the context of the current task. */
+		portSAVE_CONTEXT();			
+
+		/* Increment the tick count - this may wake a task. */
+		vTaskIncrementTick();
+
+		/* Find the highest priority task that is ready to run. */
+		vTaskSwitchContext();
+		
+		/* End the interrupt in the AIC. */
+		AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;;
+		
+		portRESTORE_CONTEXT();
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+void vPortDisableInterruptsFromThumb( void )
+{
+	asm volatile ( 
+		"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+		"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+		"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+		"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+		"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+		"BX		R14" );					/* Return back to thumb.					*/
+}
+		
+void vPortEnableInterruptsFromThumb( void )
+{
+	asm volatile ( 
+		"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
+		"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
+		"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
+		"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
+		"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+		"BX		R14" );					/* Return back to thumb.					*/
+}
+
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	asm volatile ( 
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			asm volatile ( 
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
+

20080212/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h

@@ -0,0 +1,260 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+	Changes from V3.2.3
+	
+	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+	Changes from V3.2.4
+
+	+ Removed the use of the %0 parameter within the assembler macros and 
+	  replaced them with hard coded registers.  This will ensure the
+	  assembler does not select the link register as the temp register as
+	  was occasionally happening previously.
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+
+	Changes from V4.5.0
+
+	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+	  and replaced them with portYIELD_FROM_ISR() macro.  Application code 
+	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+	  macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned portLONG
+#define portBASE_TYPE	portLONG
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/	
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+#define portBYTE_ALIGNMENT			4
+#define portNOP()					asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/	
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile unsigned portLONG ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	asm volatile (														\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile unsigned portLONG ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	asm volatile (														\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+
+#define portYIELD_FROM_ISR()		vTaskSwitchContext()
+#define portYIELD()					asm volatile ( "SWI" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in 
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not 
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+	
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+			
+	#define portENABLE_INTERRUPTS()												\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

20080212/Source/portable/GCC/ARM7_LPC2000/port.c

@@ -0,0 +1,246 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V2.5.2
+		
+	+ ulCriticalNesting is now saved as part of the task context, as is 
+	  therefore added to the initial task stack during pxPortInitialiseStack.
+
+	Changes from V3.2.2
+
+	+ Bug fix - The prescale value for the timer setup is now written to T0_PR 
+	  instead of T0_PC.  This bug would have had no effect unless a prescale 
+	  value was actually used.
+*/
+
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( portSTACK_TYPE ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( portSTACK_TYPE ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( portSTACK_TYPE ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER			( ( unsigned portCHAR ) 0x01 )
+#define portPRESCALE_VALUE			0x00
+#define portINTERRUPT_ON_MATCH		( ( unsigned portLONG ) 0x01 )
+#define portRESET_COUNT_ON_MATCH	( ( unsigned portLONG ) 0x02 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL		( ( unsigned portLONG ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT	( ( unsigned portLONG ) 0x0010 )
+#define portTIMER_VIC_ENABLE		( ( unsigned portLONG ) 0x0020 )
+
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+portSTACK_TYPE *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
+
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+unsigned portLONG ulCompareMatch;
+extern void ( vTickISR )( void );
+
+	/* A 1ms tick does not require the use of the timer prescale.  This is
+	defaulted to zero but can be used if necessary. */
+	T0_PR = portPRESCALE_VALUE;
+
+	/* Calculate the match value required for our wanted tick rate. */
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Protect against divide by zero.  Using an if() statement still results
+	in a warning - hence the #if. */
+	#if portPRESCALE_VALUE != 0
+	{
+		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+	}
+	#endif
+	T0_MR0 = ulCompareMatch;
+
+	/* Generate tick with timer 0 compare match. */
+	T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
+
+	/* Setup the VIC for the timer. */
+	VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
+	VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+	
+	/* The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+
+	VICVectAddr0 = ( portLONG ) vTickISR;
+	VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
+
+	/* Start the timer - interrupts are disabled when this function is called
+	so it is okay to do this here. */
+	T0_TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
+
+
+

20080212/Source/portable/GCC/ARM7_LPC2000/portISR.c

@@ -0,0 +1,228 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V2.5.2
+		
+	+ The critical section management functions have been changed.  These no
+	  longer modify the stack and are safe to use at all optimisation levels.
+	  The functions are now also the same for both ARM and THUMB modes.
+
+	Changes from V2.6.0
+
+	+ Removed the 'static' from the definition of vNonPreemptiveTick() to 
+	  allow the demo to link when using the cooperative scheduler.
+
+	Changes from V3.2.4
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( unsigned portCHAR ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( unsigned portLONG ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( unsigned portLONG ) 0 )
+volatile unsigned portLONG ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/* 
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task 
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return 
+	address, but an SWI ISR does not.  Add the offset manually so the same 
+	ISR return code can be used in both cases. */
+	asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();	
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The ISR used for the scheduler tick.
+ */
+void vTickISR( void ) __attribute__((naked));
+void vTickISR( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT();	
+
+	/* Increment the RTOS tick count, then look for the highest priority 
+	task that is ready to run. */
+	vTaskIncrementTick();
+
+	#if configUSE_PREEMPTION == 1
+		vTaskSwitchContext();
+	#endif
+
+	/* Ready for the next interrupt. */
+	T0_IR = portTIMER_MATCH_ISR_BIT;
+	VICVectAddr = portCLEAR_VIC_INTERRUPT;
+	
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+			
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	asm volatile ( 
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			asm volatile ( 
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}

20080212/Source/portable/GCC/ARM7_LPC2000/portmacro.h

@@ -0,0 +1,260 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+	Changes from V3.2.3
+	
+	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+	Changes from V3.2.4
+
+	+ Removed the use of the %0 parameter within the assembler macros and 
+	  replaced them with hard coded registers.  This will ensure the
+	  assembler does not select the link register as the temp register as
+	  was occasionally happening previously.
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+
+	Changes from V4.5.0
+
+	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+	  and replaced them with portYIELD_FROM_ISR() macro.  Application code 
+	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+	  macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned portLONG
+#define portBASE_TYPE	portLONG
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/	
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+#define portBYTE_ALIGNMENT			4
+#define portNOP()					asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/	
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile unsigned portLONG ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	asm volatile (														\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile unsigned portLONG ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	asm volatile (														\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+
+#define portYIELD_FROM_ISR()		vTaskSwitchContext()
+#define portYIELD()					asm volatile ( "SWI" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in 
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not 
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+	
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+			
+	#define portENABLE_INTERRUPTS()												\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

20080212/Source/portable/GCC/ARM7_LPC23xx/port.c

@@ -0,0 +1,235 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( portSTACK_TYPE ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( portSTACK_TYPE ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( portSTACK_TYPE ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER                ( ( unsigned portCHAR ) 0x01 )
+#define portPRESCALE_VALUE              0x00
+#define portINTERRUPT_ON_MATCH          ( ( unsigned portLONG ) 0x01 )
+#define portRESET_COUNT_ON_MATCH        ( ( unsigned portLONG ) 0x02 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL           ( ( unsigned portLONG ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT       ( ( unsigned portLONG ) 0x0010 )
+#define portTIMER_VIC_ENABLE            ( ( unsigned portLONG ) 0x0020 )
+
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+portSTACK_TYPE *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
+
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+unsigned portLONG ulCompareMatch;
+
+	PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);
+	T0TCR  = 2;         /* Stop and reset the timer */
+	T0CTCR = 0;         /* Timer mode               */
+	
+	/* A 1ms tick does not require the use of the timer prescale.  This is
+	defaulted to zero but can be used if necessary. */
+	T0PR = portPRESCALE_VALUE;
+
+	/* Calculate the match value required for our wanted tick rate. */
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Protect against divide by zero.  Using an if() statement still results
+	in a warning - hence the #if. */
+	#if portPRESCALE_VALUE != 0
+	{
+		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+	}
+	#endif
+	T0MR1 = ulCompareMatch;
+
+	/* Generate tick with timer 0 compare match. */
+	T0MCR  = (3 << 3);  /* Reset timer on match and generate interrupt */
+
+	/* Setup the VIC for the timer. */
+	VICIntEnable = 0x00000010;
+	
+	/* The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if configUSE_PREEMPTION == 1
+	{
+		extern void ( vPreemptiveTick )( void );
+		VICVectAddr4 = ( portLONG ) vPreemptiveTick;
+	}
+	#else
+	{
+		extern void ( vNonPreemptiveTick )( void );
+		VICVectAddr4 = ( portLONG ) vNonPreemptiveTick;
+	}
+	#endif
+
+	VICVectCntl4 = 1;
+
+	/* Start the timer - interrupts are disabled when this function is called
+	so it is okay to do this here. */
+	T0TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
+
+
+

20080212/Source/portable/GCC/ARM7_LPC23xx/portISR.c

@@ -0,0 +1,217 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( unsigned portCHAR ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( unsigned portLONG ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( unsigned portLONG ) 0 )
+volatile unsigned portLONG ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/* 
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task 
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return 
+	address, but an SWI ISR does not.  Add the offset manually so the same 
+	ISR return code can be used in both cases. */
+	asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();	
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to 
+	simply increment the system tick. */
+	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+	void vNonPreemptiveTick( void )
+	{	
+		vTaskIncrementTick();
+		T0IR = 2;
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;
+	}
+
+#else
+
+	/* The preemptive scheduler is defined as "naked" as the full context is
+	saved on entry as part of the context switch. */
+	void vPreemptiveTick( void ) __attribute__((naked));
+	void vPreemptiveTick( void )
+	{
+		/* Save the context of the interrupted task. */
+		portSAVE_CONTEXT();	
+
+		/* Increment the RTOS tick count, then look for the highest priority 
+		task that is ready to run. */
+		vTaskIncrementTick();
+		vTaskSwitchContext();
+
+		/* Ready for the next interrupt. */
+		T0IR = 2;
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;
+		
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT();
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+			
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	asm volatile ( 
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			asm volatile ( 
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}

20080212/Source/portable/GCC/ARM7_LPC23xx/portmacro.h

@@ -0,0 +1,250 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+	Changes from V3.2.3
+	
+	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+	Changes from V3.2.4
+
+	+ Removed the use of the %0 parameter within the assembler macros and 
+	  replaced them with hard coded registers.  This will ensure the
+	  assembler does not select the link register as the temp register as
+	  was occasionally happening previously.
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+
+	Changes from V4.5.0
+
+	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+	  and replaced them with portYIELD_FROM_ISR() macro.  Application code 
+	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+	  macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned portLONG
+#define portBASE_TYPE	portLONG
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/	
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+#define portBYTE_ALIGNMENT			4
+#define portNOP()					asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/	
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile unsigned portLONG ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	asm volatile (														\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile unsigned portLONG ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	asm volatile (														\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+
+#define portYIELD_FROM_ISR()		vTaskSwitchContext()
+#define portYIELD()					asm volatile ( "SWI" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in 
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not 
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+	
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+			
+	#define portENABLE_INTERRUPTS()												\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

20080212/Source/portable/GCC/ARM_CM3/port.c

@@ -0,0 +1,330 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+	Changes between V4.0.0 and V4.0.1
+
+	+ Reduced the code used to setup the initial stack frame.
+	+ The kernel no longer has to install or handle the fault interrupt.
+	
+	Change from V4.4.0:
+
+	+ Introduced usage of configKERNEL_INTERRUPT_PRIORITY macro to set the
+	  interrupt priority used by the kernel.
+*/
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is 
+defined.  The value should also ensure backward compatibility.  
+FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+	#define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL		( ( volatile unsigned portLONG *) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD		( ( volatile unsigned portLONG *) 0xe000e014 )
+#define portNVIC_INT_CTRL			( ( volatile unsigned portLONG *) 0xe000ed04 )
+#define portNVIC_SYSPRI2			( ( volatile unsigned portLONG *) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK		0x00000004
+#define portNVIC_SYSTICK_INT		0x00000002
+#define portNVIC_SYSTICK_ENABLE		0x00000001
+#define portNVIC_PENDSVSET			0x10000000
+#define portNVIC_PENDSV_PRI			( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
+#define portNVIC_SYSTICK_PRI		( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR			( 0x01000000 )
+
+/* The priority used by the kernel is assigned to a variable to make access
+from inline assembler easier. */
+const unsigned portLONG ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
+
+/* 
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Set the MSP/PSP to a known value.
+ */
+void prvSetMSP( unsigned long ulValue ) __attribute__ (( naked ));
+void prvSetPSP( unsigned long ulValue ) __attribute__ (( naked )); 
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) pxCode;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = 0;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;	/* R0 */
+	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+	*pxTopOfStack = 0x00000000; /* uxCriticalNesting. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void prvSetPSP( unsigned long ulValue )
+{
+	asm volatile( "msr psp, r0" );
+	asm volatile( "bx lr" );
+}
+/*-----------------------------------------------------------*/
+
+void prvSetMSP( unsigned long ulValue )
+{
+	asm volatile( "msr msp, r0" );
+	asm volatile( "bx lr" );
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+portBASE_TYPE xPortStartScheduler( void )
+{
+	/* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
+	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
+	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+	
+	/* Start the first task. */
+	prvSetPSP( 0 );
+	prvSetMSP( *((unsigned portLONG *) 0 ) );
+	*(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;
+
+	/* Enable interrupts */
+	portENABLE_INTERRUPTS();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the CM3 port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+void vPortYieldFromISR( void )
+{
+	/* Set a PendSV to request a context switch. */
+	*(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;
+
+	/* This function is also called in response to a Yield(), so we want
+	the yield to occur immediately. */
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* Start first task if the stack has not yet been setup. */
+	__asm volatile
+	( 
+	"	mrs r0, psp						\n"
+	"	cbz r0, no_save					\n"
+	"									\n"	/* Save the context into the TCB. */					
+	"	stmdb r0!, {r4-r11}				\n"
+	"	sub r0, #0x04					\n"
+	"	ldr r1, uxCriticalNestingConst	\n"
+	"	ldr r2, pxCurrentTCBConst		\n"
+	"	ldr r1, [r1]					\n"
+	"	ldr r2, [r2]					\n"
+	"	str r1, [r0]					\n"			
+	"	str r0, [r2]					\n"
+	"									\n"
+	"no_save:\n"	
+	"	push {r14}						\n"
+	"	bl vPortSwitchContext			\n"
+	"	pop {r14}						\n"
+	"									\n"	/* Restore the context. */	
+	"	ldr r1, pxCurrentTCBConst		\n"
+	"	ldr r1, [r1]					\n"
+	"	ldr r0, [r1]					\n"
+	"	ldmia r0!, {r1, r4-r11}			\n"
+	"	ldr r2, uxCriticalNestingConst	\n"
+	"	str r1, [r2]					\n"
+	"	msr psp, r0						\n"
+	"	orr r14, #0xd					\n"
+	"									\n"	/* Exit with interrupts in the state required by the task. */	
+	"	cbnz r1, sv_disable_interrupts	\n"
+	"	bx r14							\n"
+	"									\n"
+	"sv_disable_interrupts:				\n"
+	"	ldr r1, =ulKernelPriority 		\n"
+	"	ldr r1, [r1]					\n"
+	"	msr	basepri, r1					\n"
+	"	bx r14							\n"
+	"									\n"
+	"	.align 2						\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	"uxCriticalNestingConst: .word uxCriticalNesting	\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	extern void vTaskIncrementTick( void );
+	extern void vPortYieldFromISR( void );
+
+	/* Call the scheduler tick function. */
+	__asm volatile
+	( 
+	"	push {r14}							\n"
+	"	bl vPortIncrementTick				\n"
+	"	pop {r14}" 
+	);
+
+	/* If using preemption, also force a context switch. */
+	#if configUSE_PREEMPTION == 1
+	__asm volatile
+	( 
+	"	push {r14}							\n"
+	"	bl vPortYieldFromISR				\n"
+	"	pop {r14}" 
+	);
+	#endif
+
+	/* Exit with interrupts in the correct state. */
+	__asm volatile
+	(
+	"    ldr r2, uxCriticalNestingConst2	\n" 
+	"    ldr r2, [r2]						\n"
+	"    cbnz r2, tick_disable_interrupts	\n"
+	"    bx r14" 
+	);
+
+   __asm volatile
+   (
+	"tick_disable_interrupts:				\n"
+	"	ldr r1, =ulKernelPriority 			\n"
+	"	ldr r1, [r1]						\n"
+	"	msr	basepri, r1						\n"
+	"    bx r14								\n"
+	"										\n"
+	"	.align 2							\n"
+	"uxCriticalNestingConst2: .word uxCriticalNesting"
+	);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+	/* Configure SysTick to interrupt at the requested rate. */
+	*(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+	*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSwitchContext( void )
+{
+	vPortSetInterruptMask();
+	vTaskSwitchContext();
+	vPortClearInterruptMask();
+}
+/*-----------------------------------------------------------*/
+
+void vPortIncrementTick( void )
+{
+	vPortSetInterruptMask();
+	vTaskIncrementTick();
+	vPortClearInterruptMask();
+}
+
+/*-----------------------------------------------------------*/
+

20080212/Source/portable/GCC/ARM_CM3/portmacro.h

@@ -0,0 +1,148 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+	Change from V4.4.0:
+
+	+ Introduced usage of configKERNEL_INTERRUPT_PRIORITY macro to set the
+	  interrupt priority used by the kernel.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned portLONG
+#define portBASE_TYPE	long
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/	
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+#define portBYTE_ALIGNMENT			4
+/*-----------------------------------------------------------*/	
+
+
+/* Scheduler utilities. */
+extern void vPortYieldFromISR( void );
+
+#define portYIELD()					vPortYieldFromISR()
+
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+#define vPortSetInterruptMask()							\
+	__asm volatile										\
+	(													\
+		"	push { r0 }								\n"	\
+		"	ldr r0, =ulKernelPriority 				\n"	\
+		"	ldr r0, [r0]							\n"	\
+		"	msr basepri, r0							\n" \
+		"	pop { r0 }								"	\
+	)
+	
+/*-----------------------------------------------------------*/
+
+#define vPortClearInterruptMask()						\
+	__asm volatile										\
+	(													\
+		"	push { r0 }								\n"	\
+		"	mov r0, #0								\n"	\
+		"	msr basepri, r0							\n"	\
+		"	pop	 { r0 }								"	\
+	)
+
+/*-----------------------------------------------------------*/
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	vPortSetInterruptMask();
+#define portENABLE_INTERRUPTS()		vPortClearInterruptMask();
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define inline
+#define portNOP()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

20080212/Source/portable/GCC/ATMega323/port.c

@@ -0,0 +1,439 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/* 
+
+Changes from V2.6.0
+
+	+ AVR port - Replaced the inb() and outb() functions with direct memory
+	  access.  This allows the port to be built with the 20050414 build of
+	  WinAVR.
+*/
+
+#include <stdlib.h>
+#include <avr/interrupt.h>
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the AVR port.
+ *----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED					( ( portSTACK_TYPE ) 0x80 )
+
+/* Hardware constants for timer 1. */
+#define portCLEAR_COUNTER_ON_MATCH				( ( unsigned portCHAR ) 0x08 )
+#define portPRESCALE_64							( ( unsigned portCHAR ) 0x03 )
+#define portCLOCK_PRESCALER						( ( unsigned portLONG ) 64 )
+#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE	( ( unsigned portCHAR ) 0x10 )
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void tskTCB;
+extern volatile tskTCB * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Macro to save all the general purpose registers, the save the stack pointer
+ * into the TCB.  
+ * 
+ * The first thing we do is save the flags then disable interrupts.  This is to 
+ * guard our stack against having a context switch interrupt after we have already 
+ * pushed the registers onto the stack - causing the 32 registers to be on the 
+ * stack twice. 
+ * 
+ * r1 is set to zero as the compiler expects it to be thus, however some
+ * of the math routines make use of R1. 
+ * 
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
+ * so we need not worry about reading/writing to the stack pointer. 
+ */
+
+#define portSAVE_CONTEXT()									\
+	asm volatile (	"push	r0						\n\t"	\
+					"in		r0, __SREG__			\n\t"	\
+					"cli							\n\t"	\
+					"push	r0						\n\t"	\
+					"push	r1						\n\t"	\
+					"clr	r1						\n\t"	\
+					"push	r2						\n\t"	\
+					"push	r3						\n\t"	\
+					"push	r4						\n\t"	\
+					"push	r5						\n\t"	\
+					"push	r6						\n\t"	\
+					"push	r7						\n\t"	\
+					"push	r8						\n\t"	\
+					"push	r9						\n\t"	\
+					"push	r10						\n\t"	\
+					"push	r11						\n\t"	\
+					"push	r12						\n\t"	\
+					"push	r13						\n\t"	\
+					"push	r14						\n\t"	\
+					"push	r15						\n\t"	\
+					"push	r16						\n\t"	\
+					"push	r17						\n\t"	\
+					"push	r18						\n\t"	\
+					"push	r19						\n\t"	\
+					"push	r20						\n\t"	\
+					"push	r21						\n\t"	\
+					"push	r22						\n\t"	\
+					"push	r23						\n\t"	\
+					"push	r24						\n\t"	\
+					"push	r25						\n\t"	\
+					"push	r26						\n\t"	\
+					"push	r27						\n\t"	\
+					"push	r28						\n\t"	\
+					"push	r29						\n\t"	\
+					"push	r30						\n\t"	\
+					"push	r31						\n\t"	\
+					"lds	r26, pxCurrentTCB		\n\t"	\
+					"lds	r27, pxCurrentTCB + 1	\n\t"	\
+					"in		r0, 0x3d				\n\t"	\
+					"st		x+, r0					\n\t"	\
+					"in		r0, 0x3e				\n\t"	\
+					"st		x+, r0					\n\t"	\
+				);
+
+/* 
+ * Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
+ * the context save so we can write to the stack pointer. 
+ */
+
+#define portRESTORE_CONTEXT()								\
+	asm volatile (	"lds	r26, pxCurrentTCB		\n\t"	\
+					"lds	r27, pxCurrentTCB + 1	\n\t"	\
+					"ld		r28, x+					\n\t"	\
+					"out	__SP_L__, r28			\n\t"	\
+					"ld		r29, x+					\n\t"	\
+					"out	__SP_H__, r29			\n\t"	\
+					"pop	r31						\n\t"	\
+					"pop	r30						\n\t"	\
+					"pop	r29						\n\t"	\
+					"pop	r28						\n\t"	\
+					"pop	r27						\n\t"	\
+					"pop	r26						\n\t"	\
+					"pop	r25						\n\t"	\
+					"pop	r24						\n\t"	\
+					"pop	r23						\n\t"	\
+					"pop	r22						\n\t"	\
+					"pop	r21						\n\t"	\
+					"pop	r20						\n\t"	\
+					"pop	r19						\n\t"	\
+					"pop	r18						\n\t"	\
+					"pop	r17						\n\t"	\
+					"pop	r16						\n\t"	\
+					"pop	r15						\n\t"	\
+					"pop	r14						\n\t"	\
+					"pop	r13						\n\t"	\
+					"pop	r12						\n\t"	\
+					"pop	r11						\n\t"	\
+					"pop	r10						\n\t"	\
+					"pop	r9						\n\t"	\
+					"pop	r8						\n\t"	\
+					"pop	r7						\n\t"	\
+					"pop	r6						\n\t"	\
+					"pop	r5						\n\t"	\
+					"pop	r4						\n\t"	\
+					"pop	r3						\n\t"	\
+					"pop	r2						\n\t"	\
+					"pop	r1						\n\t"	\
+					"pop	r0						\n\t"	\
+					"out	__SREG__, r0			\n\t"	\
+					"pop	r0						\n\t"	\
+				);
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from timer 1, compare match A.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+unsigned portSHORT usAddress;
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+
+	/* Simulate how the stack would look after a call to vPortYield() generated by 
+	the compiler. */
+
+	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+	/* The start of the task code will be popped off the stack last, so place
+	it on first. */
+	usAddress = ( unsigned portSHORT ) pxCode;
+	*pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );
+	pxTopOfStack--;
+
+	usAddress >>= 8;
+	*pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );
+	pxTopOfStack--;
+
+	/* Next simulate the stack as if after a call to portSAVE_CONTEXT().  
+	portSAVE_CONTEXT places the flags on the stack immediately after r0
+	to ensure the interrupts get disabled as soon as possible, and so ensuring
+	the stack use is minimal should a context switch interrupt occur. */
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x00;	/* R0 */
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+
+	/* Now the remaining registers.   The compiler expects R1 to be 0. */
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x00;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x02;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x03;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x04;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x05;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x06;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x07;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x08;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x09;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x10;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x11;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x12;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x13;	/* R13 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x14;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x15;	/* R15 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x16;	/* R16 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x17;	/* R17 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x18;	/* R18 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x19;	/* R19 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x20;	/* R20 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x21;	/* R21 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x22;	/* R22 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x23;	/* R23 */
+	pxTopOfStack--;
+
+	/* Place the parameter on the stack in the expected location. */
+	usAddress = ( unsigned portSHORT ) pvParameters;
+	*pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );
+	pxTopOfStack--;
+
+	usAddress >>= 8;
+	*pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff );
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x26;	/* R26 X */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x27;	/* R27 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x28;	/* R28 Y */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x29;	/* R29 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x30;	/* R30 Z */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x031;	/* R31 */
+	pxTopOfStack--;
+
+	/*lint +e950 +e611 +e923 */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT();
+
+	/* Simulate a function call end as generated by the compiler.  We will now
+	jump to the start of the task the context of which we have just restored. */
+	asm volatile ( "ret" );
+
+	/* Should not get here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the AVR port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__ ( ( naked ) );
+void vPortYield( void )
+{
+	portSAVE_CONTEXT();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT();
+
+	asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch function used by the tick.  This must be identical to 
+ * vPortYield() from the call to vTaskSwitchContext() onwards.  The only
+ * difference from vPortYield() is the tick count is incremented as the
+ * call comes from the tick ISR.
+ */
+void vPortYieldFromTick( void ) __attribute__ ( ( naked ) );
+void vPortYieldFromTick( void )
+{
+	portSAVE_CONTEXT();
+	vTaskIncrementTick();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT();
+
+	asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer 1 compare match A to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+unsigned portLONG ulCompareMatch;
+unsigned portCHAR ucHighByte, ucLowByte;
+
+	/* Using 16bit timer 1 to generate the tick.  Correct fuses must be
+	selected for the configCPU_CLOCK_HZ clock. */
+
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* We only have 16 bits so have to scale to get our required tick rate. */
+	ulCompareMatch /= portCLOCK_PRESCALER;
+
+	/* Adjust for correct value. */
+	ulCompareMatch -= ( unsigned portLONG ) 1;
+
+	/* Setup compare match value for compare match A.  Interrupts are disabled 
+	before this is called so we need not worry here. */
+	ucLowByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff );
+	ulCompareMatch >>= 8;
+	ucHighByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff );
+	OCR1AH = ucHighByte;
+	OCR1AL = ucLowByte;
+
+	/* Setup clock source and compare match behaviour. */
+	ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
+	TCCR1B = ucLowByte;
+
+	/* Enable the interrupt - this is okay as interrupt are currently globally
+	disabled. */
+	ucLowByte = TIMSK;
+	ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+	TIMSK = ucLowByte;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+	/*
+	 * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+	 * the context is saved at the start of vPortYieldFromTick().  The tick
+	 * count is incremented after the context is saved.
+	 */
+	void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal, naked ) );
+	void SIG_OUTPUT_COMPARE1A( void )
+	{
+		vPortYieldFromTick();
+		asm volatile ( "reti" );
+	}
+#else
+
+	/*
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 */
+	void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal ) );
+	void SIG_OUTPUT_COMPARE1A( void )
+	{
+		vTaskIncrementTick();
+	}
+#endif
+
+
+	

20080212/Source/portable/GCC/ATMega323/portmacro.h

@@ -0,0 +1,118 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+Changes from V1.2.3
+
+	+ portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it 
+	  base 16.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	unsigned portCHAR
+#define portBASE_TYPE	char
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/	
+
+/* Critical section management. */
+#define portENTER_CRITICAL()		asm volatile ( "in		__tmp_reg__, __SREG__" :: );	\
+									asm volatile ( "cli" :: );								\
+									asm volatile ( "push	__tmp_reg__" :: )
+
+#define portEXIT_CRITICAL()			asm volatile ( "pop		__tmp_reg__" :: );				\
+									asm volatile ( "out		__SREG__, __tmp_reg__" :: )
+
+#define portDISABLE_INTERRUPTS()	asm volatile ( "cli" :: );
+#define portENABLE_INTERRUPTS()		asm volatile ( "sei" :: );
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+#define portBYTE_ALIGNMENT			1
+#define portNOP()					asm volatile ( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD()					vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

20080212/Source/portable/GCC/AVR32_UC3/exception.S

@@ -0,0 +1,297 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Exception and interrupt vectors.
+ *
+ * This file maps all events supported by an AVR32UC.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32UC devices with an INTC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <avr32/io.h>
+#include "intc.h"
+
+
+//! @{
+//! \verbatim
+
+
+  .section  .exception, "ax", @progbits
+
+
+// Start of Exception Vector Table.
+
+  // EVBA must be aligned with a power of two strictly greater than the EVBA-
+  // relative offset of the last vector.
+  .balign 0x200
+
+  // Export symbol.
+  .global _evba
+  .type _evba, @function
+_evba:
+
+        .org  0x000
+        // Unrecoverable Exception.
+_handle_Unrecoverable_Exception:
+        rjmp $
+
+        .org  0x004
+        // TLB Multiple Hit: UNUSED IN AVR32UC.
+_handle_TLB_Multiple_Hit:
+        rjmp $
+
+        .org  0x008
+        // Bus Error Data Fetch.
+_handle_Bus_Error_Data_Fetch:
+        rjmp $
+
+        .org  0x00C
+         // Bus Error Instruction Fetch.
+_handle_Bus_Error_Instruction_Fetch:
+        rjmp $
+
+        .org  0x010
+        // NMI.
+_handle_NMI:
+        rjmp $
+
+        .org  0x014
+        // Instruction Address.
+_handle_Instruction_Address:
+        rjmp $
+
+        .org  0x018
+        // ITLB Protection.
+_handle_ITLB_Protection:
+        rjmp $
+
+        .org  0x01C
+        // Breakpoint.
+_handle_Breakpoint:
+        rjmp $
+
+        .org  0x020
+        // Illegal Opcode.
+_handle_Illegal_Opcode:
+        rjmp $
+
+        .org  0x024
+        // Unimplemented Instruction.
+_handle_Unimplemented_Instruction:
+        rjmp $
+
+        .org  0x028
+        // Privilege Violation.
+_handle_Privilege_Violation:
+        rjmp $
+
+        .org  0x02C
+        // Floating-Point: UNUSED IN AVR32UC.
+_handle_Floating_Point:
+        rjmp $
+
+        .org  0x030
+        // Coprocessor Absent: UNUSED IN AVR32UC.
+_handle_Coprocessor_Absent:
+        rjmp $
+
+        .org  0x034
+        // Data Address (Read).
+_handle_Data_Address_Read:
+        rjmp $
+
+        .org  0x038
+        // Data Address (Write).
+_handle_Data_Address_Write:
+        rjmp $
+
+        .org  0x03C
+        // DTLB Protection (Read).
+_handle_DTLB_Protection_Read:
+        rjmp $
+
+        .org  0x040
+        // DTLB Protection (Write).
+_handle_DTLB_Protection_Write:
+        rjmp $
+
+        .org  0x044
+        // DTLB Modified: UNUSED IN AVR32UC.
+_handle_DTLB_Modified:
+        rjmp $
+
+        .org  0x050
+        // ITLB Miss: UNUSED IN AVR32UC.
+_handle_ITLB_Miss:
+        rjmp $
+
+        .org  0x060
+        // DTLB Miss (Read): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Read:
+        rjmp $
+
+        .org  0x070
+        // DTLB Miss (Write): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Write:
+        rjmp $
+
+        .org  0x100
+        // Supervisor Call.
+_handle_Supervisor_Call:
+        lda.w   pc, SCALLYield
+
+
+// Interrupt support.
+// The interrupt controller must provide the offset address relative to EVBA.
+// Important note:
+//   All interrupts call a C function named _get_interrupt_handler.
+//   This function will read group and interrupt line number to then return in
+//   R12 a pointer to a user-provided interrupt handler.
+
+  .balign 4
+
+_int0:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int0_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int0_normal:
+#endif
+  mov     r12, 0  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int1:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int1_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int1_normal:
+#endif
+  mov     r12, 1  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int2:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int2_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int2_normal:
+#endif
+  mov     r12, 2  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int3:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int3_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int3_normal:
+#endif
+  mov     r12, 3  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+
+// Constant data area.
+
+  .balign 4
+
+  // Values to store in the interrupt priority registers for the various interrupt priority levels.
+  // The interrupt priority registers contain the interrupt priority level and
+  // the EVBA-relative interrupt vector offset.
+  .global ipr_val
+  .type ipr_val, @object
+ipr_val:
+  .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
+        (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
+        (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
+        (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
+
+
+//! \endverbatim
+//! @}

20080212/Source/portable/GCC/AVR32_UC3/port.c

@@ -0,0 +1,450 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port source for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+/* Standard includes. */
+#include <sys/cpu.h>
+#include <sys/usart.h>
+#include <malloc.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* AVR32 UC3 includes. */
+#include <avr32/io.h>
+#include "gpio.h"
+#if( configTICK_USE_TC==1 )
+	#include "tc.h"
+#endif
+
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SR            ( ( portSTACK_TYPE ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
+#define portINSTRUCTION_SIZE      ( ( portSTACK_TYPE ) 0 )
+
+/* Each task maintains its own critical nesting variable. */
+#define portNO_CRITICAL_NESTING   ( ( unsigned portLONG ) 0 )
+volatile unsigned portLONG ulCriticalNesting = 9999UL;
+
+#if( configTICK_USE_TC==0 )
+	static void prvScheduleNextTick( void );
+#else
+	static void prvClearTcInt( void );
+#endif
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Low-level initialization routine called during startup, before the main
+ * function.
+ * This version comes in replacement to the default one provided by Newlib.
+ * Newlib's _init_startup only calls init_exceptions, but Newlib's exception
+ * vectors are not compatible with the SCALL management in the current FreeRTOS
+ * port. More low-level initializations are besides added here.
+ */
+void _init_startup(void)
+{
+	/* Import the Exception Vector Base Address. */
+	extern void _evba;
+
+	#if configHEAP_INIT
+		extern void __heap_start__;
+		extern void __heap_end__;
+		portBASE_TYPE *pxMem;
+	#endif
+
+	/* Load the Exception Vector Base Address in the corresponding system register. */
+	Set_system_register( AVR32_EVBA, ( int ) &_evba );
+
+	/* Enable exceptions. */
+	ENABLE_ALL_EXCEPTIONS();
+
+	/* Initialize interrupt handling. */
+	INTC_init_interrupts();
+
+	#if configHEAP_INIT
+
+		/* Initialize the heap used by malloc. */
+		for( pxMem = &__heap_start__; pxMem < ( portBASE_TYPE * )&__heap_end__; )
+		{
+			*pxMem++ = 0xA5A5A5A5;
+		}
+
+	#endif
+
+	/* Give the used CPU clock frequency to Newlib, so it can work properly. */
+	set_cpu_hz( configCPU_CLOCK_HZ );
+
+	/* Code section present if and only if the debug trace is activated. */
+	#if configDBG
+	{
+		static const gpio_map_t DBG_USART_GPIO_MAP =
+		{
+			{ configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
+			{ configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
+		};
+
+		/* Initialize the USART used for the debug trace with the configured parameters. */
+		set_usart_base( ( void * ) configDBG_USART );
+		gpio_enable_module( DBG_USART_GPIO_MAP,
+		                    sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
+		usart_init( configDBG_USART_BAUDRATE );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * malloc, realloc and free are meant to be called through respectively
+ * pvPortMalloc, pvPortRealloc and vPortFree.
+ * The latter functions call the former ones from within sections where tasks
+ * are suspended, so the latter functions are task-safe. __malloc_lock and
+ * __malloc_unlock use the same mechanism to also keep the former functions
+ * task-safe as they may be called directly from Newlib's functions.
+ * However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE
+ * CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do
+ * not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable
+ * interrupts during memory allocation management as this may be a very time-
+ * consuming process.
+ */
+
+/*
+ * Lock routine called by Newlib on malloc / realloc / free entry to guarantee a
+ * safe section as memory allocation management uses global data.
+ * See the aforementioned details.
+ */
+void __malloc_lock(struct _reent *ptr)
+{
+	vTaskSuspendAll();
+}
+
+/*
+ * Unlock routine called by Newlib on malloc / realloc / free exit to guarantee
+ * a safe section as memory allocation management uses global data.
+ * See the aforementioned details.
+ */
+void __malloc_unlock(struct _reent *ptr)
+{
+	xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+/* Added as there is no such function in FreeRTOS. */
+void *pvPortRealloc( void *pv, size_t xWantedSize )
+{
+void *pvReturn;
+
+	vTaskSuspendAll();
+	{
+		pvReturn = realloc( pv, xWantedSize );
+	}
+	xTaskResumeAll();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+/* The cooperative scheduler requires a normal IRQ service routine to
+simply increment the system tick. */
+/* The preemptive scheduler is defined as "naked" as the full context is saved
+on entry as part of the context switch. */
+__attribute__((__naked__)) static void vTick( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT_OS_INT();
+
+	#if( configTICK_USE_TC==1 )
+		/* Clear the interrupt flag. */
+		prvClearTcInt();
+	#else
+		/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+		clock cycles from now. */
+		prvScheduleNextTick();
+	#endif
+
+	/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+	calls in a critical section . */
+	portENTER_CRITICAL();
+		vTaskIncrementTick();
+	portEXIT_CRITICAL();
+
+	/* Restore the context of the "elected task". */
+	portRESTORE_CONTEXT_OS_INT();
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((__naked__)) void SCALLYield( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT_SCALL();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT_SCALL();
+}
+/*-----------------------------------------------------------*/
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+__attribute__((__noinline__)) void vPortEnterCritical( void )
+{
+	/* Disable interrupts */
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	 directly.  Increment ulCriticalNesting to keep a count of how many times
+	 portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((__noinline__)) void vPortExitCritical( void )
+{
+	if(ulCriticalNesting > portNO_CRITICAL_NESTING)
+	{
+		ulCriticalNesting--;
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable all interrupt/exception. */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* When the task starts, it will expect to find the function parameter in R12. */
+	pxTopOfStack--;
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808;					/* R8 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909;					/* R9 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A;					/* R10 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B;					/* R11 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters;					/* R12 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF;					/* R14/LR */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR;				/* SR */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF;					/* R0 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101;					/* R1 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202;					/* R2 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303;					/* R3 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404;					/* R4 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505;					/* R5 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606;					/* R6 */
+	*pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707;					/* R7 */
+	*pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING;			/* ulCriticalNesting */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the AVR32 port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+clock cycles from now. */
+#if( configTICK_USE_TC==0 )
+	static void prvScheduleFirstTick(void)
+	{
+		unsigned long lCycles;
+
+		lCycles = Get_system_register(AVR32_COUNT);
+		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+		// generation feature does not get disabled.
+		if(0 == lCycles)
+		{
+			lCycles++;
+		}
+		Set_system_register(AVR32_COMPARE, lCycles);
+	}
+	
+	__attribute__((__noinline__)) static void prvScheduleNextTick(void)
+	{
+		unsigned long lCycles, lCount;
+
+		lCycles = Get_system_register(AVR32_COMPARE);
+		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+		// generation feature does not get disabled.
+		if(0 == lCycles)
+		{
+			lCycles++;
+		}
+		lCount = Get_system_register(AVR32_COUNT);
+		if( lCycles < lCount )
+		{		// We missed a tick, recover for the next.
+			lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		}
+		Set_system_register(AVR32_COMPARE, lCycles);
+	}
+#else
+	__attribute__((__noinline__)) static void prvClearTcInt(void)
+	{
+		AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt(void)
+{
+#if( configTICK_USE_TC==1 )
+
+	volatile avr32_tc_t *tc = &AVR32_TC;
+
+	// Options for waveform genration.
+	tc_waveform_opt_t waveform_opt =
+	{
+	.channel  = configTICK_TC_CHANNEL,             /* Channel selection. */
+
+	.bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */
+	.beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */
+	.bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */
+	.bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */
+
+	.aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */
+	.aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */
+	.acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */
+	.acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
+
+	.wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
+	.enetrg   = FALSE,                             /* External event trigger enable. */
+	.eevt     = 0,                                 /* External event selection. */
+	.eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */
+	.cpcdis   = FALSE,                             /* Counter disable when RC compare. */
+	.cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */
+
+	.burst    = FALSE,                             /* Burst signal selection. */
+	.clki     = FALSE,                             /* Clock inversion. */
+	.tcclks   = TC_CLOCK_SOURCE_TC2                /* Internal source clock 2. */
+	};
+
+	tc_interrupt_t tc_interrupt =
+	{
+		.etrgs=0,
+		.ldrbs=0,
+		.ldras=0,
+		.cpcs =1,
+		.cpbs =0,
+		.cpas =0,
+		.lovrs=0,
+		.covfs=0,
+	};
+
+#endif
+
+	/* Disable all interrupt/exception. */
+	portDISABLE_INTERRUPTS();
+
+	/* Register the compare interrupt handler to the interrupt controller and
+	enable the compare interrupt. */
+
+	#if( configTICK_USE_TC==1 )
+	{
+		INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
+
+		/* Initialize the timer/counter. */
+		tc_init_waveform(tc, &waveform_opt);
+
+		/* Set the compare triggers.
+		Remember TC counter is 16-bits, so counting second is not possible!
+		That's why we configure it to count ms. */
+		tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
+
+		tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
+
+		/* Start the timer/counter. */
+		tc_start(tc, configTICK_TC_CHANNEL);
+	}
+	#else
+	{
+		INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
+		prvScheduleFirstTick();
+	}
+	#endif
+}

20080212/Source/portable/GCC/AVR32_UC3/portmacro.h

@@ -0,0 +1,678 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port source for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+#include <avr32/io.h>
+#include "intc.h"
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  unsigned portLONG
+#define portBASE_TYPE   portLONG
+
+#define TASK_DELAY_MS(x)   ( (x)        /portTICK_RATE_MS )
+#define TASK_DELAY_S(x)    ( (x)*1000   /portTICK_RATE_MS )
+#define TASK_DELAY_MIN(x)  ( (x)*60*1000/portTICK_RATE_MS )
+
+#define configTICK_TC_IRQ             ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_RATE_MS      ( ( portTickType ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    4
+#define portNOP()             {__asm__ __volatile__ ("nop");}
+/*-----------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------*/
+
+/* INTC-specific. */
+#define DISABLE_ALL_EXCEPTIONS()    Disable_global_exception()
+#define ENABLE_ALL_EXCEPTIONS()     Enable_global_exception()
+
+#define DISABLE_ALL_INTERRUPTS()    Disable_global_interrupt()
+#define ENABLE_ALL_INTERRUPTS()     Enable_global_interrupt()
+
+#define DISABLE_INT_LEVEL(int_lev)  Disable_interrupt_level(int_lev)
+#define ENABLE_INT_LEVEL(int_lev)   Enable_interrupt_level(int_lev)
+
+
+/*
+ * Debug trace.
+ * Activated if and only if configDBG is nonzero.
+ * Prints a formatted string to stdout.
+ * The current source file name and line number are output with a colon before
+ * the formatted string.
+ * A carriage return and a linefeed are appended to the output.
+ * stdout is redirected to the USART configured by configDBG_USART.
+ * The parameters are the same as for the standard printf function.
+ * There is no return value.
+ * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
+ * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
+ */
+#if configDBG
+#define portDBG_TRACE(...) \
+{\
+  fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
+  printf(__VA_ARGS__);\
+  fputs("\r\n", stdout);\
+}
+#else
+#define portDBG_TRACE(...)
+#endif
+
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS()  DISABLE_ALL_INTERRUPTS()
+#define portENABLE_INTERRUPTS()   ENABLE_ALL_INTERRUPTS()
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()      vPortEnterCritical();
+#define portEXIT_CRITICAL()       vPortExitCritical();
+
+
+/* Added as there is no such function in FreeRTOS. */
+extern void *pvPortRealloc( void *pv, size_t xSize );
+/*-----------------------------------------------------------*/
+
+
+/*=============================================================================================*/
+
+/*
+ * Restore Context for cases other than INTi.
+ */
+#define portRESTORE_CONTEXT()															\
+{																						\
+  extern volatile unsigned portLONG ulCriticalNesting;									\
+  extern volatile void *volatile pxCurrentTCB;											\
+																						\
+  __asm__ __volatile__ (																\
+    /* Set SP to point to new stack */													\
+    "mov     r8, LO(%[pxCurrentTCB])													\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])													\n\t"\
+    "ld.w    r0, r8[0]																	\n\t"\
+    "ld.w    sp, r0[0]																	\n\t"\
+																						\
+    /* Restore ulCriticalNesting variable */											\
+    "ld.w    r0, sp++																	\n\t"\
+    "mov     r8, LO(%[ulCriticalNesting])												\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])												\n\t"\
+    "st.w    r8[0], r0																	\n\t"\
+																						\
+    /* Restore R0..R7 */																\
+    "ldm     sp++, r0-r7																\n\t"\
+    /* R0-R7 should not be used below this line */										\
+    /* Skip PC and SR (will do it at the end) */										\
+    "sub     sp, -2*4																	\n\t"\
+    /* Restore R8..R12 and LR */														\
+    "ldm     sp++, r8-r12, lr															\n\t"\
+    /* Restore SR */																	\
+    "ld.w    r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */					\
+    "mtsr    %[SR], r0																	\n\t"\
+    /* Restore r0 */																	\
+    "ld.w    r0, sp[-9*4]																\n\t"\
+    /* Restore PC */																	\
+    "ld.w    pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */		\
+    :																					\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),										\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),												\
+      [SR] "i" (AVR32_SR)																\
+  );																					\
+}
+
+
+/*
+ * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
+ * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
+ *
+ * Had to make different versions because registers saved on the system stack
+ * are not the same between INT0..3 exceptions and the scall exception.
+ */
+
+// Task context stack layout:
+  // R8  (*)
+  // R9  (*)
+  // R10 (*)
+  // R11 (*)
+  // R12 (*)
+  // R14/LR (*)
+  // R15/PC (*)
+  // SR (*)
+  // R0
+  // R1
+  // R2
+  // R3
+  // R4
+  // R5
+  // R6
+  // R7
+  // ulCriticalNesting
+// (*) automatically done for INT0..INT3, but not for SCALL
+
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT()														\
+{																						\
+  /* Save R0..R7 */																		\
+  __asm__ __volatile__ ("stm     --sp, r0-r7");											\
+																						\
+  /* With the cooperative scheduler, as there is no context switch by interrupt, */		\
+  /* there is also no context save. */													\
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT()													\
+{																						\
+  __asm__ __volatile__ (																\
+    /* Restore R0..R7 */																\
+    "ldm     sp++, r0-r7\n\t"															\
+																						\
+    /* With the cooperative scheduler, as there is no context switch by interrupt, */	\
+    /* there is also no context restore. */												\
+    "rete"																				\
+  );																					\
+}
+
+#else
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT()																	\
+{																									\
+  extern volatile unsigned portLONG ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* When we come here */																			\
+  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */					\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Save R0..R7 */																				\
+    "stm     --sp, r0-r7																			\n\t"\
+																									\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
+    "mov     r8, LO(%[ulCriticalNesting])\n\t"														\
+    "orh     r8, HI(%[ulCriticalNesting])\n\t"														\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    --sp, r0																				\n\t"\
+																									\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case we don't want to do a task switch because we don't know what the stack */		\
+    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
+    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
+    /* will just be restoring the interrupt handler, no way!!! */									\
+    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
+    "ld.w    r0, sp[9*4]\n\t" /* Read SR in stack */												\
+    "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */									\
+    "cp.w    r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */						\
+    "brhi    LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]													\n\t"\
+																									\
+    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
+    /* NOTE: we don't enter a critical section here because all interrupt handlers */				\
+    /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */							\
+    /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */			\
+    /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */		\
+    "mov     r8, LO(%[pxCurrentTCB])\n\t"															\
+    "orh     r8, HI(%[pxCurrentTCB])\n\t"															\
+    "ld.w    r0, r8[0]\n\t"																			\
+    "st.w    r0[0], sp\n"																			\
+																									\
+    "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:"															\
+    :																								\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),													\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),															\
+      [LINE] "i" (__LINE__)																			\
+  );																								\
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT()																\
+{																									\
+  extern volatile unsigned portLONG ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */		\
+  /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+  /* level and allow other lower interrupt level to occur). */										\
+  /* In this case we don't want to do a task switch because we don't know what the stack */			\
+  /* currently looks like (we don't know what the interrupted interrupt handler was doing). */		\
+  /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */			\
+  /* will just be restoring the interrupt handler, no way!!! */										\
+  __asm__ __volatile__ (																			\
+    "ld.w    r0, sp[9*4]\n\t" /* Read SR in stack */												\
+    "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */									\
+    "cp.w    r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */						\
+    "brhi    LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]"												\
+    :																								\
+    : [LINE] "i" (__LINE__)																			\
+  );																								\
+																									\
+  /* Else */																						\
+  /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */		\
+  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
+  portENTER_CRITICAL();																				\
+  vTaskSwitchContext();																				\
+  portEXIT_CRITICAL();																				\
+																									\
+  /* Restore all registers */																		\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Set SP to point to new stack */																\
+    "mov     r8, LO(%[pxCurrentTCB])																\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])																\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "ld.w    sp, r0[0]																				\n"\
+																									\
+    "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]:														\n\t"\
+																									\
+    /* Restore ulCriticalNesting variable */														\
+    "ld.w    r0, sp++																				\n\t"																			\
+    "mov     r8, LO(%[ulCriticalNesting])															\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])															\n\t"\
+    "st.w    r8[0], r0																				\n\t"\
+																									\
+    /* Restore R0..R7 */																			\
+    "ldm     sp++, r0-r7																			\n\t"\
+																									\
+    /* Now, the stack should be R8..R12, LR, PC and SR */											\
+    "rete"																							\
+    :																								\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),													\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),															\
+      [LINE] "i" (__LINE__)																			\
+  );																								\
+}
+
+#endif
+
+
+/*
+ * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
+ *
+ * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
+ *
+ */
+#define portSAVE_CONTEXT_SCALL()															\
+{																							\
+  extern volatile unsigned portLONG ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */		\
+  /* If SR[M2:M0] == 001 */																	\
+  /*    PC and SR are on the stack.  */														\
+  /* Else (other modes) */																	\
+  /*    Nothing on the stack. */															\
+																							\
+  /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */		\
+  /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */		\
+  /* in an interrupt|exception handler. */													\
+																							\
+  __asm__ __volatile__ (																	\
+    /* in order to save R0-R7 */															\
+    "sub     sp, 6*4																		\n\t"\
+    /* Save R0..R7 */																		\
+    "stm     --sp, r0-r7																	\n\t"\
+																							\
+    /* in order to save R8-R12 and LR */													\
+    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */			\
+    "sub     r7, sp,-16*4																	\n\t"\
+    /* Copy PC and SR in other places in the stack. */										\
+    "ld.w    r0, r7[-2*4]																	\n\t" /* Read SR */\
+    "st.w    r7[-8*4], r0																	\n\t" /* Copy SR */\
+    "ld.w    r0, r7[-1*4]																	\n\t" /* Read PC */\
+    "st.w    r7[-7*4], r0																	\n\t" /* Copy PC */\
+																							\
+    /* Save R8..R12 and LR on the stack. */													\
+    "stm     --r7, r8-r12, lr																\n\t"\
+																							\
+    /* Arriving here we have the following stack organizations: */							\
+    /* R8..R12, LR, PC, SR, R0..R7. */														\
+																							\
+    /* Now we can finalize the save. */														\
+																							\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */								\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    --sp, r0"																		\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting)											\
+  );																						\
+																							\
+  /* Disable the its which may cause a context switch (i.e. cause a change of */			\
+  /* pxCurrentTCB). */																		\
+  /* Basically, all accesses to the pxCurrentTCB structure should be put in a */			\
+  /* critical section because it is a global structure. */									\
+  portENTER_CRITICAL();																		\
+																							\
+  /* Store SP in the first member of the structure pointed to by pxCurrentTCB */			\
+  __asm__ __volatile__ (																	\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    r0[0], sp"																		\
+    :																						\
+    : [pxCurrentTCB] "i" (&pxCurrentTCB)													\
+  );																						\
+}
+
+/*
+ * portRESTORE_CONTEXT() for SupervisorCALL exception.
+ */
+#define portRESTORE_CONTEXT_SCALL()															\
+{																							\
+  extern volatile unsigned portLONG ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  /* Restore all registers */																\
+																							\
+  /* Set SP to point to new stack */														\
+  __asm__ __volatile__ (																	\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "ld.w    sp, r0[0]"																		\
+    :																						\
+    : [pxCurrentTCB] "i" (&pxCurrentTCB)													\
+  );																						\
+																							\
+  /* Leave pxCurrentTCB variable access critical section */									\
+  portEXIT_CRITICAL();																		\
+																							\
+  __asm__ __volatile__ (																	\
+    /* Restore ulCriticalNesting variable */												\
+    "ld.w    r0, sp++																		\n\t"\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "st.w    r8[0], r0																		\n\t"\
+																							\
+    /* skip PC and SR */																	\
+    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */			\
+    "sub     r7, sp, -10*4																	\n\t"\
+    /* Restore r8-r12 and LR */																\
+    "ldm     r7++, r8-r12, lr																\n\t"\
+																							\
+    /* RETS will take care of the extra PC and SR restore. */								\
+    /* So, we have to prepare the stack for this. */										\
+    "ld.w    r0, r7[-8*4]																	\n\t" /* Read SR */\
+    "st.w    r7[-2*4], r0																	\n\t" /* Copy SR */\
+    "ld.w    r0, r7[-7*4]																	\n\t" /* Read PC */\
+    "st.w    r7[-1*4], r0																	\n\t" /* Copy PC */\
+																							\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+																							\
+    "sub     sp, -6*4																		\n\t"\
+																							\
+    "rets"																					\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting)											\
+  );																						\
+}
+
+
+/*
+ * The ISR used depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR()															\
+{																							\
+  /* Save R0..R7 */																			\
+  __asm__ __volatile__ ("stm     --sp, r0-r7");												\
+																							\
+  /* With the cooperative scheduler, as there is no context switch by interrupt, */			\
+  /* there is also no context save. */														\
+}
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR()															\
+{																							\
+  __asm__ __volatile__ (																	\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+																							\
+    /* With the cooperative scheduler, as there is no context switch by interrupt, */		\
+    /* there is also no context restore. */													\
+    "rete"																					\
+  );																						\
+}
+
+#else
+
+/*
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR()															\
+{																							\
+  extern volatile unsigned portLONG ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  /* When we come here */																	\
+  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */			\
+																							\
+  __asm__ __volatile__ (																	\
+    /* Save R0..R7 */																		\
+    "stm     --sp, r0-r7																	\n\t"\
+																							\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */								\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    --sp, r0																		\n\t"\
+																									\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case we don't want to do a task switch because we don't know what the stack */		\
+    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
+    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
+    /* will just be restoring the interrupt handler, no way!!! */									\
+    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
+    "ld.w    r0, sp[9*4]																	\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																	\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																			\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]											\n\t"\
+																							\
+    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */			\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    r0[0], sp																		\n"\
+																							\
+    "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:"													\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),											\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),													\
+      [LINE] "i" (__LINE__)																	\
+  );																						\
+}
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR()															\
+{																							\
+  extern volatile unsigned portLONG ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  __asm__ __volatile__ (																	\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */		\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */		\
+    /* level and allow other lower interrupt level to occur). */										\
+    /* In this case it's of no use to switch context and restore a new SP because we purposedly */		\
+    /* did not previously save SP in its TCB. */																				\
+    "ld.w    r0, sp[9*4]																	\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																	\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																			\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]											\n\t"\
+																							\
+    /* If a switch is required then we just need to call */									\
+    /* vTaskSwitchContext() as the context has already been */								\
+    /* saved. */																			\
+    "cp.w    r12, 1																			\n\t" /* Check if Switch context is required. */\
+    "brne    LABEL_ISR_RESTORE_CONTEXT_%[LINE]"												\
+    :																						\
+    : [LINE] "i" (__LINE__)																	\
+  );																						\
+																							\
+  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */	\
+  portENTER_CRITICAL();																		\
+  vTaskSwitchContext();																		\
+  portEXIT_CRITICAL();																		\
+																							\
+  __asm__ __volatile__ (																	\
+    "LABEL_ISR_RESTORE_CONTEXT_%[LINE]:														\n\t"\
+    /* Restore the context of which ever task is now the highest */							\
+    /* priority that is ready to run. */													\
+																							\
+    /* Restore all registers */																\
+																							\
+    /* Set SP to point to new stack */														\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "ld.w    sp, r0[0]																		\n"\
+																							\
+    "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]:												\n\t"\
+																							\
+    /* Restore ulCriticalNesting variable */												\
+    "ld.w    r0, sp++																		\n\t"\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "st.w    r8[0], r0																		\n\t"\
+																							\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+																							\
+    /* Now, the stack should be R8..R12, LR, PC and SR  */									\
+    "rete"																					\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),											\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),													\
+      [LINE] "i" (__LINE__)																	\
+  );																						\
+}
+
+#endif
+
+
+#define portYIELD()                 {__asm__ __volatile__ ("scall");}
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */

20080212/Source/portable/GCC/H8S2329/port.c

@@ -0,0 +1,316 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the H8S port.
+ *----------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------*/
+
+/* When the task starts interrupts should be enabled. */
+#define portINITIAL_CCR			( ( portSTACK_TYPE ) 0x00 )
+
+/* Hardware specific constants used to generate the RTOS tick from the TPU. */
+#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( unsigned portCHAR ) 0x20 )
+#define portCLOCK_DIV_64				( ( unsigned portCHAR ) 0x03 )
+#define portCLOCK_DIV					( ( unsigned portLONG ) 64 )
+#define portTGRA_INTERRUPT_ENABLE		( ( unsigned portCHAR ) 0x01 )
+#define portTIMER_CHANNEL				( ( unsigned portCHAR ) 0x02 )
+#define portMSTP13						( ( unsigned portSHORT ) 0x2000 )
+
+/*
+ * Setup TPU channel one for the RTOS tick at the requested frequency.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The ISR used by portYIELD(). This is installed as a trap handler.
+ */
+void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+unsigned portLONG ulValue;
+
+	/* This requires an even address. */
+	ulValue = ( unsigned portLONG ) pxTopOfStack;
+	if( ulValue & 1UL )
+	{
+		pxTopOfStack = pxTopOfStack - 1;
+	}
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0xaa;
+	pxTopOfStack--;
+	*pxTopOfStack = 0xbb;
+	pxTopOfStack--;
+	*pxTopOfStack = 0xcc;
+	pxTopOfStack--;
+	*pxTopOfStack = 0xdd;
+
+	/* The initial stack mimics an interrupt stack.  First there is the program
+	counter (24 bits). */
+	ulValue = ( unsigned portLONG ) pxCode;
+
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );
+
+	/* Followed by the CCR. */	
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_CCR;
+
+	/* Next all the general purpose registers - with the parameters being passed
+	in ER0.  The parameter order must match that used by the compiler when the
+	"saveall" function attribute is used. */
+
+	/* ER6 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	
+	/* ER0 */
+	ulValue = ( unsigned portLONG ) pvParameters;
+
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff );
+	
+	/* ER1 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+
+	/* ER2 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+
+	/* ER3 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+
+	/* ER4 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+
+	/* ER5 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+extern void * pxCurrentTCB;
+
+	/* Setup the hardware to generate the tick. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run.  This
+	mirrors the function epilogue code generated by the compiler when the
+	"saveall" function attribute is used. */
+	asm volatile ( 
+					"MOV.L		@_pxCurrentTCB, ER6			\n\t"
+					"MOV.L		@ER6, ER7					\n\t"
+					"LDM.L     	@SP+, (ER4-ER5)				\n\t"
+					"LDM.L     	@SP+, (ER0-ER3)				\n\t"
+					"MOV.L     	@ER7+, ER6					\n\t"
+					"RTE									\n\t"
+				);
+
+	( void ) pxCurrentTCB;
+
+	/* Should not get here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the h8 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  This is a trap handler.  The "saveall" function
+ * attribute is used so the context is saved by the compiler prologue.  All
+ * we have to do is save the stack pointer.
+ */
+void vPortYield( void )
+{
+	portSAVE_STACK_POINTER();
+		vTaskSwitchContext();
+	portRESTORE_STACK_POINTER();
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The interrupt handler installed for the RTOS tick depends on whether the 
+ * preemptive or cooperative scheduler is being used. 
+ */
+#if( configUSE_PREEMPTION == 1 )
+
+	/* 
+	 * The preemptive scheduler is used so the ISR calls vTaskSwitchContext().
+	 * The function prologue saves the context so all we have to do is save
+	 * the stack pointer.
+	 */
+	void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );
+	void vTickISR( void )
+	{
+		portSAVE_STACK_POINTER();
+		
+		vTaskIncrementTick();
+		vTaskSwitchContext();
+
+		/* Clear the interrupt. */
+		TSR1 &= ~0x01;
+
+		portRESTORE_STACK_POINTER();
+	}
+
+#else
+
+	/*
+	 * The cooperative scheduler is being used so all we have to do is 
+	 * periodically increment the tick.  This can just be a normal ISR and
+	 * the "saveall" attribute is not required.
+	 */
+	void vTickISR( void ) __attribute__ ( ( interrupt_handler ) );
+	void vTickISR( void )
+	{
+		vTaskIncrementTick();
+
+		/* Clear the interrupt. */
+		TSR1 &= ~0x01;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer 1 compare match to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const unsigned portLONG ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV;
+
+	/* Turn the module on. */
+	MSTPCR &= ~portMSTP13;
+
+	/* Configure timer 1. */
+	TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64;
+
+	/* Configure the compare match value for a tick of configTICK_RATE_HZ. */
+	TGR1A = ulCompareMatch;
+
+	/* Start the timer and enable the interrupt - we can do this here as 
+	interrupts are globally disabled when this function is called. */
+	TIER1 |= portTGRA_INTERRUPT_ENABLE;
+	TSTR |= portTIMER_CHANNEL;
+}
+/*-----------------------------------------------------------*/
+
+
+

20080212/Source/portable/GCC/H8S2329/portmacro.h

@@ -0,0 +1,149 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned portCHAR
+#define portBASE_TYPE	char
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+#define portYIELD()					asm volatile( "TRAPA #0" )
+#define portNOP()					asm volatile( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENABLE_INTERRUPTS()		asm volatile( "ANDC	#0x7F, CCR" );
+#define portDISABLE_INTERRUPTS()	asm volatile( "ORC  #0x80, CCR" );
+
+/* Push the CCR then disable interrupts. */
+#define portENTER_CRITICAL()  		asm volatile( "STC	CCR, @-ER7" ); \
+                               		portDISABLE_INTERRUPTS();
+
+/* Pop the CCR to set the interrupt masking back to its previous state. */
+#define  portEXIT_CRITICAL()    	asm volatile( "LDC  @ER7+, CCR" );
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Context switch macros.  These macros are very simple as the context 
+is saved simply by selecting the saveall attribute of the context switch 
+interrupt service routines.  These macros save and restore the stack
+pointer to the TCB. */
+
+#define portSAVE_STACK_POINTER()								\
+extern void* pxCurrentTCB;										\
+																\
+	asm volatile(												\
+					"MOV.L	@_pxCurrentTCB, ER5			\n\t" 	\
+					"MOV.L	ER7, @ER5					\n\t"	\
+				);												\
+	( void ) pxCurrentTCB;
+
+
+#define	portRESTORE_STACK_POINTER()								\
+extern void* pxCurrentTCB;										\
+																\
+	asm volatile(												\
+					"MOV.L	@_pxCurrentTCB, ER5			\n\t"	\
+					"MOV.L	@ER5, ER7					\n\t"	\
+				);												\
+	( void ) pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/* Macros to allow a context switch from within an application ISR. */
+
+#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {
+
+#define portEXIT_SWITCHING_ISR( x )							\
+	if( x )													\
+	{														\
+		extern void vTaskSwitchContext( void );				\
+		vTaskSwitchContext();								\
+	}														\
+	} portRESTORE_STACK_POINTER();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

20080212/Source/portable/GCC/HCS12/port.c

@@ -0,0 +1,252 @@
+/* 
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/* GCC/HCS12 port by Jefferson L Smith, 2005 */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Port includes */
+#include <sys/ports_def.h>
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the HCS12 port.
+ *----------------------------------------------------------*/
+
+
+/*
+ * Configure a timer to generate the RTOS tick at the frequency specified 
+ * within FreeRTOSConfig.h.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/* NOTE: Interrupt service routines must be in non-banked memory - as does the
+scheduler startup function. */
+#define ATTR_NEAR	__attribute__((near))
+
+/* Manual context switch function.  This is the SWI ISR. */
+// __attribute__((interrupt))
+void ATTR_NEAR vPortYield( void );
+
+/* Tick context switch function.  This is the timer ISR. */
+// __attribute__((interrupt))
+void ATTR_NEAR vPortTickInterrupt( void );
+
+/* Function in non-banked memory which actually switches to first task. */
+portBASE_TYPE ATTR_NEAR xStartSchedulerNear( void );
+
+/* Calls to portENTER_CRITICAL() can be nested.  When they are nested the 
+critical section should not be left (i.e. interrupts should not be re-enabled)
+until the nesting depth reaches 0.  This variable simply tracks the nesting 
+depth.  Each task maintains it's own critical nesting depth variable so 
+uxCriticalNesting is saved and restored from the task stack during a context
+switch. */
+volatile unsigned portBASE_TYPE uxCriticalNesting = 0x80;  // un-initialized
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
+	expected by the HCS12 RTI instruction. */
+
+
+	/* The address of the task function is placed in the stack byte at a time. */
+	*pxTopOfStack   = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 1 );
+	*--pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 0 );
+
+	/* Next are all the registers that form part of the task context. */
+
+	/* Y register */
+	*--pxTopOfStack = ( portSTACK_TYPE ) 0xff;
+	*--pxTopOfStack = ( portSTACK_TYPE ) 0xee;
+
+	/* X register */
+	*--pxTopOfStack = ( portSTACK_TYPE ) 0xdd;
+	*--pxTopOfStack = ( portSTACK_TYPE ) 0xcc;
+ 
+	/* A register contains parameter high byte. */
+	*--pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 0 );
+
+	/* B register contains parameter low byte. */
+	*--pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 1 );
+
+	/* CCR: Note that when the task starts interrupts will be enabled since
+	"I" bit of CCR is cleared */
+	*--pxTopOfStack = ( portSTACK_TYPE ) 0x80;		// keeps Stop disabled (MCU default)
+	
+	/* tmp softregs used by GCC. Values right now don't	matter. */
+	__asm("\n\
+		movw _.frame, 2,-%0							\n\
+		movw _.tmp, 2,-%0							\n\
+		movw _.z, 2,-%0								\n\
+		movw _.xy, 2,-%0							\n\
+		;movw _.d2, 2,-%0							\n\
+		;movw _.d1, 2,-%0							\n\
+	": "=A"(pxTopOfStack) : "0"(pxTopOfStack) );
+
+	#ifdef BANKED_MODEL
+		/* The page of the task. */
+		*--pxTopOfStack = 0x30;      // can only directly start in PPAGE 0x30
+	#endif
+	
+	/* The critical nesting depth is initialised with 0 (meaning not in
+	a critical section). */
+	*--pxTopOfStack = ( portSTACK_TYPE ) 0x00;
+
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the HCS12 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Enable hardware RTI timer */
+	/* Ignores configTICK_RATE_HZ */
+	RTICTL = 0x50;			// 16 MHz xtal: 976.56 Hz, 1024mS 
+	CRGINT |= 0x80;			// RTIE
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+	/* xPortStartScheduler() does not start the scheduler directly because 
+	the header file containing the xPortStartScheduler() prototype is part 
+	of the common kernel code, and therefore cannot use the CODE_SEG pragma. 
+	Instead it simply calls the locally defined xNearStartScheduler() - 
+	which does use the CODE_SEG pragma. */
+
+	short register d;
+	__asm ("jmp  xStartSchedulerNear		; will never return": "=d"(d));
+	return d;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xStartSchedulerNear( void )
+{
+	/* Configure the timer that will generate the RTOS tick.  Interrupts are
+	disabled when this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task. */
+	portRESTORE_CONTEXT();
+
+	portISR_TAIL();
+
+	/* Should not get here! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch functions.  These are interrupt service routines.
+ */
+
+/*
+ * Manual context switch forced by calling portYIELD().  This is the SWI
+ * handler.
+ */
+void vPortYield( void )
+{
+	portISR_HEAD();
+	/* NOTE: This is the trap routine (swi) although not defined as a trap.
+	   It will fill the stack the same way as an ISR in order to mix preemtion
+	   and cooperative yield. */
+
+	portSAVE_CONTEXT();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT();
+
+	portISR_TAIL();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * RTOS tick interrupt service routine.  If the cooperative scheduler is 
+ * being used then this simply increments the tick count.  If the 
+ * preemptive scheduler is being used a context switch can occur.
+ */
+void vPortTickInterrupt( void )
+{
+	portISR_HEAD();
+
+	/* Clear tick timer flag */
+	CRGFLG = 0x80;
+
+	#if configUSE_PREEMPTION == 1
+	{
+		/* A context switch might happen so save the context. */
+		portSAVE_CONTEXT();
+
+		/* Increment the tick ... */
+		vTaskIncrementTick();
+
+		/* ... then see if the new tick value has necessitated a
+		context switch. */
+		vTaskSwitchContext();
+
+		/* Restore the context of a task - which may be a different task
+		to that interrupted. */
+		portRESTORE_CONTEXT();
+	}
+	#else
+	{
+		vTaskIncrementTick();
+	}
+	#endif
+
+	portISR_TAIL();
+}
+

20080212/Source/portable/GCC/HCS12/portmacro.h

@@ -0,0 +1,256 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned portCHAR
+#define portBASE_TYPE	char
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			1
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )
+#define portYIELD()					__asm( "swi" );
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENABLE_INTERRUPTS()				__asm( "cli" )	
+#define portDISABLE_INTERRUPTS()			__asm( "sei" )
+
+/*
+ * Disable interrupts before incrementing the count of critical section nesting.
+ * The nesting count is maintained so we know when interrupts should be
+ * re-enabled.  Once interrupts are disabled the nesting count can be accessed
+ * directly.  Each task maintains its own nesting count.
+ */
+#define portENTER_CRITICAL()  									\
+{																\
+	extern volatile unsigned portBASE_TYPE uxCriticalNesting;	\
+																\
+	portDISABLE_INTERRUPTS();									\
+	uxCriticalNesting++;										\
+}
+
+/*
+ * Interrupts are disabled so we can access the nesting count directly.  If the
+ * nesting is found to be 0 (no nesting) then we are leaving the critical 
+ * section and interrupts can be re-enabled.
+ */
+#define  portEXIT_CRITICAL()									\
+{																\
+	extern volatile unsigned portBASE_TYPE uxCriticalNesting;	\
+																\
+	uxCriticalNesting--;										\
+	if( uxCriticalNesting == 0 )								\
+	{															\
+		portENABLE_INTERRUPTS();								\
+	}															\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* 
+ * These macros are very simple as the processor automatically saves and 
+ * restores its registers as interrupts are entered and exited.  In
+ * addition to the (automatically stacked) registers we also stack the 
+ * critical nesting count.  Each task maintains its own critical nesting
+ * count as it is legitimate for a task to yield from within a critical
+ * section.  If the banked memory model is being used then the PPAGE
+ * register is also stored as part of the tasks context.
+ */
+
+#ifdef BANKED_MODEL
+	/* 
+	 * Load the stack pointer for the task, then pull the critical nesting
+	 * count and PPAGE register from the stack.  The remains of the 
+	 * context are restored by the RTI instruction.
+	 */
+	#define portRESTORE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		lds  0,x				; Stack				\n\
+											\n\
+		movb 1,sp+,uxCriticalNesting						\n\
+		movb 1,sp+,0x30				; PPAGE				\n\
+		" );									\
+	}
+
+	/* 
+	 * By the time this macro is called the processor has already stacked the
+	 * registers.  Simply stack the nesting count and PPAGE value, then save 
+	 * the task stack pointer.
+	 */
+	#define portSAVE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		movb 0x30, 1,-sp			; PPAGE				\n\
+		movb uxCriticalNesting, 1,-sp						\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		sts  0,x				; Stack				\n\
+		" );									\
+	}
+#else
+
+	/* 
+	 * These macros are as per the BANKED versions above, but without saving
+	 * and restoring the PPAGE register.
+	 */
+
+	#define portRESTORE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		lds  0,x				; Stack				\n\
+											\n\
+		movb 1,sp+,uxCriticalNesting						\n\
+		" );									\
+	}
+
+	#define portSAVE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		movb uxCriticalNesting, 1,-sp						\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		sts  0,x				; Stack				\n\
+		" );									\
+	}
+#endif
+
+/*
+ * Utility macros to save/restore correct software registers for GCC. This is
+ * useful when GCC does not generate appropriate ISR head/tail code.
+ */
+#define portISR_HEAD()									\
+{											\
+		__asm("									\n\
+		movw _.frame, 2,-sp							\n\
+		movw _.tmp, 2,-sp							\n\
+		movw _.z, 2,-sp								\n\
+		movw _.xy, 2,-sp							\n\
+		;movw _.d2, 2,-sp							\n\
+		;movw _.d1, 2,-sp							\n\
+		");									\
+}
+
+#define portISR_TAIL()									\
+{											\
+		__asm("									\n\
+		movw 2,sp+, _.xy							\n\
+		movw 2,sp+, _.z								\n\
+		movw 2,sp+, _.tmp							\n\
+		movw 2,sp+, _.frame							\n\
+		;movw 2,sp+, _.d1							\n\
+		;movw 2,sp+, _.d2							\n\
+		rti									\n\
+		");									\
+}
+
+/*
+ * Utility macro to call macros above in correct order in order to perform a
+ * task switch from within a standard ISR.  This macro can only be used if
+ * the ISR does not use any local (stack) variables.  If the ISR uses stack
+ * variables portYIELD() should be used in it's place.
+ */
+
+#define portTASK_SWITCH_FROM_ISR()								\
+	portSAVE_CONTEXT();											\
+	vTaskSwitchContext();										\
+	portRESTORE_CONTEXT();
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

20080212/Source/portable/GCC/MCF5235/port.c

@@ -0,0 +1,273 @@
+/*
+    FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
+    MCF5235 Port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#include <stdlib.h>
+
+#include "FreeRTOS.h"
+#include "FreeRTOSConfig.h"
+#include "task.h"
+
+/* ------------------------ Types ----------------------------------------- */
+typedef volatile unsigned long vuint32;
+typedef volatile unsigned short vuint16;
+typedef volatile unsigned char vuint8;
+
+/* ------------------------ Defines --------------------------------------- */
+#define portVECTOR_TABLE                __RAMVEC
+#define portVECTOR_SYSCALL              ( 32 + portTRAP_YIELD )
+#define portVECTOR_TIMER                ( 64 + 36 )
+
+#define MCF_PIT_PRESCALER               512UL
+#define MCF_PIT_TIMER_TICKS             ( FSYS_2 / MCF_PIT_PRESCALER )
+#define MCF_PIT_MODULUS_REGISTER(freq)  ( MCF_PIT_TIMER_TICKS / ( freq ) - 1UL)
+
+#define MCF_PIT_PMR0                    ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150002 ] ) )
+#define MCF_PIT_PCSR0                   ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150000 ] ) )
+#define MCF_PIT_PCSR_PRE(x)             ( ( ( x ) & 0x000F ) << 8 )
+#define MCF_PIT_PCSR_EN                 ( 0x0001 )
+#define MCF_PIT_PCSR_RLD                ( 0x0002 )
+#define MCF_PIT_PCSR_PIF                ( 0x0004 )
+#define MCF_PIT_PCSR_PIE                ( 0x0008 )
+#define MCF_PIT_PCSR_OVW                ( 0x0010 )
+#define MCF_INTC0_ICR36                 ( *( vuint8 * )( void * )( &__IPSBAR[ 0x000C64 ] ) )
+#define MCF_INTC0_IMRH                  ( *( vuint32 * )( void * )( &__IPSBAR[ 0x000C08 ] ) )
+#define MCF_INTC0_IMRH_INT_MASK36       ( 0x00000010 )
+#define MCF_INTC0_IMRH_MASKALL          ( 0x00000001 )
+#define MCF_INTC0_ICRn_IP(x)            ( ( ( x ) & 0x07 ) << 0 )
+#define MCF_INTC0_ICRn_IL(x)            ( ( ( x ) & 0x07 ) << 3 )
+
+#define portNO_CRITICAL_NESTING         ( ( unsigned portLONG ) 0 )
+#define portINITIAL_CRITICAL_NESTING    ( ( unsigned portLONG ) 10 )
+
+/* ------------------------ Static variables ------------------------------ */
+volatile unsigned portLONG              ulCriticalNesting = portINITIAL_CRITICAL_NESTING;
+
+/* ------------------------ Static functions ------------------------------ */
+#if configUSE_PREEMPTION == 0
+static void prvPortPreemptiveTick ( void ) __attribute__ ((interrupt_handler));
+#else
+static void prvPortPreemptiveTick ( void );
+#endif
+
+/* ------------------------ Start implementation -------------------------- */
+
+portSTACK_TYPE *
+pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode,
+                       void *pvParameters )
+{
+    /* Place the parameter on the stack in the expected location. */
+    *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
+    pxTopOfStack--;
+
+    /* Place dummy return address on stack. Tasks should never terminate so
+     * we can set this to anything. */
+    *pxTopOfStack = ( portSTACK_TYPE ) 0;
+    pxTopOfStack--;
+
+    /* Create a Motorola Coldfire exception stack frame. First comes the return
+     * address. */
+    *pxTopOfStack = ( portSTACK_TYPE ) pxCode;
+    pxTopOfStack--;
+
+    /* Format, fault-status, vector number for exception stack frame. Task
+     * run in supervisor mode. */
+    *pxTopOfStack = 0x40002000UL | ( portVECTOR_SYSCALL + 32 ) << 18;
+    pxTopOfStack--;
+
+    /* Set the initial critical section nesting counter to zero. This value
+     * is used to restore the value of ulCriticalNesting. */
+    *pxTopOfStack = 0;
+    *pxTopOfStack--;
+
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xA6;    /* A6 / FP */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xA5;    /* A5 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xA4;    /* A4 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xA3;    /* A3 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xA2;    /* A2 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xA1;    /* A1 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xA0;    /* A0 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xD7;    /* D7 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xD6;    /* D6 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xD5;    /* D5 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xD4;    /* D4 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xD3;    /* D3 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xD2;    /* D2 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xD1;    /* D1 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( portSTACK_TYPE ) 0xD0;    /* D0 */
+
+    return pxTopOfStack;
+}
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ */
+static void
+prvPortYield( void )
+{
+    asm volatile ( "move.w  #0x2700, %sr\n\t" );
+#if _GCC_USES_FP == 1
+    asm volatile ( "unlk %fp\n\t" );
+#endif
+     /* Perform the context switch.  First save the context of the current task. */
+    portSAVE_CONTEXT(  );
+
+    /* Find the highest priority task that is ready to run. */
+    vTaskSwitchContext(  );
+
+    /* Restore the context of the new task. */
+    portRESTORE_CONTEXT(  );
+}
+
+#if configUSE_PREEMPTION == 0
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+static void
+prvPortPreemptiveTick ( void )
+{
+    /* The cooperative scheduler requires a normal IRQ service routine to
+     * simply increment the system tick.
+     */
+
+    vTaskIncrementTick(  );
+    MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
+}
+
+#else
+
+static void
+prvPortPreemptiveTick( void )
+{
+    asm volatile ( "move.w  #0x2700, %sr\n\t" );
+#if _GCC_USES_FP == 1
+    asm volatile ( "unlk %fp\n\t" );
+#endif
+    portSAVE_CONTEXT(  );
+    MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
+    vTaskIncrementTick(  );
+    vTaskSwitchContext(  );
+    portRESTORE_CONTEXT(  );
+}
+#endif
+
+void
+vPortEnterCritical()
+{
+    /* FIXME: We should store the old IPL here - How are we supposed to do
+     * this.
+     */
+    ( void )portSET_IPL( portIPL_MAX );
+
+    /* Now interrupts are disabled ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
+    ulCriticalNesting++;
+}
+
+void
+vPortExitCritical()
+{
+    if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+    {
+        /* Decrement the nesting count as we are leaving a critical section. */
+        ulCriticalNesting--;
+
+        /* If the nesting level has reached zero then interrupts should be
+        re-enabled. */
+        if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+        {
+            ( void )portSET_IPL( 0 );
+        }
+    }
+}
+
+portBASE_TYPE
+xPortStartScheduler( void )
+{
+    extern void     ( *portVECTOR_TABLE[  ] ) (  );
+
+    /* Add entry in vector table for yield system call. */
+    portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield;
+    /* Add entry in vector table for periodic timer. */
+    portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick;
+
+    /* Configure the timer for the system clock. */
+    if ( configTICK_RATE_HZ > 0)
+    {
+        /* Configure prescaler */
+        MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW;
+        /* Initialize the periodic timer interrupt. */
+        MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ );
+        /* Configure interrupt priority and level and unmask interrupt. */
+        MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 );
+        MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 | MCF_INTC0_IMRH_MASKALL );
+        /* Enable interrupts */
+        MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF;
+    }
+
+    /* Restore the context of the first task that is going to run. */
+    portRESTORE_CONTEXT(  );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+
+void
+vPortEndScheduler( void )
+{
+}

20080212/Source/portable/GCC/MCF5235/portmacro.h

@@ -0,0 +1,168 @@
+/*
+    FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
+    MCF5235 Port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ------------------------ Data types for Coldfire ----------------------- */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  unsigned int
+#define portBASE_TYPE   int
+
+#if( USE_16_BIT_TICKS == 1 )
+    typedef unsigned portSHORT portTickType;
+    #define portMAX_DELAY ( portTickType ) 0xffff
+#else
+    typedef unsigned portLONG portTickType;
+    #define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+
+/* ------------------------ Architecture specifics ------------------------ */
+#define portSTACK_GROWTH                ( -1 )
+#define portTICK_RATE_MS                ( ( portTickType ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT              4
+
+#define portTRAP_YIELD                  0   /* Trap 0 */
+#define portIPL_MAX                     7   /* Only NMI interrupt 7 allowed. */
+
+/* ------------------------ FreeRTOS macros for port ---------------------- */
+
+/*
+ * This function must be called when the current state of the active task
+ * should be stored. It must be called immediately after exception
+ * processing from the CPU, i.e. there exists a Coldfire exception frame at
+ * the current position in the stack. The function reserves space on
+ * the stack for the CPU registers and other task dependent values (e.g
+ * ulCriticalNesting) and updates the top of the stack in the TCB.
+ */
+#define portSAVE_CONTEXT()                                                   \
+    asm volatile ( /* reserve space for task state. */                       \
+                   "lea.l   (-64, %sp), %sp\n\t"                             \
+                   /* push data register %d0-%d7/%a0-%a6 on stack. */        \
+                   "movem.l %d0-%d7/%a0-%a6, (%sp)\n\t"                      \
+                   /* push ulCriticalNesting counter on stack. */            \
+                   "lea.l  (60, %sp), %a0\n\t"                               \
+                   "move.l  ulCriticalNesting, (%a0)\n\t"                    \
+                   /* set the new top of the stack in the TCB. */            \
+                   "move.l  pxCurrentTCB, %a0\n\t"                           \
+                   "move.l  %sp, (%a0)");
+
+/*.
+ * This function restores the current active and continues its execution.
+ * It loads the current TCB and restores the processor registers, the
+ * task dependent values (e.g ulCriticalNesting). Finally execution
+ * is continued by executing an rte instruction.
+ */
+#define portRESTORE_CONTEXT()                                                \
+    asm volatile ( "move.l  pxCurrentTCB, %sp\n\t"                           \
+                   "move.l  (%sp), %sp\n\t"                                  \
+                   /* stack pointer now points to the saved registers. */    \
+                   "movem.l (%sp), %d0-%d7/%a0-%a6\n\t"                      \
+                   /* restore ulCriticalNesting counter from stack. */       \
+                   "lea.l   (%sp, 60), %sp\n\t"                              \
+                   "move.l  (%sp)+, ulCriticalNesting\n\t"                   \
+                   /* stack pointer now points to exception frame. */        \
+                   "rte\n\t" );
+
+#define portENTER_CRITICAL()                                                 \
+    vPortEnterCritical();
+
+#define portEXIT_CRITICAL()                                                  \
+    vPortExitCritical();
+
+#define portSET_IPL( xIPL )                                                  \
+    asm_set_ipl( xIPL )
+
+#define portDISABLE_INTERRUPTS() \
+    do { ( void )portSET_IPL( portIPL_MAX ); } while( 0 )
+#define portENABLE_INTERRUPTS() \
+    do { ( void )portSET_IPL( 0 ); } while( 0 )
+
+#define portYIELD()                                                          \
+    asm volatile ( " trap   %0\n\t" : : "i"(portTRAP_YIELD) )
+
+#define portNOP()                                                            \
+    asm volatile ( "nop\n\t" )
+
+#define portENTER_SWITCHING_ISR()                                            \
+    asm volatile ( "move.w  #0x2700, %sr" );                                 \
+    /* Save the context of the interrupted task. */                          \
+    portSAVE_CONTEXT(  );                                                    \
+    {
+
+#define portEXIT_SWITCHING_ISR( SwitchRequired )                             \
+        /* If a switch is required we call vTaskSwitchContext(). */          \
+        if( SwitchRequired )                                                 \
+        {                                                                    \
+            vTaskSwitchContext(  );                                          \
+        }                                                                    \
+    }                                                                        \
+    portRESTORE_CONTEXT(  );
+
+/* ------------------------ Function prototypes --------------------------- */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+int asm_set_ipl( unsigned long int uiNewIPL );
+
+/* ------------------------ Compiler specifics ---------------------------- */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )                   \
+    void vFunction( void *pvParameters )
+
+#define portTASK_FUNCTION( vFunction, pvParameters )                         \
+    void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* PORTMACRO_H */
+

20080212/Source/portable/GCC/MSP430F449/port.c

@@ -0,0 +1,337 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+	Changes from V2.5.2
+		
+	+ usCriticalNesting now has a volatile qualifier.
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <signal.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK, 
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ			( ( portTickType ) 32768 )
+#define portINITIAL_CRITICAL_NESTING	( ( unsigned portSHORT ) 10 )
+#define portFLAGS_INT_ENABLED	( ( portSTACK_TYPE ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void tskTCB;
+extern volatile tskTCB * volatile pxCurrentTCB;
+
+/* Most ports implement critical sections by placing the interrupt flags on
+the stack before disabling interrupts.  Exiting the critical section is then
+simply a case of popping the flags from the stack.  As mspgcc does not use
+a frame pointer this cannot be done as modifying the stack will clobber all
+the stack variables.  Instead each task maintains a count of the critical
+section nesting depth.  Each time a critical section is entered the count is
+incremented.  Each time a critical section is left the count is decremented -
+with interrupts only being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+/* 
+ * Macro to save a task context to the task stack.  This simply pushes all the 
+ * general purpose msp430 registers onto the stack, followed by the 
+ * usCriticalNesting value used by the task.  Finally the resultant stack 
+ * pointer value is saved into the task control block so it can be retrieved 
+ * the next time the task executes.
+ */
+#define portSAVE_CONTEXT()									\
+	asm volatile (	"push	r4						\n\t"	\
+					"push	r5						\n\t"	\
+					"push	r6						\n\t"	\
+					"push	r7						\n\t"	\
+					"push	r8						\n\t"	\
+					"push	r9						\n\t"	\
+					"push	r10						\n\t"	\
+					"push	r11						\n\t"	\
+					"push	r12						\n\t"	\
+					"push	r13						\n\t"	\
+					"push	r14						\n\t"	\
+					"push	r15						\n\t"	\
+					"mov.w	usCriticalNesting, r14	\n\t"	\
+					"push	r14						\n\t"	\
+					"mov.w	pxCurrentTCB, r12		\n\t"	\
+					"mov.w	r1, @r12				\n\t"	\
+				);
+
+/* 
+ * Macro to restore a task context from the task stack.  This is effectively
+ * the reverse of portSAVE_CONTEXT().  First the stack pointer value is
+ * loaded from the task control block.  Next the value for usCriticalNesting
+ * used by the task is retrieved from the stack - followed by the value of all
+ * the general purpose msp430 registers.
+ */
+#define portRESTORE_CONTEXT()								\
+	asm volatile (	"mov.w	pxCurrentTCB, r12		\n\t"	\
+					"mov.w	@r12, r1				\n\t"	\
+					"pop	r15						\n\t"	\
+					"mov.w	r15, usCriticalNesting	\n\t"	\
+					"pop	r15						\n\t"	\
+					"pop	r14						\n\t"	\
+					"pop	r13						\n\t"	\
+					"pop	r12						\n\t"	\
+					"pop	r11						\n\t"	\
+					"pop	r10						\n\t"	\
+					"pop	r9						\n\t"	\
+					"pop	r8						\n\t"	\
+					"pop	r7						\n\t"	\
+					"pop	r6						\n\t"	\
+					"pop	r5						\n\t"	\
+					"pop	r4						\n\t"	\
+					"reti							\n\t"	\
+				);
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ * 
+ * See the header file portable.h.
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+	/* 
+		Place a few bytes of known values on the bottom of the stack. 
+		This is just useful for debugging and can be included if required.
+
+		*pxTopOfStack = ( portSTACK_TYPE ) 0x1111;
+		pxTopOfStack--;
+		*pxTopOfStack = ( portSTACK_TYPE ) 0x2222;
+		pxTopOfStack--;
+		*pxTopOfStack = ( portSTACK_TYPE ) 0x3333;
+		pxTopOfStack--; 
+	*/
+
+	/* The msp430 automatically pushes the PC then SR onto the stack before 
+	executing an ISR.  We want the stack to look just as if this has happened
+	so place a pointer to the start of the task on the stack first - followed
+	by the flags we want the task to use when it starts up. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pxCode;
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+	/* Next the general purpose registers. */
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x4444;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x5555;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x6666;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x7777;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x8888;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x9999;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0xcccc;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0xdddd;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0xeeee;
+	pxTopOfStack--;
+
+	/* When the task starts is will expect to find the function parameter in
+	R15. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
+	pxTopOfStack--;
+
+	/* The code generated by the mspgcc compiler does not maintain separate
+	stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+	use the stack as per other ports.  Instead a variable is used to keep
+	track of the critical section nesting.  This variable has to be stored
+	as part of the task context and is initially set to zero. */
+	*pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here as the tasks are now running! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the MSP430 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.  
+ *
+ * The first thing we do is save the registers so we can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__ ( ( naked ) );
+void vPortYield( void )
+{
+	/* We want the stack of the task being saved to look exactly as if the task
+	was saved during a pre-emptive RTOS tick ISR.  Before calling an ISR the 
+	msp430 places the status register onto the stack.  As this is a function 
+	call and not an ISR we have to do this manually. */
+	asm volatile ( "push	r2" );
+	_DINT();
+
+	/* Save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Switch to the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.  This uses timer 0
+ * but could alternatively use the watchdog timer or timer 1. 
+ */
+static void prvSetupTimerInterrupt( void )
+{
+	/* Ensure the timer is stopped. */
+	TACTL = 0;
+
+	/* Run the timer of the ACLK. */
+	TACTL = TASSEL_1;
+
+	/* Clear everything to start with. */
+	TACTL |= TACLR;
+
+	/* Set the compare match value according to the tick rate we want. */
+	TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
+
+	/* Enable the interrupts. */
+	TACCTL0 = CCIE;
+
+	/* Start up clean. */
+	TACTL |= TACLR;
+
+	/* Up mode. */
+	TACTL |= MC_1;
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The interrupt service routine used depends on whether the pre-emptive
+ * scheduler is being used or not.
+ */
+
+#if configUSE_PREEMPTION == 1
+
+	/*
+	 * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+	 * the context is saved at the start of vPortYieldFromTick().  The tick
+	 * count is incremented after the context is saved.
+	 */
+	interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) );
+	interrupt (TIMERA0_VECTOR) prvTickISR( void )
+	{
+		/* Save the context of the interrupted task. */
+		portSAVE_CONTEXT();
+
+		/* Increment the tick count then switch to the highest priority task
+		that is ready to run. */
+		vTaskIncrementTick();
+		vTaskSwitchContext();
+
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT();
+	}
+
+#else
+
+	/*
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 */
+	interrupt (TIMERA0_VECTOR) prvTickISR( void );
+	interrupt (TIMERA0_VECTOR) prvTickISR( void )
+	{
+		vTaskIncrementTick();
+	}
+#endif
+
+
+	

20080212/Source/portable/GCC/MSP430F449/portmacro.h

@@ -0,0 +1,138 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	unsigned portSHORT
+#define portBASE_TYPE	portSHORT
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/	
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()	asm volatile ( "DINT" )
+#define portENABLE_INTERRUPTS()		asm volatile ( "EINT" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( unsigned portSHORT ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile unsigned portSHORT usCriticalNesting;							\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile unsigned portSHORT usCriticalNesting;							\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD()					vPortYield()
+#define portNOP()			asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

20080212/Source/portable/GCC/MicroBlaze/port.c

@@ -0,0 +1,347 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <string.h>
+
+/* Hardware includes. */
+#include <xintc.h>
+#include <xintc_i.h>
+#include <xtmrctr.h>
+
+/* Tasks are started with interrupts enabled. */
+#define portINITIAL_MSR_STATE		( ( portSTACK_TYPE ) 0x02 )
+
+/* Tasks are started with a critical section nesting of 0 - however prior
+to the scheduler being commenced we don't want the critical nesting level
+to reach zero, so it is initialised to a high value. */
+#define portINITIAL_NESTING_VALUE	( 0xff )
+
+/* Our hardware setup only uses one counter. */
+#define portCOUNTER_0 				0
+
+/* The stack used by the ISR is filled with a known value to assist in
+debugging. */
+#define portISR_STACK_FILL_VALUE	0x55555555
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task 
+maintains it's own count, so this variable is saved as part of the task
+context. */
+volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* To limit the amount of stack required by each task, this port uses a
+separate stack for interrupts. */
+unsigned portLONG *pulISRStack;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been made.
+ * 
+ * See the header file portable.h.
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+extern void *_SDA2_BASE_, *_SDA_BASE_;
+const unsigned portLONG ulR2 = ( unsigned portLONG ) &_SDA2_BASE_;
+const unsigned portLONG ulR13 = ( unsigned portLONG ) &_SDA_BASE_;
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is essential for the Microblaze port and these lines must
+	not be omitted.  The parameter value will overwrite the 
+	0x22222222 value during the function prologue. */
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x22222222;
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x33333333;
+	pxTopOfStack--; 
+
+	/* First stack an initial value for the critical section nesting.  This
+	is initialised to zero as tasks are started with interrupts enabled. */
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x00;	/* R0. */
+
+	/* Place an initial value for all the general purpose registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) ulR2;	/* R2 - small data area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x03;	/* R3. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x04;	/* R4. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x06;	/* R6. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x07;	/* R7. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x08;	/* R8. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x09;	/* R9. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x0a;	/* R10. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x0b;	/* R11. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x0c;	/* R12. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) ulR13;	/* R13 - small data read write area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) pxCode;	/* R14. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x0f;	/* R15. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x10;	/* R16. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x11;	/* R17. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x12;	/* R18. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x13;	/* R19. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x14;	/* R20. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x15;	/* R21. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x16;	/* R22. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x17;	/* R23. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x18;	/* R24. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x19;	/* R25. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x1a;	/* R26. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x1b;	/* R27. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x1c;	/* R28. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x1d;	/* R29. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x1e;	/* R30. */
+	pxTopOfStack--;
+
+	/* The MSR is stacked between R30 and R31. */
+	*pxTopOfStack = portINITIAL_MSR_STATE;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x1f;	/* R31. */
+	pxTopOfStack--;
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+extern void ( __FreeRTOS_interrupt_Handler )( void );
+extern void ( vStartFirstTask )( void );
+
+
+	/* Setup the FreeRTOS interrupt handler.  Code copied from crt0.s. */
+	asm volatile ( 	"la	r6, r0, __FreeRTOS_interrupt_handler		\n\t" \
+					"sw	r6, r1, r0									\n\t" \
+					"lhu r7, r1, r0									\n\t" \
+					"shi r7, r0, 0x12								\n\t" \
+					"shi r6, r0, 0x16 " );
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Allocate the stack to be used by the interrupt handler. */
+	pulISRStack = ( unsigned portLONG * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
+
+	/* Restore the context of the first task that is going to run. */
+	if( pulISRStack != NULL )
+	{
+		/* Fill the ISR stack with a known value to facilitate debugging. */
+		memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
+		pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
+
+		/* Kick off the first task. */
+		vStartFirstTask();
+	}
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.  
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+	/* Perform the context switch in a critical section to assure it is
+	not interrupted by the tick ISR.  It is not a problem to do this as
+	each task maintains it's own interrupt status. */
+	portENTER_CRITICAL();
+		/* Jump directly to the yield function to ensure there is no
+		compiler generated prologue code. */
+		asm volatile (	"bralid r14, VPortYieldASM		\n\t" \
+						"or r0, r0, r0					\n\t" );
+	portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.   
+ */
+static void prvSetupTimerInterrupt( void )
+{
+XTmrCtr xTimer;
+const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+unsigned portBASE_TYPE uxMask;
+
+	/* The OPB timer1 is used to generate the tick.  Use the provided library
+	functions to enable the timer and set the tick frequency. */
+	XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
+	XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
+   	XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
+	XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
+
+	/* Set the timer interrupt enable bit while maintaining the other bit 
+	states. */
+	uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
+	uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
+	XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );	
+	
+	XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
+	XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
+	XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt handler placed in the interrupt vector when the scheduler is
+ * started.  The task context has already been saved when this is called.
+ * This handler determines the interrupt source and calls the relevant 
+ * peripheral handler.
+ */
+void vTaskISRHandler( void )
+{
+static unsigned portLONG ulPending;    
+
+	/* Which interrupts are pending? */
+	ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
+
+	if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
+	{
+		static XIntc_VectorTableEntry *pxTablePtr;
+		static XIntc_Config *pxConfig;
+		static unsigned portLONG ulInterruptMask;
+
+		ulInterruptMask = ( unsigned portLONG ) 1 << ulPending;
+
+		/* Get the configuration data using the device ID */
+		pxConfig = &XIntc_ConfigTable[ ( unsigned portLONG ) XPAR_INTC_SINGLE_DEVICE_ID ];
+
+		pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
+		if( pxConfig->AckBeforeService & ( ulInterruptMask  ) )
+		{
+			XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
+			pxTablePtr->Handler( pxTablePtr->CallBackRef );
+		}
+		else
+		{
+			pxTablePtr->Handler( pxTablePtr->CallBackRef );
+			XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * Handler for the timer interrupt.
+ */
+void vTickISR( void *pvBaseAddress )
+{
+unsigned portLONG ulCSR;
+
+	/* Increment the RTOS tick - this might cause a task to unblock. */
+	vTaskIncrementTick();
+
+	/* Clear the timer interrupt */
+	ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);	
+	XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
+
+	/* If we are using the preemptive scheduler then we also need to determine
+	if this tick should cause a context switch. */
+	#if configUSE_PREEMPTION == 1
+		vTaskSwitchContext();
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+

20080212/Source/portable/GCC/MicroBlaze/portasm.s

@@ -0,0 +1,171 @@
+	.extern pxCurrentTCB
+	.extern vTaskISRHandler
+	.extern vTaskSwitchContext
+	.extern uxCriticalNesting
+	.extern pulISRStack
+
+	.global __FreeRTOS_interrupt_handler
+	.global VPortYieldASM
+	.global vStartFirstTask
+
+
+.macro portSAVE_CONTEXT
+	/* Make room for the context on the stack. */
+	addik r1, r1, -132
+	/* Save r31 so it can then be used. */
+	swi r31, r1, 4
+	/* Copy the msr into r31 - this is stacked later. */
+	mfs r31, rmsr
+	/* Stack general registers. */
+	swi r30, r1, 12
+	swi r29, r1, 16
+	swi r28, r1, 20
+	swi r27, r1, 24
+	swi r26, r1, 28
+	swi r25, r1, 32
+	swi r24, r1, 36
+	swi r23, r1, 40
+	swi r22, r1, 44
+	swi r21, r1, 48
+	swi r20, r1, 52
+	swi r19, r1, 56
+	swi r18, r1, 60
+	swi r17, r1, 64
+	swi r16, r1, 68
+	swi r15, r1, 72
+	swi r13, r1, 80
+	swi r12, r1, 84
+	swi r11, r1, 88
+	swi r10, r1, 92
+	swi r9, r1, 96
+	swi r8, r1, 100
+	swi r7, r1, 104
+	swi r6, r1, 108
+	swi r5, r1, 112
+	swi r4, r1, 116
+	swi r3, r1, 120
+	swi r2, r1, 124
+	/* Stack the critical section nesting value. */
+	lwi r3, r0, uxCriticalNesting
+	swi r3, r1, 128
+	/* Save the top of stack value to the TCB. */
+	lwi r3, r0, pxCurrentTCB
+	sw	r1, r0, r3
+	
+	.endm
+
+.macro portRESTORE_CONTEXT
+	/* Load the top of stack value from the TCB. */
+	lwi r3, r0, pxCurrentTCB
+	lw	r1, r0, r3	
+	/* Restore the general registers. */
+	lwi r31, r1, 4		
+	lwi r30, r1, 12		
+	lwi r29, r1, 16	
+	lwi r28, r1, 20	
+	lwi r27, r1, 24	
+	lwi r26, r1, 28	
+	lwi r25, r1, 32	
+	lwi r24, r1, 36	
+	lwi r23, r1, 40	
+	lwi r22, r1, 44	
+	lwi r21, r1, 48	
+	lwi r20, r1, 52	
+	lwi r19, r1, 56	
+	lwi r18, r1, 60	
+	lwi r17, r1, 64	
+	lwi r16, r1, 68	
+	lwi r15, r1, 72	
+	lwi r14, r1, 76	
+	lwi r13, r1, 80	
+	lwi r12, r1, 84	
+	lwi r11, r1, 88	
+	lwi r10, r1, 92	
+	lwi r9, r1, 96	
+	lwi r8, r1, 100	
+	lwi r7, r1, 104
+	lwi r6, r1, 108
+	lwi r5, r1, 112
+	lwi r4, r1, 116
+	lwi r2, r1, 124
+
+	/* Load the critical nesting value. */
+	lwi r3, r1, 128
+	swi r3, r0, uxCriticalNesting
+
+	/* Obtain the MSR value from the stack. */
+	lwi r3, r1, 8
+
+	/* Are interrupts enabled in the MSR?  If so return using an return from 
+	interrupt instruction to ensure interrupts are enabled only once the task
+	is running again. */
+	andi r3, r3, 2
+	beqid r3, 36
+	or r0, r0, r0
+
+	/* Reload the rmsr from the stack, clear the enable interrupt bit in the
+	value before saving back to rmsr register, then return enabling interrupts
+	as we return. */
+	lwi r3, r1, 8
+	andi r3, r3, ~2
+	mts rmsr, r3
+	lwi r3, r1, 120
+	addik r1, r1, 132
+	rtid r14, 0
+	or r0, r0, r0
+
+	/* Reload the rmsr from the stack, place it in the rmsr register, and
+	return without enabling interrupts. */
+	lwi r3, r1, 8
+	mts rmsr, r3
+	lwi r3, r1, 120
+	addik r1, r1, 132
+	rtsd r14, 0
+	or r0, r0, r0
+
+	.endm
+
+	.text
+	.align  2
+
+
+__FreeRTOS_interrupt_handler:
+	portSAVE_CONTEXT
+	/* Entered via an interrupt so interrupts must be enabled in msr. */
+	ori r31, r31, 2
+	/* Stack msr. */
+	swi r31, r1, 8
+	/* Stack the return address.  As we entered via an interrupt we do
+	not need to modify the return address prior to stacking. */
+	swi r14, r1, 76
+	/* Now switch to use the ISR stack. */
+	lwi r3, r0, pulISRStack
+	add r1, r3, r0
+	bralid r15, vTaskISRHandler
+	or r0, r0, r0
+	portRESTORE_CONTEXT
+
+
+VPortYieldASM:
+	portSAVE_CONTEXT
+	/* Stack msr. */
+	swi r31, r1, 8
+	/* Modify the return address so we return to the instruction after the
+	exception. */
+	addi r14, r14, 8
+	swi r14, r1, 76
+	/* Now switch to use the ISR stack. */
+	lwi r3, r0, pulISRStack
+	add r1, r3, r0
+	bralid r15, vTaskSwitchContext
+	or r0, r0, r0
+	portRESTORE_CONTEXT
+
+vStartFirstTask:
+	portRESTORE_CONTEXT
+	
+	
+
+
+
+

20080212/Source/portable/GCC/MicroBlaze/portmacro.h

@@ -0,0 +1,133 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned portLONG
+#define portBASE_TYPE	portLONG
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/	
+
+/* Interrupt control macros. */
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS()	microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS()		microblaze_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL()		{														\
+										extern unsigned portBASE_TYPE uxCriticalNesting;	\
+										microblaze_disable_interrupts();					\
+										uxCriticalNesting++;								\
+									}
+									
+#define portEXIT_CRITICAL()			{														\
+										extern unsigned portBASE_TYPE uxCriticalNesting;	\
+										/* Interrupts are disabled, so we can */			\
+										/* access the variable directly. */					\
+										uxCriticalNesting--;								\
+										if( uxCriticalNesting == 0 )			\
+										{													\
+											/* The nesting has unwound and we 				\
+											can enable interrupts again. */					\
+											portENABLE_INTERRUPTS();						\
+										}													\
+									}
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() vPortYield()
+
+void vTaskSwitchContext();
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+#define portNOP()					asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

20080212/Source/portable/GCC/STR75x/port.c

@@ -0,0 +1,208 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ST STR75x ARM7
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include "75x_tb.h"
+#include "75x_eic.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( portSTACK_TYPE ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( portSTACK_TYPE ) 4 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( unsigned portLONG ) 0 )
+
+/* Prescale used on the timer clock when calculating the tick period. */
+#define portPRESCALE 20
+
+
+/*-----------------------------------------------------------*/
+
+/* Setup the TB to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+portSTACK_TYPE *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
+
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+extern void vPortISRStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+EIC_IRQInitTypeDef  EIC_IRQInitStructure;	
+TB_InitTypeDef      TB_InitStructure;
+
+	/* Setup the EIC for the TB. */
+	EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
+	EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
+	EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
+	EIC_IRQInit(&EIC_IRQInitStructure);
+	
+	/* Setup the TB for the generation of the tick interrupt. */
+	TB_InitStructure.TB_Mode = TB_Mode_Timing;
+	TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
+	TB_InitStructure.TB_Prescaler = portPRESCALE;
+	TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / ( portPRESCALE + 1 ) ) / configTICK_RATE_HZ ) + 1;
+	TB_Init(&TB_InitStructure);
+	
+	/* Enable TB Update interrupt */
+	TB_ITConfig(TB_IT_Update, ENABLE);
+
+	/* Clear TB Update interrupt pending bit */
+	TB_ClearITPendingBit(TB_IT_Update);
+
+	/* Enable TB */
+	TB_Cmd(ENABLE);
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
+

20080212/Source/portable/GCC/STR75x/portISR.c

@@ -0,0 +1,198 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( unsigned portLONG ) 0 )
+
+volatile unsigned portLONG ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	asm volatile (														\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS PC, LR, #4											\n\t"	\
+	);																	
+}
+/*-----------------------------------------------------------*/
+
+void vPortTickISR( void )
+{
+	/* Increment the RTOS tick count, then look for the highest priority 
+	task that is ready to run. */
+	vTaskIncrementTick();
+	
+	#if configUSE_PREEMPTION == 1
+		vTaskSwitchContext();
+	#endif
+			
+	/* Ready for the next interrupt. */
+	TB_ClearITPendingBit( TB_IT_Update );	
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+			
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	asm volatile ( 
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			asm volatile ( 
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
+
+
+
+
+

20080212/Source/portable/GCC/STR75x/portmacro.h

@@ -0,0 +1,155 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned portLONG
+#define portBASE_TYPE	portLONG
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/	
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+#define portBYTE_ALIGNMENT			4
+#define portYIELD()					asm volatile ( "SWI 0" )
+#define portNOP()					asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/	
+
+/* Critical section handling. */
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in 
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not 
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+	
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+			
+	#define portENABLE_INTERRUPTS()												\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/	
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/	
+
+/* Compiler specifics */
+#define inline
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+