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Richard Barry
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247
20080212/Demo/WizNET_DEMO_TERN_186/include/SOCKET.H
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247
20080212/Demo/WizNET_DEMO_TERN_186/include/SOCKET.H
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/*
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********************************************************************************
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* TERN, Inc.
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* (c) Copyright 2005, http://www.tern.com
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*
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* - Derived based on development version provided by Wiznet.
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*
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* Filename : socket.h
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* Programmer(s):
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* Created : 2002/06/20
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* Modified :
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* 2002/09/27 : - Renaming
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* INT_STATUS --> INT_REG
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* STATUS(i) --> INT_STATUS(i)
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* C_STATUS(i) --> SOCK_STATUS(i)
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* 2003/11/06 : Ported for use with TERN controller. Note all byte access is at even addresses
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* 2005/10/8 : Modified constants for easier initialization.
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*
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* Description : Header file of W3100A for TERN embedded controller
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********************************************************************************
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*/
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#ifndef __SOCKET_H__
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#define __SOCKET_H__
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#include "types.h"
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#include "i2chip_hw.h"
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#include <dos.h>
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/*******************************************************************/
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#define MAX_SOCK_NUM 4 // Concurrent maxmium number of socket
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#define I2CHIP_C0_CR 0x00
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#define I2CHIP_C1_CR 0x01
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#define I2CHIP_C2_CR 0x02
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#define I2CHIP_C3_CR 0x03
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#define I2CHIP_C0_ISR 0x04
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#define I2CHIP_C1_ISR 0x05
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#define I2CHIP_C2_ISR 0x06
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#define I2CHIP_C3_ISR 0x07
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#define I2CHIP_IR 0x08
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#define I2CHIP_IMR 0x09
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#define I2CHIP_IDM_OR 0x0C
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#define I2CHIP_IDM_AR0 0x0D
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#define I2CHIP_IDM_AR1 0x0E
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#define I2CHIP_IDM_DR 0x0F
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#define I2CHIP_C0_RW_PR 0x10
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#define I2CHIP_C0_RR_PR 0x14
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#define I2CHIP_C0_TA_PR 0x18
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#define I2CHIP_C1_RW_PR 0x1C
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#define I2CHIP_C1_RR_PR 0x20
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#define I2CHIP_C1_TA_PR 0x24
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#define I2CHIP_C2_RW_PR 0x28
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#define I2CHIP_C2_RR_PR 0x2C
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#define I2CHIP_C2_TA_PR 0x30
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#define I2CHIP_C3_RW_PR 0x34
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#define I2CHIP_C3_RR_PR 0x38
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#define I2CHIP_C3_TA_PR 0x3C
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#define I2CHIP_C0_TW_PR 0x40
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#define I2CHIP_C0_TR_PR 0x44
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#define I2CHIP_C1_TW_PR 0x4C
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#define I2CHIP_C1_TR_PR 0x50
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#define I2CHIP_C2_TW_PR 0x58
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#define I2CHIP_C2_TR_PR 0x5C
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#define I2CHIP_C3_TW_PR 0x64
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#define I2CHIP_C3_TR_PR 0x68
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#define I2CHIP_GAR 0x80
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#define I2CHIP_SMR 0x84
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#define I2CHIP_SHAR 0x88
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#define I2CHIP_SIPR 0x8E
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#define I2CHIP_IRTR 0x92
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#define I2CHIP_RCR 0x94
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#define I2CHIP_RMSR 0x95
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#define I2CHIP_TMSR 0x96
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#define I2CHIP_C0_SSR 0xA0
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#define I2CHIP_C0_SOPR 0xA1
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#define I2CHIP_C0_DIR 0xA8
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#define I2CHIP_CO_DPR 0xAC
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#define I2CHIP_C0_SPR 0xAE
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#define I2CHIP_C0_IPR 0xB0
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#define I2CHIP_C0_TOSR 0xB1
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#define I2CHIP_C0_MSSR 0xB2
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#define I2CHIP_C1_SSR 0xB8
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#define I2CHIP_C1_SOPR 0xB9
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#define I2CHIP_C1_DIR 0xC0
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#define I2CHIP_C1_DPR 0xC4
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#define I2CHIP_C1_SPR 0xC6
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#define I2CHIP_C1_IPR 0xC8
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#define I2CHIP_C1_TOSR 0xC9
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#define I2CHIP_C1_MSSR 0xCA
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#define I2CHIP_C2_SSR 0xD0
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#define I2CHIP_C2_SOPR 0xD1
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#define I2CHIP_C2_DIR 0xD8
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#define I2CHIP_C2_DPR 0xDC
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#define I2CHIP_C2_SPR 0xDE
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#define I2CHIP_C2_IPR 0xE0
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#define I2CHIP_C2_TOSR 0xE1
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#define I2CHIP_C2_MSSR 0xE2
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#define I2CHIP_C3_SSR 0xE8
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#define I2CHIP_C3_SOPR 0xE9
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#define I2CHIP_C3_DIR 0xF0
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#define I2CHIP_C3_DPR 0xF4
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#define I2CHIP_C3_SPR 0xF6
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#define I2CHIP_C3_IPR 0xF8
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#define I2CHIP_C3_TOSR 0xF9
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#define I2CHIP_C3_MSSR 0xFA
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#define MAX_SEGMENT_SIZE 1460 // Maximum TCP transmission packet size
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#define MAX_BUF_SIZE1 0
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/* SOCKET OPTION(Settting OPT_PROTOCOL REG.) */
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#define SOCKOPT_BROADCAST 0x80 // Transmission, Reception of broadcasting data
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#define SOCKOPT_NDTIMEOUT 0x40 // Setting timeout
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#define SOCKOPT_NDACK 0x20 // Setting No Delayed Ack(TCP)
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#define SOCKOPT_SWS 0x10 // Setting Silly Window Syndrome(TCP)
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/* OPTION(Setting OPT_PROTOCOL REG.) for MAC LAYER RAW MODE */
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#define MACLOPT_RXERR 0x80 // Setting reception of error packet
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#define MACLOPT_BROADCAST 0x40 // Setting reception of broadcast packet
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#define MACLOPT_PROMISC 0x20 // Setting reception of promiscuous packet
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/* Distinguish TCP / UDP / IP RAW / MAC RAW (Setting OPT_PROTOCOL REG.) */
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#define SOCK_CLOSEDM 0x00 // unused socket
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#define SOCK_STREAM 0x01 // TCP
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#define SOCK_DGRAM 0x02 // UDP
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#define SOCK_IPL_RAW 0x03 // IP LAYER RAW SOCK
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#define SOCK_MACL_RAW 0x04 // MAC LAYER RAW SOCK
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/* Setting IP PROTOCOL */
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#define IPPROTO_IP 0 // dummy for IP
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#define IPPROTO_ICMP 1 // control message protocol
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#define IPPROTO_IGMP 2 // internet group management protocol
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#define IPPROTO_GGP 3 // gateway^2 (deprecated)
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#define IPPROTO_TCP 6 // tcp
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#define IPPROTO_PUP 12 // pup
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#define IPPROTO_UDP 17 // user datagram protocol
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#define IPPROTO_IDP 22 // xns idp
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#define IPPROTO_ND 77 // UNOFFICIAL net disk proto
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#define IPPROTO_RAW 255 // raw IP packet
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/* Select parameter to use */
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#define SEL_CONTROL 0 //Confirm socket status
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#define SEL_SEND 1 // Confirm Tx free buffer size
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#define SEL_RECV 2 // Confirm Rx data size
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/* Command variables */
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#define CSYS_INIT 0x01 // To set up network information(mac address, gateway address,
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// subnet mask, source ip)
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#define CSOCK_INIT 0x02 // To initialize socket
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#define CCONNECT 0x04 // To establish connection as tcp client mode
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#define CLISTEN 0x08 // To wait for connection request as tcp server mode
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#define CCLOSE 0x10 // To terminate connection
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#define CSEND 0x20 // To send data
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#define CRECV 0x40 // To receive data
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#define CSW_RESET 0x80 // To do software reset
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#define CSET_MEMORY_TEST 0x80 // To set the memory test bit
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#define CRESET_MEMORY_TEST 0x00 // To clear the memory test bit
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/* Status Variables */
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#define SSYS_INIT_OK 0x01 // Completion of CSYS_INIT command
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#define SSOCK_INIT_OK 0x02 // Completion of CSOCK_INIT command
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#define SESTABLISHED 0x04 // Completion of connection setup
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#define SCLOSED 0x08 // Completion of CCLOSED command
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#define SSEND_OK 0x20 // Completion of sending data
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#define SRECV_OK 0x40 // Completion of receiving data
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/* Socket Status Vabiables */
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#define SOCK_CLOSED 0x00 // Status of connection closed
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#define SOCK_ARP 0x01 // Status of ARP
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#define SOCK_LISTEN 0x02 // Status of waiting for TCP connection setup
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#define SOCK_SYNSENT 0x03 // Status of setting up TCP connection
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#define SOCK_SYNSENT_ACK 0x04 // Status of setting up TCP connection
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#define SOCK_SYNRECV 0x05 // Status of setting up TCP connection
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#define SOCK_ESTABLISHED 0x06 // Status of TCP connection established
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#define SOCK_CLOSE_WAIT 0x07 // Status of closing TCP connection
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#define SOCK_LAST_ACK 0x08 // Status of closing TCP connection
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#define SOCK_FIN_WAIT1 0x09 // Status of closing TCP connection
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#define SOCK_FIN_WAIT2 0x0A // Status of closing TCP connection
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#define SOCK_CLOSING 0x0B // Status of closing TCP connection
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#define SOCK_TIME_WAIT 0x0C // Status of closing TCP connection
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#define SOCK_RESET 0x0D // Status of closing TCP connection
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#define SOCK_INIT 0x0E // Status of socket initialization
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#define SOCK_UDP 0x0F // Status of UDP
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#define SOCK_RAW 0x10 // Status of IP RAW
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/* TERN Behavior Parameters */
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#define TERN_TDMA_THRES 10000 // Use DMA for transmits if data > thres bytes.
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#define TERN_RDMA_THRES 10000 // Use DMA for receives if data > thres bytes.
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// High thres value effectively disables DMA
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void far interrupt in4_isr_i2chip(void);
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//void ISR_ESTABLISHED(SOCKET s);
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//void ISR_CLOSED(SOCKET s);
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//void ISR_RX(SOCKET s);
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void initW3100A(void);
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void sysinit(u_char sbufsize, u_char rbufsize);
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void setsubmask(u_char * addr);
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void setgateway(u_char * addr);
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void setMACAddr(u_char * addr);
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void setIP(u_char * addr);
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char socket(SOCKET s, u_char protocol, u_int port, u_char flag);
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void setIPprotocol(SOCKET s, u_char ipprotocol);
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void setINTMask(u_char mask);
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void settimeout(u_char * val);
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void setTOS(SOCKET s, u_char tos);
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void GetDestAddr(SOCKET s, u_char* addr);
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//void setbroadcast(SOCKET s);
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char connect(SOCKET s, u_char far * addr, u_int port);
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char NBconnect(SOCKET s, u_char far * addr, u_int port);
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//char listen(SOCKET s, u_char far * addr, u_int far * port);
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char NBlisten(SOCKET s);
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void initseqnum(SOCKET s);
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int send(SOCKET s, u_char far * buf, u_int len);
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int send_in(SOCKET s, u_char far * buf, u_int len);
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int recv(SOCKET s, u_char far * buf, u_int len);
|
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|
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u_int sendto(SOCKET , u_char far * buf, u_int, u_char * addr, u_int);
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u_int sendto_in(SOCKET , u_char far *, u_int);
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u_int recvfrom(SOCKET , u_char far * buf, u_int, u_char * addr, u_int *);
|
||||
|
||||
u_int read_data(SOCKET s, u_int src_offset, u_char far * dst, u_int len);
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u_int write_data(SOCKET s, u_char far * src, u_int dst_offset, u_int len);
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|
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void close(SOCKET s);
|
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char reset_sock(SOCKET s);
|
||||
|
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u_int select(SOCKET s, u_char func);
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void recv_clear(SOCKET s);
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u_char tx_empty(SOCKET s);
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#endif // __SOCKET_H__
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64
20080212/Demo/WizNET_DEMO_TERN_186/include/TYPES.H
Normal file
64
20080212/Demo/WizNET_DEMO_TERN_186/include/TYPES.H
Normal file
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@ -0,0 +1,64 @@
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/*
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********************************************************************************
|
||||
* Wiznet.
|
||||
* 5F Simmtech Bldg., 228-3, Nonhyun-dong, Kangnam-gu,
|
||||
* Seoul, Korea
|
||||
*
|
||||
* (c) Copyright 2002, Wiznet, Seoul, Korea
|
||||
*
|
||||
* Filename : types.h
|
||||
* Programmer(s):
|
||||
* Created : 2002/01/
|
||||
* Modified :
|
||||
* Description : Define of data type.
|
||||
********************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _TYPES_H_
|
||||
#define _TYPES_H_
|
||||
|
||||
#ifndef NULL
|
||||
# define NULL ((void *) 0)
|
||||
#endif
|
||||
|
||||
typedef enum { false, true } bool;
|
||||
|
||||
#ifndef _SIZE_T
|
||||
#define _SIZE_T
|
||||
typedef unsigned int size_t;
|
||||
#endif
|
||||
|
||||
typedef unsigned char BYTE; // 8-bit value
|
||||
typedef unsigned char UCHAR; // 8-bit value
|
||||
typedef int INT; // 16-bit value
|
||||
typedef unsigned int UINT; // 16-bit value
|
||||
typedef unsigned short USHORT; // 16-bit value
|
||||
typedef unsigned short WORD; // 16-bit value
|
||||
typedef unsigned long ULONG; // 32-bit value
|
||||
typedef unsigned long DWORD; // 32-bit value
|
||||
|
||||
// bsd
|
||||
typedef unsigned char u_char; // 8-bit value
|
||||
typedef unsigned short u_short; // 16-bit value
|
||||
typedef unsigned int u_int; // 16-bit value
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||||
typedef unsigned long u_long; // 32-bit value
|
||||
|
||||
typedef UCHAR SOCKET;
|
||||
|
||||
|
||||
/* Type for treating 4 byte variables with byte by byte */
|
||||
typedef union un_l2cval
|
||||
{
|
||||
u_long lVal;
|
||||
u_char cVal[4];
|
||||
};
|
||||
|
||||
/* Type for treating 2 byte variables with byte by byte */
|
||||
typedef union un_i2cval
|
||||
{
|
||||
u_int iVal;
|
||||
u_char cVal[2];
|
||||
};
|
||||
|
||||
#endif // _TYPES_H_
|
||||
|
||||
264
20080212/Demo/WizNET_DEMO_TERN_186/include/ae.H
Normal file
264
20080212/Demo/WizNET_DEMO_TERN_186/include/ae.H
Normal file
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|
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#ifndef _AE_H_
|
||||
#define _AE_H_
|
||||
|
||||
/*********************************************************************
|
||||
ae.h headers for AM188ES 6-20-99 7-16-98
|
||||
*********************************************************************/
|
||||
/* Data structure for Serial operation */
|
||||
|
||||
typedef struct {
|
||||
unsigned char ready; /* TRUE when ready */
|
||||
unsigned char baud;
|
||||
unsigned int mode;
|
||||
unsigned char iflag; /* interrupt status */
|
||||
unsigned char* in_buf; /* Input buffer */
|
||||
unsigned int in_tail; /* Input buffer TAIL ptr */
|
||||
unsigned int in_head; /* Input buffer HEAD ptr */
|
||||
unsigned int in_size; /* Input buffer size */
|
||||
unsigned int in_crcnt; /* Input <CR> count */
|
||||
unsigned char in_mt; /* Input buffer FLAG */
|
||||
unsigned char in_full; /* input buffer full */
|
||||
unsigned char* out_buf; /* Output buffer */
|
||||
unsigned int out_tail; /* Output buffer TAIL ptr */
|
||||
unsigned int out_head; /* Output buffer HEAD ptr */
|
||||
unsigned int out_size; /* Output buffer size */
|
||||
unsigned char out_full; /* Output buffer FLAG */
|
||||
unsigned char out_mt; /* Output buffer MT */
|
||||
unsigned char tmso; // transmit macro service operation
|
||||
unsigned char rts;
|
||||
unsigned char dtr;
|
||||
unsigned char en485;
|
||||
unsigned char err;
|
||||
unsigned char node;
|
||||
unsigned char cr; /* scc CR register */
|
||||
unsigned char slave;
|
||||
unsigned int in_segm; /* input buffer segment */
|
||||
unsigned int in_offs; /* input buffer offset */
|
||||
unsigned int out_segm; /* output buffer segment */
|
||||
unsigned int out_offs; /* output buffer offset */
|
||||
unsigned char byte_delay; /* V25 macro service byte delay */
|
||||
} COM;
|
||||
|
||||
|
||||
typedef struct{
|
||||
unsigned char sec1;
|
||||
unsigned char sec10;
|
||||
unsigned char min1;
|
||||
unsigned char min10;
|
||||
unsigned char hour1;
|
||||
unsigned char hour10;
|
||||
unsigned char day1;
|
||||
unsigned char day10;
|
||||
unsigned char mon1;
|
||||
unsigned char mon10;
|
||||
unsigned char year1;
|
||||
unsigned char year10;
|
||||
unsigned char wk;
|
||||
} TIM;
|
||||
|
||||
void ae_init(void);
|
||||
void ae_reset(void);
|
||||
void led(int i); //P12 used for led
|
||||
void delay_ms(int m);
|
||||
void delay0(unsigned int t);
|
||||
void HLPRsetvect(
|
||||
unsigned int wVec, /* Interrupt vector number */
|
||||
void far *ih /* Interrupt handler to install */
|
||||
);
|
||||
|
||||
void clka_en(int i);
|
||||
void clkb_en(int i);
|
||||
void pwr_save_en(int i);
|
||||
void hitwd(void);
|
||||
|
||||
//
|
||||
// reset ee to remain enabled for reads
|
||||
// where s = segment register value pointing to ee starting addr.
|
||||
// for example = 0x8000
|
||||
//
|
||||
void amd_ee_read_reset(unsigned int s);
|
||||
|
||||
//
|
||||
// sec=0x00-0x07 for AM29F010, 16K/sector
|
||||
// sec=0 0x00000-0x03fff
|
||||
// sec=1 0x04000-0x07fff
|
||||
// sec=2 0x08000-0x0bfff
|
||||
// sec=3 0x0c000-0x0ffff
|
||||
// sec=4 0x10000-0x13fff
|
||||
// sec=5 0x14000-0x17fff
|
||||
// sec=6 0x18000-0x1bfff
|
||||
// sec=7 0x1c000-0x1ffff
|
||||
//
|
||||
// sec=0x10-0x17 for AM29F040
|
||||
// sec=10 0x00000-0x0ffff
|
||||
// sec=11 0x10000-0x1ffff
|
||||
// sec=12 0x20000-0x2ffff
|
||||
// sec=13 0x30000-0x3ffff
|
||||
// sec=14 0x40000-0x4ffff
|
||||
// sec=15 0x50000-0x5ffff
|
||||
// sec=16 0x60000-0x6ffff
|
||||
// sec=17 0x70000-0x7ffff
|
||||
// segm=segment register value pointing to ee address 0
|
||||
// returns: if pass, return(0);
|
||||
// if fail, return(1);
|
||||
//
|
||||
int amd_ee_sec_erase(unsigned int segm, unsigned char sec );
|
||||
|
||||
//
|
||||
// write one byte dat to AM29F040, at address of s:o
|
||||
// Approximately 70 us for 0 wait, 80us for 1 wait.
|
||||
// where s=segment register, it is fixed to 0x8000
|
||||
// o=offset register
|
||||
// returns: if pass, return(0);
|
||||
// if fail, return(1);
|
||||
//
|
||||
// Be aware of that a data bit "0" can not be programmed back to a "1" !!!
|
||||
// Attempting to do so will hang up the system !!!
|
||||
// you can program the "1"s to "0"s.
|
||||
// Only erase operation can convert "0"s to "1"s
|
||||
//
|
||||
//
|
||||
|
||||
int amd_ee_byte_pro_512(unsigned int s, unsigned int o, unsigned char dat);
|
||||
|
||||
//
|
||||
// write one byte dat to AM29F010, at address of s:o, 80us per byte approx.
|
||||
// where s=segment register, you may use s=0x8000-0xe000
|
||||
// o=offset register
|
||||
// returns: if pass, return(0);
|
||||
// if fail, return(1);
|
||||
//
|
||||
// Be aware of that a data bit "0" can not be programmed back to a "1" !!!
|
||||
// Attempting to do so will hang up the system !!!
|
||||
// you can program the "1"s to "0"s.
|
||||
// Only erase operation can convert "0"s to "1"s
|
||||
//
|
||||
|
||||
int amd_ee_byte_pro_128(unsigned int s, unsigned int o, unsigned char dat);
|
||||
|
||||
//
|
||||
// unsigned char rtc_rds(char* time_string);
|
||||
// put a time string into time_string, based on the reading of RTC.
|
||||
// At least 15 bytes of buffer must be available for the time_string
|
||||
// returns 0, if RTC OK, or returns 1, if problem
|
||||
//
|
||||
unsigned char rtc_rds(char* time_string);
|
||||
int rtc_rd(TIM *r);
|
||||
void rtc_init(unsigned char*);
|
||||
unsigned char r_rd(void);
|
||||
int r_out(unsigned char v);
|
||||
|
||||
|
||||
void t2_init(unsigned int tm,unsigned int ta,void interrupt far(*t2_isr)());
|
||||
void t1_init(unsigned int tm,unsigned int ta,unsigned int tb,void interrupt far(*t1_isr)());
|
||||
void t0_init(unsigned int tm,unsigned int ta,unsigned int tb,void interrupt far(*t0_isr)());
|
||||
unsigned int t2_rd(void);
|
||||
unsigned int t1_rd(void);
|
||||
unsigned int t0_rd(void);
|
||||
|
||||
// Analog to Digital conversion using TLC2543 on the A-Engine-88/86
|
||||
// Input:
|
||||
// unsigned char c = input channel
|
||||
// c = 0, input ch = AD0
|
||||
// c = 1, input ch = AD1
|
||||
// c = 2, input ch = AD2
|
||||
// c = 3, input ch = AD3
|
||||
// c = 4, input ch = AD4
|
||||
// c = 5, input ch = AD5
|
||||
// c = 6, input ch = AD6
|
||||
// c = 7, input ch = AD7
|
||||
// c = 8, input ch = AD8
|
||||
// c = 9, input ch = AD9
|
||||
// c = a, input ch = AD10
|
||||
// In order to operate ADC, P11 must be input.
|
||||
// P11 is shared by RTC, EE. It must be high while power on/reset
|
||||
// For AE88, using PPI for ADC, I20,I21,I22 must be output
|
||||
// For AE86, using PAL for ADC, T0=CLK, T1=DIN, T2=ADCS
|
||||
// Enter the ae_ad12(unsigned char c); EE is stopped first.
|
||||
// Enter the ae86_ad12(unsigned char c); EE is stopped first.
|
||||
//
|
||||
// Output: 12 bit AD data of the previous channel !
|
||||
// Unipolar:
|
||||
// (Vref+ - Vref-)=0x7ff
|
||||
// Vref- = 0x000
|
||||
// Vref+ = 0xfff
|
||||
//
|
||||
//
|
||||
int ae_ad12(unsigned char c);
|
||||
|
||||
// outportb(0x120,1); // T0=0, CLK
|
||||
// outportb(0x128,1); // T1=0, DIN
|
||||
// outportb(0x130,1); // T2=0, ADCS
|
||||
int ae86_ad12(unsigned char c);
|
||||
|
||||
void nmi_init(void interrupt far (* nmi_isr)());
|
||||
void int0_init(unsigned char i, void interrupt far (*int0_isr)());
|
||||
void int1_init(unsigned char i, void interrupt far (*int1_isr)());
|
||||
void int2_init(unsigned char i, void interrupt far (*int2_isr)());
|
||||
void int3_init(unsigned char i, void interrupt far (*int3_isr)());
|
||||
void int4_init(unsigned char i, void interrupt far (*int4_isr)());
|
||||
void int5_init(unsigned char i, void interrupt far (*int5_isr)());
|
||||
void int6_init(unsigned char i, void interrupt far (*int6_isr)());
|
||||
|
||||
|
||||
//
|
||||
// void pio_init(char bit, char mode)
|
||||
// where bit=0-31
|
||||
// mode=0, Normal operation
|
||||
// mode=1, Input with pullup/down
|
||||
// mode=2, Output
|
||||
// mode=3, input without pull
|
||||
//
|
||||
void pio_init(char bit, char mode);
|
||||
|
||||
|
||||
//
|
||||
// void pio_wr(char bit, char dat)
|
||||
// where bit=0-31
|
||||
// dat=0/1
|
||||
//
|
||||
void pio_wr(char bit, char dat);
|
||||
|
||||
//
|
||||
// unsigned int pio_rd(char port)
|
||||
// return P15-P0, if port=0
|
||||
// return P31-P16, if port=1
|
||||
//
|
||||
unsigned int pio_rd(char port);
|
||||
|
||||
// setup I/O wait states for I/O instructions
|
||||
// where wait = 0-7
|
||||
// wait=0, wait states = 0, I/O enable for 100 ns
|
||||
// wait=1, wait states = 1, I/O enable for 100+25 ns
|
||||
// wait=2, wait states = 2, I/O enable for 100+50 ns
|
||||
// wait=3, wait states = 3, I/O enable for 100+75 ns
|
||||
// wait=4, wait states = 5, I/O enable for 100+125 ns
|
||||
// wait=5, wait states = 7, I/O enable for 100+175 ns
|
||||
// wait=6, wait states = 9, I/O enable for 100+225 ns
|
||||
// wait=7, wait states = 15, I/O enable for 100+375 ns
|
||||
void io_wait(char wait);
|
||||
|
||||
unsigned int crc16(unsigned char *wptr, unsigned int count);
|
||||
|
||||
/******************************************************
|
||||
void ae_da(int dat1, int dat2)
|
||||
output dat to U11 DAC of AE88
|
||||
Requires P12=CLK, P26=DI, P29=LD/CS as output pins !
|
||||
where dat1 for channel A, dat2 for channel B; dat1/2 = 0-4095
|
||||
*******************************************************/
|
||||
void ae_da(int dat1, int dat2);
|
||||
|
||||
/******************************************************
|
||||
void ae86_da(int dat1, int dat2)
|
||||
output dat to U15 DAC of AE86
|
||||
Requires T0=CLK=0x120, T1=DI=0x128, T3=LD/CS=0x138
|
||||
where dat1 for channel A, dat2 for channel B; dat1/2 = 0-4095
|
||||
Output 0-2.5V at VA=J4.16, VB=J4.18
|
||||
*******************************************************/
|
||||
void ae86_da(int dat1, int dat2);
|
||||
void interrupt reset_io_trap();
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
309
20080212/Demo/WizNET_DEMO_TERN_186/include/i2chip_hw.h
Normal file
309
20080212/Demo/WizNET_DEMO_TERN_186/include/i2chip_hw.h
Normal file
|
|
@ -0,0 +1,309 @@
|
|||
/*
|
||||
********************************************************************************
|
||||
* TERN, Inc.
|
||||
* (c) Copyright 2005, http://www.tern.com
|
||||
*
|
||||
* - Created to support i2chip module on a variety of TERN hardware platforms.
|
||||
********************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _I2CHIP_HW_H_
|
||||
#define _I2CHIP_HW_H_
|
||||
|
||||
#include "types.h"
|
||||
|
||||
#ifdef TERN_SC // SensorCore controller, has mapping identical to the RL
|
||||
#define TERN_RL
|
||||
#endif
|
||||
|
||||
#ifdef TERN_RL // R-Engine-L controller, with mapping at MCS0.
|
||||
#define I2CHIP_MCS_DIRECT
|
||||
#define I2CHIP_INT4
|
||||
#define TERN_RE
|
||||
#endif // TERN_RL
|
||||
|
||||
#ifdef TERN_5E
|
||||
#define TERN_586
|
||||
#endif
|
||||
|
||||
#ifdef TERN_RD
|
||||
#define TERN_RE
|
||||
#endif // TERN_RD
|
||||
|
||||
#ifdef TERN_RE
|
||||
#define TERN_186
|
||||
#endif
|
||||
|
||||
#ifdef TERN_P51
|
||||
void p51_window(unsigned int page);
|
||||
#define I2CHIP_WINDOW
|
||||
#define I2CHIP_P51
|
||||
#ifdef TERN_186
|
||||
#define I2CHIP_INT4
|
||||
#define TERN_16_BIT
|
||||
#endif // TERN_186
|
||||
#ifdef TERN_586
|
||||
#define I2CHIP_INT0
|
||||
#define I2CHIP_WINDOW_IO
|
||||
#endif // TERN_586
|
||||
#endif // TERN_P51
|
||||
|
||||
#ifdef TERN_CEYE
|
||||
#define TERN_EE // C-Eye configured with onboard i2chip, same as EE
|
||||
#endif
|
||||
|
||||
#ifdef TERN_EE
|
||||
#define TERN_186
|
||||
#define I2CHIP_MCS_DIRECT
|
||||
#define I2CHIP_INT4
|
||||
#define TERN_16_BIT
|
||||
#endif // TERN_EE
|
||||
|
||||
#ifdef TERN_MMC
|
||||
#define I2CHIP_WINDOW
|
||||
#define I2CHIP_MMC
|
||||
#ifdef TERN_RD
|
||||
#define I2CHIP_INT3
|
||||
#else
|
||||
#ifdef TERN_186
|
||||
#define I2CHIP_INT4
|
||||
#endif // TERN_186
|
||||
#endif // TERN_RD
|
||||
#ifdef TERN_586
|
||||
#define I2CHIP_INT0
|
||||
#define I2CHIP_WINDOW_IO
|
||||
#endif // TERN_586
|
||||
#endif // TERN_MMC
|
||||
|
||||
#ifdef TERN_586
|
||||
#include "586.h"
|
||||
void interrupt far int0_isr(void);
|
||||
void interrupt far spu_m_isr(void);
|
||||
void interrupt far spu_1_isr(void);
|
||||
void interrupt far spu_2_isr(void);
|
||||
#define MMCR 0xdf00
|
||||
#endif // TERN_586
|
||||
|
||||
#ifdef TERN_186
|
||||
#ifndef TERN_RE
|
||||
#include "ae.h"
|
||||
#else
|
||||
#include "re.h"
|
||||
#define I2CHIP_SHIFTED_ADDRESS
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef I2CHIP_MCS_DIRECT
|
||||
#ifndef I2CHIP_WINDOW
|
||||
#ifndef I2CHIP_WINDOW_IO
|
||||
#error You must define the TERN address mapping used to drive the I2CHIP module!
|
||||
#endif // I2CHIP_WINDOW_IO
|
||||
#endif // I2CHIP_MMC_WINDOW
|
||||
#endif // I2CHIP_MCS_DIRECT
|
||||
|
||||
#ifndef I2CHIP_INT0
|
||||
#ifndef I2CHIP_INT3
|
||||
#ifndef I2CHIP_INT4
|
||||
#ifndef I2CHIP_POLL
|
||||
#error You must specify an interrupt/polling mechanism for the I2CHIP module!
|
||||
#endif // I2CHIP_POLL
|
||||
#endif // I2CHIP_INT3
|
||||
#endif // I2CHIP_INT4
|
||||
#endif // I2CHIP_INT0
|
||||
|
||||
#ifdef I2CHIP_POLL
|
||||
#define I2CHIP_POLL_ISR(a) { delay_ms(20); disable(); a(); enable(); }
|
||||
#define INT_INIT(isr)
|
||||
#define INT_EOI
|
||||
#endif // I2CHIP_POLL
|
||||
|
||||
#ifdef I2CHIP_INT4
|
||||
#define INT_INIT(isr) int4_init(1, isr)
|
||||
#define INT_EOI outport(0xff22,0x0010)
|
||||
#define I2CHIP_POLL_ISR(a)
|
||||
#endif
|
||||
|
||||
#ifdef I2CHIP_INT3
|
||||
#define INT_INIT(isr) int3_init(1, isr)
|
||||
#define INT_EOI outport(0xff22,0x000f)
|
||||
#define I2CHIP_POLL_ISR(a)
|
||||
#endif
|
||||
|
||||
#ifdef I2CHIP_INT0
|
||||
#define INT_INIT(isr) int0_init(1, isr)
|
||||
#define INT_EOI outportb(_MPICOCW2_IO,0x61); // 586 only EOI
|
||||
#define I2CHIP_POLL_ISR(a)
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef I2CHIP_SHIFTED_ADDRESS
|
||||
#define SA_OFFSET(a) ((a) << 1)
|
||||
#else
|
||||
#define SA_OFFSET(a) a
|
||||
#endif // I2CHIP_SHIFTED_ADDRESS ... *if*
|
||||
|
||||
|
||||
// -------------------- WINDOW-RELATED DEFINES ----------------------
|
||||
#ifdef I2CHIP_WINDOW
|
||||
void i2chip_set_page(u_int addr);
|
||||
#define I2CHIP_SET_PAGE(p) i2chip_set_page(p)
|
||||
|
||||
u_char far* i2chip_mkptr(u_int addr);
|
||||
void i2chip_push_window(u_int addr);
|
||||
void i2chip_pop_window(void);
|
||||
u_int i2chip_get_window(void);
|
||||
void i2chip_set_window(u_int window_addr);
|
||||
|
||||
// Set to command window.
|
||||
// Note that if you're using other MMC chips within your application, you will
|
||||
// need to call this function regularly, if you've changed the MMC chip/page
|
||||
// selection via mmc_window(). The driver code otherwise assume that you never
|
||||
// change away from chip 7, page 0.
|
||||
#define WINDOW_RESTORE_BASE i2chip_mkptr(0)
|
||||
|
||||
// ----------------------- I2CHIP_WINDOW_IO ----------------------------
|
||||
#ifdef I2CHIP_WINDOW_IO
|
||||
|
||||
#ifdef TERN_5E
|
||||
#define I2CHIP_BASE_SEG 0x2000 // Address offset for W3100A
|
||||
#else
|
||||
#define I2CHIP_BASE_SEG 0x1800 // Address offset for W3100A
|
||||
#endif
|
||||
|
||||
#define COMMAND_BASE_SEG 0x0000
|
||||
#define SEND_DATA_BUF 0x4000 // Internal Tx buffer address of W3100A
|
||||
#define RECV_DATA_BUF 0x6000 // Internal Rx buffer address of W3100A
|
||||
#define WINDOW_BASE_SEGM COMMAND_BASE_SEG
|
||||
|
||||
#define MK_FP_WINDOW(a, b) i2chip_mkptr(a+SA_OFFSET(b))
|
||||
#define MK_FP_SA MK_FP_WINDOW
|
||||
|
||||
u_char io_read_value(u_char far* addr);
|
||||
void io_write_value(u_char far* addr, u_char value);
|
||||
#define READ_VALUE(a) io_read_value(a)
|
||||
#define WRITE_VALUE(a, v) io_write_value(a, v)
|
||||
|
||||
#define WINDOW_PTR_INC(a) \
|
||||
if ((FP_OFF(a) & 0xff) == 0xff) \
|
||||
a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \
|
||||
else \
|
||||
a++;
|
||||
|
||||
#endif // I2CHIP_WINDOW_IO
|
||||
|
||||
// -------------------- !NOT! I2CHIP_WINDOW_IO ----------------------------
|
||||
#ifndef I2CHIP_WINDOW_IO
|
||||
|
||||
#define READ_VALUE(a) *(a)
|
||||
#define WRITE_VALUE(a, v) *(a) = v
|
||||
|
||||
#define WINDOW_BASE_SEGM 0x8000
|
||||
#define MK_FP_WINDOW(a, b) i2chip_mkptr(a+SA_OFFSET(b))
|
||||
#define MK_FP_SA MK_FP_WINDOW
|
||||
|
||||
#ifdef I2CHIP_SHIFTED_ADDRESS
|
||||
#define COMMAND_BASE_SEG 0x0000
|
||||
#define SEND_DATA_BUF 0x8000
|
||||
#define RECV_DATA_BUF 0xC000
|
||||
#define WINDOW_PTR_INC(a) \
|
||||
if ((FP_OFF(a) & 0xff) == 0xfe) \
|
||||
a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \
|
||||
else \
|
||||
a+=2;
|
||||
#else
|
||||
#define COMMAND_BASE_SEG 0x0000
|
||||
#define SEND_DATA_BUF 0x4000
|
||||
#define RECV_DATA_BUF 0x6000
|
||||
#define WINDOW_PTR_INC(a) \
|
||||
if ((FP_OFF(a) & 0xff) == 0xff) \
|
||||
a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \
|
||||
else \
|
||||
a++;
|
||||
#endif // I2CHIP_SHIFTED_ADDRESS
|
||||
#endif // NOT I2CHIP_WINDOW_IO
|
||||
|
||||
#endif // I2CHIP_WINDOW
|
||||
|
||||
// -------------------- I2CHIP_DIRECT ----------------------------
|
||||
#ifdef I2CHIP_MCS_DIRECT
|
||||
|
||||
#define READ_VALUE(a) *(a)
|
||||
#define WRITE_VALUE(a, v) *(a) = v
|
||||
|
||||
#define I2CHIP_BASE_SEG 0x8000
|
||||
#define MK_FP_SA(a, b) MK_FP(a, SA_OFFSET(b))
|
||||
#define WINDOW_PTR_INC(a) a+=SA_OFFSET(1);
|
||||
#define WINDOW_RESTORE_BASE
|
||||
#define MK_FP_WINDOW MK_FP_SA
|
||||
#define WINDOW_BASE_SEG I2CHIP_BASE_SEG
|
||||
#define COMMAND_BASE_SEG I2CHIP_BASE_SEG
|
||||
|
||||
#ifdef I2CHIP_SHIFTED_ADDRESS
|
||||
#define SEND_DATA_BUF 0x8800 // Internal Tx buffer address of W3100A
|
||||
#define RECV_DATA_BUF 0x8C00 // Internal Rx buffer address of W3100A
|
||||
#else
|
||||
#define SEND_DATA_BUF 0x8400 // Internal Tx buffer address of W3100A
|
||||
#define RECV_DATA_BUF 0x8600 // Internal Rx buffer address of W3100A
|
||||
#endif // I2CHIP_SHIFTED_ADDRESS
|
||||
|
||||
#endif // I2CHIP_MCS_DIRECT
|
||||
|
||||
/* Internal register set of W3100A */
|
||||
#define COMMAND(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, i)))
|
||||
#define INT_STATUS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_C0_ISR + i)))
|
||||
#define INT_REG ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_IR)))
|
||||
#define INTMASK ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_IMR)))
|
||||
#define RESETSOCK ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x0A)))
|
||||
|
||||
#define RX_PTR_BASE I2CHIP_C0_RW_PR
|
||||
#define RX_PTR_SIZE (I2CHIP_C1_RW_PR - I2CHIP_C0_RW_PR)
|
||||
|
||||
#define RX_WR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i)))
|
||||
#define RX_RD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i + 0x04)))
|
||||
#define RX_ACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i + 0x08)))
|
||||
|
||||
#define TX_PTR_BASE I2CHIP_C0_TW_PR
|
||||
#define TX_PTR_SIZE (I2CHIP_C1_TW_PR - I2CHIP_C0_TW_PR)
|
||||
|
||||
#define TX_WR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i)))
|
||||
#define TX_RD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i + 0x04)))
|
||||
#define TX_ACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i + 0x08)))
|
||||
|
||||
/* Shadow Register Pointer Define */
|
||||
/* For windowing purposes, these are definitely outside the first 256-byte Window...
|
||||
therefore, use the MK_FP_WINDOW macros instead. */
|
||||
#define SHADOW_RXWR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E0 + 3*i)))
|
||||
#define SHADOW_RXRD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E1 + 3*i)))
|
||||
#define SHADOW_TXACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E2 + 3*i)))
|
||||
#define SHADOW_TXWR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1F0 + 3*i)))
|
||||
#define SHADOW_TXRD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1F1 + 3*i)))
|
||||
|
||||
#define SOCK_BASE I2CHIP_C0_SSR
|
||||
#define SOCK_SIZE (I2CHIP_C1_SSR - I2CHIP_C0_SSR)
|
||||
|
||||
#define SOCK_STATUS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i)))
|
||||
#define OPT_PROTOCOL(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x01)))
|
||||
#define DST_HA_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x02)))
|
||||
#define DST_IP_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x08)))
|
||||
#define DST_PORT_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x0C)))
|
||||
#define SRC_PORT_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x0E)))
|
||||
#define IP_PROTOCOL(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x10)))
|
||||
#define TOS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,SOCK_BASE + SOCK_SIZE * i + 0x11)))
|
||||
#define MSS(i) ((u_int far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x12)))
|
||||
#define P_WINDOW(i) ((u_int far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,SOCK_BASE + SOCK_SIZE * i + 0x14)))
|
||||
#define WINDOW(i) ((u_int far*)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x16)))
|
||||
|
||||
#define GATEWAY_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_GAR)))
|
||||
#define SUBNET_MASK_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SMR)))
|
||||
|
||||
#define SRC_HA_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SHAR)))
|
||||
#define SRC_IP_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SIPR)))
|
||||
#define TIMEOUT_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_IRTR)))
|
||||
|
||||
#define RX_DMEM_SIZE ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_RMSR)))
|
||||
#define TX_DMEM_SIZE ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_TMSR)))
|
||||
|
||||
void i2chip_init(void);
|
||||
|
||||
#endif // _irchip_hw_h
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#ifndef _SYSTEM_COMMON_H_
|
||||
#define _SYSTEM_COMMON_H_
|
||||
|
||||
typedef unsigned char UCHAR8;
|
||||
typedef unsigned int UINT16;
|
||||
|
||||
#define RETURN_OK 0 // Non-zero return values are always
|
||||
// error values.
|
||||
#define RETURN_ILLEGAL 1 // Some sort of illegal argument.
|
||||
#define RETURN_MEM 2 // Out of memory space.
|
||||
|
||||
#endif // _SYSTEM_COMMON_H_
|
||||
Loading…
Add table
Add a link
Reference in a new issue