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Richard Barry
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2632 changed files with 751681 additions and 0 deletions
145
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.C
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145
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.C
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/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : Byte1.C
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : ByteIO
|
||||
** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.283
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 16/06/2005, 21:10
|
||||
** Abstract :
|
||||
** This bean "ByteIO" implements an one-byte input/output.
|
||||
** It uses one 8-bit port.
|
||||
** Note: This bean is set to work in Output direction only.
|
||||
** Methods of this bean are mostly implemented as a macros
|
||||
** (if supported by target langauage and compiler).
|
||||
** Settings :
|
||||
** Port name : B
|
||||
**
|
||||
** Initial direction : Output (direction cannot be changed)
|
||||
** Initial output value : 255 = 0FFH
|
||||
** Initial pull option : off
|
||||
**
|
||||
** 8-bit data register : PORTB [1]
|
||||
** 8-bit control register : DDRB [3]
|
||||
**
|
||||
** ----------------------------------------------------
|
||||
** Bit | Pin | Name
|
||||
** ----------------------------------------------------
|
||||
** 0 | 24 | PB0_ADDR0_DATA0
|
||||
** 1 | 25 | PB1_ADDR1_DATA1
|
||||
** 2 | 26 | PB2_ADDR2_DATA2
|
||||
** 3 | 27 | PB3_ADDR3_DATA3
|
||||
** 4 | 28 | PB4_ADDR4_DATA4
|
||||
** 5 | 29 | PB5_ADDR5_DATA5
|
||||
** 6 | 30 | PB6_ADDR6_DATA6
|
||||
** 7 | 31 | PB7_ADDR7_DATA7
|
||||
** ----------------------------------------------------
|
||||
** Contents :
|
||||
** PutBit - void Byte1_PutBit(byte Bit,bool Val);
|
||||
** NegBit - void Byte1_NegBit(byte Bit);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
|
||||
/* MODULE Byte1. */
|
||||
|
||||
#include "Byte1.h"
|
||||
/*Including shared modules, which are used for all project*/
|
||||
#include "PE_Types.h"
|
||||
#include "PE_Error.h"
|
||||
#include "PE_Const.h"
|
||||
#include "IO_Map.h"
|
||||
#include "PE_Timer.h"
|
||||
|
||||
#include "Cpu.h"
|
||||
|
||||
/* Definition of DATA and CODE segments for this bean. User can specify where
|
||||
these segments will be located on "Build options" tab of the selected CPU bean. */
|
||||
#pragma DATA_SEG Byte1_DATA /* Data section for this module. */
|
||||
#pragma CODE_SEG Byte1_CODE /* Code section for this module. */
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : Byte1_GetMsk (bean ByteIO)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
byte Byte1_Table[8]={ 1, 2, 4, 8, 16, 32, 64, 128 }; /* Table of mask constants */
|
||||
|
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byte Byte1_GetMsk(byte Value)
|
||||
{
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||||
return((Value<8)?Byte1_Table[Value]:0); /* Return appropriate bit mask */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : Byte1_PutBit (bean ByteIO)
|
||||
**
|
||||
** Description :
|
||||
** This method writes the new value to the specified bit
|
||||
** of the output value.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Bitnum - Number of the bit (0 to 7)
|
||||
** Val - New value of the bit (FALSE or TRUE)
|
||||
** FALSE = "0" or "Low", TRUE = "1" or "High"
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
void Byte1_PutBit(byte BitNum, byte Value)
|
||||
{
|
||||
byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */
|
||||
|
||||
if (Mask) /* Is bit mask correct? */
|
||||
if (Value) { /* Is it one to be written? */
|
||||
PORTB |= Mask; /* Set appropriate bit on port */
|
||||
}
|
||||
else { /* Is it zero to be written? */
|
||||
PORTB &= ~Mask; /* Clear appropriate bit on port */
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : Byte1_NegBit (bean ByteIO)
|
||||
**
|
||||
** Description :
|
||||
** This method negates (invertes) the specified bit of the
|
||||
** output value.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Bit - Number of the bit to invert (0 to 7)
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
void Byte1_NegBit(byte BitNum)
|
||||
{
|
||||
byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */
|
||||
|
||||
if (Mask) { /* Is bit mask correct? */
|
||||
PORTB ^= Mask; /* Negate appropriate bit on port */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* END Byte1. */
|
||||
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
111
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.H
Normal file
111
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.H
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|
@ -0,0 +1,111 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : Byte1.H
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : ByteIO
|
||||
** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.283
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 16/06/2005, 21:10
|
||||
** Abstract :
|
||||
** This bean "ByteIO" implements an one-byte input/output.
|
||||
** It uses one 8-bit port.
|
||||
** Note: This bean is set to work in Output direction only.
|
||||
** Methods of this bean are mostly implemented as a macros
|
||||
** (if supported by target langauage and compiler).
|
||||
** Settings :
|
||||
** Port name : B
|
||||
**
|
||||
** Initial direction : Output (direction cannot be changed)
|
||||
** Initial output value : 255 = 0FFH
|
||||
** Initial pull option : off
|
||||
**
|
||||
** 8-bit data register : PORTB [1]
|
||||
** 8-bit control register : DDRB [3]
|
||||
**
|
||||
** ----------------------------------------------------
|
||||
** Bit | Pin | Name
|
||||
** ----------------------------------------------------
|
||||
** 0 | 24 | PB0_ADDR0_DATA0
|
||||
** 1 | 25 | PB1_ADDR1_DATA1
|
||||
** 2 | 26 | PB2_ADDR2_DATA2
|
||||
** 3 | 27 | PB3_ADDR3_DATA3
|
||||
** 4 | 28 | PB4_ADDR4_DATA4
|
||||
** 5 | 29 | PB5_ADDR5_DATA5
|
||||
** 6 | 30 | PB6_ADDR6_DATA6
|
||||
** 7 | 31 | PB7_ADDR7_DATA7
|
||||
** ----------------------------------------------------
|
||||
** Contents :
|
||||
** PutBit - void Byte1_PutBit(byte Bit,bool Val);
|
||||
** NegBit - void Byte1_NegBit(byte Bit);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
#ifndef __Byte1_H
|
||||
#define __Byte1_H
|
||||
|
||||
/* MODULE Byte1. */
|
||||
|
||||
/*Including shared modules, which are used in the whole project*/
|
||||
#include "PE_Types.h"
|
||||
#include "PE_Error.h"
|
||||
#include "PE_Const.h"
|
||||
#include "IO_Map.h"
|
||||
#include "PE_Timer.h"
|
||||
|
||||
#include "Cpu.h"
|
||||
|
||||
#pragma CODE_SEG Byte1_CODE /* Code section for this module. */
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : Byte1_PutBit (bean ByteIO)
|
||||
**
|
||||
** Description :
|
||||
** This method writes the new value to the specified bit
|
||||
** of the output value.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** BitNum - Number of the bit (0 to 7)
|
||||
** Val - New value of the bit (FALSE or TRUE)
|
||||
** FALSE = "0" or "Low", TRUE = "1" or "High"
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
void Byte1_PutBit(byte BitNum, byte Value);
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : Byte1_NegBit (bean ByteIO)
|
||||
**
|
||||
** Description :
|
||||
** This method negates (invertes) the specified bit of the
|
||||
** output value.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** BitNum - Number of the bit to invert (0 to 7)
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
void Byte1_NegBit(byte BitNum);
|
||||
|
||||
#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */
|
||||
|
||||
/* END Byte1. */
|
||||
|
||||
#endif /* __Byte1_H*/
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
205
20080212/Demo/HCS12_CodeWarrior_banked/CODE/COM0.C
Normal file
205
20080212/Demo/HCS12_CodeWarrior_banked/CODE/COM0.C
Normal file
|
|
@ -0,0 +1,205 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : COM0.C
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : AsynchroSerial
|
||||
** Version : Bean 02.231, Driver 01.08, CPU db: 2.87.283
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 19/06/2005, 15:07
|
||||
** Abstract :
|
||||
** This bean "AsynchroSerial" implements an asynchronous serial
|
||||
** communication. The bean supports different settings of
|
||||
** parity, word width, stop-bit and communication speed,
|
||||
** user can select interrupt or polling handler.
|
||||
** Communication speed can be changed also in runtime.
|
||||
** The bean requires one on-chip asynchronous serial channel.
|
||||
** Settings :
|
||||
** Serial channel : SCI0
|
||||
**
|
||||
** Protocol
|
||||
** Init baud rate : 38400baud
|
||||
** Width : 8 bits
|
||||
** Stop bits : 1
|
||||
** Parity : none
|
||||
** Breaks : Disabled
|
||||
**
|
||||
** Registers
|
||||
** Input buffer : SCI0DRL [207]
|
||||
** Output buffer : SCI0DRL [207]
|
||||
** Control register : SCI0CR1 [202]
|
||||
** Mode register : SCI0CR2 [203]
|
||||
** Baud setting reg. : SCI0BD [200]
|
||||
** Special register : SCI0SR1 [204]
|
||||
**
|
||||
** Input interrupt
|
||||
** Vector name : INT_SCI0
|
||||
** Priority : 1
|
||||
**
|
||||
** Output interrupt
|
||||
** Vector name : INT_SCI0
|
||||
** Priority : 1
|
||||
**
|
||||
** Used pins :
|
||||
** ----------------------------------------------------
|
||||
** Function | On package | Name
|
||||
** ----------------------------------------------------
|
||||
** Input | 89 | PS0_RxD0
|
||||
** Output | 90 | PS1_TxD0
|
||||
** ----------------------------------------------------
|
||||
**
|
||||
**
|
||||
** Used baud modes :
|
||||
** ----------------------------------------------------
|
||||
** No. | Mode ID | Baud rate
|
||||
** ----------------------------------------------------
|
||||
** 0 | Bm_38400baud | 38400baud
|
||||
** 1 | Bm_19200baud | 19200baud
|
||||
** 2 | Bm_9600baud | 9600baud
|
||||
** 3 | Bm_4800baud | 4800baud
|
||||
** ----------------------------------------------------
|
||||
** Contents :
|
||||
** SetBaudRateMode - byte COM0_SetBaudRateMode(byte Mod);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
/* MODULE COM0. */
|
||||
|
||||
#pragma MESSAGE DISABLE C4002 /* WARNING C4002: Result not used is ignored */
|
||||
#pragma MESSAGE DISABLE C4301 /* INFORMATION C4301: Inline expansion done for function call */
|
||||
|
||||
#include "COM0.h"
|
||||
#include "TickTimer.h"
|
||||
#include "Byte1.h"
|
||||
|
||||
/* Definition of DATA and CODE segments for this bean. User can specify where
|
||||
these segments will be located on "Build options" tab of the selected CPU bean. */
|
||||
#pragma DATA_SEG COM0_DATA /* Data section for this module. */
|
||||
#pragma CODE_SEG COM0_CODE /* Code section for this module. */
|
||||
|
||||
|
||||
#define OVERRUN_ERR 1 /* Overrun error flag bit */
|
||||
#define FRAMING_ERR 2 /* Framing error flag bit */
|
||||
#define PARITY_ERR 4 /* Parity error flag bit */
|
||||
#define CHAR_IN_RX 8 /* Char is in RX buffer */
|
||||
#define FULL_TX 16 /* Full transmit buffer */
|
||||
#define RUNINT_FROM_TX 32 /* Interrupt is in progress */
|
||||
#define FULL_RX 64 /* Full receive buffer */
|
||||
#define NOISE_ERR 128 /* Noise erorr flag bit */
|
||||
#define IDLE_ERR 256 /* Idle character flag bit */
|
||||
#define BREAK_ERR 512 /* Break detect */
|
||||
|
||||
static word SerFlag; /* Flags for serial communication */
|
||||
/* Bits: 0 - OverRun error */
|
||||
/* 1 - Framing error */
|
||||
/* 2 - Parity error */
|
||||
/* 3 - Char in RX buffer */
|
||||
/* 4 - Full TX buffer */
|
||||
/* 5 - Running int from TX */
|
||||
/* 6 - Full RX buffer */
|
||||
/* 7 - Noise error */
|
||||
/* 8 - Idle character */
|
||||
/* 9 - Break detected */
|
||||
/* 10 - Unused */
|
||||
static word PrescHigh;
|
||||
static byte NumMode; /* Number of selected baud mode */
|
||||
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : HWEnDi (bean AsynchroSerial)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
static void HWEnDi(void)
|
||||
{
|
||||
SCI0CR2_TE = 1; /* Enable transmitter */
|
||||
SCI0CR2_RE = 1; /* Enable receiver */
|
||||
SCI0CR2_RIE = 1; /* Enable recieve interrupt */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : COM0_SetBaudRateMode (bean AsynchroSerial)
|
||||
**
|
||||
** Description :
|
||||
** This method changes the channel communication speed (baud
|
||||
** rate). This method can be used only if you specify a list
|
||||
** of possible period settings at design time (see <Timing
|
||||
** dialog box> - Runtime setting - from a list of values).
|
||||
** Each of these settings constitutes a mode and Processor
|
||||
** Expert^[TM] assigns them a mode identifier. The prescaler
|
||||
** and compare values corresponding to each mode are
|
||||
** calculated at design time. You may switch modes at
|
||||
** runtime by referring only to a mode identifier. No
|
||||
** run-time calculations are performed, all the calculations
|
||||
** are performed at design time.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Mod - Timing mode to set
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ===================================================================
|
||||
*/
|
||||
byte COM0_SetBaudRateMode(byte Mod)
|
||||
{
|
||||
static const word COM0_PrescHigh[4] = {41,81,163,326};
|
||||
|
||||
if(Mod >= 4) /* Is mode in baud mode list */
|
||||
return ERR_VALUE; /* If no then error */
|
||||
NumMode = Mod; /* New baud mode */
|
||||
PrescHigh = COM0_PrescHigh[Mod]; /* Prescaler in high speed mode */
|
||||
SCI0BD = PrescHigh; /* Set prescaler bits */
|
||||
return ERR_OK; /* OK */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : COM0_Init (bean AsynchroSerial)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
void COM0_Init(void)
|
||||
{
|
||||
PrescHigh = 41; /* Precaler in high speed mode */
|
||||
SerFlag = 0; /* Reset flags */
|
||||
NumMode = 0; /* Number of selected baud mode */
|
||||
/* SCI0CR1: LOOPS=0,SCISWAI=1,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
|
||||
SCI0CR1 = 64; /* Set the SCI configuration */
|
||||
/* SCI0SR2: ??=0,??=0,??=0,??=0,??=0,BRK13=0,TXDIR=0,RAF=0 */
|
||||
SCI0SR2 = 0; /* Set the Break Character Length and Transmitter pin data direction in Single-wire mode */
|
||||
SCI0SR1; /* Reset interrupt request flags */
|
||||
/* SCI0CR2: SCTIE=0,TCIE=0,RIE=0,ILIE=0,TE=0,RE=0,RWU=0,SBK=0 */
|
||||
SCI0CR2 = 0; /* Disable error interrupts */
|
||||
SCI0BD = PrescHigh; /* Set prescaler bits */
|
||||
HWEnDi(); /* Enable/disable device according to status flags */
|
||||
}
|
||||
|
||||
|
||||
/* END COM0. */
|
||||
|
||||
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
191
20080212/Demo/HCS12_CodeWarrior_banked/CODE/COM0.H
Normal file
191
20080212/Demo/HCS12_CodeWarrior_banked/CODE/COM0.H
Normal file
|
|
@ -0,0 +1,191 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : COM0.H
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : AsynchroSerial
|
||||
** Version : Bean 02.231, Driver 01.08, CPU db: 2.87.283
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 19/06/2005, 15:07
|
||||
** Abstract :
|
||||
** This bean "AsynchroSerial" implements an asynchronous serial
|
||||
** communication. The bean supports different settings of
|
||||
** parity, word width, stop-bit and communication speed,
|
||||
** user can select interrupt or polling handler.
|
||||
** Communication speed can be changed also in runtime.
|
||||
** The bean requires one on-chip asynchronous serial channel.
|
||||
** Settings :
|
||||
** Serial channel : SCI0
|
||||
**
|
||||
** Protocol
|
||||
** Init baud rate : 38400baud
|
||||
** Width : 8 bits
|
||||
** Stop bits : 1
|
||||
** Parity : none
|
||||
** Breaks : Disabled
|
||||
**
|
||||
** Registers
|
||||
** Input buffer : SCI0DRL [207]
|
||||
** Output buffer : SCI0DRL [207]
|
||||
** Control register : SCI0CR1 [202]
|
||||
** Mode register : SCI0CR2 [203]
|
||||
** Baud setting reg. : SCI0BD [200]
|
||||
** Special register : SCI0SR1 [204]
|
||||
**
|
||||
** Input interrupt
|
||||
** Vector name : INT_SCI0
|
||||
** Priority : 1
|
||||
**
|
||||
** Output interrupt
|
||||
** Vector name : INT_SCI0
|
||||
** Priority : 1
|
||||
**
|
||||
** Used pins :
|
||||
** ----------------------------------------------------
|
||||
** Function | On package | Name
|
||||
** ----------------------------------------------------
|
||||
** Input | 89 | PS0_RxD0
|
||||
** Output | 90 | PS1_TxD0
|
||||
** ----------------------------------------------------
|
||||
**
|
||||
**
|
||||
** Used baud modes :
|
||||
** ----------------------------------------------------
|
||||
** No. | Mode ID | Baud rate
|
||||
** ----------------------------------------------------
|
||||
** 0 | Bm_38400baud | 38400baud
|
||||
** 1 | Bm_19200baud | 19200baud
|
||||
** 2 | Bm_9600baud | 9600baud
|
||||
** 3 | Bm_4800baud | 4800baud
|
||||
** ----------------------------------------------------
|
||||
** Contents :
|
||||
** SetBaudRateMode - byte COM0_SetBaudRateMode(byte Mod);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
#ifndef __COM0
|
||||
#define __COM0
|
||||
|
||||
/* MODULE COM0. */
|
||||
|
||||
#include "Cpu.h"
|
||||
|
||||
#define COM0_Bm_38400baud 0 /* Constant for switch to mode 0 */
|
||||
#define COM0_Bm_19200baud 1 /* Constant for switch to mode 1 */
|
||||
#define COM0_Bm_9600baud 2 /* Constant for switch to mode 2 */
|
||||
#define COM0_Bm_4800baud 3 /* Constant for switch to mode 3 */
|
||||
|
||||
|
||||
|
||||
#ifndef __BWUserType_tItem
|
||||
#define __BWUserType_tItem
|
||||
typedef struct { /* Item of the index table for possible baudrates */
|
||||
word div; /* divisior */
|
||||
byte val; /* values of the prescalers */
|
||||
} tItem;
|
||||
#endif
|
||||
#ifndef __BWUserType_COM0_TError
|
||||
#define __BWUserType_COM0_TError
|
||||
typedef union {
|
||||
byte err;
|
||||
struct {
|
||||
bool OverRun : 1; /* OverRun error flag */
|
||||
bool Framing : 1; /* Framing error flag */
|
||||
bool Parity : 1; /* Parity error flag */
|
||||
bool RxBufOvf : 1; /* Rx buffer full error flag */
|
||||
bool Noise : 1; /* Noise error */
|
||||
bool Break : 1; /* Break detect */
|
||||
bool Idle : 1; /* Idle characted */
|
||||
}errName;
|
||||
} COM0_TError;
|
||||
#endif
|
||||
#ifndef __BWUserType_TDirection
|
||||
#define __BWUserType_TDirection
|
||||
typedef enum { /* */
|
||||
TXD_INPUT,
|
||||
TXD_OUTPUT
|
||||
} TDirection;
|
||||
#endif
|
||||
|
||||
#ifndef __BWUserType_COM0_TComData
|
||||
#define __BWUserType_COM0_TComData
|
||||
typedef byte COM0_TComData ; /* User type for communication. Size of this type depends on the communication data witdh. */
|
||||
#endif
|
||||
|
||||
#pragma CODE_SEG COM0_CODE /* Code section for this module. */
|
||||
|
||||
byte COM0_SetBaudRateMode(byte Mod);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : COM0_SetBaudRateMode (bean AsynchroSerial)
|
||||
**
|
||||
** Description :
|
||||
** This method changes the channel communication speed (baud
|
||||
** rate). This method can be used only if you specify a list
|
||||
** of possible period settings at design time (see <Timing
|
||||
** dialog box> - Runtime setting - from a list of values).
|
||||
** Each of these settings constitutes a mode and Processor
|
||||
** Expert^[TM] assigns them a mode identifier. The prescaler
|
||||
** and compare values corresponding to each mode are
|
||||
** calculated at design time. You may switch modes at
|
||||
** runtime by referring only to a mode identifier. No
|
||||
** run-time calculations are performed, all the calculations
|
||||
** are performed at design time.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Mod - Timing mode to set
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
|
||||
__interrupt void COM0_Interrupt(void);
|
||||
#pragma CODE_SEG COM0_CODE /* Code section for this module. */
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : COM0_Interrupt (bean AsynchroSerial)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
|
||||
void COM0_Init(void);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : COM0_Init (bean AsynchroSerial)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
|
||||
#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */
|
||||
|
||||
/* END COM0. */
|
||||
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#endif /* ifndef __COM0 */
|
||||
112
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Copy of Vectors.c
Normal file
112
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Copy of Vectors.c
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : Cpu.C
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : MC9S12DP256_112
|
||||
** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 16/06/2005, 19:18
|
||||
** Abstract :
|
||||
** This bean "MC9S12DP256_112" implements properties, methods,
|
||||
** and events of the CPU.
|
||||
** Settings :
|
||||
**
|
||||
** Contents :
|
||||
** EnableInt - void Cpu_EnableInt(void);
|
||||
** DisableInt - void Cpu_DisableInt(void);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
|
||||
#include "Cpu.h"
|
||||
#include "TickTimer.h"
|
||||
#include "Byte1.h"
|
||||
|
||||
extern void near _EntryPoint(void); /* Startup routine */
|
||||
extern void near vPortTickInterrupt( void );
|
||||
extern void near vPortYield( void );
|
||||
extern void near vCOM0_ISR( void );
|
||||
|
||||
typedef void (*near tIsrFunc)(void);
|
||||
const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */
|
||||
Cpu_Interrupt, /* 0 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 1 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 2 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 3 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 4 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 5 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 6 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 7 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 8 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 9 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 10 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 11 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 12 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 13 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 14 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 15 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 16 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 17 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 18 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 19 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 20 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 21 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 22 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 23 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 24 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 25 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 26 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 27 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 28 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 29 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 30 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 31 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 32 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 33 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 34 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 35 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 36 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 37 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 38 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 39 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 40 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 41 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 42 Default (unused) interrupt */
|
||||
vCOM0_ISR,
|
||||
Cpu_Interrupt, /* 44 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 45 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 46 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 47 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 48 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 49 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 50 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 51 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 52 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 53 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 54 Default (unused) interrupt */
|
||||
vPortTickInterrupt,
|
||||
Cpu_Interrupt, /* 56 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 57 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 58 Default (unused) interrupt */
|
||||
vPortYield, /* 59 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 60 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 61 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 62 Default (unused) interrupt */
|
||||
_EntryPoint /* Reset vector */
|
||||
};
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
198
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.C
Normal file
198
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.C
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : Cpu.C
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : MC9S12DP256_112
|
||||
** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 18/06/2005, 16:21
|
||||
** Abstract :
|
||||
** This bean "MC9S12DP256_112" implements properties, methods,
|
||||
** and events of the CPU.
|
||||
** Settings :
|
||||
**
|
||||
** Contents :
|
||||
** EnableInt - void Cpu_EnableInt(void);
|
||||
** DisableInt - void Cpu_DisableInt(void);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
/* MODULE Cpu. */
|
||||
|
||||
#include "TickTimer.h"
|
||||
#include "Byte1.h"
|
||||
#include "COM0.h"
|
||||
#include "PE_Types.h"
|
||||
#include "PE_Error.h"
|
||||
#include "PE_Const.h"
|
||||
#include "IO_Map.h"
|
||||
#include "PE_Timer.h"
|
||||
#include "Events.h"
|
||||
#include "Cpu.h"
|
||||
|
||||
#define CGM_DELAY 3071UL
|
||||
|
||||
|
||||
/* Global variables */
|
||||
volatile byte CCR_reg; /* Current CCR reegister */
|
||||
byte CpuMode = HIGH_SPEED; /* Current speed mode */
|
||||
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : Cpu_Interrupt (bean MC9S12DP256_112)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
|
||||
|
||||
__interrupt void Cpu_Interrupt(void)
|
||||
{
|
||||
}
|
||||
|
||||
#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : Cpu_DisableInt (bean MC9S12DP256_112)
|
||||
**
|
||||
** Description :
|
||||
** Disable maskable interrupts
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
/*
|
||||
void Cpu_DisableInt(void)
|
||||
|
||||
** This method is implemented as macro in the header module. **
|
||||
*/
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : Cpu_EnableInt (bean MC9S12DP256_112)
|
||||
**
|
||||
** Description :
|
||||
** Enable maskable interrupts
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
/*
|
||||
void Cpu_EnableInt(void)
|
||||
|
||||
** This method is implemented as macro in the header module. **
|
||||
*/
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : _EntryPoint (bean MC9S12DP256_112)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */
|
||||
#define INITRG_ADR 0x0011 /* Register map position register */
|
||||
#pragma NO_FRAME
|
||||
#pragma NO_EXIT
|
||||
void _EntryPoint(void)
|
||||
{
|
||||
/*** ### MC9S12DP256_112 "Cpu" init code ... ***/
|
||||
/*** PE initialization code after reset ***/
|
||||
/* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */
|
||||
*(byte*)INITRG_ADR = 0; /* Set the register map position */
|
||||
asm nop; /* nop instruction */
|
||||
INITRM=1; /* Set the RAM map position */
|
||||
INITEE=1; /* Set the EEPROM map position */
|
||||
/* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */
|
||||
MISC=1;
|
||||
/* System clock initialization */
|
||||
CLKSEL=0;
|
||||
CLKSEL_PLLSEL = 0; /* Select clock source from XTAL */
|
||||
PLLCTL_PLLON = 0; /* Disable the PLL */
|
||||
SYNR = 24; /* Set the multiplier register */
|
||||
REFDV = 15; /* Set the divider register */
|
||||
PLLCTL = 192;
|
||||
PLLCTL_PLLON = 1; /* Enable the PLL */
|
||||
while(!CRGFLG_LOCK); /* Wait */
|
||||
CLKSEL_PLLSEL = 1; /* Select clock source from PLL */
|
||||
/*** End of PE initialization code after reset ***/
|
||||
|
||||
__asm jmp _Startup; /* Jump to C startup code */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_low_level_init (bean MC9S12DP256_112)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
void PE_low_level_init(void)
|
||||
{
|
||||
/* Common initialization of the CPU registers */
|
||||
/* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */
|
||||
output( TSCR1, input( TSCR1 ) & ~192 | 32 );
|
||||
/* TCTL2: OM0=0,OL0=0 */
|
||||
output( TCTL2, input( TCTL2 ) & ~3 );
|
||||
/* TCTL1: OM7=0,OL7=0 */
|
||||
output( TCTL1, input( TCTL1 ) & ~192 );
|
||||
/* TIE: C0I=0 */
|
||||
output( TIE, input( TIE ) & ~1 );
|
||||
/* TTOV: TOV0=0 */
|
||||
output( TTOV, input( TTOV ) & ~1 );
|
||||
/* TSCR2: TOI=0,TCRE=1 */
|
||||
output( TSCR2, input( TSCR2 ) & ~128 | 8 );
|
||||
/* TIOS: IOS7=1,IOS0=1 */
|
||||
output( TIOS, input( TIOS ) | 129 );
|
||||
/* PWMCTL: PSWAI=0,PFRZ=0 */
|
||||
output( PWMCTL, input( PWMCTL ) & ~12 );
|
||||
/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */
|
||||
output( PWMSDN, 0 );
|
||||
/* ICSYS: SH37=0,SH26=0,SH15=0,SH04=0,TFMOD=0,PACMX=0,BUFEN=0,LATQ=0 */
|
||||
output( ICSYS, 0 );
|
||||
/* MCCTL: MODMC=1 */
|
||||
output( MCCTL, input( MCCTL ) | 64 );
|
||||
/* ### MC9S12DP256_112 "Cpu" init code ... */
|
||||
/* ### TimerInt "TickTimer" init code ... */
|
||||
TickTimer_Init();
|
||||
/* ### ByteIO "Byte1" init code ... */
|
||||
PORTB = 255; /* Prepare value for output */
|
||||
DDRB = 255; /* Set direction to output */
|
||||
/* ### Asynchro serial "COM0" init code ... */
|
||||
DDRS &= ~1;
|
||||
PTS |= 2;
|
||||
DDRS |= 2;
|
||||
COM0_Init();
|
||||
/* Common peripheral initialization - ENABLE */
|
||||
/* TSCR1: TEN=1 */
|
||||
output( TSCR1, input( TSCR1 ) | 128 );
|
||||
INTCR_IRQEN = 0; /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */
|
||||
__DI(); /* Disable interrupts */
|
||||
}
|
||||
|
||||
/* END Cpu. */
|
||||
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
111
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.H
Normal file
111
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.H
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : Cpu.H
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : MC9S12DP256_112
|
||||
** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 14/06/2005, 16:34
|
||||
** Abstract :
|
||||
** This bean "MC9S12DP256_112" implements properties, methods,
|
||||
** and events of the CPU.
|
||||
** Settings :
|
||||
**
|
||||
** Contents :
|
||||
** EnableInt - void Cpu_EnableInt(void);
|
||||
** DisableInt - void Cpu_DisableInt(void);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
#ifndef __Cpu
|
||||
#define __Cpu
|
||||
|
||||
/* Active configuration define symbol */
|
||||
#define PEcfg_112pin 1
|
||||
|
||||
/*Include shared modules, which are used for whole project*/
|
||||
#include "PE_Types.h"
|
||||
#include "PE_Error.h"
|
||||
#include "PE_Const.h"
|
||||
#include "IO_Map.h"
|
||||
#include "PE_Timer.h"
|
||||
|
||||
/* MODULE Cpu. */
|
||||
|
||||
|
||||
/* Global variables */
|
||||
extern volatile byte CCR_reg; /* Current CCR reegister */
|
||||
extern byte CpuMode; /* Current speed mode */
|
||||
|
||||
|
||||
|
||||
|
||||
#define Cpu_DisableInt() __DI() /* Disable interrupts */
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : Cpu_DisableInt (bean MC9S12DP256_112)
|
||||
**
|
||||
** Description :
|
||||
** Disable maskable interrupts
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
#define Cpu_EnableInt() __EI() /* Enable interrupts */
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : Cpu_EnableInt (bean MC9S12DP256_112)
|
||||
**
|
||||
** Description :
|
||||
** Enable maskable interrupts
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
|
||||
|
||||
__interrupt void Cpu_Interrupt(void);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : Cpu_Interrupt (bean MC9S12DP256_112)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */
|
||||
|
||||
void PE_low_level_init(void);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_low_level_init (bean MC9S12DP256_112)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
/* END Cpu. */
|
||||
|
||||
#endif /* ifndef __Cpu */
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
153
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Events.C
Normal file
153
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Events.C
Normal file
|
|
@ -0,0 +1,153 @@
|
|||
/** ###################################################################
|
||||
** Filename : Events.C
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : Events
|
||||
** Version : Driver 01.01
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 14/06/2005, 16:34
|
||||
** Abstract :
|
||||
** This is user's event module.
|
||||
** Put your event handler code here.
|
||||
** Settings :
|
||||
** Contents :
|
||||
** TickTimer_OnInterrupt - void TickTimer_OnInterrupt(void);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
/* MODULE Events */
|
||||
|
||||
|
||||
/*Including used modules for compilling procedure*/
|
||||
#include "Cpu.h"
|
||||
#include "Events.h"
|
||||
#include "TickTimer.h"
|
||||
#include "Byte1.h"
|
||||
#include "COM0.h"
|
||||
|
||||
/*Include shared modules, which are used for whole project*/
|
||||
#include "PE_Types.h"
|
||||
#include "PE_Error.h"
|
||||
#include "PE_Const.h"
|
||||
#include "IO_Map.h"
|
||||
#include "PE_Timer.h"
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : TickTimer_OnInterrupt (module Events)
|
||||
**
|
||||
** From bean : TickTimer [TimerInt]
|
||||
** Description :
|
||||
** When a timer interrupt occurs this event is called (only
|
||||
** when the bean is enabled - "Enable" and the events are
|
||||
** enabled - "EnableEvent").
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
void TickTimer_OnInterrupt(void)
|
||||
{
|
||||
/* Write your code here ... */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : COM0_OnError (module Events)
|
||||
**
|
||||
** From bean : COM0 [AsynchroSerial]
|
||||
** Description :
|
||||
** This event is called when a channel error (not the error
|
||||
** returned by a given method) occurs. The errors can be
|
||||
** read using <GetError> method.
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
void COM0_OnError(void)
|
||||
{
|
||||
/* Write your code here ... */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : COM0_OnRxChar (module Events)
|
||||
**
|
||||
** From bean : COM0 [AsynchroSerial]
|
||||
** Description :
|
||||
** This event is called after a correct character is
|
||||
** received. This
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
void COM0_OnRxChar(void)
|
||||
{
|
||||
/* Write your code here ... */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : COM0_OnTxChar (module Events)
|
||||
**
|
||||
** From bean : COM0 [AsynchroSerial]
|
||||
** Description :
|
||||
** This event is called after a character is transmitted.
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
void COM0_OnTxChar(void)
|
||||
{
|
||||
/* Write your code here ... */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : COM0_OnFullRxBuf (module Events)
|
||||
**
|
||||
** From bean : COM0 [AsynchroSerial]
|
||||
** Description :
|
||||
** This event is called when the input buffer is full.
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
void COM0_OnFullRxBuf(void)
|
||||
{
|
||||
/* Write your code here ... */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : COM0_OnFreeTxBuf (module Events)
|
||||
**
|
||||
** From bean : COM0 [AsynchroSerial]
|
||||
** Description :
|
||||
** This event is called after the last character in output
|
||||
** buffer is transmitted.
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
void COM0_OnFreeTxBuf(void)
|
||||
{
|
||||
/* Write your code here ... */
|
||||
}
|
||||
|
||||
/* END Events */
|
||||
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
130
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Events.H
Normal file
130
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Events.H
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
/** ###################################################################
|
||||
** Filename : Events.H
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : Events
|
||||
** Version : Driver 01.01
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 14/06/2005, 16:34
|
||||
** Abstract :
|
||||
** This is user's event module.
|
||||
** Put your event handler code here.
|
||||
** Settings :
|
||||
** Contents :
|
||||
** TickTimer_OnInterrupt - void TickTimer_OnInterrupt(void);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
#ifndef __Events_H
|
||||
#define __Events_H
|
||||
/* MODULE Events */
|
||||
|
||||
#include "PE_Types.h"
|
||||
#include "PE_Error.h"
|
||||
#include "PE_Const.h"
|
||||
#include "IO_Map.h"
|
||||
#include "PE_Timer.h"
|
||||
|
||||
void TickTimer_OnInterrupt(void);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : TickTimer_OnInterrupt (module Events)
|
||||
**
|
||||
** From bean : TickTimer [TimerInt]
|
||||
** Description :
|
||||
** When a timer interrupt occurs this event is called (only
|
||||
** when the bean is enabled - "Enable" and the events are
|
||||
** enabled - "EnableEvent").
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
|
||||
void COM0_OnError(void);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : COM0_OnError (module Events)
|
||||
**
|
||||
** From bean : COM0 [AsynchroSerial]
|
||||
** Description :
|
||||
** This event is called when a channel error (not the error
|
||||
** returned by a given method) occurs. The errors can be
|
||||
** read using <GetError> method.
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
void COM0_OnRxChar(void);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : COM0_OnRxChar (module Events)
|
||||
**
|
||||
** From bean : COM0 [AsynchroSerial]
|
||||
** Description :
|
||||
** This event is called after a correct character is
|
||||
** received. This
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
void COM0_OnTxChar(void);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : COM0_OnTxChar (module Events)
|
||||
**
|
||||
** From bean : COM0 [AsynchroSerial]
|
||||
** Description :
|
||||
** This event is called after a character is transmitted.
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
void COM0_OnFullRxBuf(void);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : COM0_OnFullRxBuf (module Events)
|
||||
**
|
||||
** From bean : COM0 [AsynchroSerial]
|
||||
** Description :
|
||||
** This event is called when the input buffer is full.
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
void COM0_OnFreeTxBuf(void);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Event : COM0_OnFreeTxBuf (module Events)
|
||||
**
|
||||
** From bean : COM0 [AsynchroSerial]
|
||||
** Description :
|
||||
** This event is called after the last character in output
|
||||
** buffer is transmitted.
|
||||
** Parameters : None
|
||||
** Returns : Nothing
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
/* END Events */
|
||||
#endif /* __Events_H*/
|
||||
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
559
20080212/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.C
Normal file
559
20080212/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.C
Normal file
|
|
@ -0,0 +1,559 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : IO_Map.C
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : IO_Map
|
||||
** Version : Driver 01.01
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 13/06/2005, 20:14
|
||||
** Abstract :
|
||||
** This bean "IO_Map" implements an IO devices mapping.
|
||||
** Settings :
|
||||
**
|
||||
** Contents :
|
||||
** No public methods
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
/* Based on CPU DB MC9S12DP256_112, version 2.87.278 */
|
||||
#include "PE_types.h"
|
||||
#include "IO_Map.h"
|
||||
|
||||
volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */
|
||||
volatile ATD0DIENSTR _ATD0DIEN; /* ATD 0 Input Enable Mask Register */
|
||||
volatile ATD0STAT0STR _ATD0STAT0; /* ATD 0 Status Register 0 */
|
||||
volatile ATD0STAT1STR _ATD0STAT1; /* ATD 0 Status Register 1 */
|
||||
volatile ATD1DIENSTR _ATD1DIEN; /* ATD 1 Input Enable Mask Register */
|
||||
volatile ATD1STAT0STR _ATD1STAT0; /* ATD 1 Status Register 0 */
|
||||
volatile ATD1STAT1STR _ATD1STAT1; /* ATD 1 Status Register 1 */
|
||||
volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */
|
||||
volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */
|
||||
volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */
|
||||
volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */
|
||||
volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */
|
||||
volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */
|
||||
volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */
|
||||
volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */
|
||||
volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */
|
||||
volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */
|
||||
volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */
|
||||
volatile CAN0BTR0STR _CAN0BTR0; /* MSCAN 0 Bus Timing Register 0 */
|
||||
volatile CAN0BTR1STR _CAN0BTR1; /* MSCAN 0 Bus Timing Register 1 */
|
||||
volatile CAN0CTL0STR _CAN0CTL0; /* MSCAN 0 Control 0 Register */
|
||||
volatile CAN0CTL1STR _CAN0CTL1; /* MSCAN 0 Control 1 Register */
|
||||
volatile CAN0IDACSTR _CAN0IDAC; /* MSCAN 0 Identifier Acceptance Control Register */
|
||||
volatile CAN0IDAR0STR _CAN0IDAR0; /* MSCAN 0 Identifier Acceptance Register 0 */
|
||||
volatile CAN0IDAR1STR _CAN0IDAR1; /* MSCAN 0 Identifier Acceptance Register 1 */
|
||||
volatile CAN0IDAR2STR _CAN0IDAR2; /* MSCAN 0 Identifier Acceptance Register 2 */
|
||||
volatile CAN0IDAR3STR _CAN0IDAR3; /* MSCAN 0 Identifier Acceptance Register 3 */
|
||||
volatile CAN0IDAR4STR _CAN0IDAR4; /* MSCAN 0 Identifier Acceptance Register 4 */
|
||||
volatile CAN0IDAR5STR _CAN0IDAR5; /* MSCAN 0 Identifier Acceptance Register 5 */
|
||||
volatile CAN0IDAR6STR _CAN0IDAR6; /* MSCAN 0 Identifier Acceptance Register 6 */
|
||||
volatile CAN0IDAR7STR _CAN0IDAR7; /* MSCAN 0 Identifier Acceptance Register 7 */
|
||||
volatile CAN0IDMR0STR _CAN0IDMR0; /* MSCAN 0 Identifier Mask Register 0 */
|
||||
volatile CAN0IDMR1STR _CAN0IDMR1; /* MSCAN 0 Identifier Mask Register 1 */
|
||||
volatile CAN0IDMR2STR _CAN0IDMR2; /* MSCAN 0 Identifier Mask Register 2 */
|
||||
volatile CAN0IDMR3STR _CAN0IDMR3; /* MSCAN 0 Identifier Mask Register 3 */
|
||||
volatile CAN0IDMR4STR _CAN0IDMR4; /* MSCAN 0 Identifier Mask Register 4 */
|
||||
volatile CAN0IDMR5STR _CAN0IDMR5; /* MSCAN 0 Identifier Mask Register 5 */
|
||||
volatile CAN0IDMR6STR _CAN0IDMR6; /* MSCAN 0 Identifier Mask Register 6 */
|
||||
volatile CAN0IDMR7STR _CAN0IDMR7; /* MSCAN 0 Identifier Mask Register 7 */
|
||||
volatile CAN0RFLGSTR _CAN0RFLG; /* MSCAN 0 Receiver Flag Register */
|
||||
volatile CAN0RIERSTR _CAN0RIER; /* MSCAN 0 Receiver Interrupt Enable Register */
|
||||
volatile CAN0RXDLRSTR _CAN0RXDLR; /* MSCAN 0 Receive Data Length Register */
|
||||
volatile CAN0RXDSR0STR _CAN0RXDSR0; /* MSCAN 0 Receive Data Segment Register 0 */
|
||||
volatile CAN0RXDSR1STR _CAN0RXDSR1; /* MSCAN 0 Receive Data Segment Register 1 */
|
||||
volatile CAN0RXDSR2STR _CAN0RXDSR2; /* MSCAN 0 Receive Data Segment Register 2 */
|
||||
volatile CAN0RXDSR3STR _CAN0RXDSR3; /* MSCAN 0 Receive Data Segment Register 3 */
|
||||
volatile CAN0RXDSR4STR _CAN0RXDSR4; /* MSCAN 0 Receive Data Segment Register 4 */
|
||||
volatile CAN0RXDSR5STR _CAN0RXDSR5; /* MSCAN 0 Receive Data Segment Register 5 */
|
||||
volatile CAN0RXDSR6STR _CAN0RXDSR6; /* MSCAN 0 Receive Data Segment Register 6 */
|
||||
volatile CAN0RXDSR7STR _CAN0RXDSR7; /* MSCAN 0 Receive Data Segment Register 7 */
|
||||
volatile CAN0RXERRSTR _CAN0RXERR; /* MSCAN 0 Receive Error Counter Register */
|
||||
volatile CAN0RXIDR0STR _CAN0RXIDR0; /* MSCAN 0 Receive Identifier Register 0 */
|
||||
volatile CAN0RXIDR1STR _CAN0RXIDR1; /* MSCAN 0 Receive Identifier Register 1 */
|
||||
volatile CAN0RXIDR2STR _CAN0RXIDR2; /* MSCAN 0 Receive Identifier Register 2 */
|
||||
volatile CAN0RXIDR3STR _CAN0RXIDR3; /* MSCAN 0 Receive Identifier Register 3 */
|
||||
volatile CAN0TAAKSTR _CAN0TAAK; /* MSCAN 0 Transmitter Message Abort Control */
|
||||
volatile CAN0TARQSTR _CAN0TARQ; /* MSCAN 0 Transmitter Message Abort Request */
|
||||
volatile CAN0TBSELSTR _CAN0TBSEL; /* MSCAN 0 Transmit Buffer Selection */
|
||||
volatile CAN0TFLGSTR _CAN0TFLG; /* MSCAN 0 Transmitter Flag Register */
|
||||
volatile CAN0TIERSTR _CAN0TIER; /* MSCAN 0 Transmitter Interrupt Enable Register */
|
||||
volatile CAN0TXDLRSTR _CAN0TXDLR; /* MSCAN 0 Transmit Data Length Register */
|
||||
volatile CAN0TXDSR0STR _CAN0TXDSR0; /* MSCAN 0 Transmit Data Segment Register 0 */
|
||||
volatile CAN0TXDSR1STR _CAN0TXDSR1; /* MSCAN 0 Transmit Data Segment Register 1 */
|
||||
volatile CAN0TXDSR2STR _CAN0TXDSR2; /* MSCAN 0 Transmit Data Segment Register 2 */
|
||||
volatile CAN0TXDSR3STR _CAN0TXDSR3; /* MSCAN 0 Transmit Data Segment Register 3 */
|
||||
volatile CAN0TXDSR4STR _CAN0TXDSR4; /* MSCAN 0 Transmit Data Segment Register 4 */
|
||||
volatile CAN0TXDSR5STR _CAN0TXDSR5; /* MSCAN 0 Transmit Data Segment Register 5 */
|
||||
volatile CAN0TXDSR6STR _CAN0TXDSR6; /* MSCAN 0 Transmit Data Segment Register 6 */
|
||||
volatile CAN0TXDSR7STR _CAN0TXDSR7; /* MSCAN 0 Transmit Data Segment Register 7 */
|
||||
volatile CAN0TXERRSTR _CAN0TXERR; /* MSCAN 0 Transmit Error Counter Register */
|
||||
volatile CAN0TXIDR0STR _CAN0TXIDR0; /* MSCAN 0 Transmit Identifier Register 0 */
|
||||
volatile CAN0TXIDR1STR _CAN0TXIDR1; /* MSCAN 0 Transmit Identifier Register 1 */
|
||||
volatile CAN0TXIDR2STR _CAN0TXIDR2; /* MSCAN 0 Transmit Identifier Register 2 */
|
||||
volatile CAN0TXIDR3STR _CAN0TXIDR3; /* MSCAN 0 Transmit Identifier Register 3 */
|
||||
volatile CAN0TXTBPRSTR _CAN0TXTBPR; /* MSCAN 0 Transmit Buffer Priority */
|
||||
volatile CAN1BTR0STR _CAN1BTR0; /* MSCAN 1 Bus Timing Register 0 */
|
||||
volatile CAN1BTR1STR _CAN1BTR1; /* MSCAN 1 Bus Timing Register 1 */
|
||||
volatile CAN1CTL0STR _CAN1CTL0; /* MSCAN 1 Control 0 Register */
|
||||
volatile CAN1CTL1STR _CAN1CTL1; /* MSCAN 1 Control 1 Register */
|
||||
volatile CAN1IDACSTR _CAN1IDAC; /* MSCAN 1 Identifier Acceptance Control Register */
|
||||
volatile CAN1IDAR0STR _CAN1IDAR0; /* MSCAN 1 Identifier Acceptance Register 0 */
|
||||
volatile CAN1IDAR1STR _CAN1IDAR1; /* MSCAN 1 Identifier Acceptance Register 1 */
|
||||
volatile CAN1IDAR2STR _CAN1IDAR2; /* MSCAN 1 Identifier Acceptance Register 2 */
|
||||
volatile CAN1IDAR3STR _CAN1IDAR3; /* MSCAN 1 Identifier Acceptance Register 3 */
|
||||
volatile CAN1IDAR4STR _CAN1IDAR4; /* MSCAN 1 Identifier Acceptance Register 4 */
|
||||
volatile CAN1IDAR5STR _CAN1IDAR5; /* MSCAN 1 Identifier Acceptance Register 5 */
|
||||
volatile CAN1IDAR6STR _CAN1IDAR6; /* MSCAN 1 Identifier Acceptance Register 6 */
|
||||
volatile CAN1IDAR7STR _CAN1IDAR7; /* MSCAN 1 Identifier Acceptance Register 7 */
|
||||
volatile CAN1IDMR0STR _CAN1IDMR0; /* MSCAN 1 Identifier Mask Register 0 */
|
||||
volatile CAN1IDMR1STR _CAN1IDMR1; /* MSCAN 1 Identifier Mask Register 1 */
|
||||
volatile CAN1IDMR2STR _CAN1IDMR2; /* MSCAN 1 Identifier Mask Register 2 */
|
||||
volatile CAN1IDMR3STR _CAN1IDMR3; /* MSCAN 1 Identifier Mask Register 3 */
|
||||
volatile CAN1IDMR4STR _CAN1IDMR4; /* MSCAN 1 Identifier Mask Register 4 */
|
||||
volatile CAN1IDMR5STR _CAN1IDMR5; /* MSCAN 1 Identifier Mask Register 5 */
|
||||
volatile CAN1IDMR6STR _CAN1IDMR6; /* MSCAN 1 Identifier Mask Register 6 */
|
||||
volatile CAN1IDMR7STR _CAN1IDMR7; /* MSCAN 1 Identifier Mask Register 7 */
|
||||
volatile CAN1RFLGSTR _CAN1RFLG; /* MSCAN 1 Receiver Flag Register */
|
||||
volatile CAN1RIERSTR _CAN1RIER; /* MSCAN 1 Receiver Interrupt Enable Register */
|
||||
volatile CAN1RXDLRSTR _CAN1RXDLR; /* MSCAN 1 Receive Data Length Register */
|
||||
volatile CAN1RXDSR0STR _CAN1RXDSR0; /* MSCAN 1 Receive Data Segment Register 0 */
|
||||
volatile CAN1RXDSR1STR _CAN1RXDSR1; /* MSCAN 1 Receive Data Segment Register 1 */
|
||||
volatile CAN1RXDSR2STR _CAN1RXDSR2; /* MSCAN 1 Receive Data Segment Register 2 */
|
||||
volatile CAN1RXDSR3STR _CAN1RXDSR3; /* MSCAN 1 Receive Data Segment Register 3 */
|
||||
volatile CAN1RXDSR4STR _CAN1RXDSR4; /* MSCAN 1 Receive Data Segment Register 4 */
|
||||
volatile CAN1RXDSR5STR _CAN1RXDSR5; /* MSCAN 1 Receive Data Segment Register 5 */
|
||||
volatile CAN1RXDSR6STR _CAN1RXDSR6; /* MSCAN 1 Receive Data Segment Register 6 */
|
||||
volatile CAN1RXDSR7STR _CAN1RXDSR7; /* MSCAN 1 Receive Data Segment Register 7 */
|
||||
volatile CAN1RXERRSTR _CAN1RXERR; /* MSCAN 1 Receive Error Counter Register */
|
||||
volatile CAN1RXIDR0STR _CAN1RXIDR0; /* MSCAN 1 Receive Identifier Register 0 */
|
||||
volatile CAN1RXIDR1STR _CAN1RXIDR1; /* MSCAN 1 Receive Identifier Register 1 */
|
||||
volatile CAN1RXIDR2STR _CAN1RXIDR2; /* MSCAN 1 Receive Identifier Register 2 */
|
||||
volatile CAN1RXIDR3STR _CAN1RXIDR3; /* MSCAN 1 Receive Identifier Register 3 */
|
||||
volatile CAN1TAAKSTR _CAN1TAAK; /* MSCAN 1 Transmitter Message Abort Control */
|
||||
volatile CAN1TARQSTR _CAN1TARQ; /* MSCAN 1 Transmitter Message Abort Request */
|
||||
volatile CAN1TBSELSTR _CAN1TBSEL; /* MSCAN 1 Transmit Buffer Selection */
|
||||
volatile CAN1TFLGSTR _CAN1TFLG; /* MSCAN 1 Transmitter Flag Register */
|
||||
volatile CAN1TIERSTR _CAN1TIER; /* MSCAN 1 Transmitter Interrupt Enable Register */
|
||||
volatile CAN1TXDLRSTR _CAN1TXDLR; /* MSCAN 1 Transmit Data Length Register */
|
||||
volatile CAN1TXDSR0STR _CAN1TXDSR0; /* MSCAN 1 Transmit Data Segment Register 0 */
|
||||
volatile CAN1TXDSR1STR _CAN1TXDSR1; /* MSCAN 1 Transmit Data Segment Register 1 */
|
||||
volatile CAN1TXDSR2STR _CAN1TXDSR2; /* MSCAN 1 Transmit Data Segment Register 2 */
|
||||
volatile CAN1TXDSR3STR _CAN1TXDSR3; /* MSCAN 1 Transmit Data Segment Register 3 */
|
||||
volatile CAN1TXDSR4STR _CAN1TXDSR4; /* MSCAN 1 Transmit Data Segment Register 4 */
|
||||
volatile CAN1TXDSR5STR _CAN1TXDSR5; /* MSCAN 1 Transmit Data Segment Register 5 */
|
||||
volatile CAN1TXDSR6STR _CAN1TXDSR6; /* MSCAN 1 Transmit Data Segment Register 6 */
|
||||
volatile CAN1TXDSR7STR _CAN1TXDSR7; /* MSCAN 1 Transmit Data Segment Register 7 */
|
||||
volatile CAN1TXERRSTR _CAN1TXERR; /* MSCAN 1 Transmit Error Counter Register */
|
||||
volatile CAN1TXIDR0STR _CAN1TXIDR0; /* MSCAN 1 Transmit Identifier Register 0 */
|
||||
volatile CAN1TXIDR1STR _CAN1TXIDR1; /* MSCAN 1 Transmit Identifier Register 1 */
|
||||
volatile CAN1TXIDR2STR _CAN1TXIDR2; /* MSCAN 1 Transmit Identifier Register 2 */
|
||||
volatile CAN1TXIDR3STR _CAN1TXIDR3; /* MSCAN 1 Transmit Identifier Register 3 */
|
||||
volatile CAN1TXTBPRSTR _CAN1TXTBPR; /* MSCAN 1 Transmit Buffer Priority */
|
||||
volatile CAN2BTR0STR _CAN2BTR0; /* MSCAN 2 Bus Timing Register 0 */
|
||||
volatile CAN2BTR1STR _CAN2BTR1; /* MSCAN 2 Bus Timing Register 1 */
|
||||
volatile CAN2CTL0STR _CAN2CTL0; /* MSCAN 2 Control 0 Register */
|
||||
volatile CAN2CTL1STR _CAN2CTL1; /* MSCAN 2 Control 1 Register */
|
||||
volatile CAN2IDACSTR _CAN2IDAC; /* MSCAN 2 Identifier Acceptance Control Register */
|
||||
volatile CAN2IDAR0STR _CAN2IDAR0; /* MSCAN 2 Identifier Acceptance Register 0 */
|
||||
volatile CAN2IDAR1STR _CAN2IDAR1; /* MSCAN 2 Identifier Acceptance Register 1 */
|
||||
volatile CAN2IDAR2STR _CAN2IDAR2; /* MSCAN 2 Identifier Acceptance Register 2 */
|
||||
volatile CAN2IDAR3STR _CAN2IDAR3; /* MSCAN 2 Identifier Acceptance Register 3 */
|
||||
volatile CAN2IDAR4STR _CAN2IDAR4; /* MSCAN 2 Identifier Acceptance Register 4 */
|
||||
volatile CAN2IDAR5STR _CAN2IDAR5; /* MSCAN 2 Identifier Acceptance Register 5 */
|
||||
volatile CAN2IDAR6STR _CAN2IDAR6; /* MSCAN 2 Identifier Acceptance Register 6 */
|
||||
volatile CAN2IDAR7STR _CAN2IDAR7; /* MSCAN 2 Identifier Acceptance Register 7 */
|
||||
volatile CAN2IDMR0STR _CAN2IDMR0; /* MSCAN 2 Identifier Mask Register 0 */
|
||||
volatile CAN2IDMR1STR _CAN2IDMR1; /* MSCAN 2 Identifier Mask Register 1 */
|
||||
volatile CAN2IDMR2STR _CAN2IDMR2; /* MSCAN 2 Identifier Mask Register 2 */
|
||||
volatile CAN2IDMR3STR _CAN2IDMR3; /* MSCAN 2 Identifier Mask Register 3 */
|
||||
volatile CAN2IDMR4STR _CAN2IDMR4; /* MSCAN 2 Identifier Mask Register 4 */
|
||||
volatile CAN2IDMR5STR _CAN2IDMR5; /* MSCAN 2 Identifier Mask Register 5 */
|
||||
volatile CAN2IDMR6STR _CAN2IDMR6; /* MSCAN 2 Identifier Mask Register 6 */
|
||||
volatile CAN2IDMR7STR _CAN2IDMR7; /* MSCAN 2 Identifier Mask Register 7 */
|
||||
volatile CAN2RFLGSTR _CAN2RFLG; /* MSCAN 2 Receiver Flag Register */
|
||||
volatile CAN2RIERSTR _CAN2RIER; /* MSCAN 2 Receiver Interrupt Enable Register */
|
||||
volatile CAN2RXDLRSTR _CAN2RXDLR; /* MSCAN 2 Receive Data Length Register */
|
||||
volatile CAN2RXDSR0STR _CAN2RXDSR0; /* MSCAN 2 Receive Data Segment Register 0 */
|
||||
volatile CAN2RXDSR1STR _CAN2RXDSR1; /* MSCAN 2 Receive Data Segment Register 1 */
|
||||
volatile CAN2RXDSR2STR _CAN2RXDSR2; /* MSCAN 2 Receive Data Segment Register 2 */
|
||||
volatile CAN2RXDSR3STR _CAN2RXDSR3; /* MSCAN 2 Receive Data Segment Register 3 */
|
||||
volatile CAN2RXDSR4STR _CAN2RXDSR4; /* MSCAN 2 Receive Data Segment Register 4 */
|
||||
volatile CAN2RXDSR5STR _CAN2RXDSR5; /* MSCAN 2 Receive Data Segment Register 5 */
|
||||
volatile CAN2RXDSR6STR _CAN2RXDSR6; /* MSCAN 2 Receive Data Segment Register 6 */
|
||||
volatile CAN2RXDSR7STR _CAN2RXDSR7; /* MSCAN 2 Receive Data Segment Register 7 */
|
||||
volatile CAN2RXERRSTR _CAN2RXERR; /* MSCAN 2 Receive Error Counter Register */
|
||||
volatile CAN2RXIDR0STR _CAN2RXIDR0; /* MSCAN 2 Receive Identifier Register 0 */
|
||||
volatile CAN2RXIDR1STR _CAN2RXIDR1; /* MSCAN 2 Receive Identifier Register 1 */
|
||||
volatile CAN2RXIDR2STR _CAN2RXIDR2; /* MSCAN 2 Receive Identifier Register 2 */
|
||||
volatile CAN2RXIDR3STR _CAN2RXIDR3; /* MSCAN 2 Receive Identifier Register 3 */
|
||||
volatile CAN2TAAKSTR _CAN2TAAK; /* MSCAN 2 Transmitter Message Abort Control */
|
||||
volatile CAN2TARQSTR _CAN2TARQ; /* MSCAN 2 Transmitter Message Abort Request */
|
||||
volatile CAN2TBSELSTR _CAN2TBSEL; /* MSCAN 2 Transmit Buffer Selection */
|
||||
volatile CAN2TFLGSTR _CAN2TFLG; /* MSCAN 2 Transmitter Flag Register */
|
||||
volatile CAN2TIERSTR _CAN2TIER; /* MSCAN 2 Transmitter Interrupt Enable Register */
|
||||
volatile CAN2TXDLRSTR _CAN2TXDLR; /* MSCAN 2 Transmit Data Length Register */
|
||||
volatile CAN2TXDSR0STR _CAN2TXDSR0; /* MSCAN 2 Transmit Data Segment Register 0 */
|
||||
volatile CAN2TXDSR1STR _CAN2TXDSR1; /* MSCAN 2 Transmit Data Segment Register 1 */
|
||||
volatile CAN2TXDSR2STR _CAN2TXDSR2; /* MSCAN 2 Transmit Data Segment Register 2 */
|
||||
volatile CAN2TXDSR3STR _CAN2TXDSR3; /* MSCAN 2 Transmit Data Segment Register 3 */
|
||||
volatile CAN2TXDSR4STR _CAN2TXDSR4; /* MSCAN 2 Transmit Data Segment Register 4 */
|
||||
volatile CAN2TXDSR5STR _CAN2TXDSR5; /* MSCAN 2 Transmit Data Segment Register 5 */
|
||||
volatile CAN2TXDSR6STR _CAN2TXDSR6; /* MSCAN 2 Transmit Data Segment Register 6 */
|
||||
volatile CAN2TXDSR7STR _CAN2TXDSR7; /* MSCAN 2 Transmit Data Segment Register 7 */
|
||||
volatile CAN2TXERRSTR _CAN2TXERR; /* MSCAN 2 Transmit Error Counter Register */
|
||||
volatile CAN2TXIDR0STR _CAN2TXIDR0; /* MSCAN 2 Transmit Identifier Register 0 */
|
||||
volatile CAN2TXIDR1STR _CAN2TXIDR1; /* MSCAN 2 Transmit Identifier Register 1 */
|
||||
volatile CAN2TXIDR2STR _CAN2TXIDR2; /* MSCAN 2 Transmit Identifier Register 2 */
|
||||
volatile CAN2TXIDR3STR _CAN2TXIDR3; /* MSCAN 2 Transmit Identifier Register 3 */
|
||||
volatile CAN2TXTBPRSTR _CAN2TXTBPR; /* MSCAN 2 Transmit Buffer Priority */
|
||||
volatile CAN3BTR0STR _CAN3BTR0; /* MSCAN 3 Bus Timing Register 0 */
|
||||
volatile CAN3BTR1STR _CAN3BTR1; /* MSCAN 3 Bus Timing Register 1 */
|
||||
volatile CAN3CTL0STR _CAN3CTL0; /* MSCAN 3 Control 0 Register */
|
||||
volatile CAN3CTL1STR _CAN3CTL1; /* MSCAN 3 Control 1 Register */
|
||||
volatile CAN3IDACSTR _CAN3IDAC; /* MSCAN 3 Identifier Acceptance Control Register */
|
||||
volatile CAN3IDAR0STR _CAN3IDAR0; /* MSCAN 3 Identifier Acceptance Register 0 */
|
||||
volatile CAN3IDAR1STR _CAN3IDAR1; /* MSCAN 3 Identifier Acceptance Register 1 */
|
||||
volatile CAN3IDAR2STR _CAN3IDAR2; /* MSCAN 3 Identifier Acceptance Register 2 */
|
||||
volatile CAN3IDAR3STR _CAN3IDAR3; /* MSCAN 3 Identifier Acceptance Register 3 */
|
||||
volatile CAN3IDAR4STR _CAN3IDAR4; /* MSCAN 3 Identifier Acceptance Register 4 */
|
||||
volatile CAN3IDAR5STR _CAN3IDAR5; /* MSCAN 3 Identifier Acceptance Register 5 */
|
||||
volatile CAN3IDAR6STR _CAN3IDAR6; /* MSCAN 3 Identifier Acceptance Register 6 */
|
||||
volatile CAN3IDAR7STR _CAN3IDAR7; /* MSCAN 3 Identifier Acceptance Register 7 */
|
||||
volatile CAN3IDMR0STR _CAN3IDMR0; /* MSCAN 3 Identifier Mask Register 0 */
|
||||
volatile CAN3IDMR1STR _CAN3IDMR1; /* MSCAN 3 Identifier Mask Register 1 */
|
||||
volatile CAN3IDMR2STR _CAN3IDMR2; /* MSCAN 3 Identifier Mask Register 2 */
|
||||
volatile CAN3IDMR3STR _CAN3IDMR3; /* MSCAN 3 Identifier Mask Register 3 */
|
||||
volatile CAN3IDMR4STR _CAN3IDMR4; /* MSCAN 3 Identifier Mask Register 4 */
|
||||
volatile CAN3IDMR5STR _CAN3IDMR5; /* MSCAN 3 Identifier Mask Register 5 */
|
||||
volatile CAN3IDMR6STR _CAN3IDMR6; /* MSCAN 3 Identifier Mask Register 6 */
|
||||
volatile CAN3IDMR7STR _CAN3IDMR7; /* MSCAN 3 Identifier Mask Register 7 */
|
||||
volatile CAN3RFLGSTR _CAN3RFLG; /* MSCAN 3 Receiver Flag Register */
|
||||
volatile CAN3RIERSTR _CAN3RIER; /* MSCAN 3 Receiver Interrupt Enable Register */
|
||||
volatile CAN3RXDLRSTR _CAN3RXDLR; /* MSCAN 3 Receive Data Length Register */
|
||||
volatile CAN3RXDSR0STR _CAN3RXDSR0; /* MSCAN 3 Receive Data Segment Register 0 */
|
||||
volatile CAN3RXDSR1STR _CAN3RXDSR1; /* MSCAN 3 Receive Data Segment Register 1 */
|
||||
volatile CAN3RXDSR2STR _CAN3RXDSR2; /* MSCAN 3 Receive Data Segment Register 2 */
|
||||
volatile CAN3RXDSR3STR _CAN3RXDSR3; /* MSCAN 3 Receive Data Segment Register 3 */
|
||||
volatile CAN3RXDSR4STR _CAN3RXDSR4; /* MSCAN 3 Receive Data Segment Register 4 */
|
||||
volatile CAN3RXDSR5STR _CAN3RXDSR5; /* MSCAN 3 Receive Data Segment Register 5 */
|
||||
volatile CAN3RXDSR6STR _CAN3RXDSR6; /* MSCAN 3 Receive Data Segment Register 6 */
|
||||
volatile CAN3RXDSR7STR _CAN3RXDSR7; /* MSCAN 3 Receive Data Segment Register 7 */
|
||||
volatile CAN3RXERRSTR _CAN3RXERR; /* MSCAN 3 Receive Error Counter Register */
|
||||
volatile CAN3RXIDR0STR _CAN3RXIDR0; /* MSCAN 3 Receive Identifier Register 0 */
|
||||
volatile CAN3RXIDR1STR _CAN3RXIDR1; /* MSCAN 3 Receive Identifier Register 1 */
|
||||
volatile CAN3RXIDR2STR _CAN3RXIDR2; /* MSCAN 3 Receive Identifier Register 2 */
|
||||
volatile CAN3RXIDR3STR _CAN3RXIDR3; /* MSCAN 3 Receive Identifier Register 3 */
|
||||
volatile CAN3TAAKSTR _CAN3TAAK; /* MSCAN 3 Transmitter Message Abort Control */
|
||||
volatile CAN3TARQSTR _CAN3TARQ; /* MSCAN 3 Transmitter Message Abort Request */
|
||||
volatile CAN3TBSELSTR _CAN3TBSEL; /* MSCAN 3 Transmit Buffer Selection */
|
||||
volatile CAN3TFLGSTR _CAN3TFLG; /* MSCAN 3 Transmitter Flag Register */
|
||||
volatile CAN3TIERSTR _CAN3TIER; /* MSCAN 3 Transmitter Interrupt Enable Register */
|
||||
volatile CAN3TXDLRSTR _CAN3TXDLR; /* MSCAN 3 Transmit Data Length Register */
|
||||
volatile CAN3TXDSR0STR _CAN3TXDSR0; /* MSCAN 3 Transmit Data Segment Register 0 */
|
||||
volatile CAN3TXDSR1STR _CAN3TXDSR1; /* MSCAN 3 Transmit Data Segment Register 1 */
|
||||
volatile CAN3TXDSR2STR _CAN3TXDSR2; /* MSCAN 3 Transmit Data Segment Register 2 */
|
||||
volatile CAN3TXDSR3STR _CAN3TXDSR3; /* MSCAN 3 Transmit Data Segment Register 3 */
|
||||
volatile CAN3TXDSR4STR _CAN3TXDSR4; /* MSCAN 3 Transmit Data Segment Register 4 */
|
||||
volatile CAN3TXDSR5STR _CAN3TXDSR5; /* MSCAN 3 Transmit Data Segment Register 5 */
|
||||
volatile CAN3TXDSR6STR _CAN3TXDSR6; /* MSCAN 3 Transmit Data Segment Register 6 */
|
||||
volatile CAN3TXDSR7STR _CAN3TXDSR7; /* MSCAN 3 Transmit Data Segment Register 7 */
|
||||
volatile CAN3TXERRSTR _CAN3TXERR; /* MSCAN 3 Transmit Error Counter Register */
|
||||
volatile CAN3TXIDR0STR _CAN3TXIDR0; /* MSCAN 3 Transmit Identifier Register 0 */
|
||||
volatile CAN3TXIDR1STR _CAN3TXIDR1; /* MSCAN 3 Transmit Identifier Register 1 */
|
||||
volatile CAN3TXIDR2STR _CAN3TXIDR2; /* MSCAN 3 Transmit Identifier Register 2 */
|
||||
volatile CAN3TXIDR3STR _CAN3TXIDR3; /* MSCAN 3 Transmit Identifier Register 3 */
|
||||
volatile CAN3TXTBPRSTR _CAN3TXTBPR; /* MSCAN 3 Transmit Buffer Priority */
|
||||
volatile CAN4BTR0STR _CAN4BTR0; /* MSCAN4 Bus Timing Register 0 */
|
||||
volatile CAN4BTR1STR _CAN4BTR1; /* MSCAN4 Bus Timing Register 1 */
|
||||
volatile CAN4CTL0STR _CAN4CTL0; /* MSCAN4 Control 0 Register */
|
||||
volatile CAN4CTL1STR _CAN4CTL1; /* MSCAN4 Control 1 Register */
|
||||
volatile CAN4IDACSTR _CAN4IDAC; /* MSCAN4 Identifier Acceptance Control Register */
|
||||
volatile CAN4IDAR0STR _CAN4IDAR0; /* MSCAN4 Identifier Acceptance Register 0 */
|
||||
volatile CAN4IDAR1STR _CAN4IDAR1; /* MSCAN4 Identifier Acceptance Register 1 */
|
||||
volatile CAN4IDAR2STR _CAN4IDAR2; /* MSCAN4 Identifier Acceptance Register 2 */
|
||||
volatile CAN4IDAR3STR _CAN4IDAR3; /* MSCAN4 Identifier Acceptance Register 3 */
|
||||
volatile CAN4IDAR4STR _CAN4IDAR4; /* MSCAN4 Identifier Acceptance Register 4 */
|
||||
volatile CAN4IDAR5STR _CAN4IDAR5; /* MSCAN4 Identifier Acceptance Register 5 */
|
||||
volatile CAN4IDAR6STR _CAN4IDAR6; /* MSCAN4 Identifier Acceptance Register 6 */
|
||||
volatile CAN4IDAR7STR _CAN4IDAR7; /* MSCAN4 Identifier Acceptance Register 7 */
|
||||
volatile CAN4IDMR0STR _CAN4IDMR0; /* MSCAN4 Identifier Mask Register 0 */
|
||||
volatile CAN4IDMR1STR _CAN4IDMR1; /* MSCAN4 Identifier Mask Register 1 */
|
||||
volatile CAN4IDMR2STR _CAN4IDMR2; /* MSCAN4 Identifier Mask Register 2 */
|
||||
volatile CAN4IDMR3STR _CAN4IDMR3; /* MSCAN4 Identifier Mask Register 3 */
|
||||
volatile CAN4IDMR4STR _CAN4IDMR4; /* MSCAN4 Identifier Mask Register 4 */
|
||||
volatile CAN4IDMR5STR _CAN4IDMR5; /* MSCAN4 Identifier Mask Register 5 */
|
||||
volatile CAN4IDMR6STR _CAN4IDMR6; /* MSCAN4 Identifier Mask Register 6 */
|
||||
volatile CAN4IDMR7STR _CAN4IDMR7; /* MSCAN4 Identifier Mask Register 7 */
|
||||
volatile CAN4RFLGSTR _CAN4RFLG; /* MSCAN4 Receiver Flag Register */
|
||||
volatile CAN4RIERSTR _CAN4RIER; /* MSCAN4 Receiver Interrupt Enable Register */
|
||||
volatile CAN4RXDLRSTR _CAN4RXDLR; /* MSCAN4 Receive Data Length Register */
|
||||
volatile CAN4RXDSR0STR _CAN4RXDSR0; /* MSCAN4 Receive Data Segment Register 0 */
|
||||
volatile CAN4RXDSR1STR _CAN4RXDSR1; /* MSCAN4 Receive Data Segment Register 1 */
|
||||
volatile CAN4RXDSR2STR _CAN4RXDSR2; /* MSCAN4 Receive Data Segment Register 2 */
|
||||
volatile CAN4RXDSR3STR _CAN4RXDSR3; /* MSCAN4 Receive Data Segment Register 3 */
|
||||
volatile CAN4RXDSR4STR _CAN4RXDSR4; /* MSCAN4 Receive Data Segment Register 4 */
|
||||
volatile CAN4RXDSR5STR _CAN4RXDSR5; /* MSCAN4 Receive Data Segment Register 5 */
|
||||
volatile CAN4RXDSR6STR _CAN4RXDSR6; /* MSCAN4 Receive Data Segment Register 6 */
|
||||
volatile CAN4RXDSR7STR _CAN4RXDSR7; /* MSCAN4 Receive Data Segment Register 7 */
|
||||
volatile CAN4RXERRSTR _CAN4RXERR; /* MSCAN4 Receive Error Counter Register */
|
||||
volatile CAN4RXIDR0STR _CAN4RXIDR0; /* MSCAN4 Receive Identifier Register 0 */
|
||||
volatile CAN4RXIDR1STR _CAN4RXIDR1; /* MSCAN4 Receive Identifier Register 1 */
|
||||
volatile CAN4RXIDR2STR _CAN4RXIDR2; /* MSCAN4 Receive Identifier Register 2 */
|
||||
volatile CAN4RXIDR3STR _CAN4RXIDR3; /* MSCAN4 Receive Identifier Register 3 */
|
||||
volatile CAN4TAAKSTR _CAN4TAAK; /* MSCAN4 Transmitter Message Abort Control */
|
||||
volatile CAN4TARQSTR _CAN4TARQ; /* MSCAN 4 Transmitter Message Abort Request */
|
||||
volatile CAN4TBSELSTR _CAN4TBSEL; /* MSCAN4 Transmit Buffer Selection */
|
||||
volatile CAN4TFLGSTR _CAN4TFLG; /* MSCAN4 Transmitter Flag Register */
|
||||
volatile CAN4TIERSTR _CAN4TIER; /* MSCAN4 Transmitter Interrupt Enable Register */
|
||||
volatile CAN4TXDLRSTR _CAN4TXDLR; /* MSCAN4 Transmit Data Length Register */
|
||||
volatile CAN4TXDSR0STR _CAN4TXDSR0; /* MSCAN4 Transmit Data Segment Register 0 */
|
||||
volatile CAN4TXDSR1STR _CAN4TXDSR1; /* MSCAN4 Transmit Data Segment Register 1 */
|
||||
volatile CAN4TXDSR2STR _CAN4TXDSR2; /* MSCAN4 Transmit Data Segment Register 2 */
|
||||
volatile CAN4TXDSR3STR _CAN4TXDSR3; /* MSCAN4 Transmit Data Segment Register 3 */
|
||||
volatile CAN4TXDSR4STR _CAN4TXDSR4; /* MSCAN4 Transmit Data Segment Register 4 */
|
||||
volatile CAN4TXDSR5STR _CAN4TXDSR5; /* MSCAN4 Transmit Data Segment Register 5 */
|
||||
volatile CAN4TXDSR6STR _CAN4TXDSR6; /* MSCAN4 Transmit Data Segment Register 6 */
|
||||
volatile CAN4TXDSR7STR _CAN4TXDSR7; /* MSCAN4 Transmit Data Segment Register 7 */
|
||||
volatile CAN4TXERRSTR _CAN4TXERR; /* MSCAN4 Transmit Error Counter Register */
|
||||
volatile CAN4TXIDR0STR _CAN4TXIDR0; /* MSCAN4 Transmit Identifier Register 0 */
|
||||
volatile CAN4TXIDR1STR _CAN4TXIDR1; /* MSCAN4 Transmit Identifier Register 1 */
|
||||
volatile CAN4TXIDR2STR _CAN4TXIDR2; /* MSCAN4 Transmit Identifier Register 2 */
|
||||
volatile CAN4TXIDR3STR _CAN4TXIDR3; /* MSCAN4 Transmit Identifier Register 3 */
|
||||
volatile CAN4TXTBPRSTR _CAN4TXTBPR; /* MSCAN4 Transmit Transmit Buffer Priority */
|
||||
volatile CFORCSTR _CFORC; /* Timer Compare Force Register */
|
||||
volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */
|
||||
volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */
|
||||
volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */
|
||||
volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */
|
||||
volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */
|
||||
volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */
|
||||
volatile DDRESTR _DDRE; /* Port E Data Direction Register */
|
||||
volatile DDRHSTR _DDRH; /* Port H Data Direction Register */
|
||||
volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */
|
||||
volatile DDRKSTR _DDRK; /* Port K Data Direction Register */
|
||||
volatile DDRMSTR _DDRM; /* Port M Data Direction Register */
|
||||
volatile DDRPSTR _DDRP; /* Port P Data Direction Register */
|
||||
volatile DDRSSTR _DDRS; /* Port S Data Direction Register */
|
||||
volatile DDRTSTR _DDRT; /* Port T Data Direction Register */
|
||||
volatile DLCBARDSTR _DLCBARD; /* BDLC Analog Round Trip Delay Register */
|
||||
volatile DLCBCR1STR _DLCBCR1; /* BDLC Control Register 1 */
|
||||
volatile DLCBCR2STR _DLCBCR2; /* BDLC Control Register 2 */
|
||||
volatile DLCBDRSTR _DLCBDR; /* BDLC Data Register */
|
||||
volatile DLCBRSRSTR _DLCBRSR; /* BDLC Rate Select Register */
|
||||
volatile DLCBSVRSTR _DLCBSVR; /* BDLC State Vector Register */
|
||||
volatile DLCSCRSTR _DLCSCR; /* BDLC Control Register */
|
||||
volatile DLYCTSTR _DLYCT; /* Delay Counter Control Register */
|
||||
volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */
|
||||
volatile ECLKDIVSTR _ECLKDIV; /* EEPROM Clock Divider Register */
|
||||
volatile ECMDSTR _ECMD; /* EEPROM Command Buffer and Register */
|
||||
volatile ECNFGSTR _ECNFG; /* EEPROM Configuration Register */
|
||||
volatile EPROTSTR _EPROT; /* EEPROM Protection Register */
|
||||
volatile ESTATSTR _ESTAT; /* EEPROM Status Register */
|
||||
volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */
|
||||
volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */
|
||||
volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */
|
||||
volatile FORBYPSTR _FORBYP; /* Crg force and bypass test register */
|
||||
volatile FPROTSTR _FPROT; /* Flash Protection Register */
|
||||
volatile FSECSTR _FSEC; /* Flash Security Register */
|
||||
volatile FSTATSTR _FSTAT; /* Flash Status Register */
|
||||
volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */
|
||||
volatile IBADSTR _IBAD; /* IIC Address Register */
|
||||
volatile IBCRSTR _IBCR; /* IIC Control Register */
|
||||
volatile IBDRSTR _IBDR; /* IIC Data I/O Register */
|
||||
volatile IBFDSTR _IBFD; /* IIC Frequency Divider Register */
|
||||
volatile IBSRSTR _IBSR; /* IIC Status Register */
|
||||
volatile ICOVWSTR _ICOVW; /* Input Control Overwrite Register */
|
||||
volatile ICPARSTR _ICPAR; /* Input Control Pulse Accumulator Register */
|
||||
volatile ICSYSSTR _ICSYS; /* Input Control System Control Register */
|
||||
volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */
|
||||
volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */
|
||||
volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */
|
||||
volatile INTCRSTR _INTCR; /* Interrupt Control Register */
|
||||
volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */
|
||||
volatile ITESTSTR _ITEST; /* Interrupt Test Register */
|
||||
volatile MCCTLSTR _MCCTL; /* Modulus Down Counter underflow */
|
||||
volatile MCFLGSTR _MCFLG; /* 16-Bit Modulus Down Counter Flag Register */
|
||||
volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */
|
||||
volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */
|
||||
volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */
|
||||
volatile MODESTR _MODE; /* Mode Register */
|
||||
volatile MODRRSTR _MODRR; /* Module Routing Register */
|
||||
volatile MTST0STR _MTST0; /* MTST0 */
|
||||
volatile MTST1STR _MTST1; /* MTST1 */
|
||||
volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */
|
||||
volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */
|
||||
volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */
|
||||
volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */
|
||||
volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */
|
||||
volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */
|
||||
volatile PBCTLSTR _PBCTL; /* 16-Bit Pulse Accumulator B Control Register */
|
||||
volatile PBFLGSTR _PBFLG; /* Pulse Accumulator B Flag Register */
|
||||
volatile PEARSTR _PEAR; /* Port E Assignment Register */
|
||||
volatile PERHSTR _PERH; /* Port H Pull Device Enable Register */
|
||||
volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */
|
||||
volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */
|
||||
volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */
|
||||
volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */
|
||||
volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */
|
||||
volatile PIEHSTR _PIEH; /* Port H Interrupt Enable Register */
|
||||
volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */
|
||||
volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */
|
||||
volatile PIFHSTR _PIFH; /* Port H Interrupt Flag Register */
|
||||
volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */
|
||||
volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */
|
||||
volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */
|
||||
volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */
|
||||
volatile PORTAD1STR _PORTAD1; /* Port AD1 Register */
|
||||
volatile PORTESTR _PORTE; /* Port E Register */
|
||||
volatile PORTKSTR _PORTK; /* Port K Data Register */
|
||||
volatile PPAGESTR _PPAGE; /* Page Index Register */
|
||||
volatile PPSHSTR _PPSH; /* Port H Polarity Select Register */
|
||||
volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */
|
||||
volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */
|
||||
volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */
|
||||
volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */
|
||||
volatile PPSTSTR _PPST; /* Port T Polarity Select Register */
|
||||
volatile PTHSTR _PTH; /* Port H I/O Register */
|
||||
volatile PTIHSTR _PTIH; /* Port H Input Register */
|
||||
volatile PTIJSTR _PTIJ; /* Port J Input Register */
|
||||
volatile PTIMSTR _PTIM; /* Port M Input */
|
||||
volatile PTIPSTR _PTIP; /* Port P Input */
|
||||
volatile PTISSTR _PTIS; /* Port S Input */
|
||||
volatile PTITSTR _PTIT; /* Port T Input */
|
||||
volatile PTJSTR _PTJ; /* Port J I/O Register */
|
||||
volatile PTMSTR _PTM; /* Port M I/O Register */
|
||||
volatile PTPSTR _PTP; /* Port P I/O Register */
|
||||
volatile PTSSTR _PTS; /* Port S I/O Register */
|
||||
volatile PTTSTR _PTT; /* Port T I/O Register */
|
||||
volatile PUCRSTR _PUCR; /* Pull-Up Control Register */
|
||||
volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */
|
||||
volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */
|
||||
volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */
|
||||
volatile PWMESTR _PWME; /* PWM Enable Register */
|
||||
volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */
|
||||
volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */
|
||||
volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */
|
||||
volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */
|
||||
volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */
|
||||
volatile RDRHSTR _RDRH; /* Port H Reduced Drive Register */
|
||||
volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */
|
||||
volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */
|
||||
volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */
|
||||
volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */
|
||||
volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */
|
||||
volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */
|
||||
volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */
|
||||
volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */
|
||||
volatile SCI0CR1STR _SCI0CR1; /* SCI 0 Control Register 1 */
|
||||
volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2 */
|
||||
volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High */
|
||||
volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low */
|
||||
volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1 */
|
||||
volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2 */
|
||||
volatile SCI1CR1STR _SCI1CR1; /* SCI 1 Control Register 1 */
|
||||
volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2 */
|
||||
volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High */
|
||||
volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low */
|
||||
volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1 */
|
||||
volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2 */
|
||||
volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register */
|
||||
volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register */
|
||||
volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2 */
|
||||
volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register */
|
||||
volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register */
|
||||
volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register */
|
||||
volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register */
|
||||
volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2 */
|
||||
volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register */
|
||||
volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register */
|
||||
volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register */
|
||||
volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register */
|
||||
volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2 */
|
||||
volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register */
|
||||
volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register */
|
||||
volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */
|
||||
volatile TCTL1STR _TCTL1; /* Timer Control Registers 1 */
|
||||
volatile TCTL2STR _TCTL2; /* Timer Control Registers 2 */
|
||||
volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */
|
||||
volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */
|
||||
volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */
|
||||
volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */
|
||||
volatile TIESTR _TIE; /* Timer Interrupt Enable Register */
|
||||
volatile TIMTSTSTR _TIMTST; /* Timer Test Register */
|
||||
volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */
|
||||
volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */
|
||||
volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */
|
||||
volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */
|
||||
volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */
|
||||
volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */
|
||||
volatile ATD0CTL23STR _ATD0CTL23; /* ATD 0 Control Register 23 */
|
||||
volatile ATD0CTL45STR _ATD0CTL45; /* ATD 0 Control Register 45 */
|
||||
volatile ATD0DR0STR _ATD0DR0; /* ATD 0 Conversion Result Register 0 */
|
||||
volatile ATD0DR1STR _ATD0DR1; /* ATD 0 Conversion Result Register 1 */
|
||||
volatile ATD0DR2STR _ATD0DR2; /* ATD 0 Conversion Result Register 2 */
|
||||
volatile ATD0DR3STR _ATD0DR3; /* ATD 0 Conversion Result Register 3 */
|
||||
volatile ATD0DR4STR _ATD0DR4; /* ATD 0 Conversion Result Register 4 */
|
||||
volatile ATD0DR5STR _ATD0DR5; /* ATD 0 Conversion Result Register 5 */
|
||||
volatile ATD0DR6STR _ATD0DR6; /* ATD 0 Conversion Result Register 6 */
|
||||
volatile ATD0DR7STR _ATD0DR7; /* ATD 0 Conversion Result Register 7 */
|
||||
volatile ATD1CTL23STR _ATD1CTL23; /* ATD 1 Control Register 23 */
|
||||
volatile ATD1CTL45STR _ATD1CTL45; /* ATD 1 Control Register 45 */
|
||||
volatile ATD1DR0STR _ATD1DR0; /* ATD 1 Conversion Result Register 0 */
|
||||
volatile ATD1DR1STR _ATD1DR1; /* ATD 1 Conversion Result Register 1 */
|
||||
volatile ATD1DR2STR _ATD1DR2; /* ATD 1 Conversion Result Register 2 */
|
||||
volatile ATD1DR3STR _ATD1DR3; /* ATD 1 Conversion Result Register 3 */
|
||||
volatile ATD1DR4STR _ATD1DR4; /* ATD 1 Conversion Result Register 4 */
|
||||
volatile ATD1DR5STR _ATD1DR5; /* ATD 1 Conversion Result Register 5 */
|
||||
volatile ATD1DR6STR _ATD1DR6; /* ATD 1 Conversion Result Register 6 */
|
||||
volatile ATD1DR7STR _ATD1DR7; /* ATD 1 Conversion Result Register 7 */
|
||||
volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */
|
||||
volatile MCCNTSTR _MCCNT; /* Modulus Down-Counter Count Register */
|
||||
volatile PA10HSTR _PA10H; /* 8-Bit Pulse Accumulators Holding 10 Register */
|
||||
volatile PA32HSTR _PA32H; /* 8-Bit Pulse Accumulators Holding 32 Register */
|
||||
volatile PACN10STR _PACN10; /* Pulse Accumulators Count 10 Register */
|
||||
volatile PACN32STR _PACN32; /* Pulse Accumulators Count 32 Register */
|
||||
volatile PORTABSTR _PORTAB; /* Port AB Register */
|
||||
volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */
|
||||
volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */
|
||||
volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */
|
||||
volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register */
|
||||
volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */
|
||||
volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */
|
||||
volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */
|
||||
volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register */
|
||||
volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */
|
||||
volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */
|
||||
volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */
|
||||
volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register */
|
||||
volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register */
|
||||
volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register */
|
||||
volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */
|
||||
volatile TC0HSTR _TC0H; /* Timer Input Capture Holding Registers 0 */
|
||||
volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */
|
||||
volatile TC1HSTR _TC1H; /* Timer Input Capture Holding Registers 1 */
|
||||
volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */
|
||||
volatile TC2HSTR _TC2H; /* Timer Input Capture Holding Registers 2 */
|
||||
volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */
|
||||
volatile TC3HSTR _TC3H; /* Timer Input Capture Holding Registers 3 */
|
||||
volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */
|
||||
volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */
|
||||
volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */
|
||||
volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */
|
||||
volatile TCNTSTR _TCNT; /* Timer Count Register */
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
18408
20080212/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.H
Normal file
18408
20080212/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.H
Normal file
File diff suppressed because it is too large
Load diff
52
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PESL.h
Normal file
52
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PESL.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/* ================================================================================================================================= **
|
||||
** ================================================================================================================================= **
|
||||
** CONFIGURATION FILE FOR PESL LIBRARY **
|
||||
** ================================================================================================================================= **
|
||||
** ================================================================================================================================= */
|
||||
|
||||
#define _MC9S12A128_112 1
|
||||
#define _MC9S12A128_80 2
|
||||
#define _MC9S12A256_112 3
|
||||
#define _MC9S12A256_80 4
|
||||
#define _MC9S12A64_112 5
|
||||
#define _MC9S12A64_80 6
|
||||
#define _MC9S12C32_48 7
|
||||
#define _MC9S12C32_52 8
|
||||
#define _MC9S12C32_80 9
|
||||
#define _MC9S12D64_112 10
|
||||
#define _MC9S12D64_80 11
|
||||
#define _MC9S12DB128_112 12
|
||||
#define _MC9S12DG128_112 13
|
||||
#define _MC9S12DG128_80 14
|
||||
#define _MC9S12DG256_112 15
|
||||
#define _MC9S12DJ128_112 16
|
||||
#define _MC9S12DJ128_80 17
|
||||
#define _MC9S12DJ256_112 18
|
||||
#define _MC9S12DJ256_80 19
|
||||
#define _MC9S12DJ64_112 20
|
||||
#define _MC9S12DJ64_80 21
|
||||
#define _MC9S12DP256_112 22
|
||||
#define _MC9S12DT128_112 23
|
||||
#define _MC9S12DT256_112 24
|
||||
#define _MC9S12A32_80 25
|
||||
#define _MC9S12D32_80 26
|
||||
#define _MC9S12DP512_112 27
|
||||
#define _MC9S12A512_112 28
|
||||
#define _MC9S12E128_112 29
|
||||
#define _MC9S12E128_80 30
|
||||
#define _MC9S12E64_112 31
|
||||
|
||||
|
||||
/* Selected target MCU */
|
||||
|
||||
#define CPUtype _MC9S12DP256_112
|
||||
|
||||
|
||||
/* PESL library */
|
||||
|
||||
#pragma MESSAGE DISABLE C4000 /* WARNING C4000: Condition is always TRUE */
|
||||
#pragma MESSAGE DISABLE C4001 /* WARNING C4001: Condition is always FALSE */
|
||||
|
||||
#include "PESLlib.h"
|
||||
|
||||
|
||||
50
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Const.H
Normal file
50
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Const.H
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : PE_Const.H
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : PE_Const
|
||||
** Version : Driver 01.00
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 13/06/2005, 20:14
|
||||
** Abstract :
|
||||
** This bean "PE_Const" contains internal definitions
|
||||
** of the constants.
|
||||
** Settings :
|
||||
** Contents :
|
||||
** No public methods
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
#ifndef __PE_Const_H
|
||||
#define __PE_Const_H
|
||||
|
||||
/* Constants for detecting running mode */
|
||||
#define HIGH_SPEED 0 /* High speed */
|
||||
#define LOW_SPEED 1 /* Low speed */
|
||||
#define SLOW_SPEED 2 /* Slow speed */
|
||||
|
||||
/* Reset cause constants */
|
||||
#define RSTSRC_POR 1 /* Power-on reset */
|
||||
#define RSTSRC_PIN 8 /* External reset bit */
|
||||
#define RSTSRC_COP 4 /* COP reset */
|
||||
#define RSTSRC_ILOP 2 /* Illegal opcode reset */
|
||||
#define RSTSRC_ILAD 16 /* Illegal address reset */
|
||||
#define RSTSRC_LVI 32 /* Low voltage inhibit reset */
|
||||
|
||||
#endif /* _PE_Const_H */
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
53
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Error.H
Normal file
53
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Error.H
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : PE_Error.H
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : PE_Error
|
||||
** Version : Driver 01.00
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 13/06/2005, 20:14
|
||||
** Abstract :
|
||||
** This bean "PE_Error" contains internal definitions
|
||||
** of the error constants.
|
||||
** Settings :
|
||||
** Contents :
|
||||
** No public methods
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
#ifndef __PE_Error_H
|
||||
#define __PE_Error_H
|
||||
|
||||
#define ERR_OK 0 /* OK */
|
||||
#define ERR_SPEED 1 /* This device does not work in the active speed mode. */
|
||||
#define ERR_RANGE 2 /* Parameter out of range. */
|
||||
#define ERR_VALUE 3 /* Parameter of incorrect value. */
|
||||
#define ERR_OVERFLOW 4 /* Timer overflow. */
|
||||
#define ERR_MATH 5 /* Overflow during evaluation. */
|
||||
#define ERR_ENABLED 6 /* Device is enabled. */
|
||||
#define ERR_DISABLED 7 /* Device is disabled. */
|
||||
#define ERR_BUSY 8 /* Device is busy. */
|
||||
#define ERR_NOTAVAIL 9 /* Requested value or method not available. */
|
||||
#define ERR_RXEMPTY 10 /* No data in receiver. */
|
||||
#define ERR_TXFULL 11 /* Transmitter is full. */
|
||||
#define ERR_BUSOFF 12 /* Bus not available. */
|
||||
#define ERR_OVERRUN 13 /* Overrun error is detected. */
|
||||
#define ERR_FRAMING 14 /* Framing error is detected. */
|
||||
#define ERR_PARITY 15 /* Parity error is detected. */
|
||||
#define ERR_NOISE 16 /* Noise error is detected. */
|
||||
#define ERR_IDLE 17 /* Idle error is detectes. */
|
||||
#define ERR_FAULT 18 /* Fault error is detected. */
|
||||
#define ERR_BREAK 19 /* Break char is received during communication. */
|
||||
#define ERR_CRC 20 /* CRC error is detected. */
|
||||
#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */
|
||||
#define ERR_PROTECT 22 /* Protection error is detected. */
|
||||
|
||||
#endif __PE_Error_H
|
||||
205
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.C
Normal file
205
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.C
Normal file
|
|
@ -0,0 +1,205 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : PE_Timer.C
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : PE_Timer
|
||||
** Version : Driver 01.00
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 14/06/2005, 16:34
|
||||
** Abstract :
|
||||
** This bean "PE_Timer" implements internal methods and definitions
|
||||
** used by beans working with timers.
|
||||
** Settings :
|
||||
** Contents :
|
||||
** No public methods
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
|
||||
/* MODULE PE_Timer. */
|
||||
|
||||
#include "PE_Timer.h"
|
||||
|
||||
|
||||
|
||||
typedef unsigned long UINT32;
|
||||
|
||||
typedef union {
|
||||
UINT32 val;
|
||||
struct {
|
||||
unsigned short hi16,lo16;
|
||||
} s;
|
||||
} OP_UINT32;
|
||||
|
||||
typedef struct {
|
||||
unsigned short dummy;
|
||||
UINT32 mid;
|
||||
} M_UINT32;
|
||||
|
||||
typedef struct {
|
||||
UINT32 hi32, lo32;
|
||||
} UINT64;
|
||||
|
||||
typedef union {
|
||||
UINT64 val;
|
||||
M_UINT32 m;
|
||||
} OP_UINT64;
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_Timer_LngMul (bean PE_Timer)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
void PE_Timer_LngMul(dword va1, dword va2, dlong *var)
|
||||
{
|
||||
OP_UINT32 *va = (OP_UINT32*)&va1;
|
||||
OP_UINT32 *vb = (OP_UINT32*)&va2;
|
||||
OP_UINT64 *vr = (OP_UINT64*)var;
|
||||
|
||||
vr->val.hi32 = 0UL;
|
||||
vr->val.lo32 = ((UINT32)va->s.lo16)*((UINT32)vb->s.lo16);
|
||||
{
|
||||
OP_UINT32 tmp;
|
||||
|
||||
tmp.val = ((UINT32)va->s.lo16)*((UINT32)vb->s.hi16);
|
||||
vr->m.mid += (UINT32)tmp.s.lo16;
|
||||
vr->val.hi32 += (UINT32)tmp.s.hi16;
|
||||
}
|
||||
{
|
||||
OP_UINT32 tmp;
|
||||
|
||||
tmp.val = ((UINT32)va->s.hi16)*((UINT32)vb->s.lo16);
|
||||
vr->m.mid += (UINT32)tmp.s.lo16;
|
||||
vr->val.hi32 += (UINT32)tmp.s.hi16;
|
||||
}
|
||||
vr->val.hi32 += ((UINT32)va->s.hi16)*((UINT32)vb->s.hi16);
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_Timer_LngHi1 (bean PE_Timer)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
bool PE_Timer_LngHi1(dword High, dword Low, word *Out)
|
||||
{
|
||||
if ((High == 0) && ((Low >> 24) == 0))
|
||||
if ((Low & 0x80) != 0) {
|
||||
if ((Low >> 8) < 0xFFFF) {
|
||||
*Out = ((unsigned int)(Low >> 8))+1;
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
else {
|
||||
*Out = (unsigned int)(Low >> 8);
|
||||
return FALSE;
|
||||
}
|
||||
*Out = (unsigned int)(Low >> 8);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_Timer_LngHi2 (bean PE_Timer)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
bool PE_Timer_LngHi2(dword High, dword Low, word *Out)
|
||||
{
|
||||
if (High == 0)
|
||||
if ((Low & 0x8000) != 0) {
|
||||
if ((Low >> 16) < 0xFFFF) {
|
||||
*Out = ((unsigned int)(Low >> 16))+1;
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
else {
|
||||
*Out = (unsigned int)(Low >> 16);
|
||||
return FALSE;
|
||||
}
|
||||
*Out = (unsigned int)(Low >> 16);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_Timer_LngHi3 (bean PE_Timer)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
bool PE_Timer_LngHi3(dword High, dword Low, word *Out)
|
||||
{
|
||||
if ((High >> 8) == 0)
|
||||
if ((Low & 0x800000) != 0) {
|
||||
if (((Low >> 24) | (High << 8)) < 0xFFFF) {
|
||||
*Out = ((unsigned int)((Low >> 24) | (High << 8)))+1;
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
else {
|
||||
*Out = (unsigned int)((Low >> 24) | (High << 8));
|
||||
return FALSE;
|
||||
}
|
||||
*Out = (unsigned int)((Low >> 24) | (High << 8));
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_Timer_LngHi4 (bean PE_Timer)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
bool PE_Timer_LngHi4(dword High, dword Low, word *Out)
|
||||
{
|
||||
if ((High >> 16) == 0)
|
||||
if ((Low & 0x80000000) != 0) {
|
||||
if (High < 0xFFFF) {
|
||||
*Out = ((unsigned int)High)+1;
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
else {
|
||||
*Out = (unsigned int)High;
|
||||
return FALSE;
|
||||
}
|
||||
*Out = (unsigned int)High;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* END PE_Timer. */
|
||||
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
97
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.H
Normal file
97
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.H
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : PE_Timer.H
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : PE_Timer
|
||||
** Version : Driver 01.00
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 14/06/2005, 16:34
|
||||
** Abstract :
|
||||
** This bean "PE_Timer" implements internal methods and definitions
|
||||
** used by beans working with timers.
|
||||
** Settings :
|
||||
** Contents :
|
||||
** No public methods
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
#ifndef __PE_Timer
|
||||
#define __PE_Timer
|
||||
/*Include shared modules, which are used for whole project*/
|
||||
#include "PE_types.h"
|
||||
#include "PE_const.h"
|
||||
|
||||
/* MODULE PE_Timer. */
|
||||
|
||||
void PE_Timer_LngMul(dword va1, dword va2, dlong *var);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_Timer_LngMul (bean PE_Timer)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
bool PE_Timer_LngHi1(dword Low, dword High, word *Out);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_Timer_LngHi1 (bean PE_Timer)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
bool PE_Timer_LngHi2(dword Low, dword High, word *Out);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_Timer_LngHi2 (bean PE_Timer)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
bool PE_Timer_LngHi3(dword Low, dword High, word *Out);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_Timer_LngHi3 (bean PE_Timer)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
bool PE_Timer_LngHi4(dword Low, dword High, word *Out);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : PE_Timer_LngHi4 (bean PE_Timer)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
|
||||
#endif /* END PE_Timer. */
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
87
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Types.H
Normal file
87
20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Types.H
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : PE_Types.H
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : PE_Types
|
||||
** Version : Driver 01.04
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 13/06/2005, 20:14
|
||||
** Abstract :
|
||||
** This bean "PE_Types" contains internal definitions
|
||||
** of the types.
|
||||
** Settings :
|
||||
** Contents :
|
||||
** No public methods
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
#ifndef __PE_Types_H
|
||||
#define __PE_Types_H
|
||||
|
||||
#define FALSE 0
|
||||
#define TRUE 1
|
||||
|
||||
/*Types definition*/
|
||||
typedef unsigned char bool;
|
||||
typedef unsigned char byte;
|
||||
typedef unsigned int word;
|
||||
typedef unsigned long dword;
|
||||
typedef unsigned long dlong[2];
|
||||
typedef void (*tIntFunc)(void);
|
||||
|
||||
/* Motorola types */
|
||||
typedef unsigned char VUINT8;
|
||||
typedef signed char VINT8;
|
||||
typedef unsigned short int VUINT16;
|
||||
typedef signed short int VINT16;
|
||||
typedef unsigned long int VUINT32;
|
||||
|
||||
#define in16(var,l,h) var = ((word)(l)) | (((word)(h)) << 8)
|
||||
#define out16(l,h,val) { l = (byte)val; h = (byte)(val >> 8); }
|
||||
|
||||
#define output(P, V) P = (V)
|
||||
#define input(P) (P)
|
||||
|
||||
#define __DI() { asm sei; } /* Disable global interrupts */
|
||||
#define __EI() { asm cli; } /* Enable global interrupts */
|
||||
#define EnterCritical() { __asm pshc; __asm sei; __asm movb 1,SP+,CCR_reg; } /* This macro is used by Processor Expert. It saves CCR register and disable global interrupts. */
|
||||
#define ExitCritical() { __asm movb CCR_reg, 1,-SP; __asm pulc; } /* This macro is used by Processor Expert. It restores CCR register saved in SaveStatusReg(). */
|
||||
/* obsolete definition for backward compatibility */
|
||||
#define SaveStatusReg() EnterCritical()
|
||||
#define RestoreStatusReg() ExitCritical()
|
||||
|
||||
|
||||
typedef struct { /* Black&White Image */
|
||||
word width; /* Image width */
|
||||
word height; /* Image height */
|
||||
byte *pixmap; /* Image pixel bitmap */
|
||||
word size; /* Image size */
|
||||
char *name; /* Image name */
|
||||
} TIMAGE;
|
||||
typedef TIMAGE* PIMAGE ; /* Pointer to image */
|
||||
|
||||
/* 16-bit register (Motorola format - big endian) */
|
||||
typedef union {
|
||||
word w;
|
||||
struct {
|
||||
byte high,low;
|
||||
} b;
|
||||
} TWREG;
|
||||
|
||||
#endif /* __PE_Types_H */
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
67
20080212/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.C
Normal file
67
20080212/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.C
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/** ###################################################################
|
||||
** Filename : RTOSDemo.C
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Version : Driver 01.05
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 13/06/2005, 20:14
|
||||
** Abstract :
|
||||
** Main module.
|
||||
** Here is to be placed user's code.
|
||||
** Settings :
|
||||
** Contents :
|
||||
** No public methods
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
/* MODULE RTOSDemo */
|
||||
|
||||
/* Including used modules for compilling procedure */
|
||||
#include "Cpu.h"
|
||||
#include "Events.h"
|
||||
#include "TickTimer.h"
|
||||
#include "Byte1.h"
|
||||
#include "COM0.h"
|
||||
/* Include shared modules, which are used for whole project */
|
||||
#include "PE_Types.h"
|
||||
#include "PE_Error.h"
|
||||
#include "PE_Const.h"
|
||||
#include "IO_Map.h"
|
||||
|
||||
extern void vMain( void );
|
||||
|
||||
void main(void)
|
||||
{
|
||||
/*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/
|
||||
PE_low_level_init();
|
||||
/*** End of Processor Expert internal initialization. ***/
|
||||
|
||||
/*Write your code here*/
|
||||
|
||||
/* Just jump to the real main(). */
|
||||
__asm
|
||||
{
|
||||
jmp vMain
|
||||
}
|
||||
|
||||
|
||||
/*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/
|
||||
for(;;);
|
||||
/*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/
|
||||
} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/
|
||||
|
||||
/* END RTOSDemo */
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
64
20080212/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.PRM
Normal file
64
20080212/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.PRM
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : RTOSDemo.PRM
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 19/06/2005, 15:54
|
||||
** Abstract :
|
||||
** This file is used by the linker. It describes files to be linked,
|
||||
** memory ranges, stack size, etc. For detailed description of the PRM file
|
||||
** see CodeWarrior documentation. This file is generated by default.
|
||||
** You can switch off generation by setting the property
|
||||
** "Generate PRM file = no" on the "Build options" tab in CPU bean and then modify
|
||||
** this file if needed.
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
NAMES
|
||||
|
||||
END
|
||||
|
||||
SECTIONS
|
||||
/* List of all sections specified on the "Build options" tab */
|
||||
RAM = READ_WRITE 0x00001000 TO 0x00003FFF;
|
||||
ROM_C000 = READ_ONLY 0x0000C000 TO 0x0000C511;
|
||||
ROM_4000 = READ_ONLY 0x00004000 TO 0x00004255;
|
||||
ROM_PAGE30 = READ_ONLY 0x00308000 TO 0x00308255;
|
||||
ROM_PAGE31 = READ_ONLY 0x00318000 TO 0x00318255;
|
||||
ROM_PAGE32 = READ_ONLY 0x00328000 TO 0x00328255;
|
||||
ROM_PAGE33 = READ_ONLY 0x00338000 TO 0x00338255;
|
||||
ROM_PAGE34 = READ_ONLY 0x00348000 TO 0x00348255;
|
||||
ROM_PAGE35 = READ_ONLY 0x00358000 TO 0x00358255;
|
||||
ROM_PAGE36 = READ_ONLY 0x00368000 TO 0x00368255;
|
||||
ROM_PAGE37 = READ_ONLY 0x00378000 TO 0x00378255;
|
||||
ROM_PAGE38 = READ_ONLY 0x00388000 TO 0x00388255;
|
||||
ROM_PAGE39 = READ_ONLY 0x00398000 TO 0x00398255;
|
||||
ROM_PAGE3A = READ_ONLY 0x003A8000 TO 0x003A8255;
|
||||
ROM_PAGE3B = READ_ONLY 0x003B8000 TO 0x003B8255;
|
||||
ROM_PAGE3C = READ_ONLY 0x003C8000 TO 0x003C8255;
|
||||
ROM_PAGE3D = READ_ONLY 0x003D8000 TO 0x003D8255;
|
||||
END
|
||||
|
||||
PLACEMENT
|
||||
DEFAULT_RAM INTO RAM;
|
||||
DEFAULT_ROM INTO ROM_PAGE30, ROM_PAGE31, ROM_PAGE32, ROM_PAGE33, ROM_PAGE34, ROM_PAGE35, ROM_PAGE36,
|
||||
ROM_PAGE37, ROM_PAGE38, ROM_PAGE39, ROM_PAGE3A, ROM_PAGE3B, ROM_PAGE3C, ROM_PAGE3D;
|
||||
_PRESTART, STARTUP,
|
||||
ROM_VAR, STRINGS,
|
||||
NON_BANKED, COPY INTO ROM_C000, ROM_4000;
|
||||
END
|
||||
|
||||
INIT _EntryPoint /* The entry point of the application. This function is generated into the CPU module. */
|
||||
|
||||
STACKSIZE 0x0080 /* Size of the system stack. Value can be changed on the "Build options" tab */
|
||||
|
||||
393
20080212/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.C
Normal file
393
20080212/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.C
Normal file
|
|
@ -0,0 +1,393 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : TickTimer.C
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : TimerInt
|
||||
** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.283
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 18/06/2005, 16:21
|
||||
** Abstract :
|
||||
** This bean "TimerInt" implements a periodic interrupt.
|
||||
** When the bean and its events are enabled, the "OnInterrupt"
|
||||
** event is called periodically with the period that you specify.
|
||||
** TimerInt supports also changing the period in runtime.
|
||||
** The source of periodic interrupt can be timer compare or reload
|
||||
** register or timer-overflow interrupt (of free running counter).
|
||||
** Settings :
|
||||
** Timer name : ECT (16-bit)
|
||||
** Compare name : TC0
|
||||
** Counter shared : No
|
||||
**
|
||||
** High-speed CPU mode
|
||||
** Prescaler : divide-by-8
|
||||
** Clock : 3124000 Hz
|
||||
** Initial period/frequency
|
||||
** Xtal ticks : 16000
|
||||
** microseconds : 1000
|
||||
** milliseconds : 1
|
||||
** seconds (real) : 0.0010000
|
||||
** Hz : 1000
|
||||
** kHz : 1
|
||||
**
|
||||
** Runtime setting : period/frequency interval (continual setting)
|
||||
** ticks : 16000 to 320000 ticks
|
||||
** microseconds : 1000 to 20000 microseconds
|
||||
** milliseconds : 1 to 20 milliseconds
|
||||
** seconds (real) : 0.0010000 to 0.0200000 seconds
|
||||
** Hz : 50 to 1000 Hz
|
||||
**
|
||||
** Initialization:
|
||||
** Timer : Enabled
|
||||
** Events : Enabled
|
||||
**
|
||||
** Timer registers
|
||||
** Counter : TCNT [68]
|
||||
** Mode : TIOS [64]
|
||||
** Run : TSCR1 [70]
|
||||
** Prescaler : TSCR2 [77]
|
||||
**
|
||||
** Compare registers
|
||||
** Compare : TC0 [80]
|
||||
**
|
||||
** Flip-flop registers
|
||||
** Mode : TCTL2 [73]
|
||||
** Contents :
|
||||
** Enable - byte TickTimer_Enable(void);
|
||||
** SetPeriodTicks16 - byte TickTimer_SetPeriodTicks16(word Ticks);
|
||||
** SetPeriodTicks32 - byte TickTimer_SetPeriodTicks32(dword Ticks);
|
||||
** SetPeriodUS - byte TickTimer_SetPeriodUS(word Time);
|
||||
** SetPeriodMS - byte TickTimer_SetPeriodMS(word Time);
|
||||
** SetFreqHz - byte TickTimer_SetFreqHz(word Freq);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
|
||||
/* MODULE TickTimer. */
|
||||
|
||||
#include "Events.h"
|
||||
#include "TickTimer.h"
|
||||
|
||||
/* Definition of DATA and CODE segments for this bean. User can specify where
|
||||
these segments will be located on "Build options" tab of the selected CPU bean. */
|
||||
#pragma DATA_SEG TickTimer_DATA /* Data section for this module. */
|
||||
#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */
|
||||
|
||||
static word CmpHighVal; /* Compare register value for high speed CPU mode */
|
||||
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : SetCV (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
static void SetCV(word Val)
|
||||
{
|
||||
if (Val == 0) /* If the given value is zero */
|
||||
Val = 65535; /* then change it to the maximal one */
|
||||
TC0 = Val; /* Store given value to the compare register */
|
||||
TC7 = Val; /* Store given value to the modulo register */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : SetPV (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
static void SetPV(byte Val)
|
||||
{
|
||||
TSCR2_PR = Val; /* Store given value to the prescaler */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : HWEnDi (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
static void HWEnDi(void)
|
||||
{
|
||||
TFLG1 = 1; /* Reset interrupt request flag */
|
||||
TIE_C0I = 1; /* Enable interrupt */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_Enable (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** Enable the bean - it starts the timer. Events may be
|
||||
** generated ("DisableEvent"/"EnableEvent").
|
||||
** Parameters : None
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ===================================================================
|
||||
*/
|
||||
byte TickTimer_Enable(void)
|
||||
{
|
||||
HWEnDi(); /* Enable the device */
|
||||
return ERR_OK; /* OK */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_SetPeriodTicks16 (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method sets the new period of the generated events.
|
||||
** The period is expressed in Xtal ticks as a 16-bit unsigned
|
||||
** integer number.
|
||||
** This method is available only if runtime setting type
|
||||
** 'from interval' is selected in the Timing dialog box in
|
||||
** Runtime setting area.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Ticks - Period to set [in Xtal ticks]
|
||||
** (16000 to 65535 ticks)
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ERR_MATH - Overflow during evaluation
|
||||
** ERR_RANGE - Parameter out of range
|
||||
** ===================================================================
|
||||
*/
|
||||
byte TickTimer_SetPeriodTicks16(word Ticks)
|
||||
{
|
||||
dlong rtval; /* Result of two 32-bit numbers multiplication */
|
||||
word rtword; /* Result of 64-bit number division */
|
||||
|
||||
if (Ticks < 16000) /* Is the given value out of range? */
|
||||
return ERR_RANGE; /* If yes then error */
|
||||
PE_Timer_LngMul((dword)Ticks,838592365,&rtval); /* Multiply given value and high speed CPU mode coefficient */
|
||||
if (PE_Timer_LngHi4(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */
|
||||
rtword = 65535; /* If yes then use maximal possible value */
|
||||
CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */
|
||||
SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */
|
||||
return ERR_OK; /* OK */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_SetPeriodTicks32 (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method sets the new period of the generated events.
|
||||
** The period is expressed in Xtal ticks as a 32-bit unsigned
|
||||
** integer number.
|
||||
** This method is available only if runtime setting type
|
||||
** 'from interval' is selected in the Timing dialog box in
|
||||
** Runtime setting area.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Ticks - Period to set [in Xtal ticks]
|
||||
** (16000 to 320000 ticks)
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ERR_MATH - Overflow during evaluation
|
||||
** ERR_RANGE - Parameter out of range
|
||||
** ===================================================================
|
||||
*/
|
||||
byte TickTimer_SetPeriodTicks32(dword Ticks)
|
||||
{
|
||||
dlong rtval; /* Result of two 32-bit numbers multiplication */
|
||||
word rtword; /* Result of 64-bit number division */
|
||||
|
||||
if ((Ticks > 320000) || (Ticks < 16000)) /* Is the given value out of range? */
|
||||
return ERR_RANGE; /* Range error */
|
||||
PE_Timer_LngMul(Ticks,838592365,&rtval); /* Multiply given value and high speed CPU mode coefficient */
|
||||
if (PE_Timer_LngHi4(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */
|
||||
rtword = 65535; /* If yes then use maximal possible value */
|
||||
CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */
|
||||
SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */
|
||||
return ERR_OK; /* OK */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_SetPeriodUS (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method sets the new period of the generated events.
|
||||
** The period is expressed in microseconds as a 16-bit
|
||||
** unsigned integer number.
|
||||
** This method is available only if runtime setting type
|
||||
** 'from interval' is selected in the Timing dialog box in
|
||||
** Runtime setting area.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Time - Period to set [in microseconds]
|
||||
** (1000 to 20000 microseconds)
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ERR_MATH - Overflow during evaluation
|
||||
** ERR_RANGE - Parameter out of range
|
||||
** ===================================================================
|
||||
*/
|
||||
byte TickTimer_SetPeriodUS(word Time)
|
||||
{
|
||||
dlong rtval; /* Result of two 32-bit numbers multiplication */
|
||||
word rtword; /* Result of 64-bit number division */
|
||||
|
||||
if ((Time > 20000) || (Time < 1000)) /* Is the given value out of range? */
|
||||
return ERR_RANGE; /* If yes then error */
|
||||
PE_Timer_LngMul((dword)Time,52412023,&rtval); /* Multiply given value and high speed CPU mode coefficient */
|
||||
if (PE_Timer_LngHi3(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */
|
||||
rtword = 65535; /* If yes then use maximal possible value */
|
||||
CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */
|
||||
SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */
|
||||
return ERR_OK; /* OK */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_SetPeriodMS (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method sets the new period of the generated events.
|
||||
** The period is expressed in miliseconds as a 16-bit
|
||||
** unsigned integer number.
|
||||
** This method is available only if runtime setting type
|
||||
** 'from interval' is selected in the Timing dialog box in
|
||||
** Runtime setting area.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Time - Period to set [in miliseconds]
|
||||
** (1 to 20 milliseconds)
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ERR_MATH - Overflow during evaluation
|
||||
** ERR_RANGE - Parameter out of range
|
||||
** ===================================================================
|
||||
*/
|
||||
byte TickTimer_SetPeriodMS(word Time)
|
||||
{
|
||||
dlong rtval; /* Result of two 32-bit numbers multiplication */
|
||||
word rtword; /* Result of 64-bit number division */
|
||||
|
||||
if ((Time > 20) || (Time < 1)) /* Is the given value out of range? */
|
||||
return ERR_RANGE; /* If yes then error */
|
||||
PE_Timer_LngMul((dword)Time,204734464,&rtval); /* Multiply given value and high speed CPU mode coefficient */
|
||||
if (PE_Timer_LngHi2(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */
|
||||
rtword = 65535; /* If yes then use maximal possible value */
|
||||
CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */
|
||||
SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */
|
||||
return ERR_OK; /* OK */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_SetFreqHz (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method sets the new frequency of the generated
|
||||
** events. The frequency is expressed in Hz as a 16-bit
|
||||
** unsigned integer number.
|
||||
** This method is available only if runtime setting type
|
||||
** 'from interval' is selected in the Timing dialog box in
|
||||
** Runtime setting area.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Freq - Frequency to set [in Hz]
|
||||
** (50 to 1000 Hz)
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ERR_MATH - Overflow during evaluation
|
||||
** ERR_RANGE - Parameter out of range
|
||||
** ===================================================================
|
||||
*/
|
||||
byte TickTimer_SetFreqHz(word Freq)
|
||||
{
|
||||
dlong rtval; /* Result of two 32-bit numbers division */
|
||||
word rtword; /* Result of 64-bit number division */
|
||||
|
||||
if ((Freq > 1000) || (Freq < 50)) /* Is the given value out of range? */
|
||||
return ERR_RANGE; /* If yes then error */
|
||||
rtval[1] = 799744000 / (dword)Freq; /* Divide high speed CPU mode coefficient by the given value */
|
||||
rtval[0] = 0; /* Convert result to the type dlong */
|
||||
if (PE_Timer_LngHi1(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */
|
||||
rtword = 65535; /* If yes then use maximal possible value */
|
||||
CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */
|
||||
SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */
|
||||
return ERR_OK; /* OK */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_Init (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
void TickTimer_Init(void)
|
||||
{
|
||||
CmpHighVal = 3124; /* Compare register value for high speed CPU mode */
|
||||
SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */
|
||||
SetPV(3); /* Set prescaler register according to the selected high speed CPU mode */
|
||||
HWEnDi(); /* Enable/disable device according to status flags */
|
||||
}
|
||||
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_Interrupt (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
|
||||
__interrupt void TickTimer_Interrupt(void)
|
||||
{
|
||||
TFLG1 = 1; /* Reset interrupt request flag */
|
||||
TickTimer_OnInterrupt(); /* Invoke user event */
|
||||
}
|
||||
|
||||
#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */
|
||||
|
||||
/* END TickTimer. */
|
||||
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
276
20080212/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.H
Normal file
276
20080212/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.H
Normal file
|
|
@ -0,0 +1,276 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : TickTimer.H
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : TimerInt
|
||||
** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.283
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 18/06/2005, 16:21
|
||||
** Abstract :
|
||||
** This bean "TimerInt" implements a periodic interrupt.
|
||||
** When the bean and its events are enabled, the "OnInterrupt"
|
||||
** event is called periodically with the period that you specify.
|
||||
** TimerInt supports also changing the period in runtime.
|
||||
** The source of periodic interrupt can be timer compare or reload
|
||||
** register or timer-overflow interrupt (of free running counter).
|
||||
** Settings :
|
||||
** Timer name : ECT (16-bit)
|
||||
** Compare name : TC0
|
||||
** Counter shared : No
|
||||
**
|
||||
** High-speed CPU mode
|
||||
** Prescaler : divide-by-8
|
||||
** Clock : 3124000 Hz
|
||||
** Initial period/frequency
|
||||
** Xtal ticks : 16000
|
||||
** microseconds : 1000
|
||||
** milliseconds : 1
|
||||
** seconds (real) : 0.0010000
|
||||
** Hz : 1000
|
||||
** kHz : 1
|
||||
**
|
||||
** Runtime setting : period/frequency interval (continual setting)
|
||||
** ticks : 16000 to 320000 ticks
|
||||
** microseconds : 1000 to 20000 microseconds
|
||||
** milliseconds : 1 to 20 milliseconds
|
||||
** seconds (real) : 0.0010000 to 0.0200000 seconds
|
||||
** Hz : 50 to 1000 Hz
|
||||
**
|
||||
** Initialization:
|
||||
** Timer : Enabled
|
||||
** Events : Enabled
|
||||
**
|
||||
** Timer registers
|
||||
** Counter : TCNT [68]
|
||||
** Mode : TIOS [64]
|
||||
** Run : TSCR1 [70]
|
||||
** Prescaler : TSCR2 [77]
|
||||
**
|
||||
** Compare registers
|
||||
** Compare : TC0 [80]
|
||||
**
|
||||
** Flip-flop registers
|
||||
** Mode : TCTL2 [73]
|
||||
** Contents :
|
||||
** Enable - byte TickTimer_Enable(void);
|
||||
** SetPeriodTicks16 - byte TickTimer_SetPeriodTicks16(word Ticks);
|
||||
** SetPeriodTicks32 - byte TickTimer_SetPeriodTicks32(dword Ticks);
|
||||
** SetPeriodUS - byte TickTimer_SetPeriodUS(word Time);
|
||||
** SetPeriodMS - byte TickTimer_SetPeriodMS(word Time);
|
||||
** SetFreqHz - byte TickTimer_SetFreqHz(word Freq);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
#ifndef __TickTimer
|
||||
#define __TickTimer
|
||||
|
||||
/* MODULE TickTimer. */
|
||||
|
||||
#include "Cpu.h"
|
||||
|
||||
#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */
|
||||
|
||||
#define TickTimer_SPT16Min 16000 /* Lower bound of interval for method SetPeriodTicks16 */
|
||||
#define TickTimer_SPT16Max 65535 /* Upper bound of interval for method SetPeriodTicks16 */
|
||||
#define TickTimer_SPT32Min 16000 /* Lower bound of interval for method SetPeriodTicks32 */
|
||||
#define TickTimer_SPT32Max 320000 /* Upper bound of interval for method SetPeriodTicks32 */
|
||||
#define TickTimer_SPUSMin 1000 /* Lower bound of interval for method SetPeriodUS */
|
||||
#define TickTimer_SPUSMax 20000 /* Upper bound of interval for method SetPeriodUS */
|
||||
#define TickTimer_SPMSMin 1 /* Lower bound of interval for method SetPeriodMS */
|
||||
#define TickTimer_SPMSMax 20 /* Upper bound of interval for method SetPeriodMS */
|
||||
#define TickTimer_SFHzMin 50 /* Lower bound of interval for method SetFreqHz */
|
||||
#define TickTimer_SFHzMax 1000 /* Upper bound of interval for method SetFreqHz */
|
||||
|
||||
|
||||
byte TickTimer_Enable(void);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_Enable (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** Enable the bean - it starts the timer. Events may be
|
||||
** generated ("DisableEvent"/"EnableEvent").
|
||||
** Parameters : None
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
byte TickTimer_SetPeriodTicks16(word Ticks);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_SetPeriodTicks16 (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method sets the new period of the generated events.
|
||||
** The period is expressed in Xtal ticks as a 16-bit unsigned
|
||||
** integer number.
|
||||
** This method is available only if runtime setting type
|
||||
** 'from interval' is selected in the Timing dialog box in
|
||||
** Runtime setting area.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Ticks - Period to set [in Xtal ticks]
|
||||
** (16000 to 65535 ticks)
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ERR_MATH - Overflow during evaluation
|
||||
** ERR_RANGE - Parameter out of range
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
byte TickTimer_SetPeriodTicks32(dword Ticks);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_SetPeriodTicks32 (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method sets the new period of the generated events.
|
||||
** The period is expressed in Xtal ticks as a 32-bit unsigned
|
||||
** integer number.
|
||||
** This method is available only if runtime setting type
|
||||
** 'from interval' is selected in the Timing dialog box in
|
||||
** Runtime setting area.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Ticks - Period to set [in Xtal ticks]
|
||||
** (16000 to 320000 ticks)
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ERR_MATH - Overflow during evaluation
|
||||
** ERR_RANGE - Parameter out of range
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
byte TickTimer_SetPeriodUS(word Time);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_SetPeriodUS (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method sets the new period of the generated events.
|
||||
** The period is expressed in microseconds as a 16-bit
|
||||
** unsigned integer number.
|
||||
** This method is available only if runtime setting type
|
||||
** 'from interval' is selected in the Timing dialog box in
|
||||
** Runtime setting area.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Time - Period to set [in microseconds]
|
||||
** (1000 to 20000 microseconds)
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ERR_MATH - Overflow during evaluation
|
||||
** ERR_RANGE - Parameter out of range
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
byte TickTimer_SetPeriodMS(word Time);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_SetPeriodMS (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method sets the new period of the generated events.
|
||||
** The period is expressed in miliseconds as a 16-bit
|
||||
** unsigned integer number.
|
||||
** This method is available only if runtime setting type
|
||||
** 'from interval' is selected in the Timing dialog box in
|
||||
** Runtime setting area.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Time - Period to set [in miliseconds]
|
||||
** (1 to 20 milliseconds)
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ERR_MATH - Overflow during evaluation
|
||||
** ERR_RANGE - Parameter out of range
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
byte TickTimer_SetFreqHz(word Freq);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_SetFreqHz (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method sets the new frequency of the generated
|
||||
** events. The frequency is expressed in Hz as a 16-bit
|
||||
** unsigned integer number.
|
||||
** This method is available only if runtime setting type
|
||||
** 'from interval' is selected in the Timing dialog box in
|
||||
** Runtime setting area.
|
||||
** Parameters :
|
||||
** NAME - DESCRIPTION
|
||||
** Freq - Frequency to set [in Hz]
|
||||
** (50 to 1000 Hz)
|
||||
** Returns :
|
||||
** --- - Error code, possible codes:
|
||||
** ERR_OK - OK
|
||||
** ERR_SPEED - This device does not work in
|
||||
** the active speed mode
|
||||
** ERR_MATH - Overflow during evaluation
|
||||
** ERR_RANGE - Parameter out of range
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
|
||||
__interrupt void TickTimer_Interrupt(void);
|
||||
#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_Interrupt (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
void TickTimer_Init(void);
|
||||
/*
|
||||
** ===================================================================
|
||||
** Method : TickTimer_Init (bean TimerInt)
|
||||
**
|
||||
** Description :
|
||||
** This method is internal. It is used by Processor Expert
|
||||
** only.
|
||||
** ===================================================================
|
||||
*/
|
||||
|
||||
#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */
|
||||
|
||||
/* END TickTimer. */
|
||||
|
||||
#endif /* ifndef __TickTimer */
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
112
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Vectors.c
Normal file
112
20080212/Demo/HCS12_CodeWarrior_banked/CODE/Vectors.c
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/** ###################################################################
|
||||
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
||||
** Filename : Cpu.C
|
||||
** Project : RTOSDemo
|
||||
** Processor : MC9S12DP256BCPV
|
||||
** Beantype : MC9S12DP256_112
|
||||
** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283
|
||||
** Compiler : Metrowerks HC12 C Compiler
|
||||
** Date/Time : 16/06/2005, 19:18
|
||||
** Abstract :
|
||||
** This bean "MC9S12DP256_112" implements properties, methods,
|
||||
** and events of the CPU.
|
||||
** Settings :
|
||||
**
|
||||
** Contents :
|
||||
** EnableInt - void Cpu_EnableInt(void);
|
||||
** DisableInt - void Cpu_DisableInt(void);
|
||||
**
|
||||
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
||||
** UNIS, spol. s r.o.
|
||||
** Jundrovska 33
|
||||
** 624 00 Brno
|
||||
** Czech Republic
|
||||
** http : www.processorexpert.com
|
||||
** mail : info@processorexpert.com
|
||||
** ###################################################################*/
|
||||
|
||||
|
||||
#include "Cpu.h"
|
||||
#include "TickTimer.h"
|
||||
#include "Byte1.h"
|
||||
|
||||
extern void near _EntryPoint(void); /* Startup routine */
|
||||
extern void near vPortTickInterrupt( void );
|
||||
extern void near vPortYield( void );
|
||||
extern void near vCOM0_ISR( void );
|
||||
|
||||
typedef void (*near tIsrFunc)(void);
|
||||
const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */
|
||||
Cpu_Interrupt, /* 0 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 1 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 2 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 3 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 4 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 5 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 6 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 7 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 8 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 9 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 10 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 11 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 12 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 13 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 14 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 15 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 16 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 17 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 18 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 19 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 20 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 21 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 22 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 23 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 24 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 25 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 26 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 27 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 28 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 29 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 30 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 31 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 32 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 33 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 34 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 35 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 36 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 37 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 38 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 39 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 40 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 41 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 42 Default (unused) interrupt */
|
||||
vCOM0_ISR, /* Defined in Demo/serial/serial.c */
|
||||
Cpu_Interrupt, /* 44 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 45 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 46 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 47 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 48 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 49 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 50 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 51 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 52 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 53 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 54 Default (unused) interrupt */
|
||||
vPortTickInterrupt, /* The RTOS tick. */
|
||||
Cpu_Interrupt, /* 56 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 57 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 58 Default (unused) interrupt */
|
||||
vPortYield, /* RTOS yield software interrupt. */
|
||||
Cpu_Interrupt, /* 60 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 61 Default (unused) interrupt */
|
||||
Cpu_Interrupt, /* 62 Default (unused) interrupt */
|
||||
_EntryPoint /* Reset vector */
|
||||
};
|
||||
/*
|
||||
** ###################################################################
|
||||
**
|
||||
** This file was created by UNIS Processor Expert 03.33 for
|
||||
** the Motorola HCS12 series of microcontrollers.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
Loading…
Add table
Add a link
Reference in a new issue