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323
20080212/Demo/Common/Full/BlockQ.c Normal file
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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/**
* Creates six tasks that operate on three queues as follows:
*
* The first two tasks send and receive an incrementing number to/from a queue.
* One task acts as a producer and the other as the consumer. The consumer is a
* higher priority than the producer and is set to block on queue reads. The queue
* only has space for one item - as soon as the producer posts a message on the
* queue the consumer will unblock, pre-empt the producer, and remove the item.
*
* The second two tasks work the other way around. Again the queue used only has
* enough space for one item. This time the consumer has a lower priority than the
* producer. The producer will try to post on the queue blocking when the queue is
* full. When the consumer wakes it will remove the item from the queue, causing
* the producer to unblock, pre-empt the consumer, and immediately re-fill the
* queue.
*
* The last two tasks use the same queue producer and consumer functions. This time the queue has
* enough space for lots of items and the tasks operate at the same priority. The
* producer will execute, placing items into the queue. The consumer will start
* executing when either the queue becomes full (causing the producer to block) or
* a context switch occurs (tasks of the same priority will time slice).
*
* \page BlockQC blockQ.c
* \ingroup DemoFiles
* <HR>
*/
/*
Changes from V1.00:
+ Reversed the priority and block times of the second two demo tasks so
they operate as per the description above.
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
Changes from V4.0.2
+ The second set of tasks were created the wrong way around. This has been
corrected.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Demo program include files. */
#include "BlockQ.h"
#include "print.h"
#define blckqSTACK_SIZE ( ( unsigned portSHORT ) configMINIMAL_STACK_SIZE )
#define blckqNUM_TASK_SETS ( 3 )
/* Structure used to pass parameters to the blocking queue tasks. */
typedef struct BLOCKING_QUEUE_PARAMETERS
{
xQueueHandle xQueue; /*< The queue to be used by the task. */
portTickType xBlockTime; /*< The block time to use on queue reads/writes. */
volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */
} xBlockingQueueParameters;
/* Task function that creates an incrementing number and posts it on a queue. */
static void vBlockingQueueProducer( void *pvParameters );
/* Task function that removes the incrementing number from a queue and checks that
it is the expected number. */
static void vBlockingQueueConsumer( void *pvParameters );
/* Variables which are incremented each time an item is removed from a queue, and
found to be the expected value.
These are used to check that the tasks are still running. */
static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 };
/* Variable which are incremented each time an item is posted on a queue. These
are used to check that the tasks are still running. */
static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 };
/*-----------------------------------------------------------*/
void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority )
{
xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2;
xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4;
xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6;
const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5;
const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS;
const portTickType xDontBlock = ( portTickType ) 0;
/* Create the first two tasks as described at the top of the file. */
/* First create the structure used to pass parameters to the consumer tasks. */
pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
/* Create the queue used by the first two tasks to pass the incrementing number.
Pass a pointer to the queue in the parameter structure. */
pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
/* The consumer is created first so gets a block time as described above. */
pxQueueParameters1->xBlockTime = xBlockTime;
/* Pass in the variable that this task is going to increment so we can check it
is still running. */
pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );
/* Create the structure used to pass parameters to the producer task. */
pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
/* Pass the queue to this task also, using the parameter structure. */
pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;
/* The producer is not going to block - as soon as it posts the consumer will
wake and remove the item so the producer should always have room to post. */
pxQueueParameters2->xBlockTime = xDontBlock;
/* Pass in the variable that this task is going to increment so we can check
it is still running. */
pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );
/* Note the producer has a lower priority than the consumer when the tasks are
spawned. */
xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );
xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );
/* Create the second two tasks as described at the top of the file. This uses
the same mechanism but reverses the task priorities. */
pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
pxQueueParameters3->xBlockTime = xDontBlock;
pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );
pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;
pxQueueParameters4->xBlockTime = xBlockTime;
pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );
xTaskCreate( vBlockingQueueProducer, "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );
xTaskCreate( vBlockingQueueConsumer, "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );
/* Create the last two tasks as described above. The mechanism is again just
the same. This time both parameter structures are given a block time. */
pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
pxQueueParameters5->xBlockTime = xBlockTime;
pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );
pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;
pxQueueParameters6->xBlockTime = xBlockTime;
pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] );
xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );
xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );
}
/*-----------------------------------------------------------*/
static void vBlockingQueueProducer( void *pvParameters )
{
unsigned portSHORT usValue = 0;
xBlockingQueueParameters *pxQueueParameters;
const portCHAR * const pcTaskStartMsg = "Blocking queue producer started.\r\n";
const portCHAR * const pcTaskErrorMsg = "Could not post on blocking queue\r\n";
portSHORT sErrorEverOccurred = pdFALSE;
pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
for( ;; )
{
if( xQueueSendToBack( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )
{
vPrintDisplayMessage( &pcTaskErrorMsg );
sErrorEverOccurred = pdTRUE;
}
else
{
/* We have successfully posted a message, so increment the variable
used to check we are still running. */
if( sErrorEverOccurred == pdFALSE )
{
( *pxQueueParameters->psCheckVariable )++;
}
/* Increment the variable we are going to post next time round. The
consumer will expect the numbers to follow in numerical order. */
++usValue;
}
}
}
/*-----------------------------------------------------------*/
static void vBlockingQueueConsumer( void *pvParameters )
{
unsigned portSHORT usData, usExpectedValue = 0;
xBlockingQueueParameters *pxQueueParameters;
const portCHAR * const pcTaskStartMsg = "Blocking queue consumer started.\r\n";
const portCHAR * const pcTaskErrorMsg = "Incorrect value received on blocking queue.\r\n";
portSHORT sErrorEverOccurred = pdFALSE;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
for( ;; )
{
if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )
{
if( usData != usExpectedValue )
{
vPrintDisplayMessage( &pcTaskErrorMsg );
/* Catch-up. */
usExpectedValue = usData;
sErrorEverOccurred = pdTRUE;
}
else
{
/* We have successfully received a message, so increment the
variable used to check we are still running. */
if( sErrorEverOccurred == pdFALSE )
{
( *pxQueueParameters->psCheckVariable )++;
}
/* Increment the value we expect to remove from the queue next time
round. */
++usExpectedValue;
}
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreBlockingQueuesStillRunning( void )
{
static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 };
static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 };
portBASE_TYPE xReturn = pdPASS, xTasks;
/* Not too worried about mutual exclusion on these variables as they are 16
bits and we are only reading them. We also only care to see if they have
changed or not.
Loop through each check variable and return pdFALSE if any are found not
to have changed since the last call. */
for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )
{
if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] )
{
xReturn = pdFALSE;
}
sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];
if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] )
{
xReturn = pdFALSE;
}
sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];
}
return xReturn;
}

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20080212/Demo/Common/Full/PollQ.c Normal file
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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/**
* This is a very simple queue test. See the BlockQ. c documentation for a more
* comprehensive version.
*
* Creates two tasks that communicate over a single queue. One task acts as a
* producer, the other a consumer.
*
* The producer loops for three iteration, posting an incrementing number onto the
* queue each cycle. It then delays for a fixed period before doing exactly the
* same again.
*
* The consumer loops emptying the queue. Each item removed from the queue is
* checked to ensure it contains the expected value. When the queue is empty it
* blocks for a fixed period, then does the same again.
*
* All queue access is performed without blocking. The consumer completely empties
* the queue each time it runs so the producer should never find the queue full.
*
* An error is flagged if the consumer obtains an unexpected value or the producer
* find the queue is full.
*
* \page PollQC pollQ.c
* \ingroup DemoFiles
* <HR>
*/
/*
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "print.h"
/* Demo program include files. */
#include "PollQ.h"
#define pollqSTACK_SIZE ( ( unsigned portSHORT ) configMINIMAL_STACK_SIZE )
/* The task that posts the incrementing number onto the queue. */
static void vPolledQueueProducer( void *pvParameters );
/* The task that empties the queue. */
static void vPolledQueueConsumer( void *pvParameters );
/* Variables that are used to check that the tasks are still running with no errors. */
static volatile portSHORT sPollingConsumerCount = 0, sPollingProducerCount = 0;
/*-----------------------------------------------------------*/
void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority )
{
static xQueueHandle xPolledQueue;
const unsigned portBASE_TYPE uxQueueSize = 10;
/* Create the queue used by the producer and consumer. */
xPolledQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
/* Spawn the producer and consumer. */
xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL );
xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL );
}
/*-----------------------------------------------------------*/
static void vPolledQueueProducer( void *pvParameters )
{
unsigned portSHORT usValue = 0, usLoop;
xQueueHandle *pxQueue;
const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS;
const unsigned portSHORT usNumToProduce = 3;
const portCHAR * const pcTaskStartMsg = "Polled queue producer started.\r\n";
const portCHAR * const pcTaskErrorMsg = "Could not post on polled queue.\r\n";
portSHORT sError = pdFALSE;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
/* The queue being used is passed in as the parameter. */
pxQueue = ( xQueueHandle * ) pvParameters;
for( ;; )
{
for( usLoop = 0; usLoop < usNumToProduce; ++usLoop )
{
/* Send an incrementing number on the queue without blocking. */
if( xQueueSendToBack( *pxQueue, ( void * ) &usValue, ( portTickType ) 0 ) != pdPASS )
{
/* We should never find the queue full - this is an error. */
vPrintDisplayMessage( &pcTaskErrorMsg );
sError = pdTRUE;
}
else
{
if( sError == pdFALSE )
{
/* If an error has ever been recorded we stop incrementing the
check variable. */
++sPollingProducerCount;
}
/* Update the value we are going to post next time around. */
++usValue;
}
}
/* Wait before we start posting again to ensure the consumer runs and
empties the queue. */
vTaskDelay( xDelay );
}
}
/*-----------------------------------------------------------*/
static void vPolledQueueConsumer( void *pvParameters )
{
unsigned portSHORT usData, usExpectedValue = 0;
xQueueHandle *pxQueue;
const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS;
const portCHAR * const pcTaskStartMsg = "Polled queue consumer started.\r\n";
const portCHAR * const pcTaskErrorMsg = "Incorrect value received on polled queue.\r\n";
portSHORT sError = pdFALSE;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
/* The queue being used is passed in as the parameter. */
pxQueue = ( xQueueHandle * ) pvParameters;
for( ;; )
{
/* Loop until the queue is empty. */
while( uxQueueMessagesWaiting( *pxQueue ) )
{
if( xQueueReceive( *pxQueue, &usData, ( portTickType ) 0 ) == pdPASS )
{
if( usData != usExpectedValue )
{
/* This is not what we expected to receive so an error has
occurred. */
vPrintDisplayMessage( &pcTaskErrorMsg );
sError = pdTRUE;
/* Catch-up to the value we received so our next expected value
should again be correct. */
usExpectedValue = usData;
}
else
{
if( sError == pdFALSE )
{
/* Only increment the check variable if no errors have
occurred. */
++sPollingConsumerCount;
}
}
++usExpectedValue;
}
}
/* Now the queue is empty we block, allowing the producer to place more
items in the queue. */
vTaskDelay( xDelay );
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running with no errors. */
portBASE_TYPE xArePollingQueuesStillRunning( void )
{
static portSHORT sLastPollingConsumerCount = 0, sLastPollingProducerCount = 0;
portBASE_TYPE xReturn;
if( ( sLastPollingConsumerCount == sPollingConsumerCount ) ||
( sLastPollingProducerCount == sPollingProducerCount )
)
{
xReturn = pdFALSE;
}
else
{
xReturn = pdTRUE;
}
sLastPollingConsumerCount = sPollingConsumerCount;
sLastPollingProducerCount = sPollingProducerCount;
return xReturn;
}

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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/**
* Creates two tasks that operate on an interrupt driven serial port. A loopback
* connector should be used so that everything that is transmitted is also received.
* The serial port does not use any flow control. On a standard 9way 'D' connector
* pins two and three should be connected together.
*
* The first task repeatedly sends a string to a queue, character at a time. The
* serial port interrupt will empty the queue and transmit the characters. The
* task blocks for a pseudo random period before resending the string.
*
* The second task blocks on a queue waiting for a character to be received.
* Characters received by the serial port interrupt routine are posted onto the
* queue - unblocking the task making it ready to execute. If this is then the
* highest priority task ready to run it will run immediately - with a context
* switch occurring at the end of the interrupt service routine. The task
* receiving characters is spawned with a higher priority than the task
* transmitting the characters.
*
* With the loop back connector in place, one task will transmit a string and the
* other will immediately receive it. The receiving task knows the string it
* expects to receive so can detect an error.
*
* This also creates a third task. This is used to test semaphore usage from an
* ISR and does nothing interesting.
*
* \page ComTestC comtest.c
* \ingroup DemoFiles
* <HR>
*/
/*
Changes from V1.00:
+ The priority of the Rx task has been lowered. Received characters are
now processed (read from the queue) at the idle priority, allowing low
priority tasks to run evenly at times of a high communications overhead.
Changes from V1.01:
+ The Tx task now waits a pseudo random time between transissions.
Previously a fixed period was used but this was not such a good test as
interrupts fired at regular intervals.
Changes From V1.2.0:
+ Use vSerialPutString() instead of single character puts.
+ Only stop the check variable incrementing after two consecutive errors.
Changed from V1.2.5
+ Made the Rx task 2 priorities higher than the Tx task. Previously it was
only 1. This is done to tie in better with the other demo application
tasks.
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
+ Slight modification to task priorities.
*/
/* Scheduler include files. */
#include <stdlib.h>
#include <string.h>
#include "FreeRTOS.h"
#include "task.h"
/* Demo program include files. */
#include "serial.h"
#include "comtest.h"
#include "print.h"
/* The Tx task will transmit the sequence of characters at a pseudo random
interval. This is the maximum and minimum block time between sends. */
#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x15e )
#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0xc8 )
#define comMAX_CONSECUTIVE_ERRORS ( 2 )
#define comSTACK_SIZE ( ( unsigned portSHORT ) 256 )
#define comRX_RELATIVE_PRIORITY ( 1 )
/* Handle to the com port used by both tasks. */
static xComPortHandle xPort;
/* The transmit function as described at the top of the file. */
static void vComTxTask( void *pvParameters );
/* The receive function as described at the top of the file. */
static void vComRxTask( void *pvParameters );
/* The semaphore test function as described at the top of the file. */
static void vSemTestTask( void * pvParameters );
/* The string that is repeatedly transmitted. */
const portCHAR * const pcMessageToExchange = "Send this message over and over again to check communications interrupts. "
"0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n";
/* Variables that are incremented on each cycle of each task. These are used to
check that both tasks are still executing. */
volatile portSHORT sTxCount = 0, sRxCount = 0, sSemCount = 0;
/* The handle to the semaphore test task. */
static xTaskHandle xSemTestTaskHandle = NULL;
/*-----------------------------------------------------------*/
void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate )
{
const unsigned portBASE_TYPE uxBufferLength = 255;
/* Initialise the com port then spawn both tasks. */
xPort = xSerialPortInit( ePort, eBaudRate, serNO_PARITY, serBITS_8, serSTOP_1, uxBufferLength );
xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority, NULL );
xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority + comRX_RELATIVE_PRIORITY, NULL );
xTaskCreate( vSemTestTask, "ISRSem", comSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xSemTestTaskHandle );
}
/*-----------------------------------------------------------*/
static void vComTxTask( void *pvParameters )
{
const portCHAR * const pcTaskStartMsg = "COM Tx task started.\r\n";
portTickType xTimeToWait;
/* Stop warnings. */
( void ) pvParameters;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
for( ;; )
{
/* Send the string to the serial port. */
vSerialPutString( xPort, pcMessageToExchange, strlen( pcMessageToExchange ) );
/* We have posted all the characters in the string - increment the variable
used to check that this task is still running, then wait before re-sending
the string. */
sTxCount++;
xTimeToWait = xTaskGetTickCount();
/* Make sure we don't wait too long... */
xTimeToWait %= comTX_MAX_BLOCK_TIME;
/* ...but we do want to wait. */
if( xTimeToWait < comTX_MIN_BLOCK_TIME )
{
xTimeToWait = comTX_MIN_BLOCK_TIME;
}
vTaskDelay( xTimeToWait );
}
} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */
/*-----------------------------------------------------------*/
static void vComRxTask( void *pvParameters )
{
const portCHAR * const pcTaskStartMsg = "COM Rx task started.\r\n";
const portCHAR * const pcTaskErrorMsg = "COM read error\r\n";
const portCHAR * const pcTaskRestartMsg = "COM resynced\r\n";
const portCHAR * const pcTaskTimeoutMsg = "COM Rx timed out\r\n";
const portTickType xBlockTime = ( portTickType ) 0xffff / portTICK_RATE_MS;
const portCHAR *pcExpectedChar;
portBASE_TYPE xGotChar;
portCHAR cRxedChar;
portSHORT sResyncRequired, sConsecutiveErrors, sLatchedError;
/* Stop warnings. */
( void ) pvParameters;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
/* The first expected character is the first character in the string. */
pcExpectedChar = pcMessageToExchange;
sResyncRequired = pdFALSE;
sConsecutiveErrors = 0;
sLatchedError = pdFALSE;
for( ;; )
{
/* Receive a message from the com port interrupt routine. If a message is
not yet available the call will block the task. */
xGotChar = xSerialGetChar( xPort, &cRxedChar, xBlockTime );
if( xGotChar == pdTRUE )
{
if( sResyncRequired == pdTRUE )
{
/* We got out of sequence and are waiting for the start of the next
transmission of the string. */
if( cRxedChar == '\n' )
{
/* This is the end of the message so we can start again - with
the first character in the string being the next thing we expect
to receive. */
pcExpectedChar = pcMessageToExchange;
sResyncRequired = pdFALSE;
/* Queue a message for printing to say that we are going to try
again. */
vPrintDisplayMessage( &pcTaskRestartMsg );
/* Stop incrementing the check variable, if consecutive errors occur. */
sConsecutiveErrors++;
if( sConsecutiveErrors >= comMAX_CONSECUTIVE_ERRORS )
{
sLatchedError = pdTRUE;
}
}
}
else
{
/* We have received a character, but is it the expected character? */
if( cRxedChar != *pcExpectedChar )
{
/* This was not the expected character so post a message for
printing to say that an error has occurred. We will then wait
to resynchronise. */
vPrintDisplayMessage( &pcTaskErrorMsg );
sResyncRequired = pdTRUE;
}
else
{
/* This was the expected character so next time we will expect
the next character in the string. Wrap back to the beginning
of the string when the null terminator has been reached. */
pcExpectedChar++;
if( *pcExpectedChar == '\0' )
{
pcExpectedChar = pcMessageToExchange;
/* We have got through the entire string without error. */
sConsecutiveErrors = 0;
}
}
}
/* Increment the count that is used to check that this task is still
running. This is only done if an error has never occurred. */
if( sLatchedError == pdFALSE )
{
sRxCount++;
}
}
else
{
vPrintDisplayMessage( &pcTaskTimeoutMsg );
}
}
} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */
/*-----------------------------------------------------------*/
static void vSemTestTask( void * pvParameters )
{
const portCHAR * const pcTaskStartMsg = "ISR Semaphore test started.\r\n";
portBASE_TYPE xError = pdFALSE;
/* Stop warnings. */
( void ) pvParameters;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
for( ;; )
{
if( xSerialWaitForSemaphore( xPort ) )
{
if( xError == pdFALSE )
{
sSemCount++;
}
}
else
{
xError = pdTRUE;
}
}
} /*lint !e715 !e830 !e818 pvParameters not used but function prototype must be standard for task function. */
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreComTestTasksStillRunning( void )
{
static portSHORT sLastTxCount = 0, sLastRxCount = 0, sLastSemCount = 0;
portBASE_TYPE xReturn;
/* Not too worried about mutual exclusion on these variables as they are 16
bits and we are only reading them. We also only care to see if they have
changed or not. */
if( ( sTxCount == sLastTxCount ) || ( sRxCount == sLastRxCount ) || ( sSemCount == sLastSemCount ) )
{
xReturn = pdFALSE;
}
else
{
xReturn = pdTRUE;
}
sLastTxCount = sTxCount;
sLastRxCount = sRxCount;
sLastSemCount = sSemCount;
return xReturn;
}
/*-----------------------------------------------------------*/
void vComTestUnsuspendTask( void )
{
/* The task that is suspended on the semaphore will be referenced from the
Suspended list as it is blocking indefinitely. This call just checks that
the kernel correctly detects this and does not attempt to unsuspend the
task. */
xTaskResumeFromISR( xSemTestTaskHandle );
}

218
20080212/Demo/Common/Full/death.c Normal file
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@ -0,0 +1,218 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/**
* Create a single persistent task which periodically dynamically creates another
* four tasks. The original task is called the creator task, the four tasks it
* creates are called suicidal tasks.
*
* Two of the created suicidal tasks kill one other suicidal task before killing
* themselves - leaving just the original task remaining.
*
* The creator task must be spawned after all of the other demo application tasks
* as it keeps a check on the number of tasks under the scheduler control. The
* number of tasks it expects to see running should never be greater than the
* number of tasks that were in existence when the creator task was spawned, plus
* one set of four suicidal tasks. If this number is exceeded an error is flagged.
*
* \page DeathC death.c
* \ingroup DemoFiles
* <HR>
*/
/*
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo program include files. */
#include "death.h"
#include "print.h"
#define deathSTACK_SIZE ( ( unsigned portSHORT ) 512 )
/* The task originally created which is responsible for periodically dynamically
creating another four tasks. */
static void vCreateTasks( void *pvParameters );
/* The task function of the dynamically created tasks. */
static void vSuicidalTask( void *pvParameters );
/* A variable which is incremented every time the dynamic tasks are created. This
is used to check that the task is still running. */
static volatile portSHORT sCreationCount = 0;
/* Used to store the number of tasks that were originally running so the creator
task can tell if any of the suicidal tasks have failed to die. */
static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0;
static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 5;
/* Used to store a handle to the tasks that should be killed by a suicidal task,
before it kills itself. */
xTaskHandle xCreatedTask1, xCreatedTask2;
/*-----------------------------------------------------------*/
void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority )
{
unsigned portBASE_TYPE *puxPriority;
/* Create the Creator tasks - passing in as a parameter the priority at which
the suicidal tasks should be created. */
puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) );
*puxPriority = uxPriority;
xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL );
/* Record the number of tasks that are running now so we know if any of the
suicidal tasks have failed to be killed. */
uxTasksRunningAtStart = uxTaskGetNumberOfTasks();
}
/*-----------------------------------------------------------*/
static void vSuicidalTask( void *pvParameters )
{
portDOUBLE d1, d2;
xTaskHandle xTaskToKill;
const portTickType xDelay = ( portTickType ) 500 / portTICK_RATE_MS;
if( pvParameters != NULL )
{
/* This task is periodically created four times. Tow created tasks are
passed a handle to the other task so it can kill it before killing itself.
The other task is passed in null. */
xTaskToKill = *( xTaskHandle* )pvParameters;
}
else
{
xTaskToKill = NULL;
}
for( ;; )
{
/* Do something random just to use some stack and registers. */
d1 = 2.4;
d2 = 89.2;
d2 *= d1;
vTaskDelay( xDelay );
if( xTaskToKill != NULL )
{
/* Make sure the other task has a go before we delete it. */
vTaskDelay( ( portTickType ) 0 );
/* Kill the other task that was created by vCreateTasks(). */
vTaskDelete( xTaskToKill );
/* Kill ourselves. */
vTaskDelete( NULL );
}
}
}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */
/*-----------------------------------------------------------*/
static void vCreateTasks( void *pvParameters )
{
const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS;
unsigned portBASE_TYPE uxPriority;
const portCHAR * const pcTaskStartMsg = "Create task started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
uxPriority = *( unsigned portBASE_TYPE * ) pvParameters;
vPortFree( pvParameters );
for( ;; )
{
/* Just loop round, delaying then creating the four suicidal tasks. */
vTaskDelay( xDelay );
xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 );
xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL );
xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 );
xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL );
++sCreationCount;
}
}
/*-----------------------------------------------------------*/
/* This is called to check that the creator task is still running and that there
are not any more than four extra tasks. */
portBASE_TYPE xIsCreateTaskStillRunning( void )
{
static portSHORT sLastCreationCount = 0;
portSHORT sReturn = pdTRUE;
unsigned portBASE_TYPE uxTasksRunningNow;
if( sLastCreationCount == sCreationCount )
{
sReturn = pdFALSE;
}
uxTasksRunningNow = uxTaskGetNumberOfTasks();
if( uxTasksRunningNow < uxTasksRunningAtStart )
{
sReturn = pdFALSE;
}
else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning )
{
sReturn = pdFALSE;
}
else
{
/* Everything is okay. */
}
return sReturn;
}

593
20080212/Demo/Common/Full/dynamic.c Normal file
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@ -0,0 +1,593 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/**
* The first test creates three tasks - two counter tasks (one continuous count
* and one limited count) and one controller. A "count" variable is shared
* between all three tasks. The two counter tasks should never be in a "ready"
* state at the same time. The controller task runs at the same priority as
* the continuous count task, and at a lower priority than the limited count
* task.
*
* One counter task loops indefinitely, incrementing the shared count variable
* on each iteration. To ensure it has exclusive access to the variable it
* raises it's priority above that of the controller task before each
* increment, lowering it again to it's original priority before starting the
* next iteration.
*
* The other counter task increments the shared count variable on each
* iteration of it's loop until the count has reached a limit of 0xff - at
* which point it suspends itself. It will not start a new loop until the
* controller task has made it "ready" again by calling vTaskResume ().
* This second counter task operates at a higher priority than controller
* task so does not need to worry about mutual exclusion of the counter
* variable.
*
* The controller task is in two sections. The first section controls and
* monitors the continuous count task. When this section is operational the
* limited count task is suspended. Likewise, the second section controls
* and monitors the limited count task. When this section is operational the
* continuous count task is suspended.
*
* In the first section the controller task first takes a copy of the shared
* count variable. To ensure mutual exclusion on the count variable it
* suspends the continuous count task, resuming it again when the copy has been
* taken. The controller task then sleeps for a fixed period - during which
* the continuous count task will execute and increment the shared variable.
* When the controller task wakes it checks that the continuous count task
* has executed by comparing the copy of the shared variable with its current
* value. This time, to ensure mutual exclusion, the scheduler itself is
* suspended with a call to vTaskSuspendAll (). This is for demonstration
* purposes only and is not a recommended technique due to its inefficiency.
*
* After a fixed number of iterations the controller task suspends the
* continuous count task, and moves on to its second section.
*
* At the start of the second section the shared variable is cleared to zero.
* The limited count task is then woken from it's suspension by a call to
* vTaskResume (). As this counter task operates at a higher priority than
* the controller task the controller task should not run again until the
* shared variable has been counted up to the limited value causing the counter
* task to suspend itself. The next line after vTaskResume () is therefore
* a check on the shared variable to ensure everything is as expected.
*
*
* The second test consists of a couple of very simple tasks that post onto a
* queue while the scheduler is suspended. This test was added to test parts
* of the scheduler not exercised by the first test.
*
*
* The final set of two tasks implements a third test. This simply raises the
* priority of a task while the scheduler is suspended. Again this test was
* added to exercise parts of the code not covered by the first test.
*
* \page Priorities dynamic.c
* \ingroup DemoFiles
* <HR>
*/
/*
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
+ Added a second, simple test that uses the functions
vQueueReceiveWhenSuspendedTask() and vQueueSendWhenSuspendedTask().
Changes from V3.1.1
+ Added a third simple test that uses the vTaskPrioritySet() function
while the scheduler is suspended.
+ Modified the controller task slightly to test the calling of
vTaskResumeAll() while the scheduler is suspended.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Demo app include files. */
#include "dynamic.h"
#include "print.h"
/* Function that implements the "limited count" task as described above. */
static void vLimitedIncrementTask( void * pvParameters );
/* Function that implements the "continuous count" task as described above. */
static void vContinuousIncrementTask( void * pvParameters );
/* Function that implements the controller task as described above. */
static void vCounterControlTask( void * pvParameters );
/* The simple test functions that check sending and receiving while the
scheduler is suspended. */
static void vQueueReceiveWhenSuspendedTask( void *pvParameters );
static void vQueueSendWhenSuspendedTask( void *pvParameters );
/* The simple test functions that check raising and lowering of task priorities
while the scheduler is suspended. */
static void prvChangePriorityWhenSuspendedTask( void *pvParameters );
static void prvChangePriorityHelperTask( void *pvParameters );
/* Demo task specific constants. */
#define priSTACK_SIZE ( ( unsigned portSHORT ) configMINIMAL_STACK_SIZE )
#define priSLEEP_TIME ( ( portTickType ) 50 )
#define priLOOPS ( 5 )
#define priMAX_COUNT ( ( unsigned portLONG ) 0xff )
#define priNO_BLOCK ( ( portTickType ) 0 )
#define priSUSPENDED_QUEUE_LENGTH ( 1 )
/*-----------------------------------------------------------*/
/* Handles to the two counter tasks. These could be passed in as parameters
to the controller task to prevent them having to be file scope. */
static xTaskHandle xContinuousIncrementHandle, xLimitedIncrementHandle, xChangePriorityWhenSuspendedHandle;
/* The shared counter variable. This is passed in as a parameter to the two
counter variables for demonstration purposes. */
static unsigned portLONG ulCounter;
/* Variable used in a similar way by the test that checks the raising and
lowering of task priorities while the scheduler is suspended. */
static unsigned portLONG ulPrioritySetCounter;
/* Variables used to check that the tasks are still operating without error.
Each complete iteration of the controller task increments this variable
provided no errors have been found. The variable maintaining the same value
is therefore indication of an error. */
static unsigned portSHORT usCheckVariable = ( unsigned portSHORT ) 0;
static portBASE_TYPE xSuspendedQueueSendError = pdFALSE;
static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE;
static portBASE_TYPE xPriorityRaiseWhenSuspendedError = pdFALSE;
/* Queue used by the second test. */
xQueueHandle xSuspendedTestQueue;
/*-----------------------------------------------------------*/
/*
* Start the seven tasks as described at the top of the file.
* Note that the limited count task is given a higher priority.
*/
void vStartDynamicPriorityTasks( void )
{
xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned portLONG ) );
xTaskCreate( vContinuousIncrementTask, "CONT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle );
xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );
xTaskCreate( vCounterControlTask, "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_SEND", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RECV", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( prvChangePriorityWhenSuspendedTask, "1st_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL );
xTaskCreate( prvChangePriorityHelperTask, "2nd_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xChangePriorityWhenSuspendedHandle );
}
/*-----------------------------------------------------------*/
/*
* Just loops around incrementing the shared variable until the limit has been
* reached. Once the limit has been reached it suspends itself.
*/
static void vLimitedIncrementTask( void * pvParameters )
{
unsigned portLONG *pulCounter;
/* Take a pointer to the shared variable from the parameters passed into
the task. */
pulCounter = ( unsigned portLONG * ) pvParameters;
/* This will run before the control task, so the first thing it does is
suspend - the control task will resume it when ready. */
vTaskSuspend( NULL );
for( ;; )
{
/* Just count up to a value then suspend. */
( *pulCounter )++;
if( *pulCounter >= priMAX_COUNT )
{
vTaskSuspend( NULL );
}
}
}
/*-----------------------------------------------------------*/
/*
* Just keep counting the shared variable up. The control task will suspend
* this task when it wants.
*/
static void vContinuousIncrementTask( void * pvParameters )
{
unsigned portLONG *pulCounter;
unsigned portBASE_TYPE uxOurPriority;
/* Take a pointer to the shared variable from the parameters passed into
the task. */
pulCounter = ( unsigned portLONG * ) pvParameters;
/* Query our priority so we can raise it when exclusive access to the
shared variable is required. */
uxOurPriority = uxTaskPriorityGet( NULL );
for( ;; )
{
/* Raise our priority above the controller task to ensure a context
switch does not occur while we are accessing this variable. */
vTaskPrioritySet( NULL, uxOurPriority + 1 );
( *pulCounter )++;
vTaskPrioritySet( NULL, uxOurPriority );
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
}
}
/*-----------------------------------------------------------*/
/*
* Controller task as described above.
*/
static void vCounterControlTask( void * pvParameters )
{
unsigned portLONG ulLastCounter;
portSHORT sLoops;
portSHORT sError = pdFALSE;
const portCHAR * const pcTaskStartMsg = "Priority manipulation tasks started.\r\n";
const portCHAR * const pcTaskFailMsg = "Priority manipulation Task Failed\r\n";
/* Just to stop warning messages. */
( void ) pvParameters;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
for( ;; )
{
/* Start with the counter at zero. */
ulCounter = ( unsigned portLONG ) 0;
/* First section : */
/* Check the continuous count task is running. */
for( sLoops = 0; sLoops < priLOOPS; sLoops++ )
{
/* Suspend the continuous count task so we can take a mirror of the
shared variable without risk of corruption. */
vTaskSuspend( xContinuousIncrementHandle );
ulLastCounter = ulCounter;
vTaskResume( xContinuousIncrementHandle );
/* Now delay to ensure the other task has processor time. */
vTaskDelay( priSLEEP_TIME );
/* Check the shared variable again. This time to ensure mutual
exclusion the whole scheduler will be locked. This is just for
demo purposes! */
vTaskSuspendAll();
{
if( ulLastCounter == ulCounter )
{
/* The shared variable has not changed. There is a problem
with the continuous count task so flag an error. */
sError = pdTRUE;
xTaskResumeAll();
vPrintDisplayMessage( &pcTaskFailMsg );
vTaskSuspendAll();
}
}
xTaskResumeAll();
}
/* Second section: */
/* Suspend the continuous counter task so it stops accessing the shared variable. */
vTaskSuspend( xContinuousIncrementHandle );
/* Reset the variable. */
ulCounter = ( unsigned portLONG ) 0;
/* Resume the limited count task which has a higher priority than us.
We should therefore not return from this call until the limited count
task has suspended itself with a known value in the counter variable.
The scheduler suspension is not necessary but is included for test
purposes. */
vTaskSuspendAll();
vTaskResume( xLimitedIncrementHandle );
xTaskResumeAll();
/* Does the counter variable have the expected value? */
if( ulCounter != priMAX_COUNT )
{
sError = pdTRUE;
vPrintDisplayMessage( &pcTaskFailMsg );
}
if( sError == pdFALSE )
{
/* If no errors have occurred then increment the check variable. */
portENTER_CRITICAL();
usCheckVariable++;
portEXIT_CRITICAL();
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Resume the continuous count task and do it all again. */
vTaskResume( xContinuousIncrementHandle );
}
}
/*-----------------------------------------------------------*/
static void vQueueSendWhenSuspendedTask( void *pvParameters )
{
static unsigned portLONG ulValueToSend = ( unsigned portLONG ) 0;
const portCHAR * const pcTaskStartMsg = "Queue send while suspended task started.\r\n";
const portCHAR * const pcTaskFailMsg = "Queue send while suspended failed.\r\n";
/* Just to stop warning messages. */
( void ) pvParameters;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
for( ;; )
{
vTaskSuspendAll();
{
/* We must not block while the scheduler is suspended! */
if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )
{
if( xSuspendedQueueSendError == pdFALSE )
{
xTaskResumeAll();
vPrintDisplayMessage( &pcTaskFailMsg );
vTaskSuspendAll();
}
xSuspendedQueueSendError = pdTRUE;
}
}
xTaskResumeAll();
vTaskDelay( priSLEEP_TIME );
++ulValueToSend;
}
}
/*-----------------------------------------------------------*/
static void vQueueReceiveWhenSuspendedTask( void *pvParameters )
{
static unsigned portLONG ulExpectedValue = ( unsigned portLONG ) 0, ulReceivedValue;
const portCHAR * const pcTaskStartMsg = "Queue receive while suspended task started.\r\n";
const portCHAR * const pcTaskFailMsg = "Queue receive while suspended failed.\r\n";
portBASE_TYPE xGotValue;
/* Just to stop warning messages. */
( void ) pvParameters;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
for( ;; )
{
do
{
/* Suspending the scheduler here is fairly pointless and
undesirable for a normal application. It is done here purely
to test the scheduler. The inner xTaskResumeAll() should
never return pdTRUE as the scheduler is still locked by the
outer call. */
vTaskSuspendAll();
{
vTaskSuspendAll();
{
xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );
}
if( xTaskResumeAll() )
{
xSuspendedQueueReceiveError = pdTRUE;
}
}
xTaskResumeAll();
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
} while( xGotValue == pdFALSE );
if( ulReceivedValue != ulExpectedValue )
{
if( xSuspendedQueueReceiveError == pdFALSE )
{
vPrintDisplayMessage( &pcTaskFailMsg );
}
xSuspendedQueueReceiveError = pdTRUE;
}
++ulExpectedValue;
}
}
/*-----------------------------------------------------------*/
static void prvChangePriorityWhenSuspendedTask( void *pvParameters )
{
const portCHAR * const pcTaskStartMsg = "Priority change when suspended task started.\r\n";
const portCHAR * const pcTaskFailMsg = "Priority change when suspended task failed.\r\n";
/* Just to stop warning messages. */
( void ) pvParameters;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
for( ;; )
{
/* Start with the counter at 0 so we know what the counter should be
when we check it next. */
ulPrioritySetCounter = ( unsigned portLONG ) 0;
/* Resume the helper task. At this time it has a priority lower than
ours so no context switch should occur. */
vTaskResume( xChangePriorityWhenSuspendedHandle );
/* Check to ensure the task just resumed has not executed. */
portENTER_CRITICAL();
{
if( ulPrioritySetCounter != ( unsigned portLONG ) 0 )
{
xPriorityRaiseWhenSuspendedError = pdTRUE;
vPrintDisplayMessage( &pcTaskFailMsg );
}
}
portEXIT_CRITICAL();
/* Now try raising the priority while the scheduler is suspended. */
vTaskSuspendAll();
{
vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, ( configMAX_PRIORITIES - 1 ) );
/* Again, even though the helper task has a priority greater than
ours, it should not have executed yet because the scheduler is
suspended. */
portENTER_CRITICAL();
{
if( ulPrioritySetCounter != ( unsigned portLONG ) 0 )
{
xPriorityRaiseWhenSuspendedError = pdTRUE;
vPrintDisplayMessage( &pcTaskFailMsg );
}
}
portEXIT_CRITICAL();
}
xTaskResumeAll();
/* Now the scheduler has been resumed the helper task should
immediately preempt us and execute. When it executes it will increment
the ulPrioritySetCounter exactly once before suspending itself.
We should now always find the counter set to 1. */
portENTER_CRITICAL();
{
if( ulPrioritySetCounter != ( unsigned portLONG ) 1 )
{
xPriorityRaiseWhenSuspendedError = pdTRUE;
vPrintDisplayMessage( &pcTaskFailMsg );
}
}
portEXIT_CRITICAL();
/* Delay until we try this again. */
vTaskDelay( priSLEEP_TIME * 2 );
/* Set the priority of the helper task back ready for the next
execution of this task. */
vTaskSuspendAll();
vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, tskIDLE_PRIORITY );
xTaskResumeAll();
}
}
/*-----------------------------------------------------------*/
static void prvChangePriorityHelperTask( void *pvParameters )
{
/* Just to stop warning messages. */
( void ) pvParameters;
for( ;; )
{
/* This is the helper task for prvChangePriorityWhenSuspendedTask().
It has it's priority raised and lowered. When it runs it simply
increments the counter then suspends itself again. This allows
prvChangePriorityWhenSuspendedTask() to know how many times it has
executed. */
ulPrioritySetCounter++;
vTaskSuspend( NULL );
}
}
/*-----------------------------------------------------------*/
/* Called to check that all the created tasks are still running without error. */
portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void )
{
/* Keep a history of the check variables so we know if it has been incremented
since the last call. */
static unsigned portSHORT usLastTaskCheck = ( unsigned portSHORT ) 0;
portBASE_TYPE xReturn = pdTRUE;
/* Check the tasks are still running by ensuring the check variable
is still incrementing. */
if( usCheckVariable == usLastTaskCheck )
{
/* The check has not incremented so an error exists. */
xReturn = pdFALSE;
}
if( xSuspendedQueueSendError == pdTRUE )
{
xReturn = pdFALSE;
}
if( xSuspendedQueueReceiveError == pdTRUE )
{
xReturn = pdFALSE;
}
if( xPriorityRaiseWhenSuspendedError == pdTRUE )
{
xReturn = pdFALSE;
}
usLastTaskCheck = usCheckVariable;
return xReturn;
}

383
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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/**
* This file exercises the event mechanism whereby more than one task is
* blocked waiting for the same event.
*
* The demo creates five tasks - four 'event' tasks, and a controlling task.
* The event tasks have various different priorities and all block on reading
* the same queue. The controlling task writes data to the queue, then checks
* to see which of the event tasks read the data from the queue. The
* controlling task has the lowest priority of all the tasks so is guaranteed
* to always get preempted immediately upon writing to the queue.
*
* By selectively suspending and resuming the event tasks the controlling task
* can check that the highest priority task that is blocked on the queue is the
* task that reads the posted data from the queue.
*
* Two of the event tasks share the same priority. When neither of these tasks
* are suspended they should alternate - one reading one message from the queue,
* the other the next message, etc.
*/
/* Standard includes. */
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Demo program include files. */
#include "mevents.h"
#include "print.h"
/* Demo specific constants. */
#define evtSTACK_SIZE ( ( unsigned portBASE_TYPE ) configMINIMAL_STACK_SIZE )
#define evtNUM_TASKS ( 4 )
#define evtQUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 3 )
#define evtNO_DELAY 0
/* Just indexes used to uniquely identify the tasks. Note that two tasks are
'highest' priority. */
#define evtHIGHEST_PRIORITY_INDEX_2 3
#define evtHIGHEST_PRIORITY_INDEX_1 2
#define evtMEDIUM_PRIORITY_INDEX 1
#define evtLOWEST_PRIORITY_INDEX 0
/* Each event task increments one of these counters each time it reads data
from the queue. */
static volatile portBASE_TYPE xTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 };
/* Each time the controlling task posts onto the queue it increments the
expected count of the task that it expected to read the data from the queue
(i.e. the task with the highest priority that should be blocked on the queue).
xExpectedTaskCounters are incremented from the controlling task, and
xTaskCounters are incremented from the individual event tasks - therefore
comparing xTaskCounters to xExpectedTaskCounters shows whether or not the
correct task was unblocked by the post. */
static portBASE_TYPE xExpectedTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 };
/* Handles to the four event tasks. These are required to suspend and resume
the tasks. */
static xTaskHandle xCreatedTasks[ evtNUM_TASKS ];
/* The single queue onto which the controlling task posts, and the four event
tasks block. */
static xQueueHandle xQueue;
/* Flag used to indicate whether or not an error has occurred at any time.
An error is either the queue being full when not expected, or an unexpected
task reading data from the queue. */
static portBASE_TYPE xHealthStatus = pdPASS;
/*-----------------------------------------------------------*/
/* Function that implements the event task. This is created four times. */
static void prvMultiEventTask( void *pvParameters );
/* Function that implements the controlling task. */
static void prvEventControllerTask( void *pvParameters );
/* This is a utility function that posts data to the queue, then compares
xExpectedTaskCounters with xTaskCounters to ensure everything worked as
expected.
The event tasks all have higher priorities the controlling task. Therefore
the controlling task will always get preempted between writhing to the queue
and checking the task counters.
@param xExpectedTask The index to the task that the controlling task thinks
should be the highest priority task waiting for data, and
therefore the task that will unblock.
@param xIncrement The number of items that should be written to the queue.
*/
static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement );
/* This is just incremented each cycle of the controlling tasks function so
the main application can ensure the test is still running. */
static portBASE_TYPE xCheckVariable = 0;
/*-----------------------------------------------------------*/
void vStartMultiEventTasks( void )
{
/* Create the queue to be used for all the communications. */
xQueue = xQueueCreate( evtQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) );
/* Start the controlling task. This has the idle priority to ensure it is
always preempted by the event tasks. */
xTaskCreate( prvEventControllerTask, "EvntCTRL", evtSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
/* Start the four event tasks. Note that two have priority 3, one
priority 2 and the other priority 1. */
xTaskCreate( prvMultiEventTask, "Event0", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 0 ] ), 1, &( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ) );
xTaskCreate( prvMultiEventTask, "Event1", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 1 ] ), 2, &( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ) );
xTaskCreate( prvMultiEventTask, "Event2", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 2 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ) );
xTaskCreate( prvMultiEventTask, "Event3", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 3 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ) );
}
/*-----------------------------------------------------------*/
static void prvMultiEventTask( void *pvParameters )
{
portBASE_TYPE *pxCounter;
unsigned portBASE_TYPE uxDummy;
const portCHAR * const pcTaskStartMsg = "Multi event task started.\r\n";
/* The variable this task will increment is passed in as a parameter. */
pxCounter = ( portBASE_TYPE * ) pvParameters;
vPrintDisplayMessage( &pcTaskStartMsg );
for( ;; )
{
/* Block on the queue. */
if( xQueueReceive( xQueue, &uxDummy, portMAX_DELAY ) )
{
/* We unblocked by reading the queue - so simply increment
the counter specific to this task instance. */
( *pxCounter )++;
}
else
{
xHealthStatus = pdFAIL;
}
}
}
/*-----------------------------------------------------------*/
static void prvEventControllerTask( void *pvParameters )
{
const portCHAR * const pcTaskStartMsg = "Multi event controller task started.\r\n";
portBASE_TYPE xDummy = 0;
/* Just to stop warnings. */
( void ) pvParameters;
vPrintDisplayMessage( &pcTaskStartMsg );
for( ;; )
{
/* All tasks are blocked on the queue. When a message is posted one of
the two tasks that share the highest priority should unblock to read
the queue. The next message written should unblock the other task with
the same high priority, and so on in order. No other task should
unblock to read data as they have lower priorities. */
prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 );
prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 );
prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
/* For the rest of these tests we don't need the second 'highest'
priority task - so it is suspended. */
vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] );
/* Now suspend the other highest priority task. The medium priority
task will then be the task with the highest priority that remains
blocked on the queue. */
vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
/* This time, when we post onto the queue we will expect the medium
priority task to unblock and preempt us. */
prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 );
/* Now try resuming the highest priority task while the scheduler is
suspended. The task should start executing as soon as the scheduler
is resumed - therefore when we post to the queue again, the highest
priority task should again preempt us. */
vTaskSuspendAll();
vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
xTaskResumeAll();
prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
/* Now we are going to suspend the high and medium priority tasks. The
low priority task should then preempt us. Again the task suspension is
done with the whole scheduler suspended just for test purposes. */
vTaskSuspendAll();
vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
xTaskResumeAll();
prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 );
/* Do the same basic test another few times - selectively suspending
and resuming tasks and each time calling prvCheckTaskCounters() passing
to the function the number of the task we expected to be unblocked by
the post. */
vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
vTaskSuspendAll(); /* Just for test. */
vTaskSuspendAll(); /* Just for test. */
vTaskSuspendAll(); /* Just for even more test. */
vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
xTaskResumeAll();
xTaskResumeAll();
xTaskResumeAll();
prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 );
vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 );
vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
/* Now a slight change, first suspend all tasks. */
vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
/* Now when we resume the low priority task and write to the queue 3
times. We expect the low priority task to service the queue three
times. */
vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, evtQUEUE_LENGTH );
/* Again suspend all tasks (only the low priority task is not suspended
already). */
vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
/* This time we are going to suspend the scheduler, resume the low
priority task, then resume the high priority task. In this state we
will write to the queue three times. When the scheduler is resumed
we expect the high priority task to service all three messages. */
vTaskSuspendAll();
{
vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
for( xDummy = 0; xDummy < evtQUEUE_LENGTH; xDummy++ )
{
if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE )
{
xHealthStatus = pdFAIL;
}
}
/* The queue should not have been serviced yet!. The scheduler
is still suspended. */
if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
{
xHealthStatus = pdFAIL;
}
}
xTaskResumeAll();
/* We should have been preempted by resuming the scheduler - so by the
time we are running again we expect the high priority task to have
removed three items from the queue. */
xExpectedTaskCounters[ evtHIGHEST_PRIORITY_INDEX_1 ] += evtQUEUE_LENGTH;
if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
{
xHealthStatus = pdFAIL;
}
/* The medium priority and second high priority tasks are still
suspended. Make sure to resume them before starting again. */
vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] );
/* Just keep incrementing to show the task is still executing. */
xCheckVariable++;
}
}
/*-----------------------------------------------------------*/
static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement )
{
portBASE_TYPE xDummy = 0;
/* Write to the queue the requested number of times. The data written is
not important. */
for( xDummy = 0; xDummy < xIncrement; xDummy++ )
{
if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE )
{
/* Did not expect to ever find the queue full. */
xHealthStatus = pdFAIL;
}
}
/* All the tasks blocked on the queue have a priority higher than the
controlling task. Writing to the queue will therefore have caused this
task to be preempted. By the time this line executes the event task will
have executed and incremented its counter. Increment the expected counter
to the same value. */
( xExpectedTaskCounters[ xExpectedTask ] ) += xIncrement;
/* Check the actual counts and expected counts really are the same. */
if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
{
/* The counters were not the same. This means a task we did not expect
to unblock actually did unblock. */
xHealthStatus = pdFAIL;
}
}
/*-----------------------------------------------------------*/
portBASE_TYPE xAreMultiEventTasksStillRunning( void )
{
static portBASE_TYPE xPreviousCheckVariable = 0;
/* Called externally to periodically check that this test is still
operational. */
if( xPreviousCheckVariable == xCheckVariable )
{
xHealthStatus = pdFAIL;
}
xPreviousCheckVariable = xCheckVariable;
return xHealthStatus;
}

143
20080212/Demo/Common/Full/flash.c Normal file
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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/**
* Creates eight tasks, each of which flash an LED at a different rate. The first
* LED flashes every 125ms, the second every 250ms, the third every 375ms, etc.
*
* The LED flash tasks provide instant visual feedback. They show that the scheduler
* is still operational.
*
* The PC port uses the standard parallel port for outputs, the Flashlite 186 port
* uses IO port F.
*
* \page flashC flash.c
* \ingroup DemoFiles
* <HR>
*/
/*
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
Changes from V2.1.1
+ The stack size now uses configMINIMAL_STACK_SIZE.
+ String constants made file scope to decrease stack depth on 8051 port.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo program include files. */
#include "partest.h"
#include "flash.h"
#include "print.h"
#define ledSTACK_SIZE configMINIMAL_STACK_SIZE
/* Structure used to pass parameters to the LED tasks. */
typedef struct LED_PARAMETERS
{
unsigned portBASE_TYPE uxLED; /*< The output the task should use. */
portTickType xFlashRate; /*< The rate at which the LED should flash. */
} xLEDParameters;
/* The task that is created eight times - each time with a different xLEDParaemtes
structure passed in as the parameter. */
static void vLEDFlashTask( void *pvParameters );
/* String to print if USE_STDIO is defined. */
const portCHAR * const pcTaskStartMsg = "LED flash task started.\r\n";
/*-----------------------------------------------------------*/
void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority )
{
unsigned portBASE_TYPE uxLEDTask;
xLEDParameters *pxLEDParameters;
const unsigned portBASE_TYPE uxNumOfLEDs = 8;
const portTickType xFlashRate = 125;
/* Create the eight tasks. */
for( uxLEDTask = 0; uxLEDTask < uxNumOfLEDs; ++uxLEDTask )
{
/* Create and complete the structure used to pass parameters to the next
created task. */
pxLEDParameters = ( xLEDParameters * ) pvPortMalloc( sizeof( xLEDParameters ) );
pxLEDParameters->uxLED = uxLEDTask;
pxLEDParameters->xFlashRate = ( xFlashRate + ( xFlashRate * ( portTickType ) uxLEDTask ) );
pxLEDParameters->xFlashRate /= portTICK_RATE_MS;
/* Spawn the task. */
xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, ( void * ) pxLEDParameters, uxPriority, ( xTaskHandle * ) NULL );
}
}
/*-----------------------------------------------------------*/
static void vLEDFlashTask( void *pvParameters )
{
xLEDParameters *pxParameters;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
pxParameters = ( xLEDParameters * ) pvParameters;
for(;;)
{
/* Delay for half the flash period then turn the LED on. */
vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 );
vParTestToggleLED( pxParameters->uxLED );
/* Delay for half the flash period then turn the LED off. */
vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 );
vParTestToggleLED( pxParameters->uxLED );
}
}

346
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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
Changes from V1.2.3
+ The created tasks now include calls to tskYIELD(), allowing them to be used
with the cooperative scheduler.
*/
/**
* Creates eight tasks, each of which loops continuously performing an (emulated)
* floating point calculation.
*
* All the tasks run at the idle priority and never block or yield. This causes
* all eight tasks to time slice with the idle task. Running at the idle priority
* means that these tasks will get pre-empted any time another task is ready to run
* or a time slice occurs. More often than not the pre-emption will occur mid
* calculation, creating a good test of the schedulers context switch mechanism - a
* calculation producing an unexpected result could be a symptom of a corruption in
* the context of a task.
*
* \page FlopC flop.c
* \ingroup DemoFiles
* <HR>
*/
#include <stdlib.h>
#include <math.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "print.h"
/* Demo program include files. */
#include "flop.h"
#define mathSTACK_SIZE ( ( unsigned portSHORT ) 512 )
#define mathNUMBER_OF_TASKS ( 8 )
/* Four tasks, each of which performs a different floating point calculation.
Each of the four is created twice. */
static void vCompetingMathTask1( void *pvParameters );
static void vCompetingMathTask2( void *pvParameters );
static void vCompetingMathTask3( void *pvParameters );
static void vCompetingMathTask4( void *pvParameters );
/* These variables are used to check that all the tasks are still running. If a
task gets a calculation wrong it will
stop incrementing its check variable. */
static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };
/*-----------------------------------------------------------*/
void vStartMathTasks( unsigned portBASE_TYPE uxPriority )
{
xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
}
/*-----------------------------------------------------------*/
static void vCompetingMathTask1( void *pvParameters )
{
portDOUBLE d1, d2, d3, d4;
volatile unsigned portSHORT *pusTaskCheckVariable;
const portDOUBLE dAnswer = ( 123.4567 + 2345.6789 ) * -918.222;
const portCHAR * const pcTaskStartMsg = "Math task 1 started.\r\n";
const portCHAR * const pcTaskFailMsg = "Math task 1 failed.\r\n";
portSHORT sError = pdFALSE;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
/* Keep performing a calculation and checking the result against a constant. */
for(;;)
{
d1 = 123.4567;
d2 = 2345.6789;
d3 = -918.222;
d4 = ( d1 + d2 ) * d3;
taskYIELD();
/* If the calculation does not match the expected constant, stop the
increment of the check variable. */
if( fabs( d4 - dAnswer ) > 0.001 )
{
vPrintDisplayMessage( &pcTaskFailMsg );
sError = pdTRUE;
}
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
taskYIELD();
}
}
/*-----------------------------------------------------------*/
static void vCompetingMathTask2( void *pvParameters )
{
portDOUBLE d1, d2, d3, d4;
volatile unsigned portSHORT *pusTaskCheckVariable;
const portDOUBLE dAnswer = ( -389.38 / 32498.2 ) * -2.0001;
const portCHAR * const pcTaskStartMsg = "Math task 2 started.\r\n";
const portCHAR * const pcTaskFailMsg = "Math task 2 failed.\r\n";
portSHORT sError = pdFALSE;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
/* Keep performing a calculation and checking the result against a constant. */
for( ;; )
{
d1 = -389.38;
d2 = 32498.2;
d3 = -2.0001;
d4 = ( d1 / d2 ) * d3;
taskYIELD();
/* If the calculation does not match the expected constant, stop the
increment of the check variable. */
if( fabs( d4 - dAnswer ) > 0.001 )
{
vPrintDisplayMessage( &pcTaskFailMsg );
sError = pdTRUE;
}
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know
this task is still running okay. */
( *pusTaskCheckVariable )++;
}
taskYIELD();
}
}
/*-----------------------------------------------------------*/
static void vCompetingMathTask3( void *pvParameters )
{
portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
volatile unsigned portSHORT *pusTaskCheckVariable;
const unsigned portSHORT usArraySize = 250;
unsigned portSHORT usPosition;
const portCHAR * const pcTaskStartMsg = "Math task 3 started.\r\n";
const portCHAR * const pcTaskFailMsg = "Math task 3 failed.\r\n";
portSHORT sError = pdFALSE;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) );
/* Keep filling an array, keeping a running total of the values placed in the
array. Then run through the array adding up all the values. If the two totals
do not match, stop the check variable from incrementing. */
for( ;; )
{
dTotal1 = 0.0;
dTotal2 = 0.0;
for( usPosition = 0; usPosition < usArraySize; usPosition++ )
{
pdArray[ usPosition ] = ( portDOUBLE ) usPosition + 5.5;
dTotal1 += ( portDOUBLE ) usPosition + 5.5;
}
taskYIELD();
for( usPosition = 0; usPosition < usArraySize; usPosition++ )
{
dTotal2 += pdArray[ usPosition ];
}
dDifference = dTotal1 - dTotal2;
if( fabs( dDifference ) > 0.001 )
{
vPrintDisplayMessage( &pcTaskFailMsg );
sError = pdTRUE;
}
taskYIELD();
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
}
}
/*-----------------------------------------------------------*/
static void vCompetingMathTask4( void *pvParameters )
{
portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
volatile unsigned portSHORT *pusTaskCheckVariable;
const unsigned portSHORT usArraySize = 250;
unsigned portSHORT usPosition;
const portCHAR * const pcTaskStartMsg = "Math task 4 started.\r\n";
const portCHAR * const pcTaskFailMsg = "Math task 4 failed.\r\n";
portSHORT sError = pdFALSE;
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) );
/* Keep filling an array, keeping a running total of the values placed in the
array. Then run through the array adding up all the values. If the two totals
do not match, stop the check variable from incrementing. */
for( ;; )
{
dTotal1 = 0.0;
dTotal2 = 0.0;
for( usPosition = 0; usPosition < usArraySize; usPosition++ )
{
pdArray[ usPosition ] = ( portDOUBLE ) usPosition * 12.123;
dTotal1 += ( portDOUBLE ) usPosition * 12.123;
}
taskYIELD();
for( usPosition = 0; usPosition < usArraySize; usPosition++ )
{
dTotal2 += pdArray[ usPosition ];
}
dDifference = dTotal1 - dTotal2;
if( fabs( dDifference ) > 0.001 )
{
vPrintDisplayMessage( &pcTaskFailMsg );
sError = pdTRUE;
}
taskYIELD();
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreMathsTaskStillRunning( void )
{
/* Keep a history of the check variables so we know if they have been incremented
since the last call. */
static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };
portBASE_TYPE xReturn = pdTRUE, xTask;
/* Check the maths tasks are still running by ensuring their check variables
are still incrementing. */
for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
{
if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
{
/* The check has not incremented so an error exists. */
xReturn = pdFALSE;
}
usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
}
return xReturn;
}

342
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@ -0,0 +1,342 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
Changes from V1.2.3
+ The created tasks now include calls to tskYIELD(), allowing them to be used
with the cooperative scheduler.
*/
/**
* This does the same as flop. c, but uses variables of type long instead of
* type double.
*
* As with flop. c, the tasks created in this file are a good test of the
* scheduler context switch mechanism. The processor has to access 32bit
* variables in two or four chunks (depending on the processor). The low
* priority of these tasks means there is a high probability that a context
* switch will occur mid calculation. See the flop. c documentation for
* more information.
*
* \page IntegerC integer.c
* \ingroup DemoFiles
* <HR>
*/
/*
Changes from V1.2.1
+ The constants used in the calculations are larger to ensure the
optimiser does not truncate them to 16 bits.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "print.h"
/* Demo program include files. */
#include "integer.h"
#define intgSTACK_SIZE ( ( unsigned portSHORT ) 256 )
#define intgNUMBER_OF_TASKS ( 8 )
/* Four tasks, each of which performs a different calculation on four byte
variables. Each of the four is created twice. */
static void vCompeteingIntMathTask1( void *pvParameters );
static void vCompeteingIntMathTask2( void *pvParameters );
static void vCompeteingIntMathTask3( void *pvParameters );
static void vCompeteingIntMathTask4( void *pvParameters );
/* These variables are used to check that all the tasks are still running. If a
task gets a calculation wrong it will stop incrementing its check variable. */
static volatile unsigned portSHORT usTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };
/*-----------------------------------------------------------*/
void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority )
{
xTaskCreate( vCompeteingIntMathTask1, "IntMath1", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
xTaskCreate( vCompeteingIntMathTask2, "IntMath2", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
xTaskCreate( vCompeteingIntMathTask3, "IntMath3", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
xTaskCreate( vCompeteingIntMathTask4, "IntMath4", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
xTaskCreate( vCompeteingIntMathTask1, "IntMath5", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
xTaskCreate( vCompeteingIntMathTask2, "IntMath6", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
xTaskCreate( vCompeteingIntMathTask3, "IntMath7", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
xTaskCreate( vCompeteingIntMathTask4, "IntMath8", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
}
/*-----------------------------------------------------------*/
static void vCompeteingIntMathTask1( void *pvParameters )
{
portLONG l1, l2, l3, l4;
portSHORT sError = pdFALSE;
volatile unsigned portSHORT *pusTaskCheckVariable;
const portLONG lAnswer = ( ( portLONG ) 74565L + ( portLONG ) 1234567L ) * ( portLONG ) -918L;
const portCHAR * const pcTaskStartMsg = "Integer math task 1 started.\r\n";
const portCHAR * const pcTaskFailMsg = "Integer math task 1 failed.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
/* Keep performing a calculation and checking the result against a constant. */
for(;;)
{
l1 = ( portLONG ) 74565L;
l2 = ( portLONG ) 1234567L;
l3 = ( portLONG ) -918L;
l4 = ( l1 + l2 ) * l3;
taskYIELD();
/* If the calculation does not match the expected constant, stop the
increment of the check variable. */
if( l4 != lAnswer )
{
vPrintDisplayMessage( &pcTaskFailMsg );
sError = pdTRUE;
}
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
}
}
/*-----------------------------------------------------------*/
static void vCompeteingIntMathTask2( void *pvParameters )
{
portLONG l1, l2, l3, l4;
portSHORT sError = pdFALSE;
volatile unsigned portSHORT *pusTaskCheckVariable;
const portLONG lAnswer = ( ( portLONG ) -389000L / ( portLONG ) 329999L ) * ( portLONG ) -89L;
const portCHAR * const pcTaskStartMsg = "Integer math task 2 started.\r\n";
const portCHAR * const pcTaskFailMsg = "Integer math task 2 failed.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
/* Keep performing a calculation and checking the result against a constant. */
for( ;; )
{
l1 = -389000L;
l2 = 329999L;
l3 = -89L;
l4 = ( l1 / l2 ) * l3;
taskYIELD();
/* If the calculation does not match the expected constant, stop the
increment of the check variable. */
if( l4 != lAnswer )
{
vPrintDisplayMessage( &pcTaskFailMsg );
sError = pdTRUE;
}
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
}
}
/*-----------------------------------------------------------*/
static void vCompeteingIntMathTask3( void *pvParameters )
{
portLONG *plArray, lTotal1, lTotal2;
portSHORT sError = pdFALSE;
volatile unsigned portSHORT *pusTaskCheckVariable;
const unsigned portSHORT usArraySize = ( unsigned portSHORT ) 250;
unsigned portSHORT usPosition;
const portCHAR * const pcTaskStartMsg = "Integer math task 3 started.\r\n";
const portCHAR * const pcTaskFailMsg = "Integer math task 3 failed.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
/* Create the array we are going to use for our check calculation. */
plArray = ( portLONG * ) pvPortMalloc( ( size_t ) 250 * sizeof( portLONG ) );
/* Keep filling the array, keeping a running total of the values placed in the
array. Then run through the array adding up all the values. If the two totals
do not match, stop the check variable from incrementing. */
for( ;; )
{
lTotal1 = ( portLONG ) 0;
lTotal2 = ( portLONG ) 0;
for( usPosition = 0; usPosition < usArraySize; usPosition++ )
{
plArray[ usPosition ] = ( portLONG ) usPosition + ( portLONG ) 5;
lTotal1 += ( portLONG ) usPosition + ( portLONG ) 5;
}
taskYIELD();
for( usPosition = 0; usPosition < usArraySize; usPosition++ )
{
lTotal2 += plArray[ usPosition ];
}
if( lTotal1 != lTotal2 )
{
vPrintDisplayMessage( &pcTaskFailMsg );
sError = pdTRUE;
}
taskYIELD();
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
}
}
/*-----------------------------------------------------------*/
static void vCompeteingIntMathTask4( void *pvParameters )
{
portLONG *plArray, lTotal1, lTotal2;
portSHORT sError = pdFALSE;
volatile unsigned portSHORT *pusTaskCheckVariable;
const unsigned portSHORT usArraySize = 250;
unsigned portSHORT usPosition;
const portCHAR * const pcTaskStartMsg = "Integer math task 4 started.\r\n";
const portCHAR * const pcTaskFailMsg = "Integer math task 4 failed.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
/* Create the array we are going to use for our check calculation. */
plArray = ( portLONG * ) pvPortMalloc( ( size_t ) 250 * sizeof( portLONG ) );
/* Keep filling the array, keeping a running total of the values placed in the
array. Then run through the array adding up all the values. If the two totals
do not match, stop the check variable from incrementing. */
for( ;; )
{
lTotal1 = ( portLONG ) 0;
lTotal2 = ( portLONG ) 0;
for( usPosition = 0; usPosition < usArraySize; usPosition++ )
{
plArray[ usPosition ] = ( portLONG ) usPosition * ( portLONG ) 12;
lTotal1 += ( portLONG ) usPosition * ( portLONG ) 12;
}
taskYIELD();
for( usPosition = 0; usPosition < usArraySize; usPosition++ )
{
lTotal2 += plArray[ usPosition ];
}
if( lTotal1 != lTotal2 )
{
vPrintDisplayMessage( &pcTaskFailMsg );
sError = pdTRUE;
}
taskYIELD();
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreIntegerMathsTaskStillRunning( void )
{
/* Keep a history of the check variables so we know if they have been incremented
since the last call. */
static unsigned portSHORT usLastTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };
portBASE_TYPE xReturn = pdTRUE, xTask;
/* Check the maths tasks are still running by ensuring their check variables
are still incrementing. */
for( xTask = 0; xTask < intgNUMBER_OF_TASKS; xTask++ )
{
if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
{
/* The check has not incremented so an error exists. */
xReturn = pdFALSE;
}
usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
}
return xReturn;
}

121
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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/**
* Manages a queue of strings that are waiting to be displayed. This is used to
* ensure mutual exclusion of console output.
*
* A task wishing to display a message will call vPrintDisplayMessage (), with a
* pointer to the string as the parameter. The pointer is posted onto the
* xPrintQueue queue.
*
* The task spawned in main. c blocks on xPrintQueue. When a message becomes
* available it calls pcPrintGetNextMessage () to obtain a pointer to the next
* string, then uses the functions defined in the portable layer FileIO. c to
* display the message.
*
* <b>NOTE:</b>
* Using console IO can disrupt real time performance - depending on the port.
* Standard C IO routines are not designed for real time applications. While
* standard IO is useful for demonstration and debugging an alternative method
* should be used if you actually require console IO as part of your application.
*
* \page PrintC print.c
* \ingroup DemoFiles
* <HR>
*/
/*
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "queue.h"
/* Demo program include files. */
#include "print.h"
static xQueueHandle xPrintQueue;
/*-----------------------------------------------------------*/
void vPrintInitialise( void )
{
const unsigned portBASE_TYPE uxQueueSize = 20;
/* Create the queue on which errors will be reported. */
xPrintQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( portCHAR * ) );
}
/*-----------------------------------------------------------*/
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend )
{
#ifdef USE_STDIO
xQueueSend( xPrintQueue, ( void * ) ppcMessageToSend, ( portTickType ) 0 );
#else
/* Stop warnings. */
( void ) ppcMessageToSend;
#endif
}
/*-----------------------------------------------------------*/
const portCHAR *pcPrintGetNextMessage( portTickType xPrintRate )
{
portCHAR *pcMessage;
if( xQueueReceive( xPrintQueue, &pcMessage, xPrintRate ) == pdPASS )
{
return pcMessage;
}
else
{
return NULL;
}
}

300
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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/**
* Creates two sets of two tasks. The tasks within a set share a variable, access
* to which is guarded by a semaphore.
*
* Each task starts by attempting to obtain the semaphore. On obtaining a
* semaphore a task checks to ensure that the guarded variable has an expected
* value. It then clears the variable to zero before counting it back up to the
* expected value in increments of 1. After each increment the variable is checked
* to ensure it contains the value to which it was just set. When the starting
* value is again reached the task releases the semaphore giving the other task in
* the set a chance to do exactly the same thing. The starting value is high
* enough to ensure that a tick is likely to occur during the incrementing loop.
*
* An error is flagged if at any time during the process a shared variable is
* found to have a value other than that expected. Such an occurrence would
* suggest an error in the mutual exclusion mechanism by which access to the
* variable is restricted.
*
* The first set of two tasks poll their semaphore. The second set use blocking
* calls.
*
* \page SemTestC semtest.c
* \ingroup DemoFiles
* <HR>
*/
/*
Changes from V1.2.0:
+ The tasks that operate at the idle priority now use a lower expected
count than those running at a higher priority. This prevents the low
priority tasks from signaling an error because they have not been
scheduled enough time for each of them to count the shared variable to
the high value.
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
Changes from V2.1.1
+ The stack size now uses configMINIMAL_STACK_SIZE.
+ String constants made file scope to decrease stack depth on 8051 port.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Demo app include files. */
#include "semtest.h"
#include "print.h"
/* The value to which the shared variables are counted. */
#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xfff )
#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xff )
#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE
#define semtstNUM_TASKS ( 4 )
#define semtstDELAY_FACTOR ( ( portTickType ) 10 )
/* The task function as described at the top of the file. */
static void prvSemaphoreTest( void *pvParameters );
/* Structure used to pass parameters to each task. */
typedef struct SEMAPHORE_PARAMETERS
{
xSemaphoreHandle xSemaphore;
volatile unsigned portLONG *pulSharedVariable;
portTickType xBlockTime;
} xSemaphoreParameters;
/* Variables used to check that all the tasks are still running without errors. */
static volatile portSHORT sCheckVariables[ semtstNUM_TASKS ] = { 0 };
static volatile portSHORT sNextCheckVariable = 0;
/* Strings to print if USE_STDIO is defined. */
const portCHAR * const pcPollingSemaphoreTaskError = "Guarded shared variable in unexpected state.\r\n";
const portCHAR * const pcSemaphoreTaskStart = "Guarded shared variable task started.\r\n";
/*-----------------------------------------------------------*/
void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority )
{
xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters;
const portTickType xBlockTime = ( portTickType ) 100;
/* Create the structure used to pass parameters to the first two tasks. */
pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
if( pxFirstSemaphoreParameters != NULL )
{
/* Create the semaphore used by the first two tasks. */
vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore );
if( pxFirstSemaphoreParameters->xSemaphore != NULL )
{
/* Create the variable which is to be shared by the first two tasks. */
pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) );
/* Initialise the share variable to the value the tasks expect. */
*( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE;
/* The first two tasks do not block on semaphore calls. */
pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0;
/* Spawn the first two tasks. As they poll they operate at the idle priority. */
xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );
xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );
}
}
/* Do exactly the same to create the second set of tasks, only this time
provide a block time for the semaphore calls. */
pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
if( pxSecondSemaphoreParameters != NULL )
{
vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore );
if( pxSecondSemaphoreParameters->xSemaphore != NULL )
{
pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) );
*( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE;
pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS;
xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL );
xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL );
}
}
}
/*-----------------------------------------------------------*/
static void prvSemaphoreTest( void *pvParameters )
{
xSemaphoreParameters *pxParameters;
volatile unsigned portLONG *pulSharedVariable, ulExpectedValue;
unsigned portLONG ulCounter;
portSHORT sError = pdFALSE, sCheckVariableToUse;
/* See which check variable to use. sNextCheckVariable is not semaphore
protected! */
portENTER_CRITICAL();
sCheckVariableToUse = sNextCheckVariable;
sNextCheckVariable++;
portEXIT_CRITICAL();
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcSemaphoreTaskStart );
/* A structure is passed in as the parameter. This contains the shared
variable being guarded. */
pxParameters = ( xSemaphoreParameters * ) pvParameters;
pulSharedVariable = pxParameters->pulSharedVariable;
/* If we are blocking we use a much higher count to ensure loads of context
switches occur during the count. */
if( pxParameters->xBlockTime > ( portTickType ) 0 )
{
ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE;
}
else
{
ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE;
}
for( ;; )
{
/* Try to obtain the semaphore. */
if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS )
{
/* We have the semaphore and so expect any other tasks using the
shared variable to have left it in the state we expect to find
it. */
if( *pulSharedVariable != ulExpectedValue )
{
vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
sError = pdTRUE;
}
/* Clear the variable, then count it back up to the expected value
before releasing the semaphore. Would expect a context switch or
two during this time. */
for( ulCounter = ( unsigned portLONG ) 0; ulCounter <= ulExpectedValue; ulCounter++ )
{
*pulSharedVariable = ulCounter;
if( *pulSharedVariable != ulCounter )
{
if( sError == pdFALSE )
{
vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
}
sError = pdTRUE;
}
}
/* Release the semaphore, and if no errors have occurred increment the check
variable. */
if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE )
{
vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
sError = pdTRUE;
}
if( sError == pdFALSE )
{
if( sCheckVariableToUse < semtstNUM_TASKS )
{
( sCheckVariables[ sCheckVariableToUse ] )++;
}
}
/* If we have a block time then we are running at a priority higher
than the idle priority. This task takes a long time to complete
a cycle (deliberately so to test the guarding) so will be starving
out lower priority tasks. Block for some time to allow give lower
priority tasks some processor time. */
vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR );
}
else
{
if( pxParameters->xBlockTime == ( portTickType ) 0 )
{
/* We have not got the semaphore yet, so no point using the
processor. We are not blocking when attempting to obtain the
semaphore. */
taskYIELD();
}
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreSemaphoreTasksStillRunning( void )
{
static portSHORT sLastCheckVariables[ semtstNUM_TASKS ] = { 0 };
portBASE_TYPE xTask, xReturn = pdTRUE;
for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ )
{
if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] )
{
xReturn = pdFALSE;
}
sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ];
}
return xReturn;
}

309
20080212/Demo/Common/Minimal/AltBlckQ.c Normal file
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@ -0,0 +1,309 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* This is a version of BlockQ.c that uses the alternative (Alt) API.
*
* Creates six tasks that operate on three queues as follows:
*
* The first two tasks send and receive an incrementing number to/from a queue.
* One task acts as a producer and the other as the consumer. The consumer is a
* higher priority than the producer and is set to block on queue reads. The queue
* only has space for one item - as soon as the producer posts a message on the
* queue the consumer will unblock, pre-empt the producer, and remove the item.
*
* The second two tasks work the other way around. Again the queue used only has
* enough space for one item. This time the consumer has a lower priority than the
* producer. The producer will try to post on the queue blocking when the queue is
* full. When the consumer wakes it will remove the item from the queue, causing
* the producer to unblock, pre-empt the consumer, and immediately re-fill the
* queue.
*
* The last two tasks use the same queue producer and consumer functions. This time the queue has
* enough space for lots of items and the tasks operate at the same priority. The
* producer will execute, placing items into the queue. The consumer will start
* executing when either the queue becomes full (causing the producer to block) or
* a context switch occurs (tasks of the same priority will time slice).
*
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Demo program include files. */
#include "AltBlckQ.h"
#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE
#define blckqNUM_TASK_SETS ( 3 )
/* Structure used to pass parameters to the blocking queue tasks. */
typedef struct BLOCKING_QUEUE_PARAMETERS
{
xQueueHandle xQueue; /*< The queue to be used by the task. */
portTickType xBlockTime; /*< The block time to use on queue reads/writes. */
volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */
} xBlockingQueueParameters;
/* Task function that creates an incrementing number and posts it on a queue. */
static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters );
/* Task function that removes the incrementing number from a queue and checks that
it is the expected number. */
static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters );
/* Variables which are incremented each time an item is removed from a queue, and
found to be the expected value.
These are used to check that the tasks are still running. */
static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };
/* Variable which are incremented each time an item is posted on a queue. These
are used to check that the tasks are still running. */
static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };
/*-----------------------------------------------------------*/
void vStartAltBlockingQueueTasks( unsigned portBASE_TYPE uxPriority )
{
xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2;
xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4;
xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6;
const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5;
const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS;
const portTickType xDontBlock = ( portTickType ) 0;
/* Create the first two tasks as described at the top of the file. */
/* First create the structure used to pass parameters to the consumer tasks. */
pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
/* Create the queue used by the first two tasks to pass the incrementing number.
Pass a pointer to the queue in the parameter structure. */
pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
/* The consumer is created first so gets a block time as described above. */
pxQueueParameters1->xBlockTime = xBlockTime;
/* Pass in the variable that this task is going to increment so we can check it
is still running. */
pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );
/* Create the structure used to pass parameters to the producer task. */
pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
/* Pass the queue to this task also, using the parameter structure. */
pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;
/* The producer is not going to block - as soon as it posts the consumer will
wake and remove the item so the producer should always have room to post. */
pxQueueParameters2->xBlockTime = xDontBlock;
/* Pass in the variable that this task is going to increment so we can check
it is still running. */
pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );
/* Note the producer has a lower priority than the consumer when the tasks are
spawned. */
xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );
xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );
/* Create the second two tasks as described at the top of the file. This uses
the same mechanism but reverses the task priorities. */
pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
pxQueueParameters3->xBlockTime = xDontBlock;
pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );
pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;
pxQueueParameters4->xBlockTime = xBlockTime;
pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );
xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );
xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );
/* Create the last two tasks as described above. The mechanism is again just
the same. This time both parameter structures are given a block time. */
pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
pxQueueParameters5->xBlockTime = xBlockTime;
pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );
pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;
pxQueueParameters6->xBlockTime = xBlockTime;
pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] );
xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );
xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters )
{
unsigned portSHORT usValue = 0;
xBlockingQueueParameters *pxQueueParameters;
portSHORT sErrorEverOccurred = pdFALSE;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Alt blocking queue producer task started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
for( ;; )
{
if( xQueueAltSendToBack( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )
{
sErrorEverOccurred = pdTRUE;
}
else
{
/* We have successfully posted a message, so increment the variable
used to check we are still running. */
if( sErrorEverOccurred == pdFALSE )
{
( *pxQueueParameters->psCheckVariable )++;
}
/* Increment the variable we are going to post next time round. The
consumer will expect the numbers to follow in numerical order. */
++usValue;
}
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters )
{
unsigned portSHORT usData, usExpectedValue = 0;
xBlockingQueueParameters *pxQueueParameters;
portSHORT sErrorEverOccurred = pdFALSE;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Alt blocking queue consumer task started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
for( ;; )
{
if( xQueueAltReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )
{
if( usData != usExpectedValue )
{
/* Catch-up. */
usExpectedValue = usData;
sErrorEverOccurred = pdTRUE;
}
else
{
/* We have successfully received a message, so increment the
variable used to check we are still running. */
if( sErrorEverOccurred == pdFALSE )
{
( *pxQueueParameters->psCheckVariable )++;
}
/* Increment the value we expect to remove from the queue next time
round. */
++usExpectedValue;
}
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreAltBlockingQueuesStillRunning( void )
{
static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };
static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };
portBASE_TYPE xReturn = pdPASS, xTasks;
/* Not too worried about mutual exclusion on these variables as they are 16
bits and we are only reading them. We also only care to see if they have
changed or not.
Loop through each check variable to and return pdFALSE if any are found not
to have changed since the last call. */
for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )
{
if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] )
{
xReturn = pdFALSE;
}
sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];
if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] )
{
xReturn = pdFALSE;
}
sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];
}
return xReturn;
}

517
20080212/Demo/Common/Minimal/AltBlock.c Normal file
View file

@ -0,0 +1,517 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* This is a version of BlockTim.c that uses the light weight API.
*
* This file contains some test scenarios that ensure tasks do not exit queue
* send or receive functions prematurely. A description of the tests is
* included within the code.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Demo includes. */
#include "AltBlock.h"
/* Task priorities. */
#define bktPRIMARY_PRIORITY ( 3 )
#define bktSECONDARY_PRIORITY ( 2 )
/* Task behaviour. */
#define bktQUEUE_LENGTH ( 5 )
#define bktSHORT_WAIT ( ( ( portTickType ) 20 ) / portTICK_RATE_MS )
#define bktPRIMARY_BLOCK_TIME ( 10 )
#define bktALLOWABLE_MARGIN ( 12 )
#define bktTIME_TO_BLOCK ( 175 )
#define bktDONT_BLOCK ( ( portTickType ) 0 )
#define bktRUN_INDICATOR ( ( unsigned portBASE_TYPE ) 0x55 )
/* The queue on which the tasks block. */
static xQueueHandle xTestQueue;
/* Handle to the secondary task is required by the primary task for calls
to vTaskSuspend/Resume(). */
static xTaskHandle xSecondary;
/* Used to ensure that tasks are still executing without error. */
static portBASE_TYPE xPrimaryCycles = 0, xSecondaryCycles = 0;
static portBASE_TYPE xErrorOccurred = pdFALSE;
/* Provides a simple mechanism for the primary task to know when the
secondary task has executed. */
static volatile unsigned portBASE_TYPE xRunIndicator;
/* The two test tasks. Their behaviour is commented within the files. */
static void vPrimaryBlockTimeTestTask( void *pvParameters );
static void vSecondaryBlockTimeTestTask( void *pvParameters );
/*-----------------------------------------------------------*/
void vCreateAltBlockTimeTasks( void )
{
/* Create the queue on which the two tasks block. */
xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( portBASE_TYPE ) );
/* Create the two test tasks. */
xTaskCreate( vPrimaryBlockTimeTestTask, ( signed portCHAR * )"FBTest1", configMINIMAL_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL );
xTaskCreate( vSecondaryBlockTimeTestTask, ( signed portCHAR * )"FBTest2", configMINIMAL_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary );
}
/*-----------------------------------------------------------*/
static void vPrimaryBlockTimeTestTask( void *pvParameters )
{
portBASE_TYPE xItem, xData;
portTickType xTimeWhenBlocking;
portTickType xTimeToBlock, xBlockedTime;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Alt primary block time test started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
( void ) pvParameters;
for( ;; )
{
/*********************************************************************
Test 1
Simple block time wakeup test on queue receives. */
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
/* The queue is empty. Attempt to read from the queue using a block
time. When we wake, ensure the delta in time is as expected. */
xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem;
/* A critical section is used to minimise the jitter in the time
measurements. */
portENTER_CRITICAL();
{
xTimeWhenBlocking = xTaskGetTickCount();
/* We should unblock after xTimeToBlock having not received
anything on the queue. */
if( xQueueAltReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY )
{
xErrorOccurred = pdTRUE;
}
/* How long were we blocked for? */
xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
}
portEXIT_CRITICAL();
if( xBlockedTime < xTimeToBlock )
{
/* Should not have blocked for less than we requested. */
xErrorOccurred = pdTRUE;
}
if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )
{
/* Should not have blocked for longer than we requested,
although we would not necessarily run as soon as we were
unblocked so a margin is allowed. */
xErrorOccurred = pdTRUE;
}
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/*********************************************************************
Test 2
Simple block time wakeup test on queue sends.
First fill the queue. It should be empty so all sends should pass. */
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
if( xQueueAltSendToBack( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
}
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
/* The queue is full. Attempt to write to the queue using a block
time. When we wake, ensure the delta in time is as expected. */
xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem;
portENTER_CRITICAL();
{
xTimeWhenBlocking = xTaskGetTickCount();
/* We should unblock after xTimeToBlock having not received
anything on the queue. */
if( xQueueAltSendToBack( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL )
{
xErrorOccurred = pdTRUE;
}
/* How long were we blocked for? */
xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
}
portEXIT_CRITICAL();
if( xBlockedTime < xTimeToBlock )
{
/* Should not have blocked for less than we requested. */
xErrorOccurred = pdTRUE;
}
if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )
{
/* Should not have blocked for longer than we requested,
although we would not necessarily run as soon as we were
unblocked so a margin is allowed. */
xErrorOccurred = pdTRUE;
}
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/*********************************************************************
Test 3
Wake the other task, it will block attempting to post to the queue.
When we read from the queue the other task will wake, but before it
can run we will post to the queue again. When the other task runs it
will find the queue still full, even though it was woken. It should
recognise that its block time has not expired and return to block for
the remains of its block time.
Wake the other task so it blocks attempting to post to the already
full queue. */
xRunIndicator = 0;
vTaskResume( xSecondary );
/* We need to wait a little to ensure the other task executes. */
while( xRunIndicator != bktRUN_INDICATOR )
{
/* The other task has not yet executed. */
vTaskDelay( bktSHORT_WAIT );
}
/* Make sure the other task is blocked on the queue. */
vTaskDelay( bktSHORT_WAIT );
xRunIndicator = 0;
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
/* Now when we make space on the queue the other task should wake
but not execute as this task has higher priority. */
if( xQueueAltReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
/* Now fill the queue again before the other task gets a chance to
execute. If the other task had executed we would find the queue
full ourselves, and the other task have set xRunIndicator. */
if( xQueueAltSendToBack( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
if( xRunIndicator == bktRUN_INDICATOR )
{
/* The other task should not have executed. */
xErrorOccurred = pdTRUE;
}
/* Raise the priority of the other task so it executes and blocks
on the queue again. */
vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );
/* The other task should now have re-blocked without exiting the
queue function. */
if( xRunIndicator == bktRUN_INDICATOR )
{
/* The other task should not have executed outside of the
queue function. */
xErrorOccurred = pdTRUE;
}
/* Set the priority back down. */
vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );
}
/* Let the other task timeout. When it unblockes it will check that it
unblocked at the correct time, then suspend itself. */
while( xRunIndicator != bktRUN_INDICATOR )
{
vTaskDelay( bktSHORT_WAIT );
}
vTaskDelay( bktSHORT_WAIT );
xRunIndicator = 0;
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/*********************************************************************
Test 4
As per test 3 - but with the send and receive the other way around.
The other task blocks attempting to read from the queue.
Empty the queue. We should find that it is full. */
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
if( xQueueAltReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
}
/* Wake the other task so it blocks attempting to read from the
already empty queue. */
vTaskResume( xSecondary );
/* We need to wait a little to ensure the other task executes. */
while( xRunIndicator != bktRUN_INDICATOR )
{
vTaskDelay( bktSHORT_WAIT );
}
vTaskDelay( bktSHORT_WAIT );
xRunIndicator = 0;
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
/* Now when we place an item on the queue the other task should
wake but not execute as this task has higher priority. */
if( xQueueAltSendToBack( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
/* Now empty the queue again before the other task gets a chance to
execute. If the other task had executed we would find the queue
empty ourselves, and the other task would be suspended. */
if( xQueueAltReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
if( xRunIndicator == bktRUN_INDICATOR )
{
/* The other task should not have executed. */
xErrorOccurred = pdTRUE;
}
/* Raise the priority of the other task so it executes and blocks
on the queue again. */
vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );
/* The other task should now have re-blocked without exiting the
queue function. */
if( xRunIndicator == bktRUN_INDICATOR )
{
/* The other task should not have executed outside of the
queue function. */
xErrorOccurred = pdTRUE;
}
vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );
}
/* Let the other task timeout. When it unblockes it will check that it
unblocked at the correct time, then suspend itself. */
while( xRunIndicator != bktRUN_INDICATOR )
{
vTaskDelay( bktSHORT_WAIT );
}
vTaskDelay( bktSHORT_WAIT );
xPrimaryCycles++;
}
}
/*-----------------------------------------------------------*/
static void vSecondaryBlockTimeTestTask( void *pvParameters )
{
portTickType xTimeWhenBlocking, xBlockedTime;
portBASE_TYPE xData;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Alt secondary block time test started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
( void ) pvParameters;
for( ;; )
{
/*********************************************************************
Test 1 and 2
This task does does not participate in these tests. */
vTaskSuspend( NULL );
/*********************************************************************
Test 3
The first thing we do is attempt to read from the queue. It should be
full so we block. Note the time before we block so we can check the
wake time is as per that expected. */
portENTER_CRITICAL();
{
xTimeWhenBlocking = xTaskGetTickCount();
/* We should unblock after bktTIME_TO_BLOCK having not received
anything on the queue. */
xData = 0;
xRunIndicator = bktRUN_INDICATOR;
if( xQueueAltSendToBack( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL )
{
xErrorOccurred = pdTRUE;
}
/* How long were we inside the send function? */
xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
}
portEXIT_CRITICAL();
/* We should not have blocked for less time than bktTIME_TO_BLOCK. */
if( xBlockedTime < bktTIME_TO_BLOCK )
{
xErrorOccurred = pdTRUE;
}
/* We should of not blocked for much longer than bktALLOWABLE_MARGIN
either. A margin is permitted as we would not necessarily run as
soon as we unblocked. */
if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )
{
xErrorOccurred = pdTRUE;
}
/* Suspend ready for test 3. */
xRunIndicator = bktRUN_INDICATOR;
vTaskSuspend( NULL );
/*********************************************************************
Test 4
As per test three, but with the send and receive reversed. */
portENTER_CRITICAL();
{
xTimeWhenBlocking = xTaskGetTickCount();
/* We should unblock after bktTIME_TO_BLOCK having not received
anything on the queue. */
xRunIndicator = bktRUN_INDICATOR;
if( xQueueAltReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY )
{
xErrorOccurred = pdTRUE;
}
xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
}
portEXIT_CRITICAL();
/* We should not have blocked for less time than bktTIME_TO_BLOCK. */
if( xBlockedTime < bktTIME_TO_BLOCK )
{
xErrorOccurred = pdTRUE;
}
/* We should of not blocked for much longer than bktALLOWABLE_MARGIN
either. A margin is permitted as we would not necessarily run as soon
as we unblocked. */
if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )
{
xErrorOccurred = pdTRUE;
}
xRunIndicator = bktRUN_INDICATOR;
xSecondaryCycles++;
}
}
/*-----------------------------------------------------------*/
portBASE_TYPE xAreAltBlockTimeTestTasksStillRunning( void )
{
static portBASE_TYPE xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0;
portBASE_TYPE xReturn = pdPASS;
/* Have both tasks performed at least one cycle since this function was
last called? */
if( xPrimaryCycles == xLastPrimaryCycleCount )
{
xReturn = pdFAIL;
}
if( xSecondaryCycles == xLastSecondaryCycleCount )
{
xReturn = pdFAIL;
}
if( xErrorOccurred == pdTRUE )
{
xReturn = pdFAIL;
}
xLastSecondaryCycleCount = xSecondaryCycles;
xLastPrimaryCycleCount = xPrimaryCycles;
return xReturn;
}

243
20080212/Demo/Common/Minimal/AltPollQ.c Normal file
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@ -0,0 +1,243 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* This is a version of PollQ.c that uses the alternative (Alt) API.
*
* Creates two tasks that communicate over a single queue. One task acts as a
* producer, the other a consumer.
*
* The producer loops for three iteration, posting an incrementing number onto the
* queue each cycle. It then delays for a fixed period before doing exactly the
* same again.
*
* The consumer loops emptying the queue. Each item removed from the queue is
* checked to ensure it contains the expected value. When the queue is empty it
* blocks for a fixed period, then does the same again.
*
* All queue access is performed without blocking. The consumer completely empties
* the queue each time it runs so the producer should never find the queue full.
*
* An error is flagged if the consumer obtains an unexpected value or the producer
* find the queue is full.
*/
/*
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Demo program include files. */
#include "AltPollQ.h"
#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE
#define pollqQUEUE_SIZE ( 10 )
#define pollqPRODUCER_DELAY ( ( portTickType ) 200 / portTICK_RATE_MS )
#define pollqCONSUMER_DELAY ( pollqPRODUCER_DELAY - ( portTickType ) ( 20 / portTICK_RATE_MS ) )
#define pollqNO_DELAY ( ( portTickType ) 0 )
#define pollqVALUES_TO_PRODUCE ( ( signed portBASE_TYPE ) 3 )
#define pollqINITIAL_VALUE ( ( signed portBASE_TYPE ) 0 )
/* The task that posts the incrementing number onto the queue. */
static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters );
/* The task that empties the queue. */
static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters );
/* Variables that are used to check that the tasks are still running with no
errors. */
static volatile signed portBASE_TYPE xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE;
/*-----------------------------------------------------------*/
void vStartAltPolledQueueTasks( unsigned portBASE_TYPE uxPriority )
{
static xQueueHandle xPolledQueue;
/* Create the queue used by the producer and consumer. */
xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
/* Spawn the producer and consumer. */
xTaskCreate( vPolledQueueConsumer, ( signed portCHAR * ) "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL );
xTaskCreate( vPolledQueueProducer, ( signed portCHAR * ) "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vPolledQueueProducer, pvParameters )
{
unsigned portSHORT usValue = ( unsigned portSHORT ) 0;
signed portBASE_TYPE xError = pdFALSE, xLoop;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Alt polling queue producer task started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
for( ;; )
{
for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ )
{
/* Send an incrementing number on the queue without blocking. */
if( xQueueAltSendToBack( *( ( xQueueHandle * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS )
{
/* We should never find the queue full so if we get here there
has been an error. */
xError = pdTRUE;
}
else
{
if( xError == pdFALSE )
{
/* If an error has ever been recorded we stop incrementing the
check variable. */
portENTER_CRITICAL();
xPollingProducerCount++;
portEXIT_CRITICAL();
}
/* Update the value we are going to post next time around. */
usValue++;
}
}
/* Wait before we start posting again to ensure the consumer runs and
empties the queue. */
vTaskDelay( pollqPRODUCER_DELAY );
}
} /*lint !e818 Function prototype must conform to API. */
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters )
{
unsigned portSHORT usData, usExpectedValue = ( unsigned portSHORT ) 0;
signed portBASE_TYPE xError = pdFALSE;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Alt blocking queue consumer task started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
for( ;; )
{
/* Loop until the queue is empty. */
while( uxQueueMessagesWaiting( *( ( xQueueHandle * ) pvParameters ) ) )
{
if( xQueueAltReceive( *( ( xQueueHandle * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS )
{
if( usData != usExpectedValue )
{
/* This is not what we expected to receive so an error has
occurred. */
xError = pdTRUE;
/* Catch-up to the value we received so our next expected
value should again be correct. */
usExpectedValue = usData;
}
else
{
if( xError == pdFALSE )
{
/* Only increment the check variable if no errors have
occurred. */
portENTER_CRITICAL();
xPollingConsumerCount++;
portEXIT_CRITICAL();
}
}
/* Next time round we would expect the number to be one higher. */
usExpectedValue++;
}
}
/* Now the queue is empty we block, allowing the producer to place more
items in the queue. */
vTaskDelay( pollqCONSUMER_DELAY );
}
} /*lint !e818 Function prototype must conform to API. */
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running with no errors. */
portBASE_TYPE xAreAltPollingQueuesStillRunning( void )
{
portBASE_TYPE xReturn;
/* Check both the consumer and producer poll count to check they have both
been changed since out last trip round. We do not need a critical section
around the check variables as this is called from a higher priority than
the other tasks that access the same variables. */
if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) ||
( xPollingProducerCount == pollqINITIAL_VALUE )
)
{
xReturn = pdFALSE;
}
else
{
xReturn = pdTRUE;
}
/* Set the check variables back down so we know if they have been
incremented the next time around. */
xPollingConsumerCount = pollqINITIAL_VALUE;
xPollingProducerCount = pollqINITIAL_VALUE;
return xReturn;
}

548
20080212/Demo/Common/Minimal/AltQTest.c Normal file
View file

@ -0,0 +1,548 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* This file implements the same demo and test as GenQTest.c, but uses the
* light weight API in place of the fully featured API.
*
* See the comments at the top of GenQTest.c for a description.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
/* Demo program include files. */
#include "AltQTest.h"
#define genqQUEUE_LENGTH ( 5 )
#define genqNO_BLOCK ( 0 )
#define genqMUTEX_LOW_PRIORITY ( tskIDLE_PRIORITY )
#define genqMUTEX_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define genqMUTEX_MEDIUM_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define genqMUTEX_HIGH_PRIORITY ( tskIDLE_PRIORITY + 3 )
/*-----------------------------------------------------------*/
/*
* Tests the behaviour of the xQueueAltSendToFront() and xQueueAltSendToBack()
* macros by using both to fill a queue, then reading from the queue to
* check the resultant queue order is as expected. Queue data is also
* peeked.
*/
static void prvSendFrontAndBackTest( void *pvParameters );
/*
* The following three tasks are used to demonstrate the mutex behaviour.
* Each task is given a different priority to demonstrate the priority
* inheritance mechanism.
*
* The low priority task obtains a mutex. After this a high priority task
* attempts to obtain the same mutex, causing its priority to be inherited
* by the low priority task. The task with the inherited high priority then
* resumes a medium priority task to ensure it is not blocked by the medium
* priority task while it holds the inherited high priority. Once the mutex
* is returned the task with the inherited priority returns to its original
* low priority, and is therefore immediately preempted by first the high
* priority task and then the medium prioroity task before it can continue.
*/
static void prvLowPriorityMutexTask( void *pvParameters );
static void prvMediumPriorityMutexTask( void *pvParameters );
static void prvHighPriorityMutexTask( void *pvParameters );
/*-----------------------------------------------------------*/
/* Flag that will be latched to pdTRUE should any unexpected behaviour be
detected in any of the tasks. */
static portBASE_TYPE xErrorDetected = pdFALSE;
/* Counters that are incremented on each cycle of a test. This is used to
detect a stalled task - a test that is no longer running. */
static volatile unsigned portLONG ulLoopCounter = 0;
static volatile unsigned portLONG ulLoopCounter2 = 0;
/* The variable that is guarded by the mutex in the mutex demo tasks. */
static volatile unsigned portLONG ulGuardedVariable = 0;
/* Handles used in the mutext test to suspend and resume the high and medium
priority mutex test tasks. */
static xTaskHandle xHighPriorityMutexTask, xMediumPriorityMutexTask;
/*-----------------------------------------------------------*/
void vStartAltGenericQueueTasks( unsigned portBASE_TYPE uxPriority )
{
xQueueHandle xQueue;
xSemaphoreHandle xMutex;
/* Create the queue that we are going to use for the
prvSendFrontAndBackTest demo. */
xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( unsigned portLONG ) );
/* Create the demo task and pass it the queue just created. We are
passing the queue handle by value so it does not matter that it is
declared on the stack here. */
xTaskCreate( prvSendFrontAndBackTest, ( signed portCHAR * ) "FGenQ", configMINIMAL_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL );
/* Create the mutex used by the prvMutexTest task. */
xMutex = xSemaphoreCreateMutex();
/* Create the mutex demo tasks and pass it the mutex just created. We are
passing the mutex handle by value so it does not matter that it is declared
on the stack here. */
xTaskCreate( prvLowPriorityMutexTask, ( signed portCHAR * ) "FMuLow", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL );
xTaskCreate( prvMediumPriorityMutexTask, ( signed portCHAR * ) "FMuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask );
xTaskCreate( prvHighPriorityMutexTask, ( signed portCHAR * ) "FMuHigh", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask );
}
/*-----------------------------------------------------------*/
static void prvSendFrontAndBackTest( void *pvParameters )
{
unsigned portLONG ulData, ulData2;
xQueueHandle xQueue;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Alt queue SendToFront/SendToBack/Peek test started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
xQueue = ( xQueueHandle ) pvParameters;
for( ;; )
{
/* The queue is empty, so sending an item to the back of the queue
should have the same efect as sending it to the front of the queue.
First send to the front and check everything is as expected. */
xQueueAltSendToFront( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK );
if( uxQueueMessagesWaiting( xQueue ) != 1 )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* The data we sent to the queue should equal the data we just received
from the queue. */
if( ulLoopCounter != ulData )
{
xErrorDetected = pdTRUE;
}
/* Then do the same, sending the data to the back, checking everything
is as expected. */
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
xQueueAltSendToBack( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK );
if( uxQueueMessagesWaiting( xQueue ) != 1 )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
/* The data we sent to the queue should equal the data we just received
from the queue. */
if( ulLoopCounter != ulData )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Place 2, 3, 4 into the queue, adding items to the back of the queue. */
for( ulData = 2; ulData < 5; ulData++ )
{
xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK );
}
/* Now the order in the queue should be 2, 3, 4, with 2 being the first
thing to be read out. Now add 1 then 0 to the front of the queue. */
if( uxQueueMessagesWaiting( xQueue ) != 3 )
{
xErrorDetected = pdTRUE;
}
ulData = 1;
xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK );
ulData = 0;
xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK );
/* Now the queue should be full, and when we read the data out we
should receive 0, 1, 2, 3, 4. */
if( uxQueueMessagesWaiting( xQueue ) != 5 )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Check the data we read out is in the expected order. */
for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ )
{
/* Try peeking the data first. */
if( xQueueAltPeek( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( ulData != ulData2 )
{
xErrorDetected = pdTRUE;
}
/* Now try receiving the data for real. The value should be the
same. Clobber the value first so we know we really received it. */
ulData2 = ~ulData2;
if( xQueueAltReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( ulData != ulData2 )
{
xErrorDetected = pdTRUE;
}
}
/* The queue should now be empty again. */
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Our queue is empty once more, add 10, 11 to the back. */
ulData = 10;
if( xQueueAltSendToBack( xQueue, &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
ulData = 11;
if( xQueueAltSendToBack( xQueue, &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( uxQueueMessagesWaiting( xQueue ) != 2 )
{
xErrorDetected = pdTRUE;
}
/* Now we should have 10, 11 in the queue. Add 7, 8, 9 to the
front. */
for( ulData = 9; ulData >= 7; ulData-- )
{
if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
}
/* Now check that the queue is full, and that receiving data provides
the expected sequence of 7, 8, 9, 10, 11. */
if( uxQueueMessagesWaiting( xQueue ) != 5 )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Check the data we read out is in the expected order. */
for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ )
{
if( xQueueAltReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( ulData != ulData2 )
{
xErrorDetected = pdTRUE;
}
}
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
ulLoopCounter++;
}
}
/*-----------------------------------------------------------*/
static void prvLowPriorityMutexTask( void *pvParameters )
{
xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Fast mutex with priority inheritance test started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
( void ) pvParameters;
for( ;; )
{
/* Take the mutex. It should be available now. */
if( xSemaphoreAltTake( xMutex, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* Set our guarded variable to a known start value. */
ulGuardedVariable = 0;
/* Our priority should be as per that assigned when the task was
created. */
if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* Now unsuspend the high priority task. This will attempt to take the
mutex, and block when it finds it cannot obtain it. */
vTaskResume( xHighPriorityMutexTask );
/* We should now have inherited the prioritoy of the high priority task,
as by now it will have attempted to get the mutex. */
if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* We can attempt to set our priority to the test priority - between the
idle priority and the medium/high test priorities, but our actual
prioroity should remain at the high priority. */
vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY );
if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* Now unsuspend the medium priority task. This should not run as our
inherited priority is above that of the medium priority task. */
vTaskResume( xMediumPriorityMutexTask );
/* If the did run then it will have incremented our guarded variable. */
if( ulGuardedVariable != 0 )
{
xErrorDetected = pdTRUE;
}
/* When we give back the semaphore our priority should be disinherited
back to the priority to which we attempted to set ourselves. This means
that when the high priority task next blocks, the medium priority task
should execute and increment the guarded variable. When we next run
both the high and medium priority tasks will have been suspended again. */
if( xSemaphoreAltGive( xMutex ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* Check that the guarded variable did indeed increment... */
if( ulGuardedVariable != 1 )
{
xErrorDetected = pdTRUE;
}
/* ... and that our priority has been disinherited to
genqMUTEX_TEST_PRIORITY. */
if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* Set our priority back to our original priority ready for the next
loop around this test. */
vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY );
/* Just to show we are still running. */
ulLoopCounter2++;
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
}
}
/*-----------------------------------------------------------*/
static void prvMediumPriorityMutexTask( void *pvParameters )
{
( void ) pvParameters;
for( ;; )
{
/* The medium priority task starts by suspending itself. The low
priority task will unsuspend this task when required. */
vTaskSuspend( NULL );
/* When this task unsuspends all it does is increment the guarded
variable, this is so the low priority task knows that it has
executed. */
ulGuardedVariable++;
}
}
/*-----------------------------------------------------------*/
static void prvHighPriorityMutexTask( void *pvParameters )
{
xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters;
( void ) pvParameters;
for( ;; )
{
/* The high priority task starts by suspending itself. The low
priority task will unsuspend this task when required. */
vTaskSuspend( NULL );
/* When this task unsuspends all it does is attempt to obtain
the mutex. It should find the mutex is not available so a
block time is specified. */
if( xSemaphoreAltTake( xMutex, portMAX_DELAY ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* When we eventually obtain the mutex we just give it back then
return to suspend ready for the next test. */
if( xSemaphoreAltGive( xMutex ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreAltGenericQueueTasksStillRunning( void )
{
static unsigned portLONG ulLastLoopCounter = 0, ulLastLoopCounter2 = 0;
/* If the demo task is still running then we expect the loopcounters to
have incremented since this function was last called. */
if( ulLastLoopCounter == ulLoopCounter )
{
xErrorDetected = pdTRUE;
}
if( ulLastLoopCounter2 == ulLoopCounter2 )
{
xErrorDetected = pdTRUE;
}
ulLastLoopCounter = ulLoopCounter;
ulLastLoopCounter2 = ulLoopCounter2;
/* Errors detected in the task itself will have latched xErrorDetected
to true. */
return !xErrorDetected;
}

297
20080212/Demo/Common/Minimal/BlockQ.c Normal file
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@ -0,0 +1,297 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* Creates six tasks that operate on three queues as follows:
*
* The first two tasks send and receive an incrementing number to/from a queue.
* One task acts as a producer and the other as the consumer. The consumer is a
* higher priority than the producer and is set to block on queue reads. The queue
* only has space for one item - as soon as the producer posts a message on the
* queue the consumer will unblock, pre-empt the producer, and remove the item.
*
* The second two tasks work the other way around. Again the queue used only has
* enough space for one item. This time the consumer has a lower priority than the
* producer. The producer will try to post on the queue blocking when the queue is
* full. When the consumer wakes it will remove the item from the queue, causing
* the producer to unblock, pre-empt the consumer, and immediately re-fill the
* queue.
*
* The last two tasks use the same queue producer and consumer functions. This time the queue has
* enough space for lots of items and the tasks operate at the same priority. The
* producer will execute, placing items into the queue. The consumer will start
* executing when either the queue becomes full (causing the producer to block) or
* a context switch occurs (tasks of the same priority will time slice).
*
*/
/*
Changes from V4.1.1
+ The second set of tasks were created the wrong way around. This has been
corrected.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Demo program include files. */
#include "BlockQ.h"
#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE
#define blckqNUM_TASK_SETS ( 3 )
/* Structure used to pass parameters to the blocking queue tasks. */
typedef struct BLOCKING_QUEUE_PARAMETERS
{
xQueueHandle xQueue; /*< The queue to be used by the task. */
portTickType xBlockTime; /*< The block time to use on queue reads/writes. */
volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */
} xBlockingQueueParameters;
/* Task function that creates an incrementing number and posts it on a queue. */
static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters );
/* Task function that removes the incrementing number from a queue and checks that
it is the expected number. */
static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters );
/* Variables which are incremented each time an item is removed from a queue, and
found to be the expected value.
These are used to check that the tasks are still running. */
static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };
/* Variable which are incremented each time an item is posted on a queue. These
are used to check that the tasks are still running. */
static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };
/*-----------------------------------------------------------*/
void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority )
{
xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2;
xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4;
xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6;
const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5;
const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS;
const portTickType xDontBlock = ( portTickType ) 0;
/* Create the first two tasks as described at the top of the file. */
/* First create the structure used to pass parameters to the consumer tasks. */
pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
/* Create the queue used by the first two tasks to pass the incrementing number.
Pass a pointer to the queue in the parameter structure. */
pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
/* The consumer is created first so gets a block time as described above. */
pxQueueParameters1->xBlockTime = xBlockTime;
/* Pass in the variable that this task is going to increment so we can check it
is still running. */
pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );
/* Create the structure used to pass parameters to the producer task. */
pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
/* Pass the queue to this task also, using the parameter structure. */
pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;
/* The producer is not going to block - as soon as it posts the consumer will
wake and remove the item so the producer should always have room to post. */
pxQueueParameters2->xBlockTime = xDontBlock;
/* Pass in the variable that this task is going to increment so we can check
it is still running. */
pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );
/* Note the producer has a lower priority than the consumer when the tasks are
spawned. */
xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );
xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );
/* Create the second two tasks as described at the top of the file. This uses
the same mechanism but reverses the task priorities. */
pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
pxQueueParameters3->xBlockTime = xDontBlock;
pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );
pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;
pxQueueParameters4->xBlockTime = xBlockTime;
pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );
xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );
xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );
/* Create the last two tasks as described above. The mechanism is again just
the same. This time both parameter structures are given a block time. */
pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
pxQueueParameters5->xBlockTime = xBlockTime;
pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );
pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;
pxQueueParameters6->xBlockTime = xBlockTime;
pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] );
xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );
xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters )
{
unsigned portSHORT usValue = 0;
xBlockingQueueParameters *pxQueueParameters;
portSHORT sErrorEverOccurred = pdFALSE;
pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
for( ;; )
{
if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )
{
sErrorEverOccurred = pdTRUE;
}
else
{
/* We have successfully posted a message, so increment the variable
used to check we are still running. */
if( sErrorEverOccurred == pdFALSE )
{
( *pxQueueParameters->psCheckVariable )++;
}
/* Increment the variable we are going to post next time round. The
consumer will expect the numbers to follow in numerical order. */
++usValue;
}
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters )
{
unsigned portSHORT usData, usExpectedValue = 0;
xBlockingQueueParameters *pxQueueParameters;
portSHORT sErrorEverOccurred = pdFALSE;
pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
for( ;; )
{
if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )
{
if( usData != usExpectedValue )
{
/* Catch-up. */
usExpectedValue = usData;
sErrorEverOccurred = pdTRUE;
}
else
{
/* We have successfully received a message, so increment the
variable used to check we are still running. */
if( sErrorEverOccurred == pdFALSE )
{
( *pxQueueParameters->psCheckVariable )++;
}
/* Increment the value we expect to remove from the queue next time
round. */
++usExpectedValue;
}
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreBlockingQueuesStillRunning( void )
{
static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };
static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 };
portBASE_TYPE xReturn = pdPASS, xTasks;
/* Not too worried about mutual exclusion on these variables as they are 16
bits and we are only reading them. We also only care to see if they have
changed or not.
Loop through each check variable to and return pdFALSE if any are found not
to have changed since the last call. */
for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )
{
if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] )
{
xReturn = pdFALSE;
}
sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];
if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] )
{
xReturn = pdFALSE;
}
sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];
}
return xReturn;
}

545
20080212/Demo/Common/Minimal/GenQTest.c Normal file
View file

@ -0,0 +1,545 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* Tests the extra queue functionality introduced in FreeRTOS.org V4.5.0 -
* including xQueueSendToFront(), xQueueSendToBack(), xQueuePeek() and
* mutex behaviour.
*
* See the comments above the prvSendFrontAndBackTest() and
* prvLowPriorityMutexTask() prototypes below for more information.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
/* Demo program include files. */
#include "GenQTest.h"
#define genqQUEUE_LENGTH ( 5 )
#define genqNO_BLOCK ( 0 )
#define genqMUTEX_LOW_PRIORITY ( tskIDLE_PRIORITY )
#define genqMUTEX_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define genqMUTEX_MEDIUM_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define genqMUTEX_HIGH_PRIORITY ( tskIDLE_PRIORITY + 3 )
/*-----------------------------------------------------------*/
/*
* Tests the behaviour of the xQueueSendToFront() and xQueueSendToBack()
* macros by using both to fill a queue, then reading from the queue to
* check the resultant queue order is as expected. Queue data is also
* peeked.
*/
static void prvSendFrontAndBackTest( void *pvParameters );
/*
* The following three tasks are used to demonstrate the mutex behaviour.
* Each task is given a different priority to demonstrate the priority
* inheritance mechanism.
*
* The low priority task obtains a mutex. After this a high priority task
* attempts to obtain the same mutex, causing its priority to be inherited
* by the low priority task. The task with the inherited high priority then
* resumes a medium priority task to ensure it is not blocked by the medium
* priority task while it holds the inherited high priority. Once the mutex
* is returned the task with the inherited priority returns to its original
* low priority, and is therefore immediately preempted by first the high
* priority task and then the medium prioroity task before it can continue.
*/
static void prvLowPriorityMutexTask( void *pvParameters );
static void prvMediumPriorityMutexTask( void *pvParameters );
static void prvHighPriorityMutexTask( void *pvParameters );
/*-----------------------------------------------------------*/
/* Flag that will be latched to pdTRUE should any unexpected behaviour be
detected in any of the tasks. */
static portBASE_TYPE xErrorDetected = pdFALSE;
/* Counters that are incremented on each cycle of a test. This is used to
detect a stalled task - a test that is no longer running. */
static volatile unsigned portLONG ulLoopCounter = 0;
static volatile unsigned portLONG ulLoopCounter2 = 0;
/* The variable that is guarded by the mutex in the mutex demo tasks. */
static volatile unsigned portLONG ulGuardedVariable = 0;
/* Handles used in the mutext test to suspend and resume the high and medium
priority mutex test tasks. */
static xTaskHandle xHighPriorityMutexTask, xMediumPriorityMutexTask;
/*-----------------------------------------------------------*/
void vStartGenericQueueTasks( unsigned portBASE_TYPE uxPriority )
{
xQueueHandle xQueue;
xSemaphoreHandle xMutex;
/* Create the queue that we are going to use for the
prvSendFrontAndBackTest demo. */
xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( unsigned portLONG ) );
/* Create the demo task and pass it the queue just created. We are
passing the queue handle by value so it does not matter that it is
declared on the stack here. */
xTaskCreate( prvSendFrontAndBackTest, ( signed portCHAR * )"GenQ", configMINIMAL_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL );
/* Create the mutex used by the prvMutexTest task. */
xMutex = xSemaphoreCreateMutex();
/* Create the mutex demo tasks and pass it the mutex just created. We are
passing the mutex handle by value so it does not matter that it is declared
on the stack here. */
xTaskCreate( prvLowPriorityMutexTask, ( signed portCHAR * )"MuLow", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL );
xTaskCreate( prvMediumPriorityMutexTask, ( signed portCHAR * )"MuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask );
xTaskCreate( prvHighPriorityMutexTask, ( signed portCHAR * )"MuHigh", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask );
}
/*-----------------------------------------------------------*/
static void prvSendFrontAndBackTest( void *pvParameters )
{
unsigned portLONG ulData, ulData2;
xQueueHandle xQueue;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Queue SendToFront/SendToBack/Peek test started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
xQueue = ( xQueueHandle ) pvParameters;
for( ;; )
{
/* The queue is empty, so sending an item to the back of the queue
should have the same efect as sending it to the front of the queue.
First send to the front and check everything is as expected. */
xQueueSendToFront( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK );
if( uxQueueMessagesWaiting( xQueue ) != 1 )
{
xErrorDetected = pdTRUE;
}
if( xQueueReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* The data we sent to the queue should equal the data we just received
from the queue. */
if( ulLoopCounter != ulData )
{
xErrorDetected = pdTRUE;
}
/* Then do the same, sending the data to the back, checking everything
is as expected. */
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
xQueueSendToBack( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK );
if( uxQueueMessagesWaiting( xQueue ) != 1 )
{
xErrorDetected = pdTRUE;
}
if( xQueueReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
/* The data we sent to the queue should equal the data we just received
from the queue. */
if( ulLoopCounter != ulData )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Place 2, 3, 4 into the queue, adding items to the back of the queue. */
for( ulData = 2; ulData < 5; ulData++ )
{
xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK );
}
/* Now the order in the queue should be 2, 3, 4, with 2 being the first
thing to be read out. Now add 1 then 0 to the front of the queue. */
if( uxQueueMessagesWaiting( xQueue ) != 3 )
{
xErrorDetected = pdTRUE;
}
ulData = 1;
xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK );
ulData = 0;
xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK );
/* Now the queue should be full, and when we read the data out we
should receive 0, 1, 2, 3, 4. */
if( uxQueueMessagesWaiting( xQueue ) != 5 )
{
xErrorDetected = pdTRUE;
}
if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
if( xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Check the data we read out is in the expected order. */
for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ )
{
/* Try peeking the data first. */
if( xQueuePeek( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( ulData != ulData2 )
{
xErrorDetected = pdTRUE;
}
/* Now try receiving the data for real. The value should be the
same. Clobber the value first so we know we really received it. */
ulData2 = ~ulData2;
if( xQueueReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( ulData != ulData2 )
{
xErrorDetected = pdTRUE;
}
}
/* The queue should now be empty again. */
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Our queue is empty once more, add 10, 11 to the back. */
ulData = 10;
if( xQueueSend( xQueue, &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
ulData = 11;
if( xQueueSend( xQueue, &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( uxQueueMessagesWaiting( xQueue ) != 2 )
{
xErrorDetected = pdTRUE;
}
/* Now we should have 10, 11 in the queue. Add 7, 8, 9 to the
front. */
for( ulData = 9; ulData >= 7; ulData-- )
{
if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
}
/* Now check that the queue is full, and that receiving data provides
the expected sequence of 7, 8, 9, 10, 11. */
if( uxQueueMessagesWaiting( xQueue ) != 5 )
{
xErrorDetected = pdTRUE;
}
if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
if( xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Check the data we read out is in the expected order. */
for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ )
{
if( xQueueReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( ulData != ulData2 )
{
xErrorDetected = pdTRUE;
}
}
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
ulLoopCounter++;
}
}
/*-----------------------------------------------------------*/
static void prvLowPriorityMutexTask( void *pvParameters )
{
xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Mutex with priority inheritance test started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
for( ;; )
{
/* Take the mutex. It should be available now. */
if( xSemaphoreTake( xMutex, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* Set our guarded variable to a known start value. */
ulGuardedVariable = 0;
/* Our priority should be as per that assigned when the task was
created. */
if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* Now unsuspend the high priority task. This will attempt to take the
mutex, and block when it finds it cannot obtain it. */
vTaskResume( xHighPriorityMutexTask );
/* We should now have inherited the prioritoy of the high priority task,
as by now it will have attempted to get the mutex. */
if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* We can attempt to set our priority to the test priority - between the
idle priority and the medium/high test priorities, but our actual
prioroity should remain at the high priority. */
vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY );
if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* Now unsuspend the medium priority task. This should not run as our
inherited priority is above that of the medium priority task. */
vTaskResume( xMediumPriorityMutexTask );
/* If the did run then it will have incremented our guarded variable. */
if( ulGuardedVariable != 0 )
{
xErrorDetected = pdTRUE;
}
/* When we give back the semaphore our priority should be disinherited
back to the priority to which we attempted to set ourselves. This means
that when the high priority task next blocks, the medium priority task
should execute and increment the guarded variable. When we next run
both the high and medium priority tasks will have been suspended again. */
if( xSemaphoreGive( xMutex ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* Check that the guarded variable did indeed increment... */
if( ulGuardedVariable != 1 )
{
xErrorDetected = pdTRUE;
}
/* ... and that our priority has been disinherited to
genqMUTEX_TEST_PRIORITY. */
if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* Set our priority back to our original priority ready for the next
loop around this test. */
vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY );
/* Just to show we are still running. */
ulLoopCounter2++;
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
}
}
/*-----------------------------------------------------------*/
static void prvMediumPriorityMutexTask( void *pvParameters )
{
( void ) pvParameters;
for( ;; )
{
/* The medium priority task starts by suspending itself. The low
priority task will unsuspend this task when required. */
vTaskSuspend( NULL );
/* When this task unsuspends all it does is increment the guarded
variable, this is so the low priority task knows that it has
executed. */
ulGuardedVariable++;
}
}
/*-----------------------------------------------------------*/
static void prvHighPriorityMutexTask( void *pvParameters )
{
xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters;
for( ;; )
{
/* The high priority task starts by suspending itself. The low
priority task will unsuspend this task when required. */
vTaskSuspend( NULL );
/* When this task unsuspends all it does is attempt to obtain
the mutex. It should find the mutex is not available so a
block time is specified. */
if( xSemaphoreTake( xMutex, portMAX_DELAY ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* When we eventually obtain the mutex we just give it back then
return to suspend ready for the next test. */
if( xSemaphoreGive( xMutex ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreGenericQueueTasksStillRunning( void )
{
static unsigned portLONG ulLastLoopCounter = 0, ulLastLoopCounter2 = 0;
/* If the demo task is still running then we expect the loopcounters to
have incremented since this function was last called. */
if( ulLastLoopCounter == ulLoopCounter )
{
xErrorDetected = pdTRUE;
}
if( ulLastLoopCounter2 == ulLoopCounter2 )
{
xErrorDetected = pdTRUE;
}
ulLastLoopCounter = ulLoopCounter;
ulLastLoopCounter2 = ulLoopCounter2;
/* Errors detected in the task itself will have latched xErrorDetected
to true. */
return !xErrorDetected;
}

227
20080212/Demo/Common/Minimal/PollQ.c Normal file
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@ -0,0 +1,227 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* This version of PollQ. c is for use on systems that have limited stack
* space and no display facilities. The complete version can be found in
* the Demo/Common/Full directory.
*
* Creates two tasks that communicate over a single queue. One task acts as a
* producer, the other a consumer.
*
* The producer loops for three iteration, posting an incrementing number onto the
* queue each cycle. It then delays for a fixed period before doing exactly the
* same again.
*
* The consumer loops emptying the queue. Each item removed from the queue is
* checked to ensure it contains the expected value. When the queue is empty it
* blocks for a fixed period, then does the same again.
*
* All queue access is performed without blocking. The consumer completely empties
* the queue each time it runs so the producer should never find the queue full.
*
* An error is flagged if the consumer obtains an unexpected value or the producer
* find the queue is full.
*/
/*
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Demo program include files. */
#include "PollQ.h"
#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE
#define pollqQUEUE_SIZE ( 10 )
#define pollqPRODUCER_DELAY ( ( portTickType ) 200 / portTICK_RATE_MS )
#define pollqCONSUMER_DELAY ( pollqPRODUCER_DELAY - ( portTickType ) ( 20 / portTICK_RATE_MS ) )
#define pollqNO_DELAY ( ( portTickType ) 0 )
#define pollqVALUES_TO_PRODUCE ( ( signed portBASE_TYPE ) 3 )
#define pollqINITIAL_VALUE ( ( signed portBASE_TYPE ) 0 )
/* The task that posts the incrementing number onto the queue. */
static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters );
/* The task that empties the queue. */
static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters );
/* Variables that are used to check that the tasks are still running with no
errors. */
static volatile signed portBASE_TYPE xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE;
/*-----------------------------------------------------------*/
void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority )
{
static xQueueHandle xPolledQueue;
/* Create the queue used by the producer and consumer. */
xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) );
/* Spawn the producer and consumer. */
xTaskCreate( vPolledQueueConsumer, ( signed portCHAR * ) "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL );
xTaskCreate( vPolledQueueProducer, ( signed portCHAR * ) "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vPolledQueueProducer, pvParameters )
{
unsigned portSHORT usValue = ( unsigned portSHORT ) 0;
signed portBASE_TYPE xError = pdFALSE, xLoop;
for( ;; )
{
for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ )
{
/* Send an incrementing number on the queue without blocking. */
if( xQueueSend( *( ( xQueueHandle * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS )
{
/* We should never find the queue full so if we get here there
has been an error. */
xError = pdTRUE;
}
else
{
if( xError == pdFALSE )
{
/* If an error has ever been recorded we stop incrementing the
check variable. */
portENTER_CRITICAL();
xPollingProducerCount++;
portEXIT_CRITICAL();
}
/* Update the value we are going to post next time around. */
usValue++;
}
}
/* Wait before we start posting again to ensure the consumer runs and
empties the queue. */
vTaskDelay( pollqPRODUCER_DELAY );
}
} /*lint !e818 Function prototype must conform to API. */
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters )
{
unsigned portSHORT usData, usExpectedValue = ( unsigned portSHORT ) 0;
signed portBASE_TYPE xError = pdFALSE;
for( ;; )
{
/* Loop until the queue is empty. */
while( uxQueueMessagesWaiting( *( ( xQueueHandle * ) pvParameters ) ) )
{
if( xQueueReceive( *( ( xQueueHandle * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS )
{
if( usData != usExpectedValue )
{
/* This is not what we expected to receive so an error has
occurred. */
xError = pdTRUE;
/* Catch-up to the value we received so our next expected
value should again be correct. */
usExpectedValue = usData;
}
else
{
if( xError == pdFALSE )
{
/* Only increment the check variable if no errors have
occurred. */
portENTER_CRITICAL();
xPollingConsumerCount++;
portEXIT_CRITICAL();
}
}
/* Next time round we would expect the number to be one higher. */
usExpectedValue++;
}
}
/* Now the queue is empty we block, allowing the producer to place more
items in the queue. */
vTaskDelay( pollqCONSUMER_DELAY );
}
} /*lint !e818 Function prototype must conform to API. */
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running with no errors. */
portBASE_TYPE xArePollingQueuesStillRunning( void )
{
portBASE_TYPE xReturn;
/* Check both the consumer and producer poll count to check they have both
been changed since out last trip round. We do not need a critical section
around the check variables as this is called from a higher priority than
the other tasks that access the same variables. */
if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) ||
( xPollingProducerCount == pollqINITIAL_VALUE )
)
{
xReturn = pdFALSE;
}
else
{
xReturn = pdTRUE;
}
/* Set the check variables back down so we know if they have been
incremented the next time around. */
xPollingConsumerCount = pollqINITIAL_VALUE;
xPollingProducerCount = pollqINITIAL_VALUE;
return xReturn;
}

427
20080212/Demo/Common/Minimal/QPeek.c Normal file
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@ -0,0 +1,427 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* Tests the behaviour when data is peeked from a queue when there are
* multiple tasks blocked on the queue.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
/* Demo program include files. */
#include "QPeek.h"
#define qpeekQUEUE_LENGTH ( 5 )
#define qpeekNO_BLOCK ( 0 )
#define qpeekSHORT_DELAY ( 10 )
#define qpeekLOW_PRIORITY ( tskIDLE_PRIORITY + 0 )
#define qpeekMEDIUM_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define qpeekHIGH_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define qpeekHIGHEST_PRIORITY ( tskIDLE_PRIORITY + 3 )
/*-----------------------------------------------------------*/
/*
* The following three tasks are used to demonstrate the peeking behaviour.
* Each task is given a different priority to demonstrate the order in which
* tasks are woken as data is peeked from a queue.
*/
static void prvLowPriorityPeekTask( void *pvParameters );
static void prvMediumPriorityPeekTask( void *pvParameters );
static void prvHighPriorityPeekTask( void *pvParameters );
static void prvHighestPriorityPeekTask( void *pvParameters );
/*-----------------------------------------------------------*/
/* Flag that will be latched to pdTRUE should any unexpected behaviour be
detected in any of the tasks. */
static portBASE_TYPE xErrorDetected = pdFALSE;
/* Counter that is incremented on each cycle of a test. This is used to
detect a stalled task - a test that is no longer running. */
static volatile unsigned portLONG ulLoopCounter = 0;
/* Handles to the test tasks. */
xTaskHandle xMediumPriorityTask, xHighPriorityTask, xHighestPriorityTask;
/*-----------------------------------------------------------*/
void vStartQueuePeekTasks( void )
{
xQueueHandle xQueue;
/* Create the queue that we are going to use for the test/demo. */
xQueue = xQueueCreate( qpeekQUEUE_LENGTH, sizeof( unsigned portLONG ) );
/* Create the demo tasks and pass it the queue just created. We are
passing the queue handle by value so it does not matter that it is declared
on the stack here. */
xTaskCreate( prvLowPriorityPeekTask, ( signed portCHAR * )"PeekL", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekLOW_PRIORITY, NULL );
xTaskCreate( prvMediumPriorityPeekTask, ( signed portCHAR * )"PeekM", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekMEDIUM_PRIORITY, &xMediumPriorityTask );
xTaskCreate( prvHighPriorityPeekTask, ( signed portCHAR * )"PeekH1", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGH_PRIORITY, &xHighPriorityTask );
xTaskCreate( prvHighestPriorityPeekTask, ( signed portCHAR * )"PeekH2", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGHEST_PRIORITY, &xHighestPriorityTask );
}
/*-----------------------------------------------------------*/
static void prvHighestPriorityPeekTask( void *pvParameters )
{
xQueueHandle xQueue = ( xQueueHandle ) pvParameters;
unsigned portLONG ulValue;
#ifdef USE_STDIO
{
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Queue peek test started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
}
#endif
for( ;; )
{
/* Try peeking from the queue. The queue should be empty so we will
block, allowing the high priority task to execute. */
if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
{
/* We expected to have received something by the time we unblock. */
xErrorDetected = pdTRUE;
}
/* When we reach here the high and medium priority tasks should still
be blocked on the queue. We unblocked because the low priority task
wrote a value to the queue, which we should have peeked. Peeking the
data (rather than receiving it) will leave the data on the queue, so
the high priority task should then have also been unblocked, but not
yet executed. */
if( ulValue != 0x11223344 )
{
/* We did not receive the expected value. */
xErrorDetected = pdTRUE;
}
if( uxQueueMessagesWaiting( xQueue ) != 1 )
{
/* The message should have been left on the queue. */
xErrorDetected = pdTRUE;
}
/* Now we are going to actually receive the data, so when the high
priority task runs it will find the queue empty and return to the
blocked state. */
ulValue = 0;
if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
{
/* We expected to receive the value. */
xErrorDetected = pdTRUE;
}
if( ulValue != 0x11223344 )
{
/* We did not receive the expected value - which should have been
the same value as was peeked. */
xErrorDetected = pdTRUE;
}
/* Now we will block again as the queue is once more empty. The low
priority task can then execute again. */
if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
{
/* We expected to have received something by the time we unblock. */
xErrorDetected = pdTRUE;
}
/* When we get here the low priority task should have again written to the
queue. */
if( ulValue != 0x01234567 )
{
/* We did not receive the expected value. */
xErrorDetected = pdTRUE;
}
if( uxQueueMessagesWaiting( xQueue ) != 1 )
{
/* The message should have been left on the queue. */
xErrorDetected = pdTRUE;
}
/* We only peeked the data, so suspending ourselves now should enable
the high priority task to also peek the data. The high priority task
will have been unblocked when we peeked the data as we left the data
in the queue. */
vTaskSuspend( NULL );
/* This time we are going to do the same as the above test, but the
high priority task is going to receive the data, rather than peek it.
This means that the medium priority task should never peek the value. */
if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( ulValue != 0xaabbaabb )
{
xErrorDetected = pdTRUE;
}
vTaskSuspend( NULL );
}
}
/*-----------------------------------------------------------*/
static void prvHighPriorityPeekTask( void *pvParameters )
{
xQueueHandle xQueue = ( xQueueHandle ) pvParameters;
unsigned portLONG ulValue;
for( ;; )
{
/* Try peeking from the queue. The queue should be empty so we will
block, allowing the medium priority task to execute. Both the high
and highest priority tasks will then be blocked on the queue. */
if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
{
/* We expected to have received something by the time we unblock. */
xErrorDetected = pdTRUE;
}
/* When we get here the highest priority task should have peeked the data
(unblocking this task) then suspended (allowing this task to also peek
the data). */
if( ulValue != 0x01234567 )
{
/* We did not receive the expected value. */
xErrorDetected = pdTRUE;
}
if( uxQueueMessagesWaiting( xQueue ) != 1 )
{
/* The message should have been left on the queue. */
xErrorDetected = pdTRUE;
}
/* We only peeked the data, so suspending ourselves now should enable
the medium priority task to also peek the data. The medium priority task
will have been unblocked when we peeked the data as we left the data
in the queue. */
vTaskSuspend( NULL );
/* This time we are going actually receive the value, so the medium
priority task will never peek the data - we removed it from the queue. */
if( xQueueReceive( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( ulValue != 0xaabbaabb )
{
xErrorDetected = pdTRUE;
}
vTaskSuspend( NULL );
}
}
/*-----------------------------------------------------------*/
static void prvMediumPriorityPeekTask( void *pvParameters )
{
xQueueHandle xQueue = ( xQueueHandle ) pvParameters;
unsigned portLONG ulValue;
for( ;; )
{
/* Try peeking from the queue. The queue should be empty so we will
block, allowing the low priority task to execute. The highest, high
and medium priority tasks will then all be blocked on the queue. */
if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
{
/* We expected to have received something by the time we unblock. */
xErrorDetected = pdTRUE;
}
/* When we get here the high priority task should have peeked the data
(unblocking this task) then suspended (allowing this task to also peek
the data). */
if( ulValue != 0x01234567 )
{
/* We did not receive the expected value. */
xErrorDetected = pdTRUE;
}
if( uxQueueMessagesWaiting( xQueue ) != 1 )
{
/* The message should have been left on the queue. */
xErrorDetected = pdTRUE;
}
/* Just so we know the test is still running. */
ulLoopCounter++;
/* Now we can suspend ourselves so the low priority task can execute
again. */
vTaskSuspend( NULL );
}
}
/*-----------------------------------------------------------*/
static void prvLowPriorityPeekTask( void *pvParameters )
{
xQueueHandle xQueue = ( xQueueHandle ) pvParameters;
unsigned portLONG ulValue;
for( ;; )
{
/* Write some data to the queue. This should unblock the highest
priority task that is waiting to peek data from the queue. */
ulValue = 0x11223344;
if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
{
/* We were expecting the queue to be empty so we should not of
had a problem writing to the queue. */
xErrorDetected = pdTRUE;
}
/* By the time we get here the data should have been removed from
the queue. */
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
/* Write another value to the queue, again waking the highest priority
task that is blocked on the queue. */
ulValue = 0x01234567;
if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
{
/* We were expecting the queue to be empty so we should not of
had a problem writing to the queue. */
xErrorDetected = pdTRUE;
}
/* All the other tasks should now have successfully peeked the data.
The data is still in the queue so we should be able to receive it. */
ulValue = 0;
if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
{
/* We expected to receive the data. */
xErrorDetected = pdTRUE;
}
if( ulValue != 0x01234567 )
{
/* We did not receive the expected value. */
}
/* Lets just delay a while as this is an intensive test as we don't
want to starve other tests of processing time. */
vTaskDelay( qpeekSHORT_DELAY );
/* Unsuspend the other tasks so we can repeat the test - this time
however not all the other tasks will peek the data as the high
priority task is actually going to remove it from the queue. Send
to front is used just to be different. As the queue is empty it
makes no difference to the result. */
vTaskResume( xMediumPriorityTask );
vTaskResume( xHighPriorityTask );
vTaskResume( xHighestPriorityTask );
ulValue = 0xaabbaabb;
if( xQueueSendToFront( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
{
/* We were expecting the queue to be empty so we should not of
had a problem writing to the queue. */
xErrorDetected = pdTRUE;
}
/* This time we should find that the queue is empty. The high priority
task actually removed the data rather than just peeking it. */
if( xQueuePeek( xQueue, &ulValue, qpeekNO_BLOCK ) != errQUEUE_EMPTY )
{
/* We expected to receive the data. */
xErrorDetected = pdTRUE;
}
/* Unsuspend the highest and high priority tasks so we can go back
and repeat the whole thing. The medium priority task should not be
suspended as it was not able to peek the data in this last case. */
vTaskResume( xHighPriorityTask );
vTaskResume( xHighestPriorityTask );
/* Lets just delay a while as this is an intensive test as we don't
want to starve other tests of processing time. */
vTaskDelay( qpeekSHORT_DELAY );
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreQueuePeekTasksStillRunning( void )
{
static unsigned portLONG ulLastLoopCounter = 0;
/* If the demo task is still running then we expect the loopcounter to
have incremented since this function was last called. */
if( ulLastLoopCounter == ulLoopCounter )
{
xErrorDetected = pdTRUE;
}
ulLastLoopCounter = ulLoopCounter;
/* Errors detected in the task itself will have latched xErrorDetected
to true. */
return !xErrorDetected;
}

487
20080212/Demo/Common/Minimal/blocktim.c Normal file
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@ -0,0 +1,487 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* This file contains some test scenarios that ensure tasks do not exit queue
* send or receive functions prematurely. A description of the tests is
* included within the code.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Demo includes. */
#include "blocktim.h"
/* Task priorities. */
#define bktPRIMARY_PRIORITY ( 3 )
#define bktSECONDARY_PRIORITY ( 2 )
/* Task behaviour. */
#define bktQUEUE_LENGTH ( 5 )
#define bktSHORT_WAIT ( ( ( portTickType ) 20 ) / portTICK_RATE_MS )
#define bktPRIMARY_BLOCK_TIME ( 10 )
#define bktALLOWABLE_MARGIN ( 12 )
#define bktTIME_TO_BLOCK ( 175 )
#define bktDONT_BLOCK ( ( portTickType ) 0 )
#define bktRUN_INDICATOR ( ( unsigned portBASE_TYPE ) 0x55 )
/* The queue on which the tasks block. */
static xQueueHandle xTestQueue;
/* Handle to the secondary task is required by the primary task for calls
to vTaskSuspend/Resume(). */
static xTaskHandle xSecondary;
/* Used to ensure that tasks are still executing without error. */
static portBASE_TYPE xPrimaryCycles = 0, xSecondaryCycles = 0;
static portBASE_TYPE xErrorOccurred = pdFALSE;
/* Provides a simple mechanism for the primary task to know when the
secondary task has executed. */
static volatile unsigned portBASE_TYPE xRunIndicator;
/* The two test tasks. Their behaviour is commented within the files. */
static void vPrimaryBlockTimeTestTask( void *pvParameters );
static void vSecondaryBlockTimeTestTask( void *pvParameters );
/*-----------------------------------------------------------*/
void vCreateBlockTimeTasks( void )
{
/* Create the queue on which the two tasks block. */
xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( portBASE_TYPE ) );
/* Create the two test tasks. */
xTaskCreate( vPrimaryBlockTimeTestTask, ( signed portCHAR * )"BTest1", configMINIMAL_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL );
xTaskCreate( vSecondaryBlockTimeTestTask, ( signed portCHAR * )"BTest2", configMINIMAL_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary );
}
/*-----------------------------------------------------------*/
static void vPrimaryBlockTimeTestTask( void *pvParameters )
{
portBASE_TYPE xItem, xData;
portTickType xTimeWhenBlocking;
portTickType xTimeToBlock, xBlockedTime;
( void ) pvParameters;
for( ;; )
{
/*********************************************************************
Test 1
Simple block time wakeup test on queue receives. */
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
/* The queue is empty. Attempt to read from the queue using a block
time. When we wake, ensure the delta in time is as expected. */
xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem;
/* A critical section is used to minimise the jitter in the time
measurements. */
portENTER_CRITICAL();
{
xTimeWhenBlocking = xTaskGetTickCount();
/* We should unblock after xTimeToBlock having not received
anything on the queue. */
if( xQueueReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY )
{
xErrorOccurred = pdTRUE;
}
/* How long were we blocked for? */
xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
}
portEXIT_CRITICAL();
if( xBlockedTime < xTimeToBlock )
{
/* Should not have blocked for less than we requested. */
xErrorOccurred = pdTRUE;
}
if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )
{
/* Should not have blocked for longer than we requested,
although we would not necessarily run as soon as we were
unblocked so a margin is allowed. */
xErrorOccurred = pdTRUE;
}
}
/*********************************************************************
Test 2
Simple block time wakeup test on queue sends.
First fill the queue. It should be empty so all sends should pass. */
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
}
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
/* The queue is full. Attempt to write to the queue using a block
time. When we wake, ensure the delta in time is as expected. */
xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem;
portENTER_CRITICAL();
{
xTimeWhenBlocking = xTaskGetTickCount();
/* We should unblock after xTimeToBlock having not received
anything on the queue. */
if( xQueueSend( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL )
{
xErrorOccurred = pdTRUE;
}
/* How long were we blocked for? */
xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
}
portEXIT_CRITICAL();
if( xBlockedTime < xTimeToBlock )
{
/* Should not have blocked for less than we requested. */
xErrorOccurred = pdTRUE;
}
if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )
{
/* Should not have blocked for longer than we requested,
although we would not necessarily run as soon as we were
unblocked so a margin is allowed. */
xErrorOccurred = pdTRUE;
}
}
/*********************************************************************
Test 3
Wake the other task, it will block attempting to post to the queue.
When we read from the queue the other task will wake, but before it
can run we will post to the queue again. When the other task runs it
will find the queue still full, even though it was woken. It should
recognise that its block time has not expired and return to block for
the remains of its block time.
Wake the other task so it blocks attempting to post to the already
full queue. */
xRunIndicator = 0;
vTaskResume( xSecondary );
/* We need to wait a little to ensure the other task executes. */
while( xRunIndicator != bktRUN_INDICATOR )
{
/* The other task has not yet executed. */
vTaskDelay( bktSHORT_WAIT );
}
/* Make sure the other task is blocked on the queue. */
vTaskDelay( bktSHORT_WAIT );
xRunIndicator = 0;
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
/* Now when we make space on the queue the other task should wake
but not execute as this task has higher priority. */
if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
/* Now fill the queue again before the other task gets a chance to
execute. If the other task had executed we would find the queue
full ourselves, and the other task have set xRunIndicator. */
if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
if( xRunIndicator == bktRUN_INDICATOR )
{
/* The other task should not have executed. */
xErrorOccurred = pdTRUE;
}
/* Raise the priority of the other task so it executes and blocks
on the queue again. */
vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );
/* The other task should now have re-blocked without exiting the
queue function. */
if( xRunIndicator == bktRUN_INDICATOR )
{
/* The other task should not have executed outside of the
queue function. */
xErrorOccurred = pdTRUE;
}
/* Set the priority back down. */
vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );
}
/* Let the other task timeout. When it unblockes it will check that it
unblocked at the correct time, then suspend itself. */
while( xRunIndicator != bktRUN_INDICATOR )
{
vTaskDelay( bktSHORT_WAIT );
}
vTaskDelay( bktSHORT_WAIT );
xRunIndicator = 0;
/*********************************************************************
Test 4
As per test 3 - but with the send and receive the other way around.
The other task blocks attempting to read from the queue.
Empty the queue. We should find that it is full. */
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
}
/* Wake the other task so it blocks attempting to read from the
already empty queue. */
vTaskResume( xSecondary );
/* We need to wait a little to ensure the other task executes. */
while( xRunIndicator != bktRUN_INDICATOR )
{
vTaskDelay( bktSHORT_WAIT );
}
vTaskDelay( bktSHORT_WAIT );
xRunIndicator = 0;
for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
{
/* Now when we place an item on the queue the other task should
wake but not execute as this task has higher priority. */
if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
/* Now empty the queue again before the other task gets a chance to
execute. If the other task had executed we would find the queue
empty ourselves, and the other task would be suspended. */
if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
if( xRunIndicator == bktRUN_INDICATOR )
{
/* The other task should not have executed. */
xErrorOccurred = pdTRUE;
}
/* Raise the priority of the other task so it executes and blocks
on the queue again. */
vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );
/* The other task should now have re-blocked without exiting the
queue function. */
if( xRunIndicator == bktRUN_INDICATOR )
{
/* The other task should not have executed outside of the
queue function. */
xErrorOccurred = pdTRUE;
}
vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );
}
/* Let the other task timeout. When it unblockes it will check that it
unblocked at the correct time, then suspend itself. */
while( xRunIndicator != bktRUN_INDICATOR )
{
vTaskDelay( bktSHORT_WAIT );
}
vTaskDelay( bktSHORT_WAIT );
xPrimaryCycles++;
}
}
/*-----------------------------------------------------------*/
static void vSecondaryBlockTimeTestTask( void *pvParameters )
{
portTickType xTimeWhenBlocking, xBlockedTime;
portBASE_TYPE xData;
( void ) pvParameters;
for( ;; )
{
/*********************************************************************
Test 1 and 2
This task does does not participate in these tests. */
vTaskSuspend( NULL );
/*********************************************************************
Test 3
The first thing we do is attempt to read from the queue. It should be
full so we block. Note the time before we block so we can check the
wake time is as per that expected. */
portENTER_CRITICAL();
{
xTimeWhenBlocking = xTaskGetTickCount();
/* We should unblock after bktTIME_TO_BLOCK having not received
anything on the queue. */
xData = 0;
xRunIndicator = bktRUN_INDICATOR;
if( xQueueSend( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL )
{
xErrorOccurred = pdTRUE;
}
/* How long were we inside the send function? */
xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
}
portEXIT_CRITICAL();
/* We should not have blocked for less time than bktTIME_TO_BLOCK. */
if( xBlockedTime < bktTIME_TO_BLOCK )
{
xErrorOccurred = pdTRUE;
}
/* We should of not blocked for much longer than bktALLOWABLE_MARGIN
either. A margin is permitted as we would not necessarily run as
soon as we unblocked. */
if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )
{
xErrorOccurred = pdTRUE;
}
/* Suspend ready for test 3. */
xRunIndicator = bktRUN_INDICATOR;
vTaskSuspend( NULL );
/*********************************************************************
Test 4
As per test three, but with the send and receive reversed. */
portENTER_CRITICAL();
{
xTimeWhenBlocking = xTaskGetTickCount();
/* We should unblock after bktTIME_TO_BLOCK having not received
anything on the queue. */
xRunIndicator = bktRUN_INDICATOR;
if( xQueueReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY )
{
xErrorOccurred = pdTRUE;
}
xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
}
portEXIT_CRITICAL();
/* We should not have blocked for less time than bktTIME_TO_BLOCK. */
if( xBlockedTime < bktTIME_TO_BLOCK )
{
xErrorOccurred = pdTRUE;
}
/* We should of not blocked for much longer than bktALLOWABLE_MARGIN
either. A margin is permitted as we would not necessarily run as soon
as we unblocked. */
if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )
{
xErrorOccurred = pdTRUE;
}
xRunIndicator = bktRUN_INDICATOR;
xSecondaryCycles++;
}
}
/*-----------------------------------------------------------*/
portBASE_TYPE xAreBlockTimeTestTasksStillRunning( void )
{
static portBASE_TYPE xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0;
portBASE_TYPE xReturn = pdPASS;
/* Have both tasks performed at least one cycle since this function was
last called? */
if( xPrimaryCycles == xLastPrimaryCycleCount )
{
xReturn = pdFAIL;
}
if( xSecondaryCycles == xLastSecondaryCycleCount )
{
xReturn = pdFAIL;
}
if( xErrorOccurred == pdTRUE )
{
xReturn = pdFAIL;
}
xLastSecondaryCycleCount = xSecondaryCycles;
xLastPrimaryCycleCount = xPrimaryCycles;
return xReturn;
}

297
20080212/Demo/Common/Minimal/comtest.c Normal file
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@ -0,0 +1,297 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* This version of comtest. c is for use on systems that have limited stack
* space and no display facilities. The complete version can be found in
* the Demo/Common/Full directory.
*
* Creates two tasks that operate on an interrupt driven serial port. A
* loopback connector should be used so that everything that is transmitted is
* also received. The serial port does not use any flow control. On a
* standard 9way 'D' connector pins two and three should be connected together.
*
* The first task posts a sequence of characters to the Tx queue, toggling an
* LED on each successful post. At the end of the sequence it sleeps for a
* pseudo-random period before resending the same sequence.
*
* The UART Tx end interrupt is enabled whenever data is available in the Tx
* queue. The Tx end ISR removes a single character from the Tx queue and
* passes it to the UART for transmission.
*
* The second task blocks on the Rx queue waiting for a character to become
* available. When the UART Rx end interrupt receives a character it places
* it in the Rx queue, waking the second task. The second task checks that the
* characters removed from the Rx queue form the same sequence as those posted
* to the Tx queue, and toggles an LED for each correct character.
*
* The receiving task is spawned with a higher priority than the transmitting
* task. The receiver will therefore wake every time a character is
* transmitted so neither the Tx or Rx queue should ever hold more than a few
* characters.
*
*/
/*
Changes from V1.2.0:
+ Reduced the maximum time between successive transmissions. This provides
for a more rigorous test.
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
Changes from V2.5.1
+ The constant comOFFSET_TIME added to the delay period to ensure a more
random delay period is used.
*/
/* Scheduler include files. */
#include <stdlib.h>
#include "FreeRTOS.h"
#include "task.h"
/* Demo program include files. */
#include "serial.h"
#include "comtest.h"
#include "partest.h"
#define comSTACK_SIZE configMINIMAL_STACK_SIZE
#define comTX_LED_OFFSET ( 0 )
#define comRX_LED_OFFSET ( 1 )
#define comTOTAL_PERMISSIBLE_ERRORS ( 2 )
/* The Tx task will transmit the sequence of characters at a pseudo random
interval. This is the maximum and minimum block time between sends. */
#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x96 )
#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0x32 )
#define comOFFSET_TIME ( ( portTickType ) 3 )
/* We should find that each character can be queued for Tx immediately and we
don't have to block to send. */
#define comNO_BLOCK ( ( portTickType ) 0 )
/* The Rx task will block on the Rx queue for a long period. */
#define comRX_BLOCK_TIME ( ( portTickType ) 0xffff )
/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */
#define comFIRST_BYTE ( 'A' )
#define comLAST_BYTE ( 'X' )
#define comBUFFER_LEN ( ( unsigned portBASE_TYPE ) ( comLAST_BYTE - comFIRST_BYTE ) + ( unsigned portBASE_TYPE ) 1 )
#define comINITIAL_RX_COUNT_VALUE ( 0 )
/* Handle to the com port used by both tasks. */
static xComPortHandle xPort = NULL;
/* The transmit task as described at the top of the file. */
static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters );
/* The receive task as described at the top of the file. */
static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters );
/* The LED that should be toggled by the Rx and Tx tasks. The Rx task will
toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED
( uxBaseLED + comTX_LED_OFFSET ). */
static unsigned portBASE_TYPE uxBaseLED = 0;
/* Check variable used to ensure no error have occurred. The Rx task will
increment this variable after every successfully received sequence. If at any
time the sequence is incorrect the the variable will stop being incremented. */
static volatile unsigned portBASE_TYPE uxRxLoops = comINITIAL_RX_COUNT_VALUE;
/*-----------------------------------------------------------*/
void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED )
{
/* Initialise the com port then spawn the Rx and Tx tasks. */
uxBaseLED = uxLED;
xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN );
/* The Tx task is spawned with a lower priority than the Rx task. */
xTaskCreate( vComTxTask, ( signed portCHAR * ) "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( xTaskHandle * ) NULL );
xTaskCreate( vComRxTask, ( signed portCHAR * ) "COMRx", comSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vComTxTask, pvParameters )
{
signed portCHAR cByteToSend;
portTickType xTimeToWait;
/* Just to stop compiler warnings. */
( void ) pvParameters;
for( ;; )
{
/* Simply transmit a sequence of characters from comFIRST_BYTE to
comLAST_BYTE. */
for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ )
{
if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS )
{
vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET );
}
}
/* Turn the LED off while we are not doing anything. */
vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE );
/* We have posted all the characters in the string - wait before
re-sending. Wait a pseudo-random time as this will provide a better
test. */
xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME;
/* Make sure we don't wait too long... */
xTimeToWait %= comTX_MAX_BLOCK_TIME;
/* ...but we do want to wait. */
if( xTimeToWait < comTX_MIN_BLOCK_TIME )
{
xTimeToWait = comTX_MIN_BLOCK_TIME;
}
vTaskDelay( xTimeToWait );
}
} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vComRxTask, pvParameters )
{
signed portCHAR cExpectedByte, cByteRxed;
portBASE_TYPE xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE;
/* Just to stop compiler warnings. */
( void ) pvParameters;
for( ;; )
{
/* We expect to receive the characters from comFIRST_BYTE to
comLAST_BYTE in an incrementing order. Loop to receive each byte. */
for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ )
{
/* Block on the queue that contains received bytes until a byte is
available. */
if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) )
{
/* Was this the byte we were expecting? If so, toggle the LED,
otherwise we are out on sync and should break out of the loop
until the expected character sequence is about to restart. */
if( cByteRxed == cExpectedByte )
{
vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET );
}
else
{
xResyncRequired = pdTRUE;
break; /*lint !e960 Non-switch break allowed. */
}
}
}
/* Turn the LED off while we are not doing anything. */
vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE );
/* Did we break out of the loop because the characters were received in
an unexpected order? If so wait here until the character sequence is
about to restart. */
if( xResyncRequired == pdTRUE )
{
while( cByteRxed != comLAST_BYTE )
{
/* Block until the next char is available. */
xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME );
}
/* Note that an error occurred which caused us to have to resync.
We use this to stop incrementing the loop counter so
sAreComTestTasksStillRunning() will return false - indicating an
error. */
xErrorOccurred++;
/* We have now resynced with the Tx task and can continue. */
xResyncRequired = pdFALSE;
}
else
{
if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS )
{
/* Increment the count of successful loops. As error
occurring (i.e. an unexpected character being received) will
prevent this counter being incremented for the rest of the
execution. Don't worry about mutual exclusion on this
variable - it doesn't really matter as we just want it
to change. */
uxRxLoops++;
}
}
}
} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */
/*-----------------------------------------------------------*/
portBASE_TYPE xAreComTestTasksStillRunning( void )
{
portBASE_TYPE xReturn;
/* If the count of successful reception loops has not changed than at
some time an error occurred (i.e. a character was received out of sequence)
and we will return false. */
if( uxRxLoops == comINITIAL_RX_COUNT_VALUE )
{
xReturn = pdFALSE;
}
else
{
xReturn = pdTRUE;
}
/* Reset the count of successful Rx loops. When this function is called
again we expect this to have been incremented. */
uxRxLoops = comINITIAL_RX_COUNT_VALUE;
return xReturn;
}

289
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@ -0,0 +1,289 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* Simple demonstration of the usage of counting semaphore.
*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Demo program include files. */
#include "countsem.h"
/* The maximum count value that the semaphore used for the demo can hold. */
#define countMAX_COUNT_VALUE ( 200 )
/* Constants used to indicate whether or not the semaphore should have been
created with its maximum count value, or its minimum count value. These
numbers are used to ensure that the pointers passed in as the task parameters
are valid. */
#define countSTART_AT_MAX_COUNT ( 0xaa )
#define countSTART_AT_ZERO ( 0x55 )
/* Two tasks are created for the test. One uses a semaphore created with its
count value set to the maximum, and one with the count value set to zero. */
#define countNUM_TEST_TASKS ( 2 )
#define countDONT_BLOCK ( 0 )
/*-----------------------------------------------------------*/
/* Flag that will be latched to pdTRUE should any unexpected behaviour be
detected in any of the tasks. */
static portBASE_TYPE xErrorDetected = pdFALSE;
/*-----------------------------------------------------------*/
/*
* The demo task. This simply counts the semaphore up to its maximum value,
* the counts it back down again. The result of each semaphore 'give' and
* 'take' is inspected, with an error being flagged if it is found not to be
* the expected result.
*/
static void prvCountingSemaphoreTask( void *pvParameters );
/*
* Utility function to increment the semaphore count value up from zero to
* countMAX_COUNT_VALUE.
*/
static void prvIncrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter );
/*
* Utility function to decrement the semaphore count value up from
* countMAX_COUNT_VALUE to zero.
*/
static void prvDecrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter );
/*-----------------------------------------------------------*/
/* The structure that is passed into the task as the task parameter. */
typedef struct COUNT_SEM_STRUCT
{
/* The semaphore to be used for the demo. */
xSemaphoreHandle xSemaphore;
/* Set to countSTART_AT_MAX_COUNT if the semaphore should be created with
its count value set to its max count value, or countSTART_AT_ZERO if it
should have been created with its count value set to 0. */
unsigned portBASE_TYPE uxExpectedStartCount;
/* Incremented on each cycle of the demo task. Used to detect a stalled
task. */
unsigned portBASE_TYPE uxLoopCounter;
} xCountSemStruct;
/* Two structures are defined, one is passed to each test task. */
static xCountSemStruct xParameters[ countNUM_TEST_TASKS ];
/*-----------------------------------------------------------*/
void vStartCountingSemaphoreTasks( void )
{
/* Create the semaphores that we are going to use for the test/demo. The
first should be created such that it starts at its maximum count value,
the second should be created such that it starts with a count value of zero. */
xParameters[ 0 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, countMAX_COUNT_VALUE );
xParameters[ 0 ].uxExpectedStartCount = countSTART_AT_MAX_COUNT;
xParameters[ 0 ].uxLoopCounter = 0;
xParameters[ 1 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, 0 );
xParameters[ 1 ].uxExpectedStartCount = 0;
xParameters[ 1 ].uxLoopCounter = 0;
/* Were the semaphores created? */
if( ( xParameters[ 0 ].xSemaphore != NULL ) || ( xParameters[ 1 ].xSemaphore != NULL ) )
{
/* Create the demo tasks, passing in the semaphore to use as the parameter. */
xTaskCreate( prvCountingSemaphoreTask, ( signed portCHAR * ) "CNT1", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 0 ] ), tskIDLE_PRIORITY, NULL );
xTaskCreate( prvCountingSemaphoreTask, ( signed portCHAR * ) "CNT2", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 1 ] ), tskIDLE_PRIORITY, NULL );
}
}
/*-----------------------------------------------------------*/
static void prvDecrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter )
{
unsigned portBASE_TYPE ux;
/* If the semaphore count is at its maximum then we should not be able to
'give' the semaphore. */
if( xSemaphoreGive( xSemaphore ) == pdPASS )
{
xErrorDetected = pdTRUE;
}
/* We should be able to 'take' the semaphore countMAX_COUNT_VALUE times. */
for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ )
{
if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) != pdPASS )
{
/* We expected to be able to take the semaphore. */
xErrorDetected = pdTRUE;
}
( *puxLoopCounter )++;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* If the semaphore count is zero then we should not be able to 'take'
the semaphore. */
if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS )
{
xErrorDetected = pdTRUE;
}
}
/*-----------------------------------------------------------*/
static void prvIncrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter )
{
unsigned portBASE_TYPE ux;
/* If the semaphore count is zero then we should not be able to 'take'
the semaphore. */
if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS )
{
xErrorDetected = pdTRUE;
}
/* We should be able to 'give' the semaphore countMAX_COUNT_VALUE times. */
for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ )
{
if( xSemaphoreGive( xSemaphore ) != pdPASS )
{
/* We expected to be able to take the semaphore. */
xErrorDetected = pdTRUE;
}
( *puxLoopCounter )++;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* If the semaphore count is at its maximum then we should not be able to
'give' the semaphore. */
if( xSemaphoreGive( xSemaphore ) == pdPASS )
{
xErrorDetected = pdTRUE;
}
}
/*-----------------------------------------------------------*/
static void prvCountingSemaphoreTask( void *pvParameters )
{
xCountSemStruct *pxParameter;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Counting semaphore demo started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
/* The semaphore to be used was passed as the parameter. */
pxParameter = ( xCountSemStruct * ) pvParameters;
/* Did we expect to find the semaphore already at its max count value, or
at zero? */
if( pxParameter->uxExpectedStartCount == countSTART_AT_MAX_COUNT )
{
prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
}
/* Now we expect the semaphore count to be 0, so this time there is an
error if we can take the semaphore. */
if( xSemaphoreTake( pxParameter->xSemaphore, 0 ) == pdPASS )
{
xErrorDetected = pdTRUE;
}
for( ;; )
{
prvIncrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
}
}
/*-----------------------------------------------------------*/
portBASE_TYPE xAreCountingSemaphoreTasksStillRunning( void )
{
static unsigned portBASE_TYPE uxLastCount0 = 0, uxLastCount1 = 0;
portBASE_TYPE xReturn = pdPASS;
/* Return fail if any 'give' or 'take' did not result in the expected
behaviour. */
if( xErrorDetected != pdFALSE )
{
xReturn = pdFAIL;
}
/* Return fail if either task is not still incrementing its loop counter. */
if( uxLastCount0 == xParameters[ 0 ].uxLoopCounter )
{
xReturn = pdFAIL;
}
else
{
uxLastCount0 = xParameters[ 0 ].uxLoopCounter;
}
if( uxLastCount1 == xParameters[ 1 ].uxLoopCounter )
{
xReturn = pdFAIL;
}
else
{
uxLastCount1 = xParameters[ 1 ].uxLoopCounter;
}
return xReturn;
}

223
20080212/Demo/Common/Minimal/crflash.c Normal file
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@ -0,0 +1,223 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* This demo application file demonstrates the use of queues to pass data
* between co-routines.
*
* N represents the number of 'fixed delay' co-routines that are created and
* is set during initialisation.
*
* N 'fixed delay' co-routines are created that just block for a fixed
* period then post the number of an LED onto a queue. Each such co-routine
* uses a different block period. A single 'flash' co-routine is also created
* that blocks on the same queue, waiting for the number of the next LED it
* should flash. Upon receiving a number it simply toggle the instructed LED
* then blocks on the queue once more. In this manner each LED from LED 0 to
* LED N-1 is caused to flash at a different rate.
*
* The 'fixed delay' co-routines are created with co-routine priority 0. The
* flash co-routine is created with co-routine priority 1. This means that
* the queue should never contain more than a single item. This is because
* posting to the queue will unblock the 'flash' co-routine, and as this has
* a priority greater than the tasks posting to the queue it is guaranteed to
* have emptied the queue and blocked once again before the queue can contain
* any more date. An error is indicated if an attempt to post data to the
* queue fails - indicating that the queue is already full.
*
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "croutine.h"
#include "queue.h"
/* Demo application includes. */
#include "partest.h"
#include "crflash.h"
/* The queue should only need to be of length 1. See the description at the
top of the file. */
#define crfQUEUE_LENGTH 1
#define crfFIXED_DELAY_PRIORITY 0
#define crfFLASH_PRIORITY 1
/* Only one flash co-routine is created so the index is not significant. */
#define crfFLASH_INDEX 0
/* Don't allow more than crfMAX_FLASH_TASKS 'fixed delay' co-routines to be
created. */
#define crfMAX_FLASH_TASKS 8
/* We don't want to block when posting to the queue. */
#define crfPOSTING_BLOCK_TIME 0
/*
* The 'fixed delay' co-routine as described at the top of the file.
*/
static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );
/*
* The 'flash' co-routine as described at the top of the file.
*/
static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );
/* The queue used to pass data between the 'fixed delay' co-routines and the
'flash' co-routine. */
static xQueueHandle xFlashQueue;
/* This will be set to pdFALSE if we detect an error. */
static unsigned portBASE_TYPE uxCoRoutineFlashStatus = pdPASS;
/*-----------------------------------------------------------*/
/*
* See the header file for details.
*/
void vStartFlashCoRoutines( unsigned portBASE_TYPE uxNumberToCreate )
{
unsigned portBASE_TYPE uxIndex;
if( uxNumberToCreate > crfMAX_FLASH_TASKS )
{
uxNumberToCreate = crfMAX_FLASH_TASKS;
}
/* Create the queue used to pass data between the co-routines. */
xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) );
if( xFlashQueue )
{
/* Create uxNumberToCreate 'fixed delay' co-routines. */
for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ )
{
xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex );
}
/* Create the 'flash' co-routine. */
xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX );
}
}
/*-----------------------------------------------------------*/
static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
{
/* Even though this is a co-routine the xResult variable does not need to be
static as we do not need it to maintain its state between blocks. */
signed portBASE_TYPE xResult;
/* The uxIndex parameter of the co-routine function is used as an index into
the xFlashRates array to obtain the delay period to use. */
static const portTickType xFlashRates[ crfMAX_FLASH_TASKS ] = { 150 / portTICK_RATE_MS,
200 / portTICK_RATE_MS,
250 / portTICK_RATE_MS,
300 / portTICK_RATE_MS,
350 / portTICK_RATE_MS,
400 / portTICK_RATE_MS,
450 / portTICK_RATE_MS,
500 / portTICK_RATE_MS };
/* Co-routines MUST start with a call to crSTART. */
crSTART( xHandle );
for( ;; )
{
/* Post our uxIndex value onto the queue. This is used as the LED to
flash. */
crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult );
if( xResult != pdPASS )
{
/* For the reasons stated at the top of the file we should always
find that we can post to the queue. If we could not then an error
has occurred. */
uxCoRoutineFlashStatus = pdFAIL;
}
crDELAY( xHandle, xFlashRates[ uxIndex ] );
}
/* Co-routines MUST end with a call to crEND. */
crEND();
}
/*-----------------------------------------------------------*/
static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
{
/* Even though this is a co-routine the variable do not need to be
static as we do not need it to maintain their state between blocks. */
signed portBASE_TYPE xResult;
unsigned portBASE_TYPE uxLEDToFlash;
/* Co-routines MUST start with a call to crSTART. */
crSTART( xHandle );
( void ) uxIndex;
for( ;; )
{
/* Block to wait for the number of the LED to flash. */
crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
if( xResult != pdPASS )
{
/* We would not expect to wake unless we received something. */
uxCoRoutineFlashStatus = pdFAIL;
}
else
{
/* We received the number of an LED to flash - flash it! */
vParTestToggleLED( uxLEDToFlash );
}
}
/* Co-routines MUST end with a call to crEND. */
crEND();
}
/*-----------------------------------------------------------*/
portBASE_TYPE xAreFlashCoRoutinesStillRunning( void )
{
/* Return pdPASS or pdFAIL depending on whether an error has been detected
or not. */
return uxCoRoutineFlashStatus;
}

247
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@ -0,0 +1,247 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* This demo file demonstrates how to send data between an ISR and a
* co-routine. A tick hook function is used to periodically pass data between
* the RTOS tick and a set of 'hook' co-routines.
*
* hookNUM_HOOK_CO_ROUTINES co-routines are created. Each co-routine blocks
* to wait for a character to be received on a queue from the tick ISR, checks
* to ensure the character received was that expected, then sends the number
* back to the tick ISR on a different queue.
*
* The tick ISR checks the numbers received back from the 'hook' co-routines
* matches the number previously sent.
*
* If at any time a queue function returns unexpectedly, or an incorrect value
* is received either by the tick hook or a co-routine then an error is
* latched.
*
* This demo relies on each 'hook' co-routine to execute between each
* hookTICK_CALLS_BEFORE_POST tick interrupts. This and the heavy use of
* queues from within an interrupt may result in an error being detected on
* slower targets simply due to timing.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "croutine.h"
#include "queue.h"
/* Demo application includes. */
#include "crhook.h"
/* The number of 'hook' co-routines that are to be created. */
#define hookNUM_HOOK_CO_ROUTINES ( 4 )
/* The number of times the tick hook should be called before a character is
posted to the 'hook' co-routines. */
#define hookTICK_CALLS_BEFORE_POST ( 500 )
/* There should never be more than one item in any queue at any time. */
#define hookHOOK_QUEUE_LENGTH ( 1 )
/* Don't block when initially posting to the queue. */
#define hookNO_BLOCK_TIME ( 0 )
/* The priority relative to other co-routines (rather than tasks) that the
'hook' co-routines should take. */
#define mainHOOK_CR_PRIORITY ( 1 )
/*-----------------------------------------------------------*/
/*
* The co-routine function itself.
*/
static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );
/*
* The tick hook function. This receives a number from each 'hook' co-routine
* then sends a number to each co-routine. An error is flagged if a send or
* receive fails, or an unexpected number is received.
*/
void vApplicationTickHook( void );
/*-----------------------------------------------------------*/
/* Queues used to send data FROM a co-routine TO the tick hook function.
The hook functions received (Rx's) on these queues. One queue per
'hook' co-routine. */
static xQueueHandle xHookRxQueues[ hookNUM_HOOK_CO_ROUTINES ];
/* Queues used to send data FROM the tick hook TO a co-routine function.
The hood function transmits (Tx's) on these queues. One queue per
'hook' co-routine. */
static xQueueHandle xHookTxQueues[ hookNUM_HOOK_CO_ROUTINES ];
/* Set to true if an error is detected at any time. */
static portBASE_TYPE xCoRoutineErrorDetected = pdFALSE;
/*-----------------------------------------------------------*/
void vStartHookCoRoutines( void )
{
unsigned portBASE_TYPE uxIndex, uxValueToPost = 0;
for( uxIndex = 0; uxIndex < hookNUM_HOOK_CO_ROUTINES; uxIndex++ )
{
/* Create a queue to transmit to and receive from each 'hook'
co-routine. */
xHookRxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) );
xHookTxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) );
/* To start things off the tick hook function expects the queue it
uses to receive data to contain a value. */
xQueueSend( xHookRxQueues[ uxIndex ], &uxValueToPost, hookNO_BLOCK_TIME );
/* Create the 'hook' co-routine itself. */
xCoRoutineCreate( prvHookCoRoutine, mainHOOK_CR_PRIORITY, uxIndex );
}
}
/*-----------------------------------------------------------*/
static unsigned portBASE_TYPE uxCallCounter = 0, uxNumberToPost = 0;
void vApplicationTickHook( void )
{
unsigned portBASE_TYPE uxReceivedNumber;
signed portBASE_TYPE xIndex, xCoRoutineWoken;
/* Is it time to talk to the 'hook' co-routines again? */
uxCallCounter++;
if( uxCallCounter >= hookTICK_CALLS_BEFORE_POST )
{
uxCallCounter = 0;
for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ )
{
xCoRoutineWoken = pdFALSE;
if( crQUEUE_RECEIVE_FROM_ISR( xHookRxQueues[ xIndex ], &uxReceivedNumber, &xCoRoutineWoken ) != pdPASS )
{
/* There is no reason why we would not expect the queue to
contain a value. */
xCoRoutineErrorDetected = pdTRUE;
}
else
{
/* Each queue used to receive data from the 'hook' co-routines
should contain the number we last posted to the same co-routine. */
if( uxReceivedNumber != uxNumberToPost )
{
xCoRoutineErrorDetected = pdTRUE;
}
/* Nothing should be blocked waiting to post to the queue. */
if( xCoRoutineWoken != pdFALSE )
{
xCoRoutineErrorDetected = pdTRUE;
}
}
}
/* Start the next cycle by posting the next number onto each Tx queue. */
uxNumberToPost++;
for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ )
{
if( crQUEUE_SEND_FROM_ISR( xHookTxQueues[ xIndex ], &uxNumberToPost, pdFALSE ) != pdTRUE )
{
/* Posting to the queue should have woken the co-routine that
was blocked on the queue. */
xCoRoutineErrorDetected = pdTRUE;
}
}
}
}
/*-----------------------------------------------------------*/
static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
{
static unsigned portBASE_TYPE uxReceivedValue[ hookNUM_HOOK_CO_ROUTINES ];
portBASE_TYPE xResult;
/* Each co-routine MUST start with a call to crSTART(); */
crSTART( xHandle );
for( ;; )
{
/* Wait to receive a value from the tick hook. */
xResult = pdFAIL;
crQUEUE_RECEIVE( xHandle, xHookTxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), portMAX_DELAY, &xResult );
/* There is no reason why we should not have received something on
the queue. */
if( xResult != pdPASS )
{
xCoRoutineErrorDetected = pdTRUE;
}
/* Send the same number back to the idle hook so it can verify it. */
xResult = pdFAIL;
crQUEUE_SEND( xHandle, xHookRxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), hookNO_BLOCK_TIME, &xResult );
if( xResult != pdPASS )
{
/* There is no reason why we should not have been able to post to
the queue. */
xCoRoutineErrorDetected = pdTRUE;
}
}
/* Each co-routine MUST end with a call to crEND(). */
crEND();
}
/*-----------------------------------------------------------*/
portBASE_TYPE xAreHookCoRoutinesStillRunning( void )
{
if( xCoRoutineErrorDetected )
{
return pdFALSE;
}
else
{
return pdTRUE;
}
}

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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/**
* Create a single persistent task which periodically dynamically creates another
* two tasks. The original task is called the creator task, the two tasks it
* creates are called suicidal tasks.
*
* One of the created suicidal tasks kill one other suicidal task before killing
* itself - leaving just the original task remaining.
*
* The creator task must be spawned after all of the other demo application tasks
* as it keeps a check on the number of tasks under the scheduler control. The
* number of tasks it expects to see running should never be greater than the
* number of tasks that were in existence when the creator task was spawned, plus
* one set of four suicidal tasks. If this number is exceeded an error is flagged.
*
* \page DeathC death.c
* \ingroup DemoFiles
* <HR>
*/
/*
Changes from V3.0.0
+ CreationCount sizes changed from unsigned portBASE_TYPE to
unsigned portSHORT to minimize the risk of overflowing.
+ Reset of usLastCreationCount added
Changes from V3.1.0
+ Changed the dummy calculation to use variables of type long, rather than
float. This allows the file to be used with ports that do not support
floating point.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo program include files. */
#include "death.h"
#define deathSTACK_SIZE ( configMINIMAL_STACK_SIZE + 60 )
/* The task originally created which is responsible for periodically dynamically
creating another four tasks. */
static portTASK_FUNCTION_PROTO( vCreateTasks, pvParameters );
/* The task function of the dynamically created tasks. */
static portTASK_FUNCTION_PROTO( vSuicidalTask, pvParameters );
/* A variable which is incremented every time the dynamic tasks are created. This
is used to check that the task is still running. */
static volatile unsigned portSHORT usCreationCount = 0;
/* Used to store the number of tasks that were originally running so the creator
task can tell if any of the suicidal tasks have failed to die.
*/
static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0;
/* Tasks are deleted by the idle task. Under heavy load the idle task might
not get much processing time, so it would be legitimate for several tasks to
remain undeleted for a short period. */
static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 2;
/* Used to store a handle to the task that should be killed by a suicidal task,
before it kills itself. */
xTaskHandle xCreatedTask;
/*-----------------------------------------------------------*/
void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority )
{
unsigned portBASE_TYPE *puxPriority;
/* Create the Creator tasks - passing in as a parameter the priority at which
the suicidal tasks should be created. */
puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) );
*puxPriority = uxPriority;
xTaskCreate( vCreateTasks, ( signed portCHAR * ) "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL );
/* Record the number of tasks that are running now so we know if any of the
suicidal tasks have failed to be killed. */
uxTasksRunningAtStart = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks();
/* FreeRTOS.org versions before V3.0 started the idle-task as the very
first task. The idle task was then already included in uxTasksRunningAtStart.
From FreeRTOS V3.0 on, the idle task is started when the scheduler is
started. Therefore the idle task is not yet accounted for. We correct
this by increasing uxTasksRunningAtStart by 1. */
uxTasksRunningAtStart++;
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vSuicidalTask, pvParameters )
{
volatile portLONG l1, l2;
xTaskHandle xTaskToKill;
const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS;
if( pvParameters != NULL )
{
/* This task is periodically created four times. Two created tasks are
passed a handle to the other task so it can kill it before killing itself.
The other task is passed in null. */
xTaskToKill = *( xTaskHandle* )pvParameters;
}
else
{
xTaskToKill = NULL;
}
for( ;; )
{
/* Do something random just to use some stack and registers. */
l1 = 2;
l2 = 89;
l2 *= l1;
vTaskDelay( xDelay );
if( xTaskToKill != NULL )
{
/* Make sure the other task has a go before we delete it. */
vTaskDelay( ( portTickType ) 0 );
/* Kill the other task that was created by vCreateTasks(). */
vTaskDelete( xTaskToKill );
/* Kill ourselves. */
vTaskDelete( NULL );
}
}
}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCreateTasks, pvParameters )
{
const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS;
unsigned portBASE_TYPE uxPriority;
uxPriority = *( unsigned portBASE_TYPE * ) pvParameters;
vPortFree( pvParameters );
for( ;; )
{
/* Just loop round, delaying then creating the four suicidal tasks. */
vTaskDelay( xDelay );
xCreatedTask = NULL;
xTaskCreate( vSuicidalTask, ( signed portCHAR * ) "SUICID1", configMINIMAL_STACK_SIZE, NULL, uxPriority, &xCreatedTask );
xTaskCreate( vSuicidalTask, ( signed portCHAR * ) "SUICID2", configMINIMAL_STACK_SIZE, &xCreatedTask, uxPriority, NULL );
++usCreationCount;
}
}
/*-----------------------------------------------------------*/
/* This is called to check that the creator task is still running and that there
are not any more than four extra tasks. */
portBASE_TYPE xIsCreateTaskStillRunning( void )
{
static portSHORT usLastCreationCount = -1;
portBASE_TYPE xReturn = pdTRUE;
static unsigned portBASE_TYPE uxTasksRunningNow;
if( usLastCreationCount == usCreationCount )
{
xReturn = pdFALSE;
}
else
{
usLastCreationCount = usCreationCount;
}
uxTasksRunningNow = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks();
if( uxTasksRunningNow < uxTasksRunningAtStart )
{
xReturn = pdFALSE;
}
else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning )
{
xReturn = pdFALSE;
}
else
{
/* Everything is okay. */
}
return xReturn;
}

407
20080212/Demo/Common/Minimal/dynamic.c Normal file
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@ -0,0 +1,407 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* The first test creates three tasks - two counter tasks (one continuous count
* and one limited count) and one controller. A "count" variable is shared
* between all three tasks. The two counter tasks should never be in a "ready"
* state at the same time. The controller task runs at the same priority as
* the continuous count task, and at a lower priority than the limited count
* task.
*
* One counter task loops indefinitely, incrementing the shared count variable
* on each iteration. To ensure it has exclusive access to the variable it
* raises it's priority above that of the controller task before each
* increment, lowering it again to it's original priority before starting the
* next iteration.
*
* The other counter task increments the shared count variable on each
* iteration of it's loop until the count has reached a limit of 0xff - at
* which point it suspends itself. It will not start a new loop until the
* controller task has made it "ready" again by calling vTaskResume ().
* This second counter task operates at a higher priority than controller
* task so does not need to worry about mutual exclusion of the counter
* variable.
*
* The controller task is in two sections. The first section controls and
* monitors the continuous count task. When this section is operational the
* limited count task is suspended. Likewise, the second section controls
* and monitors the limited count task. When this section is operational the
* continuous count task is suspended.
*
* In the first section the controller task first takes a copy of the shared
* count variable. To ensure mutual exclusion on the count variable it
* suspends the continuous count task, resuming it again when the copy has been
* taken. The controller task then sleeps for a fixed period - during which
* the continuous count task will execute and increment the shared variable.
* When the controller task wakes it checks that the continuous count task
* has executed by comparing the copy of the shared variable with its current
* value. This time, to ensure mutual exclusion, the scheduler itself is
* suspended with a call to vTaskSuspendAll (). This is for demonstration
* purposes only and is not a recommended technique due to its inefficiency.
*
* After a fixed number of iterations the controller task suspends the
* continuous count task, and moves on to its second section.
*
* At the start of the second section the shared variable is cleared to zero.
* The limited count task is then woken from it's suspension by a call to
* vTaskResume (). As this counter task operates at a higher priority than
* the controller task the controller task should not run again until the
* shared variable has been counted up to the limited value causing the counter
* task to suspend itself. The next line after vTaskResume () is therefore
* a check on the shared variable to ensure everything is as expected.
*
*
* The second test consists of a couple of very simple tasks that post onto a
* queue while the scheduler is suspended. This test was added to test parts
* of the scheduler not exercised by the first test.
*
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Demo app include files. */
#include "dynamic.h"
/* Function that implements the "limited count" task as described above. */
static portTASK_FUNCTION_PROTO( vLimitedIncrementTask, pvParameters );
/* Function that implements the "continuous count" task as described above. */
static portTASK_FUNCTION_PROTO( vContinuousIncrementTask, pvParameters );
/* Function that implements the controller task as described above. */
static portTASK_FUNCTION_PROTO( vCounterControlTask, pvParameters );
static portTASK_FUNCTION_PROTO( vQueueReceiveWhenSuspendedTask, pvParameters );
static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters );
/* Demo task specific constants. */
#define priSTACK_SIZE ( configMINIMAL_STACK_SIZE )
#define priSLEEP_TIME ( ( portTickType ) 128 / portTICK_RATE_MS )
#define priLOOPS ( 5 )
#define priMAX_COUNT ( ( unsigned portLONG ) 0xff )
#define priNO_BLOCK ( ( portTickType ) 0 )
#define priSUSPENDED_QUEUE_LENGTH ( 1 )
/*-----------------------------------------------------------*/
/* Handles to the two counter tasks. These could be passed in as parameters
to the controller task to prevent them having to be file scope. */
static xTaskHandle xContinousIncrementHandle, xLimitedIncrementHandle;
/* The shared counter variable. This is passed in as a parameter to the two
counter variables for demonstration purposes. */
static unsigned portLONG ulCounter;
/* Variables used to check that the tasks are still operating without error.
Each complete iteration of the controller task increments this variable
provided no errors have been found. The variable maintaining the same value
is therefore indication of an error. */
static unsigned portSHORT usCheckVariable = ( unsigned portSHORT ) 0;
static portBASE_TYPE xSuspendedQueueSendError = pdFALSE;
static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE;
/* Queue used by the second test. */
xQueueHandle xSuspendedTestQueue;
/*-----------------------------------------------------------*/
/*
* Start the three tasks as described at the top of the file.
* Note that the limited count task is given a higher priority.
*/
void vStartDynamicPriorityTasks( void )
{
xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned portLONG ) );
xTaskCreate( vContinuousIncrementTask, ( signed portCHAR * ) "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinousIncrementHandle );
xTaskCreate( vLimitedIncrementTask, ( signed portCHAR * ) "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );
xTaskCreate( vCounterControlTask, ( signed portCHAR * ) "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( vQueueSendWhenSuspendedTask, ( signed portCHAR * ) "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( vQueueReceiveWhenSuspendedTask, ( signed portCHAR * ) "SUSP_RX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
}
/*-----------------------------------------------------------*/
/*
* Just loops around incrementing the shared variable until the limit has been
* reached. Once the limit has been reached it suspends itself.
*/
static portTASK_FUNCTION( vLimitedIncrementTask, pvParameters )
{
unsigned portLONG *pulCounter;
/* Take a pointer to the shared variable from the parameters passed into
the task. */
pulCounter = ( unsigned portLONG * ) pvParameters;
/* This will run before the control task, so the first thing it does is
suspend - the control task will resume it when ready. */
vTaskSuspend( NULL );
for( ;; )
{
/* Just count up to a value then suspend. */
( *pulCounter )++;
if( *pulCounter >= priMAX_COUNT )
{
vTaskSuspend( NULL );
}
}
}
/*-----------------------------------------------------------*/
/*
* Just keep counting the shared variable up. The control task will suspend
* this task when it wants.
*/
static portTASK_FUNCTION( vContinuousIncrementTask, pvParameters )
{
unsigned portLONG *pulCounter;
unsigned portBASE_TYPE uxOurPriority;
/* Take a pointer to the shared variable from the parameters passed into
the task. */
pulCounter = ( unsigned portLONG * ) pvParameters;
/* Query our priority so we can raise it when exclusive access to the
shared variable is required. */
uxOurPriority = uxTaskPriorityGet( NULL );
for( ;; )
{
/* Raise our priority above the controller task to ensure a context
switch does not occur while we are accessing this variable. */
vTaskPrioritySet( NULL, uxOurPriority + 1 );
( *pulCounter )++;
vTaskPrioritySet( NULL, uxOurPriority );
}
}
/*-----------------------------------------------------------*/
/*
* Controller task as described above.
*/
static portTASK_FUNCTION( vCounterControlTask, pvParameters )
{
unsigned portLONG ulLastCounter;
portSHORT sLoops;
portSHORT sError = pdFALSE;
/* Just to stop warning messages. */
( void ) pvParameters;
for( ;; )
{
/* Start with the counter at zero. */
ulCounter = ( unsigned portLONG ) 0;
/* First section : */
/* Check the continuous count task is running. */
for( sLoops = 0; sLoops < priLOOPS; sLoops++ )
{
/* Suspend the continuous count task so we can take a mirror of the
shared variable without risk of corruption. */
vTaskSuspend( xContinousIncrementHandle );
ulLastCounter = ulCounter;
vTaskResume( xContinousIncrementHandle );
/* Now delay to ensure the other task has processor time. */
vTaskDelay( priSLEEP_TIME );
/* Check the shared variable again. This time to ensure mutual
exclusion the whole scheduler will be locked. This is just for
demo purposes! */
vTaskSuspendAll();
{
if( ulLastCounter == ulCounter )
{
/* The shared variable has not changed. There is a problem
with the continuous count task so flag an error. */
sError = pdTRUE;
}
}
xTaskResumeAll();
}
/* Second section: */
/* Suspend the continuous counter task so it stops accessing the shared variable. */
vTaskSuspend( xContinousIncrementHandle );
/* Reset the variable. */
ulCounter = ( unsigned portLONG ) 0;
/* Resume the limited count task which has a higher priority than us.
We should therefore not return from this call until the limited count
task has suspended itself with a known value in the counter variable. */
vTaskResume( xLimitedIncrementHandle );
/* Does the counter variable have the expected value? */
if( ulCounter != priMAX_COUNT )
{
sError = pdTRUE;
}
if( sError == pdFALSE )
{
/* If no errors have occurred then increment the check variable. */
portENTER_CRITICAL();
usCheckVariable++;
portEXIT_CRITICAL();
}
/* Resume the continuous count task and do it all again. */
vTaskResume( xContinousIncrementHandle );
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vQueueSendWhenSuspendedTask, pvParameters )
{
static unsigned portLONG ulValueToSend = ( unsigned portLONG ) 0;
/* Just to stop warning messages. */
( void ) pvParameters;
for( ;; )
{
vTaskSuspendAll();
{
/* We must not block while the scheduler is suspended! */
if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )
{
xSuspendedQueueSendError = pdTRUE;
}
}
xTaskResumeAll();
vTaskDelay( priSLEEP_TIME );
++ulValueToSend;
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vQueueReceiveWhenSuspendedTask, pvParameters )
{
static unsigned portLONG ulExpectedValue = ( unsigned portLONG ) 0, ulReceivedValue;
portBASE_TYPE xGotValue;
/* Just to stop warning messages. */
( void ) pvParameters;
for( ;; )
{
do
{
/* Suspending the scheduler here is fairly pointless and
undesirable for a normal application. It is done here purely
to test the scheduler. The inner xTaskResumeAll() should
never return pdTRUE as the scheduler is still locked by the
outer call. */
vTaskSuspendAll();
{
vTaskSuspendAll();
{
xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );
}
if( xTaskResumeAll() )
{
xSuspendedQueueReceiveError = pdTRUE;
}
}
xTaskResumeAll();
#if configUSE_PREEMPTION == 0
{
taskYIELD();
}
#endif
} while( xGotValue == pdFALSE );
if( ulReceivedValue != ulExpectedValue )
{
xSuspendedQueueReceiveError = pdTRUE;
}
++ulExpectedValue;
}
}
/*-----------------------------------------------------------*/
/* Called to check that all the created tasks are still running without error. */
portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void )
{
/* Keep a history of the check variables so we know if it has been incremented
since the last call. */
static unsigned portSHORT usLastTaskCheck = ( unsigned portSHORT ) 0;
portBASE_TYPE xReturn = pdTRUE;
/* Check the tasks are still running by ensuring the check variable
is still incrementing. */
if( usCheckVariable == usLastTaskCheck )
{
/* The check has not incremented so an error exists. */
xReturn = pdFALSE;
}
if( xSuspendedQueueSendError == pdTRUE )
{
xReturn = pdFALSE;
}
if( xSuspendedQueueReceiveError == pdTRUE )
{
xReturn = pdFALSE;
}
usLastTaskCheck = usCheckVariable;
return xReturn;
}

148
20080212/Demo/Common/Minimal/flash.c Normal file
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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/**
* This version of flash .c is for use on systems that have limited stack space
* and no display facilities. The complete version can be found in the
* Demo/Common/Full directory.
*
* Three tasks are created, each of which flash an LED at a different rate. The first
* LED flashes every 200ms, the second every 400ms, the third every 600ms.
*
* The LED flash tasks provide instant visual feedback. They show that the scheduler
* is still operational.
*
* The PC port uses the standard parallel port for outputs, the Flashlite 186 port
* uses IO port F and the AVR port port B.
*
*/
/*
Changes from V2.0.0
+ Delay periods are now specified using variables and constants of
portTickType rather than unsigned portLONG.
Changes from V2.5.5
+ Calls to vTaskDelay() have been replaced with vTaskDelayUntil().
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo program include files. */
#include "partest.h"
#include "flash.h"
#define ledSTACK_SIZE configMINIMAL_STACK_SIZE
#define ledNUMBER_OF_LEDS ( 3 )
#define ledFLASH_RATE_BASE ( ( portTickType ) 333 )
/* Variable used by the created tasks to calculate the LED number to use, and
the rate at which they should flash the LED. */
static volatile unsigned portBASE_TYPE uxFlashTaskNumber = 0;
/* The task that is created three times. */
static portTASK_FUNCTION_PROTO( vLEDFlashTask, pvParameters );
/*-----------------------------------------------------------*/
void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority )
{
signed portBASE_TYPE xLEDTask;
/* Create the three tasks. */
for( xLEDTask = 0; xLEDTask < ledNUMBER_OF_LEDS; ++xLEDTask )
{
/* Spawn the task. */
xTaskCreate( vLEDFlashTask, ( signed portCHAR * ) "LEDx", ledSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL );
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vLEDFlashTask, pvParameters )
{
portTickType xFlashRate, xLastFlashTime;
unsigned portBASE_TYPE uxLED;
/* The parameters are not used. */
( void ) pvParameters;
/* Calculate the LED and flash rate. */
portENTER_CRITICAL();
{
/* See which of the eight LED's we should use. */
uxLED = uxFlashTaskNumber;
/* Update so the next task uses the next LED. */
uxFlashTaskNumber++;
}
portEXIT_CRITICAL();
xFlashRate = ledFLASH_RATE_BASE + ( ledFLASH_RATE_BASE * ( portTickType ) uxLED );
xFlashRate /= portTICK_RATE_MS;
/* We will turn the LED on and off again in the delay period, so each
delay is only half the total period. */
xFlashRate /= ( portTickType ) 2;
/* We need to initialise xLastFlashTime prior to the first call to
vTaskDelayUntil(). */
xLastFlashTime = xTaskGetTickCount();
for(;;)
{
/* Delay for half the flash period then turn the LED on. */
vTaskDelayUntil( &xLastFlashTime, xFlashRate );
vParTestToggleLED( uxLED );
/* Delay for half the flash period then turn the LED off. */
vTaskDelayUntil( &xLastFlashTime, xFlashRate );
vParTestToggleLED( uxLED );
}
} /*lint !e715 !e818 !e830 Function definition must be standard for task creation. */

340
20080212/Demo/Common/Minimal/flop.c Normal file
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@ -0,0 +1,340 @@
/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* Creates eight tasks, each of which loops continuously performing an (emulated)
* floating point calculation.
*
* All the tasks run at the idle priority and never block or yield. This causes
* all eight tasks to time slice with the idle task. Running at the idle priority
* means that these tasks will get pre-empted any time another task is ready to run
* or a time slice occurs. More often than not the pre-emption will occur mid
* calculation, creating a good test of the schedulers context switch mechanism - a
* calculation producing an unexpected result could be a symptom of a corruption in
* the context of a task.
*/
#include <stdlib.h>
#include <math.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo program include files. */
#include "flop.h"
#define mathSTACK_SIZE configMINIMAL_STACK_SIZE
#define mathNUMBER_OF_TASKS ( 8 )
/* Four tasks, each of which performs a different floating point calculation.
Each of the four is created twice. */
static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters );
/* These variables are used to check that all the tasks are still running. If a
task gets a calculation wrong it will
stop incrementing its check variable. */
static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };
/*-----------------------------------------------------------*/
void vStartMathTasks( unsigned portBASE_TYPE uxPriority )
{
xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask1, pvParameters )
{
volatile portDOUBLE d1, d2, d3, d4;
volatile unsigned portSHORT *pusTaskCheckVariable;
volatile portDOUBLE dAnswer;
portSHORT sError = pdFALSE;
d1 = 123.4567;
d2 = 2345.6789;
d3 = -918.222;
dAnswer = ( d1 + d2 ) * d3;
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
/* Keep performing a calculation and checking the result against a constant. */
for(;;)
{
d1 = 123.4567;
d2 = 2345.6789;
d3 = -918.222;
d4 = ( d1 + d2 ) * d3;
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* If the calculation does not match the expected constant, stop the
increment of the check variable. */
if( fabs( d4 - dAnswer ) > 0.001 )
{
sError = pdTRUE;
}
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask2, pvParameters )
{
volatile portDOUBLE d1, d2, d3, d4;
volatile unsigned portSHORT *pusTaskCheckVariable;
volatile portDOUBLE dAnswer;
portSHORT sError = pdFALSE;
d1 = -389.38;
d2 = 32498.2;
d3 = -2.0001;
dAnswer = ( d1 / d2 ) * d3;
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
/* Keep performing a calculation and checking the result against a constant. */
for( ;; )
{
d1 = -389.38;
d2 = 32498.2;
d3 = -2.0001;
d4 = ( d1 / d2 ) * d3;
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* If the calculation does not match the expected constant, stop the
increment of the check variable. */
if( fabs( d4 - dAnswer ) > 0.001 )
{
sError = pdTRUE;
}
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know
this task is still running okay. */
( *pusTaskCheckVariable )++;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask3, pvParameters )
{
volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
volatile unsigned portSHORT *pusTaskCheckVariable;
const size_t xArraySize = 10;
size_t xPosition;
portSHORT sError = pdFALSE;
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );
/* Keep filling an array, keeping a running total of the values placed in the
array. Then run through the array adding up all the values. If the two totals
do not match, stop the check variable from incrementing. */
for( ;; )
{
dTotal1 = 0.0;
dTotal2 = 0.0;
for( xPosition = 0; xPosition < xArraySize; xPosition++ )
{
pdArray[ xPosition ] = ( portDOUBLE ) xPosition + 5.5;
dTotal1 += ( portDOUBLE ) xPosition + 5.5;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
for( xPosition = 0; xPosition < xArraySize; xPosition++ )
{
dTotal2 += pdArray[ xPosition ];
}
dDifference = dTotal1 - dTotal2;
if( fabs( dDifference ) > 0.001 )
{
sError = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask4, pvParameters )
{
volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
volatile unsigned portSHORT *pusTaskCheckVariable;
const size_t xArraySize = 10;
size_t xPosition;
portSHORT sError = pdFALSE;
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );
/* Keep filling an array, keeping a running total of the values placed in the
array. Then run through the array adding up all the values. If the two totals
do not match, stop the check variable from incrementing. */
for( ;; )
{
dTotal1 = 0.0;
dTotal2 = 0.0;
for( xPosition = 0; xPosition < xArraySize; xPosition++ )
{
pdArray[ xPosition ] = ( portDOUBLE ) xPosition * 12.123;
dTotal1 += ( portDOUBLE ) xPosition * 12.123;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
for( xPosition = 0; xPosition < xArraySize; xPosition++ )
{
dTotal2 += pdArray[ xPosition ];
}
dDifference = dTotal1 - dTotal2;
if( fabs( dDifference ) > 0.001 )
{
sError = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreMathsTaskStillRunning( void )
{
/* Keep a history of the check variables so we know if they have been incremented
since the last call. */
static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };
portBASE_TYPE xReturn = pdTRUE, xTask;
/* Check the maths tasks are still running by ensuring their check variables
are still incrementing. */
for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
{
if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
{
/* The check has not incremented so an error exists. */
xReturn = pdFALSE;
}
usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
}
return xReturn;
}

201
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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* This version of integer. c is for use on systems that have limited stack
* space and no display facilities. The complete version can be found in
* the Demo/Common/Full directory.
*
* As with the full version, the tasks created in this file are a good test
* of the scheduler context switch mechanism. The processor has to access
* 32bit variables in two or four chunks (depending on the processor). The low
* priority of these tasks means there is a high probability that a context
* switch will occur mid calculation. See flop. c documentation for
* more information.
*
*/
/*
Changes from V1.2.1
+ The constants used in the calculations are larger to ensure the
optimiser does not truncate them to 16 bits.
Changes from V1.2.3
+ uxTaskCheck is now just used as a boolean. Instead of incrementing
the variable each cycle of the task, the variable is simply set to
true. sAreIntegerMathsTaskStillRunning() sets it back to false and
expects it to have been set back to true by the time it is called
again.
+ A division has been included in the calculation.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo program include files. */
#include "integer.h"
/* The constants used in the calculation. */
#define intgCONST1 ( ( portLONG ) 123 )
#define intgCONST2 ( ( portLONG ) 234567 )
#define intgCONST3 ( ( portLONG ) -3 )
#define intgCONST4 ( ( portLONG ) 7 )
#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )
#define intgSTACK_SIZE configMINIMAL_STACK_SIZE
/* As this is the minimal version, we will only create one task. */
#define intgNUMBER_OF_TASKS ( 1 )
/* The task function. Repeatedly performs a 32 bit calculation, checking the
result against the expected result. If the result is incorrect then the
context switch must have caused some corruption. */
static portTASK_FUNCTION_PROTO( vCompeteingIntMathTask, pvParameters );
/* Variables that are set to true within the calculation task to indicate
that the task is still executing. The check task sets the variable back to
false, flagging an error if the variable is still false the next time it
is called. */
static volatile signed portBASE_TYPE xTaskCheck[ intgNUMBER_OF_TASKS ] = { ( signed portBASE_TYPE ) pdFALSE };
/*-----------------------------------------------------------*/
void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority )
{
portSHORT sTask;
for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )
{
xTaskCreate( vCompeteingIntMathTask, ( signed portCHAR * ) "IntMath", intgSTACK_SIZE, ( void * ) &( xTaskCheck[ sTask ] ), uxPriority, ( xTaskHandle * ) NULL );
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompeteingIntMathTask, pvParameters )
{
/* These variables are all effectively set to constants so they are volatile to
ensure the compiler does not just get rid of them. */
volatile portLONG lValue;
portSHORT sError = pdFALSE;
volatile signed portBASE_TYPE *pxTaskHasExecuted;
/* Set a pointer to the variable we are going to set to true each
iteration. This is also a good test of the parameter passing mechanism
within each port. */
pxTaskHasExecuted = ( volatile signed portBASE_TYPE * ) pvParameters;
/* Keep performing a calculation and checking the result against a constant. */
for( ;; )
{
/* Perform the calculation. This will store partial value in
registers, resulting in a good test of the context switch mechanism. */
lValue = intgCONST1;
lValue += intgCONST2;
/* Yield in case cooperative scheduling is being used. */
#if configUSE_PREEMPTION == 0
{
taskYIELD();
}
#endif
/* Finish off the calculation. */
lValue *= intgCONST3;
lValue /= intgCONST4;
/* If the calculation is found to be incorrect we stop setting the
TaskHasExecuted variable so the check task can see an error has
occurred. */
if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */
{
sError = pdTRUE;
}
if( sError == pdFALSE )
{
/* We have not encountered any errors, so set the flag that show
we are still executing. This will be periodically cleared by
the check task. */
portENTER_CRITICAL();
*pxTaskHasExecuted = pdTRUE;
portEXIT_CRITICAL();
}
/* Yield in case cooperative scheduling is being used. */
#if configUSE_PREEMPTION == 0
{
taskYIELD();
}
#endif
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreIntegerMathsTaskStillRunning( void )
{
portBASE_TYPE xReturn = pdTRUE;
portSHORT sTask;
/* Check the maths tasks are still running by ensuring their check variables
are still being set to true. */
for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )
{
if( xTaskCheck[ sTask ] == pdFALSE )
{
/* The check has not incremented so an error exists. */
xReturn = pdFALSE;
}
/* Reset the check variable so we can tell if it has been set by
the next time around. */
xTaskCheck[ sTask ] = pdFALSE;
}
return xReturn;
}

340
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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
The tasks defined on this page demonstrate the use of recursive mutexes.
For recursive mutex functionality the created mutex should be created using
xSemaphoreCreateRecursiveMutex(), then be manipulated
using the xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() API
functions.
This demo creates three tasks all of which access the same recursive mutex:
prvRecursiveMutexControllingTask() has the highest priority so executes
first and grabs the mutex. It then performs some recursive accesses -
between each of which it sleeps for a short period to let the lower
priority tasks execute. When it has completed its demo functionality
it gives the mutex back before suspending itself.
prvRecursiveMutexBlockingTask() attempts to access the mutex by performing
a blocking 'take'. The blocking task has a lower priority than the
controlling task so by the time it executes the mutex has already been
taken by the controlling task, causing the blocking task to block. It
does not unblock until the controlling task has given the mutex back,
and it does not actually run until the controlling task has suspended
itself (due to the relative priorities). When it eventually does obtain
the mutex all it does is give the mutex back prior to also suspending
itself. At this point both the controlling task and the blocking task are
suspended.
prvRecursiveMutexPollingTask() runs at the idle priority. It spins round
a tight loop attempting to obtain the mutex with a non-blocking call. As
the lowest priority task it will not successfully obtain the mutex until
both the controlling and blocking tasks are suspended. Once it eventually
does obtain the mutex it first unsuspends both the controlling task and
blocking task prior to giving the mutex back - resulting in the polling
task temporarily inheriting the controlling tasks priority.
*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Demo app include files. */
#include "recmutex.h"
/* Priorities assigned to the three tasks. */
#define recmuCONTROLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define recmuBLOCKING_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define recmuPOLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 )
/* The recursive call depth. */
#define recmuMAX_COUNT ( 10 )
/* Misc. */
#define recmuSHORT_DELAY ( 20 / portTICK_RATE_MS )
#define recmuNO_DELAY ( ( portTickType ) 0 )
#define recmuONE_TICK_DELAY ( ( portTickType ) 1 )
/* The three tasks as described at the top of this file. */
static void prvRecursiveMutexControllingTask( void *pvParameters );
static void prvRecursiveMutexBlockingTask( void *pvParameters );
static void prvRecursiveMutexPollingTask( void *pvParameters );
/* The mutex used by the demo. */
static xSemaphoreHandle xMutex;
/* Variables used to detect and latch errors. */
static portBASE_TYPE xErrorOccurred = pdFALSE, xControllingIsSuspended = pdFALSE, xBlockingIsSuspended = pdFALSE;
static unsigned portBASE_TYPE uxControllingCycles = 0, uxBlockingCycles, uxPollingCycles = 0;
/* Handles of the two higher priority tasks, required so they can be resumed
(unsuspended). */
static xTaskHandle xControllingTaskHandle, xBlockingTaskHandle;
/*-----------------------------------------------------------*/
void vStartRecursiveMutexTasks( void )
{
/* Just creates the mutex and the three tasks. */
xMutex = xSemaphoreCreateRecursiveMutex();
if( xMutex != NULL )
{
xTaskCreate( prvRecursiveMutexControllingTask, "Rec1", configMINIMAL_STACK_SIZE, NULL, recmuCONTROLLING_TASK_PRIORITY, &xControllingTaskHandle );
xTaskCreate( prvRecursiveMutexBlockingTask, "Rec2", configMINIMAL_STACK_SIZE, NULL, recmuBLOCKING_TASK_PRIORITY, &xBlockingTaskHandle );
xTaskCreate( prvRecursiveMutexPollingTask, "Rec3", configMINIMAL_STACK_SIZE, NULL, recmuPOLLING_TASK_PRIORITY, NULL );
}
}
/*-----------------------------------------------------------*/
static void prvRecursiveMutexControllingTask( void *pvParameters )
{
unsigned portBASE_TYPE ux;
for( ;; )
{
/* Should not be able to 'give' the mutex, as we have not yet 'taken'
it. */
if( xSemaphoreGiveRecursive( xMutex ) == pdPASS )
{
xErrorOccurred = pdTRUE;
}
for( ux = 0; ux < recmuMAX_COUNT; ux++ )
{
/* We should now be able to take the mutex as many times as
we like. A one tick delay is used so the polling task will
inherit our priority on all but the first cycle of this task.
If we did not block attempting to receive the mutex then no
priority inheritance would occur. */
if( xSemaphoreTakeRecursive( xMutex, recmuONE_TICK_DELAY ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
/* Ensure the other task attempting to access the mutex (and the
other demo tasks) are able to execute. */
vTaskDelay( recmuSHORT_DELAY );
}
/* For each time we took the mutex, give it back. */
for( ux = 0; ux < recmuMAX_COUNT; ux++ )
{
/* Ensure the other task attempting to access the mutex (and the
other demo tasks) are able to execute. */
vTaskDelay( recmuSHORT_DELAY );
/* We should now be able to give the mutex as many times as we
took it. */
if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
}
/* Having given it back the same number of times as it was taken, we
should no longer be the mutex owner, so the next give should fail. */
if( xSemaphoreGiveRecursive( xMutex ) == pdPASS )
{
xErrorOccurred = pdTRUE;
}
/* Keep count of the number of cycles this task has performed so a
stall can be detected. */
uxControllingCycles++;
/* Suspend ourselves to the blocking task can execute. */
xControllingIsSuspended = pdTRUE;
vTaskSuspend( NULL );
xControllingIsSuspended = pdFALSE;
}
}
/*-----------------------------------------------------------*/
static void prvRecursiveMutexBlockingTask( void *pvParameters )
{
for( ;; )
{
/* Attempt to obtain the mutex. We should block until the
controlling task has given up the mutex, and not actually execute
past this call until the controlling task is suspended. */
if( xSemaphoreTakeRecursive( xMutex, portMAX_DELAY ) == pdPASS )
{
if( xControllingIsSuspended != pdTRUE )
{
/* Did not expect to execute until the controlling task was
suspended. */
xErrorOccurred = pdTRUE;
}
else
{
/* Give the mutex back before suspending ourselves to allow
the polling task to obtain the mutex. */
if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
xBlockingIsSuspended = pdTRUE;
vTaskSuspend( NULL );
xBlockingIsSuspended = pdFALSE;
}
}
else
{
/* We should not leave the xSemaphoreTakeRecursive() function
until the mutex was obtained. */
xErrorOccurred = pdTRUE;
}
/* The controlling and blocking tasks should be in lock step. */
if( uxControllingCycles != ( uxBlockingCycles + 1 ) )
{
xErrorOccurred = pdTRUE;
}
/* Keep count of the number of cycles this task has performed so a
stall can be detected. */
uxBlockingCycles++;
}
}
/*-----------------------------------------------------------*/
static void prvRecursiveMutexPollingTask( void *pvParameters )
{
for( ;; )
{
/* Keep attempting to obtain the mutex. We should only obtain it when
the blocking task has suspended itself. */
if( xSemaphoreTakeRecursive( xMutex, recmuNO_DELAY ) == pdPASS )
{
/* Is the blocking task suspended? */
if( xBlockingIsSuspended != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
else
{
/* Keep count of the number of cycles this task has performed so
a stall can be detected. */
uxPollingCycles++;
/* We can resume the other tasks here even though they have a
higher priority than the polling task. When they execute they
will attempt to obtain the mutex but fail because the polling
task is still the mutex holder. The polling task (this task)
will then inherit the higher priority. */
vTaskResume( xBlockingTaskHandle );
vTaskResume( xControllingTaskHandle );
/* Release the mutex, disinheriting the higher priority again. */
if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
{
xErrorOccurred = pdTRUE;
}
}
}
#if configUSE_PREEMPTION == 0
{
taskYIELD();
}
#endif
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreRecursiveMutexTasksStillRunning( void )
{
portBASE_TYPE xReturn;
static unsigned portBASE_TYPE uxLastControllingCycles = 0, uxLastBlockingCycles = 0, uxLastPollingCycles = 0;
/* Is the controlling task still cycling? */
if( uxLastControllingCycles == uxControllingCycles )
{
xErrorOccurred = pdTRUE;
}
else
{
uxLastControllingCycles = uxControllingCycles;
}
/* Is the blocking task still cycling? */
if( uxLastBlockingCycles == uxBlockingCycles )
{
xErrorOccurred = pdTRUE;
}
else
{
uxLastBlockingCycles = uxBlockingCycles;
}
/* Is the polling task still cycling? */
if( uxLastPollingCycles == uxPollingCycles )
{
xErrorOccurred = pdTRUE;
}
else
{
uxLastPollingCycles = uxPollingCycles;
}
if( xErrorOccurred == pdTRUE )
{
xReturn = pdFAIL;
}
else
{
xReturn = pdTRUE;
}
return xReturn;
}

264
20080212/Demo/Common/Minimal/semtest.c Normal file
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/*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/*
* Creates two sets of two tasks. The tasks within a set share a variable, access
* to which is guarded by a semaphore.
*
* Each task starts by attempting to obtain the semaphore. On obtaining a
* semaphore a task checks to ensure that the guarded variable has an expected
* value. It then clears the variable to zero before counting it back up to the
* expected value in increments of 1. After each increment the variable is checked
* to ensure it contains the value to which it was just set. When the starting
* value is again reached the task releases the semaphore giving the other task in
* the set a chance to do exactly the same thing. The starting value is high
* enough to ensure that a tick is likely to occur during the incrementing loop.
*
* An error is flagged if at any time during the process a shared variable is
* found to have a value other than that expected. Such an occurrence would
* suggest an error in the mutual exclusion mechanism by which access to the
* variable is restricted.
*
* The first set of two tasks poll their semaphore. The second set use blocking
* calls.
*
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Demo app include files. */
#include "semtest.h"
/* The value to which the shared variables are counted. */
#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xfff )
#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xff )
#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE
#define semtstNUM_TASKS ( 4 )
#define semtstDELAY_FACTOR ( ( portTickType ) 10 )
/* The task function as described at the top of the file. */
static portTASK_FUNCTION_PROTO( prvSemaphoreTest, pvParameters );
/* Structure used to pass parameters to each task. */
typedef struct SEMAPHORE_PARAMETERS
{
xSemaphoreHandle xSemaphore;
volatile unsigned portLONG *pulSharedVariable;
portTickType xBlockTime;
} xSemaphoreParameters;
/* Variables used to check that all the tasks are still running without errors. */
static volatile portSHORT sCheckVariables[ semtstNUM_TASKS ] = { 0 };
static volatile portSHORT sNextCheckVariable = 0;
/*-----------------------------------------------------------*/
void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority )
{
xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters;
const portTickType xBlockTime = ( portTickType ) 100;
/* Create the structure used to pass parameters to the first two tasks. */
pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
if( pxFirstSemaphoreParameters != NULL )
{
/* Create the semaphore used by the first two tasks. */
vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore );
if( pxFirstSemaphoreParameters->xSemaphore != NULL )
{
/* Create the variable which is to be shared by the first two tasks. */
pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) );
/* Initialise the share variable to the value the tasks expect. */
*( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE;
/* The first two tasks do not block on semaphore calls. */
pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0;
/* Spawn the first two tasks. As they poll they operate at the idle priority. */
xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );
xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );
}
}
/* Do exactly the same to create the second set of tasks, only this time
provide a block time for the semaphore calls. */
pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
if( pxSecondSemaphoreParameters != NULL )
{
vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore );
if( pxSecondSemaphoreParameters->xSemaphore != NULL )
{
pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) );
*( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE;
pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS;
xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL );
xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL );
}
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( prvSemaphoreTest, pvParameters )
{
xSemaphoreParameters *pxParameters;
volatile unsigned portLONG *pulSharedVariable, ulExpectedValue;
unsigned portLONG ulCounter;
portSHORT sError = pdFALSE, sCheckVariableToUse;
/* See which check variable to use. sNextCheckVariable is not semaphore
protected! */
portENTER_CRITICAL();
sCheckVariableToUse = sNextCheckVariable;
sNextCheckVariable++;
portEXIT_CRITICAL();
/* A structure is passed in as the parameter. This contains the shared
variable being guarded. */
pxParameters = ( xSemaphoreParameters * ) pvParameters;
pulSharedVariable = pxParameters->pulSharedVariable;
/* If we are blocking we use a much higher count to ensure loads of context
switches occur during the count. */
if( pxParameters->xBlockTime > ( portTickType ) 0 )
{
ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE;
}
else
{
ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE;
}
for( ;; )
{
/* Try to obtain the semaphore. */
if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS )
{
/* We have the semaphore and so expect any other tasks using the
shared variable to have left it in the state we expect to find
it. */
if( *pulSharedVariable != ulExpectedValue )
{
sError = pdTRUE;
}
/* Clear the variable, then count it back up to the expected value
before releasing the semaphore. Would expect a context switch or
two during this time. */
for( ulCounter = ( unsigned portLONG ) 0; ulCounter <= ulExpectedValue; ulCounter++ )
{
*pulSharedVariable = ulCounter;
if( *pulSharedVariable != ulCounter )
{
sError = pdTRUE;
}
}
/* Release the semaphore, and if no errors have occurred increment the check
variable. */
if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE )
{
sError = pdTRUE;
}
if( sError == pdFALSE )
{
if( sCheckVariableToUse < semtstNUM_TASKS )
{
( sCheckVariables[ sCheckVariableToUse ] )++;
}
}
/* If we have a block time then we are running at a priority higher
than the idle priority. This task takes a long time to complete
a cycle (deliberately so to test the guarding) so will be starving
out lower priority tasks. Block for some time to allow give lower
priority tasks some processor time. */
vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR );
}
else
{
if( pxParameters->xBlockTime == ( portTickType ) 0 )
{
/* We have not got the semaphore yet, so no point using the
processor. We are not blocking when attempting to obtain the
semaphore. */
taskYIELD();
}
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreSemaphoreTasksStillRunning( void )
{
static portSHORT sLastCheckVariables[ semtstNUM_TASKS ] = { 0 };
portBASE_TYPE xTask, xReturn = pdTRUE;
for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ )
{
if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] )
{
xReturn = pdFALSE;
}
sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ];
}
return xReturn;
}

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IMPORTANT. Read the following LMI Software License Agreement ("Agreement")
completely.
In summary, this license agreement allows you to use this software only on
Luminary Micro microcontrollers, on an as-is basis, with no warranties.
LUMINARY MICRO SOFTWARE LICENSE AGREEMENT
This is a legal agreement between you (either as an individual or as an
authorized representative of your employer) and Luminary Micro, Inc. ("LMI").
It concerns your rights to use this file and any accompanying written materials
(the "Software"). In consideration for LMI allowing you to access the Software,
you are agreeing to be bound by the terms of this Agreement. If you do not
agree to all of the terms of this Agreement, do not download the Software. If
you change your mind later, stop using the Software and delete all copies of
the Software in your possession or control. Any copies of the Software that you
have already distributed, where permitted, and do not destroy will continue to
be governed by this Agreement. Your prior use will also continue to be governed
by this Agreement.
1. LICENSE GRANT. LMI grants to you, free of charge, the non-exclusive,
non-transferable right (1) to use the Software solely and exclusively on LMI's
microcontroller products, (2) to reproduce the Software, (3) to prepare
derivative works of the Software, (4) to distribute the Software and derivative
works thereof in source (human-readable) form and object (machine-readable)
form, and (5) to sublicense to others the right to use the distributed
Software. If you violate any of the terms or restrictions of this Agreement,
LMI may immediately terminate this Agreement, and require that you stop using
and delete all copies of the Software in your possession or control.
2. COPYRIGHT. The Software is licensed to you, not sold. LMI owns the Software,
and United States copyright laws and international treaty provisions protect
the Software. Therefore, you must treat the Software like any other copyrighted
material (e.g. a book or musical recording). You may not use or copy the
Software for any other purpose than what is described in this Agreement. Except
as expressly provided herein, LMI does not grant to you any express or implied
rights under any LMI or third-party patents, copyrights, trademarks, or trade
secrets. Additionally, you must reproduce and apply any copyright or other
proprietary rights notices included on or embedded in the Software to any
copies or derivative works made thereof, in whole or in part, if any.
3. SUPPORT. LMI is NOT obligated to provide any support, upgrades or new
releases of the Software. If you wish, you may contact LMI and report problems
and provide suggestions regarding the Software. LMI has no obligation
whatsoever to respond in any way to such a problem report or suggestion. LMI
may make changes to the Software at any time, without any obligation to notify
or provide updated versions of the Software to you.
4. INDEMNITY. You agree to fully defend and indemnify LMI from any and all
claims, liabilities, and costs (including reasonable attorney's fees) related
to (1) your use (including your sub-licensee's use, if permitted) of the
Software or (2) your violation of the terms and conditions of this Agreement.
5. HIGH RISK ACTIVITIES. You acknowledge that the Software is not fault
tolerant and is not designed, manufactured or intended by LMI for incorporation
into products intended for use or resale in on-line control equipment in
hazardous, dangerous to life or potentially life-threatening environments
requiring fail-safe performance, such as in the operation of nuclear
facilities, aircraft navigation or communication systems, air traffic control,
direct life support machines or weapons systems, in which the failure of
products could lead directly to death, personal injury or severe physical or
environmental damage ("High Risk Activities"). You specifically represent and
warrant that you will not use the Software or any derivative work of the
Software for High Risk Activities.
6. PRODUCT LABELING. You are not authorized to use any LMI trademarks, brand
names, or logos.
7. COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS. You must use the Software in
accordance with all applicable U.S. laws, regulations and statutes. You agree
that neither you nor your licensees (if any) intend to or will, directly or
indirectly, export or transmit the Software to any country in violation of U.S.
export restrictions.
8. GOVERNMENT USE. Use of the Software and any corresponding documentation, if
any, is provided with RESTRICTED RIGHTS. Use, duplication or disclosure by the
Government is subject to restrictions as set forth in subparagraph (c)(1)(ii)
of The Rights in Technical Data and Computer Software clause at DFARS
252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial Computer
Software--Restricted Rights at 48 CFR 52.227-19, as applicable. Manufacturer is
Luminary Micro, Inc., 108 Wild Basin Road, Ste 350, Austin, Texas 78746.
9. DISCLAIMER OF WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI
EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED "AS
IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING,
WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING THE
SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A WARRANTY OR
REPRESENTATION BY LMI THAT THE SOFTWARE OR ANY DERIVATIVE WORK DEVELOPED WITH
OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF THE
INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES.
10. LIMITATION OF LIABILITY. IN NO EVENT WILL LMI BE LIABLE, WHETHER IN
CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT,
CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR
ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS,
SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW.
11. CHOICE OF LAW; VENUE; LIMITATIONS. You agree that the statutes and laws of
the United States and the State of Texas, USA, without regard to conflicts of
laws principles, will apply to all matters relating to this Agreement or the
Software, and you agree that any litigation will be subject to the exclusive
jurisdiction of the state or federal courts in Austin, Travis County, Texas,
USA. You agree that regardless of any statute or law to the contrary, any claim
or cause of action arising out of or related to this Agreement or the Software
must be filed within one (1) year after such claim or cause of action arose or
be forever barred. YOU EXPRESSLY AGREE THAT YOU WAIVE YOUR INDIVIDUAL RIGHT TO
A TRIAL BY JURY IN ANY COURT OF COMPETENT JURISDICTION FOR ANY ACTION, DISPUTE,
CLAIM, OR CONTROVERSY CONCERNING THIS AGREEMENT OR FOR ANY ACTION, DISPUTE,
CLAIM, OR CONTROVERSY ARISING OUT OF OR RELATING TO ANY INTERPRETATION,
CONSTRUCTION, PERFORMANCE OR BREACH OF THIS AGREEMENT.
12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement between
you and LMI regarding the subject matter of this Agreement, and supersedes all
prior communications, negotiations, understandings, agreements or
representations, either written or oral, if any. This Agreement may only be
amended in written form, executed by you and LMI.
13. SEVERABILITY. If any provision of this Agreement is held for any reason to
be invalid or unenforceable, then the remaining provisions of this Agreement
will be unimpaired and, unless a modification or replacement of the invalid or
unenforceable provision is further held to deprive you or LMI of a material
benefit, in which case the Agreement will immediately terminate, the invalid or
unenforceable provision will be replaced with a provision that is valid and
enforceable and that comes closest to the intention underlying the invalid or
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14. NO WAIVER. The waiver by LMI of any breach of any provision of this
Agreement will not operate or be construed as a waiver of any other or a
subsequent breach of the same or a different provision.

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//*****************************************************************************
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __ADC_H__
#define __ADC_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ADCSequenceConfigure as the ulTrigger
// parameter.
//
//*****************************************************************************
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
//*****************************************************************************
//
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
// parameter.
//
//*****************************************************************************
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
#define ADC_CTL_IE 0x00000040 // Interrupt enable
#define ADC_CTL_END 0x00000020 // Sequence end select
#define ADC_CTL_D 0x00000010 // Differential select
#define ADC_CTL_CH0 0x00000000 // Input channel 0
#define ADC_CTL_CH1 0x00000001 // Input channel 1
#define ADC_CTL_CH2 0x00000002 // Input channel 2
#define ADC_CTL_CH3 0x00000003 // Input channel 3
#define ADC_CTL_CH4 0x00000004 // Input channel 4
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
void (*pfnHandler)(void));
extern void ADCIntUnregister(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
extern unsigned long ADCIntStatus(unsigned long ulBase,
unsigned long ulSequenceNum,
tBoolean bMasked);
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCSequenceEnable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceDisable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulTrigger,
unsigned long ulPriority);
extern void ADCSequenceStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern long ADCSequenceOverflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceOverflowClear(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceUnderflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceUnderflowClear(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer);
extern void ADCProcessorTrigger(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulFactor);
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer,
unsigned long ulCount);
extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
unsigned long ulFactor);
#ifdef __cplusplus
}
#endif
#endif // __ADC_H__

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//*****************************************************************************
//
// can.h - Defines and Macros for the CAN controller.
//
// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __CAN_H__
#define __CAN_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup can_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Miscellaneous defines for Message ID Types
//
//*****************************************************************************
//*****************************************************************************
//
//! These are the flags used by the tCANMsgObject variable when calling the
//! the CANMessageSet() and CANMessageGet() APIs.
//
//*****************************************************************************
typedef enum
{
//
//! This indicates that transmit interrupts should be enabled, or are
//! enabled.
//
MSG_OBJ_TX_INT_ENABLE = 0x00000001,
//
//! This indicates that receive interrupts should be enabled or are
//! enabled.
//
MSG_OBJ_RX_INT_ENABLE = 0x00000002,
//
//! This indicates that a message object will use or is using an extended
//! identifier.
//
MSG_OBJ_EXTENDED_ID = 0x00000004,
//
//! This indicates that a message object will use or is using filtering
//! based on the object's message Identifier.
//
MSG_OBJ_USE_ID_FILTER = 0x00000008,
//
//! This indicates that new data was available in the message object.
//
MSG_OBJ_NEW_DATA = 0x00000080,
//
//! This indicates that data was lost since this message object was last
//! read.
//
MSG_OBJ_DATA_LOST = 0x00000100,
//
//! This indicates that a message object will use or is using filtering
//! based on the direction of the transfer. If the direction filtering is
//! used then ID filtering must also be enabled.
//
MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),
//
//! This indicates that a message object will use or is using message
//! identifier filtering based of the the extended identifier.
//! If the extended identifier filtering is used then ID filtering must
//! also be enabled.
//
MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),
//
//! This indicates that a message object is a remote frame.
//
MSG_OBJ_REMOTE_FRAME = 0x00000040,
//
//! This indicates that a message object has no flags set.
//
MSG_OBJ_NO_FLAGS = 0x00000000
}
tCANObjFlags;
//*****************************************************************************
//
//! This define is used with the #tCANObjFlags enumerated values to allow
//! checking only status flags and not configuration flags.
//
//*****************************************************************************
#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
//*****************************************************************************
//
//! This structure used for encapsulating all the items associated with a CAN
//! message object in the CAN controller.
//
//*****************************************************************************
typedef struct
{
//
//! The CAN message identifier used for 11 or 29 bit identifiers.
//
unsigned long ulMsgID;
//
//! The message identifier mask used when identifier filtering is enabled.
//
unsigned long ulMsgIDMask;
//
//! This value holds various status flags and settings specified by
//! tCANObjFlags.
//
unsigned long ulFlags;
//
//! This value is the number of bytes of data in the message object.
//
unsigned long ulMsgLen;
//
//! This is a pointer to the message object's data.
//
unsigned char *pucMsgData;
}
tCANMsgObject;
//*****************************************************************************
//
//! This structure is used for encapsulating the values associated with setting
//! up the bit timing for a CAN controller. The structure is used when calling
//! the CANGetBitTiming and CANSetBitTiming functions.
//
//*****************************************************************************
typedef struct
{
//
//! This value holds the sum of the Synchronization, Propagation, and Phase
//! Buffer 1 segments, measured in time quanta. The valid values for this
//! setting range from 2 to 16.
//
unsigned int uSyncPropPhase1Seg;
//
//! This value holds the Phase Buffer 2 segment in time quanta. The valid
//! values for this setting range from 1 to 8.
//
unsigned int uPhase2Seg;
//
//! This value holds the Resynchronization Jump Width in time quanta. The
//! valid values for this setting range from 1 to 4.
//
unsigned int uSJW;
//
//! This value holds the CAN_CLK divider used to determine time quanta.
//! The valid values for this setting range from 1 to 1023.
//
unsigned int uQuantumPrescaler;
}
tCANBitClkParms;
//*****************************************************************************
//
//! This data type is used to identify the interrupt status register. This is
//! used when calling the a CANIntStatus() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the CAN interrupt status information.
//
CAN_INT_STS_CAUSE,
//
//! Read a message object's interrupt status.
//
CAN_INT_STS_OBJECT
}
tCANIntStsReg;
//*****************************************************************************
//
//! This data type is used to identify which of the several status registers
//! to read when calling the CANStatusGet() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the full CAN controller status.
//
CAN_STS_CONTROL,
//
//! Read the full 32 bit mask of message objects with a transmit request
//! set.
//
CAN_STS_TXREQUEST,
//
//! Read the full 32 bit mask of message objects with a new data available.
//
CAN_STS_NEWDAT,
//
//! Read the full 32 bit mask of message objects that are enabled.
//
CAN_STS_MSGVAL
}
tCANStsReg;
//*****************************************************************************
//
//! These definitions are used to specify interrupt sources to CANIntEnable()
//! and CANIntDisable().
//
//*****************************************************************************
typedef enum
{
//
//! This flag is used to allow a CAN controller to generate error
//! interrupts.
//
CAN_INT_ERROR = 0x00000008,
//
//! This flag is used to allow a CAN controller to generate status
//! interrupts.
//
CAN_INT_STATUS = 0x00000004,
//
//! This flag is used to allow a CAN controller to generate any CAN
//! interrupts. If this is not set then no interrupts will be generated by
//! the CAN controller.
//
CAN_INT_MASTER = 0x00000002
}
tCANIntFlags;
//*****************************************************************************
//
//! This definition is used to determine the type of message object that will
//! be set up via a call to the CANMessageSet() API.
//
//*****************************************************************************
typedef enum
{
//
//! Transmit message object.
//
MSG_OBJ_TYPE_TX,
//
//! Transmit remote request message object
//
MSG_OBJ_TYPE_TX_REMOTE,
//
//! Receive message object.
//
MSG_OBJ_TYPE_RX,
//
//! Receive remote request message object.
//
MSG_OBJ_TYPE_RX_REMOTE,
//
//! Remote frame receive remote, with auto-transmit message object.
//
MSG_OBJ_TYPE_RXTX_REMOTE
}
tMsgObjType;
//*****************************************************************************
//
//! The following enumeration contains all error or status indicators that
//! can be returned when calling the CANStatusGet() API.
//
//*****************************************************************************
typedef enum
{
//
//! CAN controller has entered a Bus Off state.
//
CAN_STATUS_BUS_OFF = 0x00000080,
//
//! CAN controller error level has reached warning level.
//
CAN_STATUS_EWARN = 0x00000040,
//
//! CAN controller error level has reached error passive level.
//
CAN_STATUS_EPASS = 0x00000020,
//
//! A message was received successfully since the last read of this status.
//
CAN_STATUS_RXOK = 0x00000010,
//
//! A message was transmitted successfully since the last read of this
//! status.
//
CAN_STATUS_TXOK = 0x00000008,
//
//! This is the mask for the last error code field.
//
CAN_STATUS_LEC_MSK = 0x00000007,
//
//! There was no error.
//
CAN_STATUS_LEC_NONE = 0x00000000,
//
//! A bit stuffing error has occurred.
//
CAN_STATUS_LEC_STUFF = 0x00000001,
//
//! A formatting error has occurred.
//
CAN_STATUS_LEC_FORM = 0x00000002,
//
//! An acknowledge error has occurred.
//
CAN_STATUS_LEC_ACK = 0x00000003,
//
//! The bus remained a bit level of 1 for longer than is allowed.
//
CAN_STATUS_LEC_BIT1 = 0x00000004,
//
//! The bus remained a bit level of 0 for longer than is allowed.
//
CAN_STATUS_LEC_BIT0 = 0x00000005,
//
//! A CRC error has occurred.
//
CAN_STATUS_LEC_CRC = 0x00000006,
//
//! This is the mask for the CAN Last Error Code (LEC).
//
CAN_STATUS_LEC_MASK = 0x00000007
}
tCANStatusCtrl;
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void CANInit(unsigned long ulBase);
extern void CANEnable(unsigned long ulBase);
extern void CANDisable(unsigned long ulBase);
extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);
extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);
extern unsigned long CANReadReg(unsigned long ulRegAddress);
extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue);
extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
tCANMsgObject *pMsgObject, tMsgObjType eMsgType);
extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);
extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);
extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);
extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);
extern unsigned long CANIntStatus(unsigned long ulBase,
tCANIntStsReg eIntStsReg);
extern tBoolean CANRetryGet(unsigned long ulBase);
extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);
extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
unsigned long *pulTxCount);
extern long CANGetIntNumber(unsigned long ulBase);
extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister,
int iSize);
extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister,
int iSize);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __CAN_H__

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//*****************************************************************************
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __COMP_H__
#define __COMP_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ComparatorConfigure() as the ulConfig
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
// the values may be selected and ORed together will values from the other
// groups.
//
//*****************************************************************************
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
#define COMP_INT_LOW 0x00000000 // Interrupt when low
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
#ifndef DEPRECATED
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
#endif
#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
//*****************************************************************************
//
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
//
//*****************************************************************************
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void));
extern void ComparatorIntUnregister(unsigned long ulBase,
unsigned long ulComp);
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked);
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
#ifdef __cplusplus
}
#endif
#endif // __COMP_H__

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//*****************************************************************************
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void CPUcpsid(void);
extern void CPUcpsie(void);
extern void CPUwfi(void);
#endif // __CPU_H__

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//*****************************************************************************
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__

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//*****************************************************************************
//
// ethernet.h - Defines and Macros for the ethernet module.
//
// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __ETHERNET_H__
#define __ETHERNET_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to EthernetConfigSet as the ulConfig value, and
// returned from EthernetConfigGet.
//
//*****************************************************************************
#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP)
#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets
#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous
#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast
#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode
#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation
#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding
//*****************************************************************************
//
// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and
// EthernetIntClear as the ulIntFlags parameter, and returned from
// EthernetIntStatus.
//
//*****************************************************************************
#define ETH_INT_PHY 0x040 // PHY Event/Interrupt
#define ETH_INT_MDIO 0x020 // Management Transaction
#define ETH_INT_RXER 0x010 // RX Error
#define ETH_INT_RXOF 0x008 // RX FIFO Overrun
#define ETH_INT_TX 0x004 // TX Complete
#define ETH_INT_TXER 0x002 // TX Error
#define ETH_INT_RX 0x001 // RX Complete
//*****************************************************************************
//
// The following define values that can be passed as register addresses to
// EthernetPHYRead and EthernetPHYWrite.
//
//*****************************************************************************
#define PHY_MR0 0 // Control
#define PHY_MR1 1 // Status
#define PHY_MR2 2 // PHY Identifier 1
#define PHY_MR3 3 // PHY Identifier 2
#define PHY_MR4 4 // Auto-Neg. Advertisement
#define PHY_MR5 5 // Auto-Neg. Link Partner Ability
#define PHY_MR6 6 // Auto-Neg. Expansion
// 7-15 Reserved/Not Implemented
#define PHY_MR16 16 // Vendor Specific
#define PHY_MR17 17 // Interrupt Control/Status
#define PHY_MR18 18 // Diagnostic Register
#define PHY_MR19 19 // Transceiver Control
// 20-22 Reserved
#define PHY_MR23 23 // LED Configuration Register
#define PHY_MR24 24 // MDI/MDIX Control Register
// 25-31 Reserved/Not Implemented
//*****************************************************************************
//
// The following define bit fields in the ETH_MR0 register
//
//*****************************************************************************
#define PHY_MR0_RESET 0x8000 // Reset the PHY
#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback
#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection
#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T
#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T
#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable
#define PHY_MR0_PWRDN 0x0800 // Power Down
#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation
#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex
#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode
#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode
//*****************************************************************************
//
// The following define bit fields in the ETH_MR1 register
//
//*****************************************************************************
#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete
#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected
#define PHY_MR1_LINK 0x0004 // Link Established
#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected
//*****************************************************************************
//
// The following define bit fields in the ETH_MR17 register
//
//*****************************************************************************
#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt
#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int.
#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int.
#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt
#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt
#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int.
//*****************************************************************************
//
// The following define bit fields in the ETH_MR18 register
//
//*****************************************************************************
#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed
#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated
#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated
#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated
#define PHY_MR18_RATE 0x0400 // Rate Negotiated
#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T
#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX
//*****************************************************************************
//
// The following define bit fields in the ETH_MR23 register
//
//*****************************************************************************
#define PHY_MR23_LED1 0x00f0 // LED1 Configuration
#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status
#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity
#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity
#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity
#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity
#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity
#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity
#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity
#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity
#define PHY_MR23_LED0 0x000f // LED0 Configuration
#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status
#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity
#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity
#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity
#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity
#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity
#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity
#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity
#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity
//*****************************************************************************
//
// The following define bit fields in the ETH_MR24 register
//
//*****************************************************************************
#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration
#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough
#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover
//*****************************************************************************
//
// Helper Macros for Ethernet Processing
//
//*****************************************************************************
//
// htonl/ntohl - big endian/little endian byte swapping macros for
// 32-bit (long) values
//
//*****************************************************************************
#ifndef htonl
#define htonl(a) \
((((a) >> 24) & 0x000000ff) | \
(((a) >> 8) & 0x0000ff00) | \
(((a) << 8) & 0x00ff0000) | \
(((a) << 24) & 0xff000000))
#endif
#ifndef ntohl
#define ntohl(a) htonl((a))
#endif
//*****************************************************************************
//
// htons/ntohs - big endian/little endian byte swapping macros for
// 16-bit (short) values
//
//*****************************************************************************
#ifndef htons
#define htons(a) \
((((a) >> 8) & 0x00ff) | \
(((a) << 8) & 0xff00))
#endif
#ifndef ntohs
#define ntohs(a) htons((a))
#endif
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk);
extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern unsigned long EthernetConfigGet(unsigned long ulBase);
extern void EthernetMACAddrSet(unsigned long ulBase,
unsigned char *pucMACAddr);
extern void EthernetMACAddrGet(unsigned long ulBase,
unsigned char *pucMACAddr);
extern void EthernetEnable(unsigned long ulBase);
extern void EthernetDisable(unsigned long ulBase);
extern tBoolean EthernetPacketAvail(unsigned long ulBase);
extern tBoolean EthernetSpaceAvail(unsigned long ulBase);
extern long EthernetPacketGetNonBlocking(unsigned long ulBase,
unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketPutNonBlocking(unsigned long ulBase,
unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
long lBufLen);
extern void EthernetIntRegister(unsigned long ulBase,
void (*pfnHandler)(void));
extern void EthernetIntUnregister(unsigned long ulBase);
extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
unsigned long ulData);
extern unsigned long EthernetPHYRead(unsigned long ulBase,
unsigned char ucRegAddr);
//*****************************************************************************
//
// Several Ethernet APIs have been renamed, with the original function name
// being deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define EthernetInit(a) \
EthernetInitExpClk(a, SysCtlClockGet())
#define EthernetPacketNonBlockingGet(a, b, c) \
EthernetPacketGetNonBlocking(a, b, c)
#define EthernetPacketNonBlockingPut(a, b, c) \
EthernetPacketPutNonBlocking(a, b, c)
#endif
#ifdef __cplusplus
}
#endif
#endif // __ETHERNET_H__

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//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulStrength,
unsigned long ulPadType);
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
unsigned long *pulStrength,
unsigned long *pulPadType);
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPortIntRegister(unsigned long ulPort,
void (*pfIntHandler)(void));
extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

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//*****************************************************************************
//
// hibernate.h - API definition for the Hibernation module.
//
// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HIBERNATE_H__
#define __HIBERNATE_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macros needed for selecting the clock source for HibernateClockSelect()
//
//*****************************************************************************
#define HIBERNATE_CLOCK_SEL_RAW 0x04
#define HIBERNATE_CLOCK_SEL_DIV128 0x00
//*****************************************************************************
//
// Macros need to configure wake events for HibernateWakeSet()
//
//*****************************************************************************
#define HIBERNATE_WAKE_PIN 0x10
#define HIBERNATE_WAKE_RTC 0x08
//*****************************************************************************
//
// Macros needed to configure low battery detect for HibernateLowBatSet()
//
//*****************************************************************************
#define HIBERNATE_LOW_BAT_DETECT 0x20
#define HIBERNATE_LOW_BAT_ABORT 0xA0
//*****************************************************************************
//
// Macros defining interrupt source bits for the interrupt functions.
//
//*****************************************************************************
#define HIBERNATE_INT_PIN_WAKE 0x08
#define HIBERNATE_INT_LOW_BAT 0x04
#define HIBERNATE_INT_RTC_MATCH_0 0x01
#define HIBERNATE_INT_RTC_MATCH_1 0x02
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void HibernateEnableExpClk(unsigned long ulHibClk);
extern void HibernateDisable(void);
extern void HibernateClockSelect(unsigned long ulClockInput);
extern void HibernateRTCEnable(void);
extern void HibernateRTCDisable(void);
extern void HibernateWakeSet(unsigned long ulWakeFlags);
extern unsigned long HibernateWakeGet(void);
extern void HibernateLowBatSet(unsigned long ulLowBatFlags);
extern unsigned long HibernateLowBatGet(void);
extern void HibernateRTCSet(unsigned long ulRTCValue);
extern unsigned long HibernateRTCGet(void);
extern void HibernateRTCMatch0Set(unsigned long ulMatch);
extern unsigned long HibernateRTCMatch0Get(void);
extern void HibernateRTCMatch1Set(unsigned long ulMatch);
extern unsigned long HibernateRTCMatch1Get(void);
extern void HibernateRTCTrimSet(unsigned long ulTrim);
extern unsigned long HibernateRTCTrimGet(void);
extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);
extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);
extern void HibernateRequest(void);
extern void HibernateIntEnable(unsigned long ulIntFlags);
extern void HibernateIntDisable(unsigned long ulIntFlags);
extern void HibernateIntRegister(void (*pfnHandler)(void));
extern void HibernateIntUnregister(void);
extern unsigned long HibernateIntStatus(tBoolean bMasked);
extern void HibernateIntClear(unsigned long ulIntFlags);
extern unsigned int HibernateIsActive(void);
//*****************************************************************************
//
// Several Hibernate module APIs have been renamed, with the original function
// name being deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define HibernateEnable(a) \
HibernateEnableExpClk(a, SysCtlClockGet())
#endif
#ifdef __cplusplus
}
#endif
#endif // __HIBERNATE_H__

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//*****************************************************************************
//
// hw_adc.h - Macros used when accessing the ADC hardware.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_ADC_H__
#define __HW_ADC_H__
//*****************************************************************************
//
// The following define the offsets of the ADC registers.
//
//*****************************************************************************
#define ADC_O_ACTSS 0x00000000 // Active sample register
#define ADC_O_RIS 0x00000004 // Raw interrupt status register
#define ADC_O_IM 0x00000008 // Interrupt mask register
#define ADC_O_ISC 0x0000000C // Interrupt status/clear register
#define ADC_O_OSTAT 0x00000010 // Overflow status register
#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.
#define ADC_O_USTAT 0x00000018 // Underflow status register
#define ADC_O_SSPRI 0x00000020 // Channel priority register
#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.
#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.
#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register
#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.
#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register
#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register
#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register
#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.
#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register
#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register
#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register
#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.
#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register
#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register
#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register
#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.
#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register
#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register
#define ADC_O_TMLB 0x00000100 // Test mode loopback register
//*****************************************************************************
//
// The following define the offsets of the ADC sequence registers.
//
//*****************************************************************************
#define ADC_O_SEQ 0x00000040 // Offset to the first sequence
#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence
#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register
#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register
#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register
#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register
//*****************************************************************************
//
// The following define the bit fields in the ADC_ACTSS register.
//
//*****************************************************************************
#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable
#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable
#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable
#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable
//*****************************************************************************
//
// The following define the bit fields in the ADC_RIS register.
//
//*****************************************************************************
#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt
#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt
#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt
#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the ADC_IM register.
//
//*****************************************************************************
#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask
#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask
#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask
#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask
//*****************************************************************************
//
// The following define the bit fields in the ADC_ISC register.
//
//*****************************************************************************
#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt
#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt
#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt
#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the ADC_OSTAT register.
//
//*****************************************************************************
#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow
#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow
#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow
#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow
//*****************************************************************************
//
// The following define the bit fields in the ADC_EMUX register.
//
//*****************************************************************************
#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask
#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event
#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event
#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event
#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event
#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event
#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event
#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event
#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event
#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event
#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask
#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event
#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event
#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event
#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event
#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event
#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event
#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event
#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event
#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event
#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask
#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event
#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event
#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event
#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event
#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event
#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event
#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event
#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event
#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event
#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask
#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event
#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event
#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event
#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event
#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event
#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event
#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event
#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event
#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event
#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event
//*****************************************************************************
//
// The following define the bit fields in the ADC_USTAT register.
//
//*****************************************************************************
#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow
#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow
#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow
#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSPRI register.
//
//*****************************************************************************
#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask
#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask
#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask
#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask
#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
//*****************************************************************************
//
// The following define the bit fields in the ADC_PSSI register.
//
//*****************************************************************************
#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3
#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2
#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1
#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0
//*****************************************************************************
//
// The following define the bit fields in the ADC_SAC register.
//
//*****************************************************************************
#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,
// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all
// registers.
//
//*****************************************************************************
#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask
#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask
#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask
#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask
#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask
#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask
#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask
#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask
#define ADC_SSMUX_MUX7_SHIFT 28
#define ADC_SSMUX_MUX6_SHIFT 24
#define ADC_SSMUX_MUX5_SHIFT 20
#define ADC_SSMUX_MUX4_SHIFT 16
#define ADC_SSMUX_MUX3_SHIFT 12
#define ADC_SSMUX_MUX2_SHIFT 8
#define ADC_SSMUX_MUX1_SHIFT 4
#define ADC_SSMUX_MUX0_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,
// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all
// registers.
//
//*****************************************************************************
#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select
#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable
#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select
#define ADC_SSCTL_D7 0x10000000 // 8th differential select
#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select
#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable
#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select
#define ADC_SSCTL_D6 0x01000000 // 7th differential select
#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select
#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable
#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select
#define ADC_SSCTL_D5 0x00100000 // 6th differential select
#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select
#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable
#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select
#define ADC_SSCTL_D4 0x00010000 // 5th differential select
#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select
#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable
#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select
#define ADC_SSCTL_D3 0x00001000 // 4th differential select
#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select
#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable
#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select
#define ADC_SSCTL_D2 0x00000100 // 3rd differential select
#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select
#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable
#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select
#define ADC_SSCTL_D1 0x00000010 // 2nd differential select
#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select
#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable
#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select
#define ADC_SSCTL_D0 0x00000001 // 1st differential select
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,
// ADC_SSFIFO2, and ADC_SSFIFO3 registers.
//
//*****************************************************************************
#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data
#define ADC_SSFIFO_DATA_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,
// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.
//
//*****************************************************************************
#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full
#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty
#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer
#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer
//*****************************************************************************
//
// The following define the bit fields in the ADC_TMLB register.
//
//*****************************************************************************
#define ADC_TMLB_LB 0x00000001 // Loopback control signals
//*****************************************************************************
//
// The following define the bit fields in the loopback ADC data.
//
//*****************************************************************************
#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask
#define ADC_LB_CONT 0x00000020 // Continuation sample
#define ADC_LB_DIFF 0x00000010 // Differential sample
#define ADC_LB_TS 0x00000008 // Temperature sensor sample
#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask
#define ADC_LB_CNT_SHIFT 6 // Sample counter shift
#define ADC_LB_MUX_SHIFT 0 // Input channel number shift
#endif // __HW_ADC_H__

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//*****************************************************************************
//
// hw_can.h - Defines and macros used when accessing the can.
//
// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_CAN_H__
#define __HW_CAN_H__
//*****************************************************************************
//
// The following define the offsets of the can registers.
//
//*****************************************************************************
#define CAN_O_CTL 0x00000000 // Control register
#define CAN_O_STS 0x00000004 // Status register
#define CAN_O_ERR 0x00000008 // Error register
#define CAN_O_BIT 0x0000000C // Bit Timing register
#define CAN_O_INT 0x00000010 // Interrupt register
#define CAN_O_TST 0x00000014 // Test register
#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register
#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.
#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.
#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register
#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register
#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.
#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.
#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.
#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register
#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register
#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register
#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register
#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.
#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.
#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register
#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register
#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.
#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.
#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.
#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register
#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register
#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register
#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register
#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register
#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register
#define CAN_O_NWDA1 0x00000120 // New Data 1 register
#define CAN_O_NWDA2 0x00000124 // New Data 2 register
#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.
#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.
#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.
#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.
//*****************************************************************************
//
// The following define the reset values of the can registers.
//
//*****************************************************************************
#define CAN_RV_CTL 0x00000001
#define CAN_RV_STS 0x00000000
#define CAN_RV_ERR 0x00000000
#define CAN_RV_BIT 0x00002301
#define CAN_RV_INT 0x00000000
#define CAN_RV_TST 0x00000000
#define CAN_RV_BRPE 0x00000000
#define CAN_RV_IF1CRQ 0x00000001
#define CAN_RV_IF1CMSK 0x00000000
#define CAN_RV_IF1MSK1 0x0000FFFF
#define CAN_RV_IF1MSK2 0x0000FFFF
#define CAN_RV_IF1ARB1 0x00000000
#define CAN_RV_IF1ARB2 0x00000000
#define CAN_RV_IF1MCTL 0x00000000
#define CAN_RV_IF1DA1 0x00000000
#define CAN_RV_IF1DA2 0x00000000
#define CAN_RV_IF1DB1 0x00000000
#define CAN_RV_IF1DB2 0x00000000
#define CAN_RV_IF2CRQ 0x00000001
#define CAN_RV_IF2CMSK 0x00000000
#define CAN_RV_IF2MSK1 0x0000FFFF
#define CAN_RV_IF2MSK2 0x0000FFFF
#define CAN_RV_IF2ARB1 0x00000000
#define CAN_RV_IF2ARB2 0x00000000
#define CAN_RV_IF2MCTL 0x00000000
#define CAN_RV_IF2DA1 0x00000000
#define CAN_RV_IF2DA2 0x00000000
#define CAN_RV_IF2DB1 0x00000000
#define CAN_RV_IF2DB2 0x00000000
#define CAN_RV_TXRQ1 0x00000000
#define CAN_RV_TXRQ2 0x00000000
#define CAN_RV_NWDA1 0x00000000
#define CAN_RV_NWDA2 0x00000000
#define CAN_RV_MSGINT1 0x00000000
#define CAN_RV_MSGINT2 0x00000000
#define CAN_RV_MSGVAL1 0x00000000
#define CAN_RV_MSGVAL2 0x00000000
//*****************************************************************************
//
// The following define the bit fields in the CAN_CTL register.
//
//*****************************************************************************
#define CAN_CTL_TEST 0x00000080 // Test mode enable
#define CAN_CTL_CCE 0x00000040 // Configuration change enable
#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission
#define CAN_CTL_EIE 0x00000008 // Error interrupt enable
#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable
#define CAN_CTL_IE 0x00000002 // Module interrupt enable
#define CAN_CTL_INIT 0x00000001 // Initialization
//*****************************************************************************
//
// The following define the bit fields in the CAN_STS register.
//
//*****************************************************************************
#define CAN_STS_BOFF 0x00000080 // Bus Off status
#define CAN_STS_EWARN 0x00000040 // Error Warning status
#define CAN_STS_EPASS 0x00000020 // Error Passive status
#define CAN_STS_RXOK 0x00000010 // Received Message Successful
#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful
#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code
#define CAN_STS_LEC_NONE 0x00000000 // No error
#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error
#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error
#define CAN_STS_LEC_ACK 0x00000003 // Ack error
#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error
#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error
#define CAN_STS_LEC_CRC 0x00000006 // CRC error
//*****************************************************************************
//
// The following define the bit fields in the CAN_ERR register.
//
//*****************************************************************************
#define CAN_ERR_RP 0x00008000 // Receive error passive status
#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status
#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos
#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status
#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos
//*****************************************************************************
//
// The following define the bit fields in the CAN_BIT register.
//
//*****************************************************************************
#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point
#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point
#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width
#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler
//*****************************************************************************
//
// The following define the bit fields in the CAN_INT register.
//
//*****************************************************************************
#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier
#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending
#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
//*****************************************************************************
//
// The following define the bit fields in the CAN_TST register.
//
//*****************************************************************************
#define CAN_TST_RX 0x00000080 // CAN_RX pin status
#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin
#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX
#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX
#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX
#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX
#define CAN_TST_LBACK 0x00000010 // Loop back mode
#define CAN_TST_SILENT 0x00000008 // Silent mode
#define CAN_TST_BASIC 0x00000004 // Basic mode
//*****************************************************************************
//
// The following define the bit fields in the CAN_BRPE register.
//
//*****************************************************************************
#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension
//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ
// registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status
#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number
//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK
// registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read
#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits
#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits
#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits
#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit
#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)
#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)
#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3
#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7
//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1
// registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask
//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2
// registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier
#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction
#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier
//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1
// registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFARB1_ID 0x0000FFFF // Identifier
//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2
// registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid
#define CAN_IFARB2_XTD 0x00004000 // Extended identifier
#define CAN_IFARB2_DIR 0x00002000 // Message direction
#define CAN_IFARB2_ID 0x00001FFF // Message identifier
//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL
// registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data
#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost
#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending
#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask
#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable
#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable
#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable
#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request
#define CAN_IFMCTL_EOB 0x00000080 // End of buffer
#define CAN_IFMCTL_DLC 0x0000000F // Data length code
//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1
// registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0
//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2
// registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2
//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1
// registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4
//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2
// registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6
//*****************************************************************************
//
// The following define the bit fields in the CAN_TXRQ1 register.
//
//*****************************************************************************
#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits
//*****************************************************************************
//
// The following define the bit fields in the CAN_TXRQ2 register.
//
//*****************************************************************************
#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits
//*****************************************************************************
//
// The following define the bit fields in the CAN_NWDA1 register.
//
//*****************************************************************************
#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits
//*****************************************************************************
//
// The following define the bit fields in the CAN_NWDA2 register.
//
//*****************************************************************************
#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits
//*****************************************************************************
//
// The following define the bit fields in the CAN_MSGINT1 register.
//
//*****************************************************************************
#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits
//*****************************************************************************
//
// The following define the bit fields in the CAN_MSGINT2 register.
//
//*****************************************************************************
#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits
//*****************************************************************************
//
// The following define the bit fields in the CAN_MSGVAL1 register.
//
//*****************************************************************************
#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits
//*****************************************************************************
//
// The following define the bit fields in the CAN_MSGVAL2 register.
//
//*****************************************************************************
#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits
#endif // __HW_CAN_H__

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//*****************************************************************************
//
// hw_comp.h - Macros used when accessing the comparator hardware.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_COMP_H__
#define __HW_COMP_H__
//*****************************************************************************
//
// The following define the offsets of the comparator registers.
//
//*****************************************************************************
#define COMP_O_MIS 0x00000000 // Interrupt status register
#define COMP_O_RIS 0x00000004 // Raw interrupt status register
#define COMP_O_INTEN 0x00000008 // Interrupt enable register
#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.
#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register
#define COMP_O_ACCTL0 0x00000024 // Comp0 control register
#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register
#define COMP_O_ACCTL1 0x00000044 // Comp1 control register
#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register
#define COMP_O_ACCTL2 0x00000064 // Comp2 control register
//*****************************************************************************
//
// The following define the bit fields in the COMP_MIS, COMP_RIS, and
// COMP_INTEN registers.
//
//*****************************************************************************
#define COMP_INT_2 0x00000004 // Comp2 interrupt
#define COMP_INT_1 0x00000002 // Comp1 interrupt
#define COMP_INT_0 0x00000001 // Comp0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the COMP_REFCTL register.
//
//*****************************************************************************
#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
#define COMP_REFCTL_VREF_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and
// COMP_ACSTAT2 registers.
//
//*****************************************************************************
#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
//*****************************************************************************
//
// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and
// COMP_ACCTL2 registers.
//
//*****************************************************************************
#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
//*****************************************************************************
//
// The following define the reset values for the comparator registers.
//
//*****************************************************************************
#define COMP_RV_MIS 0x00000000 // Interrupt status register
#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.
#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register
#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register
#endif // __HW_COMP_H__

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//*****************************************************************************
//
// hw_ethernet.h - Macros used when accessing the ethernet hardware.
//
// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_ETHERNET_H__
#define __HW_ETHERNET_H__
//*****************************************************************************
//
// The following define the offsets of the MAC registers in the Ethernet
// Controller.
//
//*****************************************************************************
#define MAC_O_IS 0x00000000 // Interrupt Status Register
#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register
#define MAC_O_IM 0x00000004 // Interrupt Mask Register
#define MAC_O_RCTL 0x00000008 // Receive Control Register
#define MAC_O_TCTL 0x0000000C // Transmit Control Register
#define MAC_O_DATA 0x00000010 // Data Register
#define MAC_O_IA0 0x00000014 // Individual Address Register 0
#define MAC_O_IA1 0x00000018 // Individual Address Register 1
#define MAC_O_THR 0x0000001C // Threshold Register
#define MAC_O_MCTL 0x00000020 // Management Control Register
#define MAC_O_MDV 0x00000024 // Management Divider Register
#define MAC_O_MADD 0x00000028 // Management Address Register
#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg
#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg
#define MAC_O_NP 0x00000034 // Number of Packets Register
#define MAC_O_TR 0x00000038 // Transmission Request Register
#define MAC_O_TS 0x0000003C // Timer Support Register
//*****************************************************************************
//
// The following define the reset values of the MAC registers.
//
//*****************************************************************************
#define MAC_RV_IS 0x00000000
#define MAC_RV_IACK 0x00000000
#define MAC_RV_IM 0x0000007F
#define MAC_RV_RCTL 0x00000008
#define MAC_RV_TCTL 0x00000000
#define MAC_RV_DATA 0x00000000
#define MAC_RV_IA0 0x00000000
#define MAC_RV_IA1 0x00000000
#define MAC_RV_THR 0x0000003F
#define MAC_RV_MCTL 0x00000000
#define MAC_RV_MDV 0x00000080
#define MAC_RV_MADD 0x00000000
#define MAC_RV_MTXD 0x00000000
#define MAC_RV_MRXD 0x00000000
#define MAC_RV_NP 0x00000000
#define MAC_RV_TR 0x00000000
//*****************************************************************************
//
// The following define the bit fields in the MAC_IS register.
//
//*****************************************************************************
#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt
#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete
#define MAC_IS_RXER 0x00000010 // RX Error
#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun
#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy
#define MAC_IS_TXER 0x00000002 // TX Error
#define MAC_IS_RXINT 0x00000001 // RX Packet Available
//*****************************************************************************
//
// The following define the bit fields in the MAC_IACK register.
//
//*****************************************************************************
#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt
#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete
#define MAC_IACK_RXER 0x00000010 // Clear RX Error
#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun
#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy
#define MAC_IACK_TXER 0x00000002 // Clear TX Error
#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available
//*****************************************************************************
//
// The following define the bit fields in the MAC_IM register.
//
//*****************************************************************************
#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt
#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete
#define MAC_IM_RXERM 0x00000010 // Mask RX Error
#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun
#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy
#define MAC_IM_TXERM 0x00000002 // Mask TX Error
#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available
//*****************************************************************************
//
// The following define the bit fields in the MAC_RCTL register.
//
//*****************************************************************************
#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO
#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC
#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode
#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets
#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver
//*****************************************************************************
//
// The following define the bit fields in the MAC_TCTL register.
//
//*****************************************************************************
#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode
#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation
#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding
#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter
//*****************************************************************************
//
// The following define the bit fields in the MAC_IA0 register.
//
//*****************************************************************************
#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address
#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address
#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address
#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address
//*****************************************************************************
//
// The following define the bit fields in the MAC_IA1 register.
//
//*****************************************************************************
#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address
#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address
//*****************************************************************************
//
// The following define the bit fields in the MAC_TXTH register.
//
//*****************************************************************************
#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value
//*****************************************************************************
//
// The following define the bit fields in the MAC_MCTL register.
//
//*****************************************************************************
#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction
#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write
#define MAC_MCTL_START 0x00000001 // Start MII Transaction
//*****************************************************************************
//
// The following define the bit fields in the MAC_MDV register.
//
//*****************************************************************************
#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX
//*****************************************************************************
//
// The following define the bit fields in the MAC_MTXD register.
//
//*****************************************************************************
#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction
//*****************************************************************************
//
// The following define the bit fields in the MAC_MRXD register.
//
//*****************************************************************************
#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.
//*****************************************************************************
//
// The following define the bit fields in the MAC_NP register.
//
//*****************************************************************************
#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO
//*****************************************************************************
//
// The following define the bit fields in the MAC_TXRQ register.
//
//*****************************************************************************
#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission
//*****************************************************************************
//
// The following define the bit fields in the MAC_TS register.
//
//*****************************************************************************
#define MAC_TS_TSEN 0x00000001 // Enable Timestamp Logic
#endif // __HW_ETHERNET_H__

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//*****************************************************************************
//
// hw_flash.h - Macros used when accessing the flash controller.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_FLASH_H__
#define __HW_FLASH_H__
//*****************************************************************************
//
// The following define the offsets of the FLASH registers.
//
//*****************************************************************************
#define FLASH_FMA 0x400FD000 // Memory address register
#define FLASH_FMD 0x400FD004 // Memory data register
#define FLASH_FMC 0x400FD008 // Memory control register
#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register
#define FLASH_FCIM 0x400FD010 // Interrupt mask register
#define FLASH_FCMISC 0x400FD014 // Interrupt status register
#define FLASH_FMPRE 0x400FE130 // FLASH read protect register
#define FLASH_FMPPE 0x400FE134 // FLASH program protect register
#define FLASH_USECRL 0x400FE140 // uSec reload register
#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0
#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1
#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2
#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3
#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0
#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1
#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2
#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMC register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC_COMT 0x00000008 // Commit user register
#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH
#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page
#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FCRIS register.
//
//*****************************************************************************
#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FCIM register.
//
//*****************************************************************************
#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMIS register.
//
//*****************************************************************************
#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE
// registers.
//
//*****************************************************************************
#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
//*****************************************************************************
//
// The following define the bit fields in the FLASH_USECRL register.
//
//*****************************************************************************
#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
#define FLASH_USECRL_SHIFT 0
//*****************************************************************************
//
// The erase size is the size of the FLASH block that is erased by an erase
// operation, and the protect size is the size of the FLASH block that is
// protected by each protection register.
//
//*****************************************************************************
#define FLASH_ERASE_SIZE 0x00000400
#define FLASH_PROTECT_SIZE 0x00000800
#endif // __HW_FLASH_H__

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//*****************************************************************************
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_GPIO_H__
#define __HW_GPIO_H__
//*****************************************************************************
//
// GPIO Register Offsets.
//
//*****************************************************************************
#define GPIO_O_DATA 0x00000000 // Data register.
#define GPIO_O_DIR 0x00000400 // Data direction register.
#define GPIO_O_IS 0x00000404 // Interrupt sense register.
#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.
#define GPIO_O_IEV 0x0000040C // Interrupt event register.
#define GPIO_O_IM 0x00000410 // Interrupt mask register.
#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.
#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.
#define GPIO_O_ICR 0x0000041C // Interrupt clear register.
#define GPIO_O_AFSEL 0x00000420 // Mode control select register.
#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.
#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.
#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.
#define GPIO_O_ODR 0x0000050C // Open drain select register.
#define GPIO_O_PUR 0x00000510 // Pull up select register.
#define GPIO_O_PDR 0x00000514 // Pull down select register.
#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.
#define GPIO_O_DEN 0x0000051C // Digital input enable register.
#define GPIO_O_LOCK 0x00000520 // Lock register.
#define GPIO_O_CR 0x00000524 // Commit register.
#define GPIO_O_PeriphID4 0x00000FD0 //
#define GPIO_O_PeriphID5 0x00000FD4 //
#define GPIO_O_PeriphID6 0x00000FD8 //
#define GPIO_O_PeriphID7 0x00000FDC //
#define GPIO_O_PeriphID0 0x00000FE0 //
#define GPIO_O_PeriphID1 0x00000FE4 //
#define GPIO_O_PeriphID2 0x00000FE8 //
#define GPIO_O_PeriphID3 0x00000FEC //
#define GPIO_O_PCellID0 0x00000FF0 //
#define GPIO_O_PCellID1 0x00000FF4 //
#define GPIO_O_PCellID2 0x00000FF8 //
#define GPIO_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// The following define the bit fields in the GPIO_LOCK register.
//
//*****************************************************************************
#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked
#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked
#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
//*****************************************************************************
//
// GPIO Register reset values.
//
//*****************************************************************************
#define GPIO_RV_DATA 0x00000000 // Data register reset value.
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.
#define GPIO_RV_IEV 0x00000000 // Interrupt event reg RV.
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.
#define GPIO_RV_LOCK 0x00000001 // Lock register RV.
#define GPIO_RV_PeriphID4 0x00000000 //
#define GPIO_RV_PeriphID5 0x00000000 //
#define GPIO_RV_PeriphID6 0x00000000 //
#define GPIO_RV_PeriphID7 0x00000000 //
#define GPIO_RV_PeriphID0 0x00000061 //
#define GPIO_RV_PeriphID1 0x00000010 //
#define GPIO_RV_PeriphID2 0x00000004 //
#define GPIO_RV_PeriphID3 0x00000000 //
#define GPIO_RV_PCellID0 0x0000000D //
#define GPIO_RV_PCellID1 0x000000F0 //
#define GPIO_RV_PCellID2 0x00000005 //
#define GPIO_RV_PCellID3 0x000000B1 //
#endif // __HW_GPIO_H__

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//*****************************************************************************
//
// hw_hibernate.h - Defines and Macros for the Hibernation module.
//
// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_HIBERNATE_H__
#define __HW_HIBERNATE_H__
//*****************************************************************************
//
// The following define the addresses of the hibernation module registers.
//
//*****************************************************************************
#define HIB_RTCC 0x400fc000 // Hibernate RTC counter
#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0
#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1
#define HIB_RTCLD 0x400fc00C // Hibernate RTC load
#define HIB_CTL 0x400fc010 // Hibernate RTC control
#define HIB_IM 0x400fc014 // Hibernate interrupt mask
#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status
#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat
#define HIB_IC 0x400fc020 // Hibernate interrupt clear
#define HIB_RTCT 0x400fc024 // Hibernate RTC trim
#define HIB_DATA 0x400fc030 // Hibernate data area
#define HIB_DATA_END 0x400fc130 // end of data area, exclusive
//*****************************************************************************
//
// The following define the bit fields in the Hibernate RTC counter register.
//
//*****************************************************************************
#define HIB_RTCC_MASK 0xffffffff // RTC counter mask
//*****************************************************************************
//
// The following define the bit fields in the Hibernate RTC match 0 register.
//
//*****************************************************************************
#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask
//*****************************************************************************
//
// The following define the bit fields in the Hibernate RTC match 1 register.
//
//*****************************************************************************
#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask
//*****************************************************************************
//
// The following define the bit fields in the Hibernate RTC load register.
//
//*****************************************************************************
#define HIB_RTCLD_MASK 0xffffffff // RTC load mask
//*****************************************************************************
//
// The following define the bit fields in the Hibernate control register
//
//*****************************************************************************
#define HIB_CTL_VABORT 0x00000080 // low bat abort
#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator
#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect
#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin
#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match
#define HIB_CTL_CLKSEL 0x00000004 // clock input selection
#define HIB_CTL_HIBREQ 0x00000002 // request hibernation
#define HIB_CTL_RTCEN 0x00000001 // RTC enable
//*****************************************************************************
//
// The following define the bit fields in the Hibernate interrupt mask reg.
//
//*****************************************************************************
#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt
#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the Hibernate raw interrupt status.
//
//*****************************************************************************
#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt
#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the Hibernate masked int status.
//
//*****************************************************************************
#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt
#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the Hibernate interrupt clear reg.
//
//*****************************************************************************
#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt
#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the Hibernate RTC trim register.
//
//*****************************************************************************
#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask
//*****************************************************************************
//
// The following define the bit fields in the Hibernate data register.
//
//*****************************************************************************
#define HIB_DATA_MASK 0xffffffff // NV memory data mask
#endif // __HW_HIBERNATE_H__

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//*****************************************************************************
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following defines the offset between the I2C master and slave registers.
//
//*****************************************************************************
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
//*****************************************************************************
//
// The following define the offsets of the I2C master registers.
//
//*****************************************************************************
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
#define I2C_MASTER_O_DR 0x00000008 // Data register
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
//*****************************************************************************
//
// The following define the offsets of the I2C slave registers.
//
//*****************************************************************************
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
#define I2C_SLAVE_O_DR 0x00000008 // Data register
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
//*****************************************************************************
//
// The followng define the bit fields in the I2C master slave address register.
//
//*****************************************************************************
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
#define I2C_MASTER_SA_SA_SHIFT 1
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Control and Status
// register.
//
//*****************************************************************************
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
#define I2C_MASTER_CS_START 0x00000002 // Start
#define I2C_MASTER_CS_RUN 0x00000001 // Run
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
//*****************************************************************************
//
// The following define values used in determining the contents of the I2C
// Master Timer Period register.
//
//*****************************************************************************
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
#define I2C_SCL_FAST 400000 // SCL fast frequency
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Interrupt Mask
// register.
//
//*****************************************************************************
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Raw Interrupt Status
// register.
//
//*****************************************************************************
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Masked Interrupt
// Status register.
//
//*****************************************************************************
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Interrupt Clear
// register.
//
//*****************************************************************************
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Configuration
// register.
//
//*****************************************************************************
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Own Address register.
//
//*****************************************************************************
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Control/Status
// register.
//
//*****************************************************************************
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Interrupt Mask
// register.
//
//*****************************************************************************
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Raw Interrupt Status
// register.
//
//*****************************************************************************
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Masked Interrupt
// Status register.
//
//*****************************************************************************
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Interrupt Clear
// register.
//
//*****************************************************************************
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
#endif // __HW_I2C_H__

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//*****************************************************************************
//
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_INTS_H__
#define __HW_INTS_H__
//*****************************************************************************
//
// The following define the fault assignments.
//
//*****************************************************************************
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
//*****************************************************************************
//
// The following define the interrupt assignments.
//
//*****************************************************************************
#define INT_GPIOA 16 // GPIO Port A
#define INT_GPIOB 17 // GPIO Port B
#define INT_GPIOC 18 // GPIO Port C
#define INT_GPIOD 19 // GPIO Port D
#define INT_GPIOE 20 // GPIO Port E
#define INT_UART0 21 // UART0 Rx and Tx
#define INT_UART1 22 // UART1 Rx and Tx
#define INT_SSI 23 // SSI Rx and Tx
#define INT_SSI0 23 // SSI0 Rx and Tx
#define INT_I2C 24 // I2C Master and Slave
#define INT_I2C0 24 // I2C0 Master and Slave
#define INT_PWM_FAULT 25 // PWM Fault
#define INT_PWM0 26 // PWM Generator 0
#define INT_PWM1 27 // PWM Generator 1
#define INT_PWM2 28 // PWM Generator 2
#define INT_QEI 29 // Quadrature Encoder
#define INT_QEI0 29 // Quadrature Encoder 0
#define INT_ADC0 30 // ADC Sequence 0
#define INT_ADC1 31 // ADC Sequence 1
#define INT_ADC2 32 // ADC Sequence 2
#define INT_ADC3 33 // ADC Sequence 3
#define INT_WATCHDOG 34 // Watchdog timer
#define INT_TIMER0A 35 // Timer 0 subtimer A
#define INT_TIMER0B 36 // Timer 0 subtimer B
#define INT_TIMER1A 37 // Timer 1 subtimer A
#define INT_TIMER1B 38 // Timer 1 subtimer B
#define INT_TIMER2A 39 // Timer 2 subtimer A
#define INT_TIMER2B 40 // Timer 2 subtimer B
#define INT_COMP0 41 // Analog Comparator 0
#define INT_COMP1 42 // Analog Comparator 1
#define INT_COMP2 43 // Analog Comparator 2
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
#define INT_FLASH 45 // FLASH Control
#define INT_GPIOF 46 // GPIO Port F
#define INT_GPIOG 47 // GPIO Port G
#define INT_GPIOH 48 // GPIO Port H
#define INT_UART2 49 // UART2 Rx and Tx
#define INT_SSI1 50 // SSI1 Rx and Tx
#define INT_TIMER3A 51 // Timer 3 subtimer A
#define INT_TIMER3B 52 // Timer 3 subtimer B
#define INT_I2C1 53 // I2C1 Master and Slave
#define INT_QEI1 54 // Quadrature Encoder 1
#define INT_CAN0 55 // CAN0
#define INT_CAN1 56 // CAN1
#define INT_CAN2 57 // CAN2
#define INT_ETH 58 // Ethernet
#define INT_HIBERNATE 59 // Hibernation module
//*****************************************************************************
//
// The total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 60
//*****************************************************************************
//
// The total number of priority levels.
//
//*****************************************************************************
#define NUM_PRIORITY 8
#define NUM_PRIORITY_BITS 3
#endif // __HW_INTS_H__

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//*****************************************************************************
//
// hw_memmap.h - Macros defining the memory map of Stellaris.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_MEMMAP_H__
#define __HW_MEMMAP_H__
//*****************************************************************************
//
// The following define the base address of the memories and peripherals.
//
//*****************************************************************************
#define FLASH_BASE 0x00000000 // FLASH memory
#define SRAM_BASE 0x20000000 // SRAM memory
#define WATCHDOG_BASE 0x40000000 // Watchdog
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
#define SSI_BASE 0x40008000 // SSI
#define SSI0_BASE 0x40008000 // SSI0
#define SSI1_BASE 0x40009000 // SSI1
#define UART0_BASE 0x4000C000 // UART0
#define UART1_BASE 0x4000D000 // UART1
#define UART2_BASE 0x4000E000 // UART2
#define I2C_MASTER_BASE 0x40020000 // I2C Master
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
#define PWM_BASE 0x40028000 // PWM
#define QEI_BASE 0x4002C000 // QEI
#define QEI0_BASE 0x4002C000 // QEI0
#define QEI1_BASE 0x4002D000 // QEI1
#define TIMER0_BASE 0x40030000 // Timer0
#define TIMER1_BASE 0x40031000 // Timer1
#define TIMER2_BASE 0x40032000 // Timer2
#define TIMER3_BASE 0x40033000 // Timer3
#define ADC_BASE 0x40038000 // ADC
#define COMP_BASE 0x4003C000 // Analog comparators
#define CAN0_BASE 0x40040000 // CAN0
#define CAN1_BASE 0x40041000 // CAN1
#define CAN2_BASE 0x40042000 // CAN2
#define ETH_BASE 0x40048000 // Ethernet
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
#endif // __HW_MEMMAP_H__

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//*****************************************************************************
//
// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_PWM_H__
#define __HW_PWM_H__
//*****************************************************************************
//
// PWM Module Register Offsets.
//
//*****************************************************************************
#define PWM_O_CTL 0x00000000 // PWM Master Control register
#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register
#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register
#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register
#define PWM_O_FAULT 0x00000010 // PWM Output Fault register
#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register
#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.
#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register
#define PWM_O_STATUS 0x00000020 // PWM Status register
//*****************************************************************************
//
// The following define the bit fields in the PWM Master Control register.
//
//*****************************************************************************
#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
//*****************************************************************************
//
// The following define the bit fields in the PWM Time Base Sync register.
//
//*****************************************************************************
#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter
#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter
#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter
//*****************************************************************************
//
// The following define the bit fields in the PWM Output Enable register.
//
//*****************************************************************************
#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable
#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable
#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable
#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable
#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable
#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable
//*****************************************************************************
//
// The following define the bit fields in the PWM Inversion register.
//
//*****************************************************************************
#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert
#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert
#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert
#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert
#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert
#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert
//*****************************************************************************
//
// The following define the bit fields in the PWM Fault register.
//
//*****************************************************************************
#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault
#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault
#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault
#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault
#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault
#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault
//*****************************************************************************
//
// PWM Interrupt Register bit definitions.
//
//*****************************************************************************
#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
//*****************************************************************************
//
// The following define the bit fields in the PWM Status register.
//
//*****************************************************************************
#define PWM_STATUS_FAULT 0x00000001 // Fault status
//*****************************************************************************
//
// PWM Generator standard offsets.
//
//*****************************************************************************
#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
//*****************************************************************************
//
// PWM_X Control Register bit definitions.
//
//*****************************************************************************
#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block
#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down
#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode
#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg
#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg
#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg
//*****************************************************************************
//
// PWM_X Interrupt/Trigger Enable Register bit definitions.
//
//*****************************************************************************
#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0
#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U
#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D
#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U
#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D
#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0
#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// PWM_X Raw Interrupt Status Register bit definitions.
//
//*****************************************************************************
#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int
#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int
#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int
#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int
#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int
#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int
//*****************************************************************************
//
// PWM_X Interrupt Status Register bit definitions.
//
//*****************************************************************************
#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
//*****************************************************************************
//
// PWM_X Generator A/B Control Register bit definitions.
//
//*****************************************************************************
#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
//*****************************************************************************
//
// PWM_X Generator A/B Control Register action definitions.
//
//*****************************************************************************
#define PWM_GEN_ACT_NONE 0x0 // Do nothing
#define PWM_GEN_ACT_INV 0x1 // Invert the output signal
#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero
#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one
#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
//*****************************************************************************
//
// PWM_X Dead Band Control Register bit definitions.
//
//*****************************************************************************
#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
//*****************************************************************************
//
// PWM Register reset values.
//
//*****************************************************************************
#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM
// output pins
#define PWM_RV_INVERT 0x00000000 // Inversion control for
// PWM output pins
#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
// output pins
#define PWM_RV_INTEN 0x00000000 // Interrupt enable
#define PWM_RV_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_STATUS 0x00000000 // Status
#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
// generator block
#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
#define PWM_RV_X_COUNT 0x00000000 // The current counter value
#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
// count
#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
// count
#endif // __HW_PWM_H__

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//*****************************************************************************
//
// hw_qei.h - Macros used when accessing the QEI hardware.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_QEI_H__
#define __HW_QEI_H__
//*****************************************************************************
//
// The following define the offsets of the QEI registers.
//
//*****************************************************************************
#define QEI_O_CTL 0x00000000 // Configuration and control reg.
#define QEI_O_STAT 0x00000004 // Status register
#define QEI_O_POS 0x00000008 // Current position register
#define QEI_O_MAXPOS 0x0000000C // Maximum position register
#define QEI_O_LOAD 0x00000010 // Velocity timer load register
#define QEI_O_TIME 0x00000014 // Velocity timer register
#define QEI_O_COUNT 0x00000018 // Velocity pulse count register
#define QEI_O_SPEED 0x0000001C // Velocity speed register
#define QEI_O_INTEN 0x00000020 // Interrupt enable register
#define QEI_O_RIS 0x00000024 // Raw interrupt status register
#define QEI_O_ISC 0x00000028 // Interrupt status register
//*****************************************************************************
//
// The following define the bit fields in the QEI_CTL register.
//
//*****************************************************************************
#define QEI_CTL_STALLEN 0x00001000 // Stall enable
#define QEI_CTL_INVI 0x00000800 // Invert Index input
#define QEI_CTL_INVB 0x00000400 // Invert PhB input
#define QEI_CTL_INVA 0x00000200 // Invert PhA input
#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask
#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128
#define QEI_CTL_VELEN 0x00000020 // Velocity enable
#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode
#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode
#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode
#define QEI_CTL_SWAP 0x00000002 // Swap input signals
#define QEI_CTL_ENABLE 0x00000001 // QEI enable
//*****************************************************************************
//
// The following define the bit fields in the QEI_STAT register.
//
//*****************************************************************************
#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation
#define QEI_STAT_ERROR 0x00000001 // Signalling error detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_POS register.
//
//*****************************************************************************
#define QEI_POS_M 0xFFFFFFFF // Current encoder position
#define QEI_POS_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_MAXPOS register.
//
//*****************************************************************************
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position
#define QEI_MAXPOS_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_LOAD register.
//
//*****************************************************************************
#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value
#define QEI_LOAD_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_TIME register.
//
//*****************************************************************************
#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value
#define QEI_TIME_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_COUNT register.
//
//*****************************************************************************
#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count
#define QEI_COUNT_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_SPEED register.
//
//*****************************************************************************
#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count
#define QEI_SPEED_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_INTEN register.
//
//*****************************************************************************
#define QEI_INTEN_ERROR 0x00000008 // Phase error detected
#define QEI_INTEN_DIR 0x00000004 // Direction change
#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired
#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_RIS register.
//
//*****************************************************************************
#define QEI_RIS_ERROR 0x00000008 // Phase error detected
#define QEI_RIS_DIR 0x00000004 // Direction change
#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired
#define QEI_RIS_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_ISC register.
//
//*****************************************************************************
#define QEI_INT_ERROR 0x00000008 // Phase error detected
#define QEI_INT_DIR 0x00000004 // Direction change
#define QEI_INT_TIMER 0x00000002 // Velocity timer expired
#define QEI_INT_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the reset values for the QEI registers.
//
//*****************************************************************************
#define QEI_RV_CTL 0x00000000 // Configuration and control reg.
#define QEI_RV_STAT 0x00000000 // Status register
#define QEI_RV_POS 0x00000000 // Current position register
#define QEI_RV_MAXPOS 0x00000000 // Maximum position register
#define QEI_RV_LOAD 0x00000000 // Velocity timer load register
#define QEI_RV_TIME 0x00000000 // Velocity timer register
#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register
#define QEI_RV_SPEED 0x00000000 // Velocity speed register
#define QEI_RV_INTEN 0x00000000 // Interrupt enable register
#define QEI_RV_RIS 0x00000000 // Raw interrupt status register
#define QEI_RV_ISC 0x00000000 // Interrupt status register
#endif // __HW_QEI_H__

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//*****************************************************************************
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_SSI_H__
#define __HW_SSI_H__
//*****************************************************************************
//
// The following define the offsets of the SSI registers.
//
//*****************************************************************************
#define SSI_O_CR0 0x00000000 // Control register 0
#define SSI_O_CR1 0x00000004 // Control register 1
#define SSI_O_DR 0x00000008 // Data register
#define SSI_O_SR 0x0000000C // Status register
#define SSI_O_CPSR 0x00000010 // Clock prescale register
#define SSI_O_IM 0x00000014 // Int mask set and clear register
#define SSI_O_RIS 0x00000018 // Raw interrupt register
#define SSI_O_MIS 0x0000001C // Masked interrupt register
#define SSI_O_ICR 0x00000020 // Interrupt clear register
//*****************************************************************************
//
// The following define the bit fields in the SSI Control register 0.
//
//*****************************************************************************
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase
#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format
#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format
#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format
#define SSI_CR0_DSS 0x0000000F // Data size select
#define SSI_CR0_DSS_4 0x00000003 // 4 bit data
#define SSI_CR0_DSS_5 0x00000004 // 5 bit data
#define SSI_CR0_DSS_6 0x00000005 // 6 bit data
#define SSI_CR0_DSS_7 0x00000006 // 7 bit data
#define SSI_CR0_DSS_8 0x00000007 // 8 bit data
#define SSI_CR0_DSS_9 0x00000008 // 9 bit data
#define SSI_CR0_DSS_10 0x00000009 // 10 bit data
#define SSI_CR0_DSS_11 0x0000000A // 11 bit data
#define SSI_CR0_DSS_12 0x0000000B // 12 bit data
#define SSI_CR0_DSS_13 0x0000000C // 13 bit data
#define SSI_CR0_DSS_14 0x0000000D // 14 bit data
#define SSI_CR0_DSS_15 0x0000000E // 15 bit data
#define SSI_CR0_DSS_16 0x0000000F // 16 bit data
//*****************************************************************************
//
// The following define the bit fields in the SSI Control register 1.
//
//*****************************************************************************
#define SSI_CR1_SOD 0x00000008 // Slave mode output disable
#define SSI_CR1_MS 0x00000004 // Master or slave mode select
#define SSI_CR1_SSE 0x00000002 // Sync serial port enable
#define SSI_CR1_LBM 0x00000001 // Loopback mode
//*****************************************************************************
//
// The following define the bit fields in the SSI Status register.
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI busy
#define SSI_SR_RFF 0x00000008 // RX FIFO full
#define SSI_SR_RNE 0x00000004 // RX FIFO not empty
#define SSI_SR_TNF 0x00000002 // TX FIFO not full
#define SSI_SR_TFE 0x00000001 // TX FIFO empty
//*****************************************************************************
//
// The following define the bit fields in the SSI clock prescale register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
//*****************************************************************************
//
// The following define information concerning the SSI Data register.
//
//*****************************************************************************
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
//*****************************************************************************
//
// The following define the bit fields in the interrupt mask set and clear,
// raw interrupt, masked interrupt, and interrupt clear registers.
//
//*****************************************************************************
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
#endif // __HW_SSI_H__

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//*****************************************************************************
//
// hw_sysctl.h - Macros used when accessing the system control hardware.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_SYSCTL_H__
#define __HW_SYSCTL_H__
//*****************************************************************************
//
// The following define the addresses of the system control registers.
//
//*****************************************************************************
#define SYSCTL_DID0 0x400fe000 // Device identification register 0
#define SYSCTL_DID1 0x400fe004 // Device identification register 1
#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0
#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1
#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2
#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3
#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4
#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register
#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register
#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0
#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1
#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2
#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register
#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register
#define SYSCTL_MISC 0x400fe058 // Interrupt status register
#define SYSCTL_RESC 0x400fe05c // Reset cause register
#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register
#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register
#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2
#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0
#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1
#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2
#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0
#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1
#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2
#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0
#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1
#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2
#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg
#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register
#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register
#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0
#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DID0 register.
//
//*****************************************************************************
#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask
#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0
#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1
#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class
#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // Sandstorm-class Device
#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Fury-class Device
#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C
#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0
#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1
#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2
#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3
#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4
#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DID1 register.
//
//*****************************************************************************
#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301
#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310
#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315
#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316
#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317
#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328
#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601
#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610
#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611
#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612
#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613
#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615
#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617
#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618
#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628
#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801
#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811
#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812
#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815
#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817
#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818
#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828
#define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110
#define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133
#define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138
#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150
#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162
#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165
#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332
#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435
#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439
#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512
#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538
#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620
#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635
#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637
#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751
#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850
#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937
#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958
#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960
#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968
#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110
#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139
#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410
#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412
#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432
#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533
#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620
#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637
#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651
#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730
#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739
#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939
#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948
#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950
#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965
#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100
#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110
#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420
#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422
#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432
#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537
#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610
#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633
#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637
#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730
#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753
#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938
#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950
#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952
#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530
#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538
#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630
#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730
#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733
#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738
#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930
#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933
#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938
#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962
#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970
#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count
#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package
#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)
#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)
#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC
#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP
#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant
#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)
#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)
#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified
#define SYSCTL_DID1_PRTNO_SHIFT 16
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC0 register.
//
//*****************************************************************************
#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash
#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash
#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash
#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash
#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash
#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC1 register.
//
//*****************************************************************************
#define SYSCTL_DC1_CAN2 0x04000000 // CAN2 module present
#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present
#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present
#define SYSCTL_DC1_PWM 0x00100000 // PWM module present
#define SYSCTL_DC1_ADC 0x00010000 // ADC module present
#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC
#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC
#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC
#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present
#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present
#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present
#define SYSCTL_DC1_PLL 0x00000010 // PLL present
#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC2 register.
//
//*****************************************************************************
#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present
#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present
#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present
#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present
#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present
#define SYSCTL_DC2_I2C1 0x00004000 // I2C 1 present
#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present
#ifndef DEPRECATED
#define SYSCTL_DC2_I2C 0x00001000 // I2C present
#endif
#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present
#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present
#ifndef DEPRECATED
#define SYSCTL_DC2_QEI 0x00000100 // QEI present
#endif
#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present
#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present
#ifndef DEPRECATED
#define SYSCTL_DC2_SSI 0x00000010 // SSI present
#endif
#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present
#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present
#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC3 register.
//
//*****************************************************************************
#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present
#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present
#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present
#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present
#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present
#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present
#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present
#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present
#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present
#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present
#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present
#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present
#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present
#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present
#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present
#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present
#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present
#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present
#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present
#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present
#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present
#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present
#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present
#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present
#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present
#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present
#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present
#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present
#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present
#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present
#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC4 register.
//
//*****************************************************************************
#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present
#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present
#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present
#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present
#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present
#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present
#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present
#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present
#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_PBORCTL register.
//
//*****************************************************************************
#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset
#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise
#define SYSCTL_PBORCTL_BOR_SH 2
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_LDOPCTL register.
//
//*****************************************************************************
#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V
#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V
#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V
#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V
#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,
// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
//
//*****************************************************************************
#define SYSCTL_SET0_CAN2 0x04000000 // CAN2 module
#define SYSCTL_SET0_CAN1 0x02000000 // CAN1 module
#define SYSCTL_SET0_CAN0 0x01000000 // CAN0 module
#define SYSCTL_SET0_PWM 0x00100000 // PWM module
#define SYSCTL_SET0_ADC 0x00010000 // ADC module
#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask
#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC
#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC
#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC
#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module
#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,
// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
//
//*****************************************************************************
#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2
#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3
#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2
#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
#define SYSCTL_SET1_I2C1 0x00004000 // I2C module 1
#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0
#ifndef DEPRECATED
#define SYSCTL_SET1_I2C 0x00001000 // I2C module
#endif
#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1
#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0
#ifndef DEPRECATED
#define SYSCTL_SET1_QEI 0x00000100 // QEI module
#endif
#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1
#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0
#ifndef DEPRECATED
#define SYSCTL_SET1_SSI 0x00000010 // SSI module
#endif
#define SYSCTL_SET1_UART2 0x00000004 // UART module 2
#define SYSCTL_SET1_UART1 0x00000002 // UART module 1
#define SYSCTL_SET1_UART0 0x00000001 // UART module 0
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,
// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
//
//*****************************************************************************
#define SYSCTL_SET2_ETH 0x50000000 // ETH module
#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module
#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module
#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module
#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module
#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module
#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and
// SYSCTL_IMS registers.
//
//*****************************************************************************
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RESC register.
//
//*****************************************************************************
#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset
#define SYSCTL_RESC_SW 0x00000010 // Software reset
#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset
#define SYSCTL_RESC_POR 0x00000002 // Power on reset
#define SYSCTL_RESC_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RCC register.
//
//*****************************************************************************
#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating
#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider
#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider
#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down
#define SYSCTL_RCC_OE 0x00001000 // PLL output enable
#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass
#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable
#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // Using a 1MHz crystal
#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // Using a 1.8432MHz crystal
#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // Using a 2MHz crystal
#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // Using a 2.4576MHz crystal
#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal
#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // Using a 3.6864MHz crystal
#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // Using a 4MHz crystal
#ifdef DEPRECATED
#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal
#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal
#endif
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal
#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal
#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal
#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal
#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal
#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal
#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator
#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator
#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4
#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en
#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en
#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable
#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable
#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field
#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_PLLCFG register.
//
//*****************************************************************************
#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1
#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2
#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4
#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
#define SYSCTL_PLLCFG_F_SHIFT 5
#define SYSCTL_PLLCFG_R_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RCC2 register.
//
//*****************************************************************************
#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider
#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down
#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass
#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select
#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator
#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator
#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4
#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.
#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DSLPCLKCFG register.
//
//*****************************************************************************
#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override
#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2
#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3
#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4
#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5
#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6
#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7
#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8
#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9
#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10
#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11
#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12
#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13
#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14
#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15
#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16
#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17
#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18
#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19
#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20
#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21
#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22
#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23
#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24
#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25
#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26
#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27
#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28
#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29
#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30
#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31
#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32
#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33
#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34
#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35
#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36
#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37
#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38
#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39
#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40
#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41
#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42
#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43
#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44
#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45
#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46
#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47
#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48
#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49
#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50
#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51
#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52
#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53
#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54
#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55
#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56
#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57
#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58
#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59
#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60
#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61
#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62
#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63
#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64
#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override
#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override
#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator
#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.
#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_CLKVCLR register.
//
//*****************************************************************************
#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_LDOARST register.
//
//*****************************************************************************
#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
#endif // __HW_SYSCTL_H__

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//*****************************************************************************
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
//*****************************************************************************
//
// The following define the offsets of the timer registers.
//
//*****************************************************************************
#define TIMER_O_CFG 0x00000000 // Configuration register
#define TIMER_O_TAMR 0x00000004 // TimerA mode register
#define TIMER_O_TBMR 0x00000008 // TimerB mode register
#define TIMER_O_CTL 0x0000000C // Control register
#define TIMER_O_IMR 0x00000018 // Interrupt mask register
#define TIMER_O_RIS 0x0000001C // Interrupt status register
#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.
#define TIMER_O_ICR 0x00000024 // Interrupt clear register
#define TIMER_O_TAILR 0x00000028 // TimerA interval load register
#define TIMER_O_TBILR 0x0000002C // TimerB interval load register
#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register
#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register
#define TIMER_O_TAPR 0x00000038 // TimerA prescale register
#define TIMER_O_TBPR 0x0000003C // TimerB prescale register
#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register
#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register
#define TIMER_O_TAR 0x00000048 // TimerA register
#define TIMER_O_TBR 0x0000004C // TimerB register
//*****************************************************************************
//
// The following define the reset values of the timer registers.
//
//*****************************************************************************
#define TIMER_RV_CFG 0x00000000 // Configuration register RV
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
#define TIMER_RV_CTL 0x00000000 // Control register RV
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
//*****************************************************************************
//
// The following define the bit fields in the TIMER_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TnMR register.
//
//*****************************************************************************
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
//*****************************************************************************
//
// The following define the bit fields in the TIMER_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert
#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge
#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge
#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable
#define TIMER_CTL_TBEN 0x00000100 // TimerB enable
#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert
#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable
#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge
#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge
#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable
#define TIMER_CTL_TAEN 0x00000001 // TimerA enable
//*****************************************************************************
//
// The following define the bit fields in the TIMER_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask
#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask
#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask
#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask
#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask
#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask
#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the TIMER_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status
#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status
#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status
#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status
#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status
#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status
#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status
//*****************************************************************************
//
// The following define the bit fields in the TIMER_MIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
//*****************************************************************************
//
// The following define the bit fields in the TIMER_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear
#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear
#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear
#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear
#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear
#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear
#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAILR register.
//
//*****************************************************************************
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBILR register.
//
//*****************************************************************************
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAMATCHR register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBMATCHR register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TnPR register.
//
//*****************************************************************************
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TnPMR register.
//
//*****************************************************************************
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAR register.
//
//*****************************************************************************
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBR register.
//
//*****************************************************************************
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
#endif // __HW_TIMER_H__

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//*****************************************************************************
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_TYPES_H__
#define __HW_TYPES_H__
//*****************************************************************************
//
// Define a boolean type, and values for true and false.
//
//*****************************************************************************
typedef unsigned char tBoolean;
#ifndef true
#define true 1
#endif
#ifndef false
#define false 0
#endif
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
#define HWREG(x) \
(*((volatile unsigned long *)(x)))
#define HWREGH(x) \
(*((volatile unsigned short *)(x)))
#define HWREGB(x) \
(*((volatile unsigned char *)(x)))
#define HWREGBITW(x, b) \
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITH(x, b) \
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITB(x, b) \
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
//*****************************************************************************
//
// Helper Macros for determining silicon revisions, etc.
//
// These macros will be used by Driverlib at "run-time" to create necessary
// conditional code blocks that will allow a single version of the Driverlib
// "binary" code to support multiple(all) Stellaris silicon revisions.
//
// It is expected that these macros will be used inside of a standard 'C'
// conditional block of code, e.g.
//
// if(DEVICE_IS_SANDSTORM())
// {
// do some Sandstorm specific code here.
// }
//
// By default, these macros will be defined as run-time checks of the
// appropriate register(s) to allow creation of run-time conditional code
// blocks for a common DriverLib across the entire Stellaris family.
//
// However, if code-space optimization is required, these macros can be "hard-
// coded" for a specific version of Stellaris silicon. Many compilers will
// then detect the "hard-coded" conditionals, and appropriately optimize the
// code blocks, eliminating any "unreachable" code. This would result in
// a smaller Driverlib, thus producing a smaller final application size, but
// at the cost of limiting the Driverlib binary to a specific Stellaris
// silicon revision.
//
//*****************************************************************************
#ifndef DEVICE_IS_SANDSTORM
#define DEVICE_IS_SANDSTORM \
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \
((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \
SYSCTL_DID0_CLASS_SANDSTORM)))
#endif
#ifndef DEVICE_IS_FURY
#define DEVICE_IS_FURY \
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \
((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \
SYSCTL_DID0_CLASS_FURY))
#endif
#ifndef DEVICE_IS_REVA2
#define DEVICE_IS_REVA2 \
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \
((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))
#endif
#ifndef DEVICE_IS_REVC1
#define DEVICE_IS_REVC1 \
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \
((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1))
#endif
#ifndef DEVICE_IS_REVC2
#define DEVICE_IS_REVC2 \
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \
((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))
#endif
#endif // __HW_TYPES_H__

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//*****************************************************************************
//
// hw_uart.h - Macros and defines used when accessing the UART hardware
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_UART_H__
#define __HW_UART_H__
//*****************************************************************************
//
// UART Register Offsets.
//
//*****************************************************************************
#define UART_O_DR 0x00000000 // Data Register
#define UART_O_RSR 0x00000004 // Receive Status Register (read)
#define UART_O_ECR 0x00000004 // Error Clear Register (write)
#define UART_O_FR 0x00000018 // Flag Register (read only)
#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg
#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg
#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
#define UART_O_CTL 0x00000030 // Control Register
#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg
#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg
#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register
#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register
#define UART_O_ICR 0x00000044 // Interrupt Clear Register
#define UART_O_PeriphID4 0x00000FD0 //
#define UART_O_PeriphID5 0x00000FD4 //
#define UART_O_PeriphID6 0x00000FD8 //
#define UART_O_PeriphID7 0x00000FDC //
#define UART_O_PeriphID0 0x00000FE0 //
#define UART_O_PeriphID1 0x00000FE4 //
#define UART_O_PeriphID2 0x00000FE8 //
#define UART_O_PeriphID3 0x00000FEC //
#define UART_O_PCellID0 0x00000FF0 //
#define UART_O_PCellID1 0x00000FF4 //
#define UART_O_PCellID2 0x00000FF8 //
#define UART_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// Data Register bits
//
//*****************************************************************************
#define UART_DR_OE 0x00000800 // Overrun Error
#define UART_DR_BE 0x00000400 // Break Error
#define UART_DR_PE 0x00000200 // Parity Error
#define UART_DR_FE 0x00000100 // Framing Error
#define UART_DR_DATA_MASK 0x000000FF // UART data
//*****************************************************************************
//
// Receive Status Register bits
//
//*****************************************************************************
#define UART_RSR_OE 0x00000008 // Overrun Error
#define UART_RSR_BE 0x00000004 // Break Error
#define UART_RSR_PE 0x00000002 // Parity Error
#define UART_RSR_FE 0x00000001 // Framing Error
//*****************************************************************************
//
// Flag Register bits
//
//*****************************************************************************
#define UART_FR_TXFE 0x00000080 // TX FIFO Empty
#define UART_FR_RXFF 0x00000040 // RX FIFO Full
#define UART_FR_TXFF 0x00000020 // TX FIFO Full
#define UART_FR_RXFE 0x00000010 // RX FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
//*****************************************************************************
//
// Integer baud-rate divisor
//
//*****************************************************************************
#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
//*****************************************************************************
//
// Fractional baud-rate divisor
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
//*****************************************************************************
//
// Line Control Register High bits
//
//*****************************************************************************
#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
#define UART_LCR_H_WLEN 0x00000060 // Word length
#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
#define UART_LCR_H_PEN 0x00000002 // Parity Enable
#define UART_LCR_H_BRK 0x00000001 // Send Break
//*****************************************************************************
//
// Control Register bits
//
//*****************************************************************************
#define UART_CTL_RXE 0x00000200 // Receive Enable
#define UART_CTL_TXE 0x00000100 // Transmit Enable
#define UART_CTL_LBE 0x00000080 // Loopback Enable
#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable
#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
//*****************************************************************************
//
// Interrupt FIFO Level Select Register bits
//
//*****************************************************************************
#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask
#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full
#define UART_IFLS_RX2_8 0x00000008 // 1/4 Full
#define UART_IFLS_RX4_8 0x00000010 // 1/2 Full
#define UART_IFLS_RX6_8 0x00000018 // 3/4 Full
#define UART_IFLS_RX7_8 0x00000020 // 7/8 Full
#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask
#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full
#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full
#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full
#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full
#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full
//*****************************************************************************
//
// Interrupt Mask Set/Clear Register bits
//
//*****************************************************************************
#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask
#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask
#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask
#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask
#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask
//*****************************************************************************
//
// Raw Interrupt Status Register
//
//*****************************************************************************
#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status
#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status
#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status
#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status
#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status
#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status
//*****************************************************************************
//
// Masked Interrupt Status Register
//
//*****************************************************************************
#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status
#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status
#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status
#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status
//*****************************************************************************
//
// Interrupt Clear Register bits
//
//*****************************************************************************
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
#define UART_RSR_ANY (UART_RSR_OE | \
UART_RSR_BE | \
UART_RSR_PE | \
UART_RSR_FE)
//*****************************************************************************
//
// Reset Values for UART Registers.
//
//*****************************************************************************
#define UART_RV_DR 0x00000000
#define UART_RV_RSR 0x00000000
#define UART_RV_ECR 0x00000000
#define UART_RV_FR 0x00000090
#define UART_RV_IBRD 0x00000000
#define UART_RV_FBRD 0x00000000
#define UART_RV_LCR_H 0x00000000
#define UART_RV_CTL 0x00000300
#define UART_RV_IFLS 0x00000012
#define UART_RV_IM 0x00000000
#define UART_RV_RIS 0x00000000
#define UART_RV_MIS 0x00000000
#define UART_RV_ICR 0x00000000
#define UART_RV_PeriphID4 0x00000000
#define UART_RV_PeriphID5 0x00000000
#define UART_RV_PeriphID6 0x00000000
#define UART_RV_PeriphID7 0x00000000
#define UART_RV_PeriphID0 0x00000011
#define UART_RV_PeriphID1 0x00000000
#define UART_RV_PeriphID2 0x00000018
#define UART_RV_PeriphID3 0x00000001
#define UART_RV_PCellID0 0x0000000D
#define UART_RV_PCellID1 0x000000F0
#define UART_RV_PCellID2 0x00000005
#define UART_RV_PCellID3 0x000000B1
#endif // __HW_UART_H__

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//*****************************************************************************
//
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_WATCHDOG_H__
#define __HW_WATCHDOG_H__
//*****************************************************************************
//
// The following define the offsets of the Watchdog Timer registers.
//
//*****************************************************************************
#define WDT_O_LOAD 0x00000000 // Load register
#define WDT_O_VALUE 0x00000004 // Current value register
#define WDT_O_CTL 0x00000008 // Control register
#define WDT_O_ICR 0x0000000C // Interrupt clear register
#define WDT_O_RIS 0x00000010 // Raw interrupt status register
#define WDT_O_MIS 0x00000014 // Masked interrupt status register
#define WDT_O_TEST 0x00000418 // Test register
#define WDT_O_LOCK 0x00000C00 // Lock register
#define WDT_O_PeriphID4 0x00000FD0 //
#define WDT_O_PeriphID5 0x00000FD4 //
#define WDT_O_PeriphID6 0x00000FD8 //
#define WDT_O_PeriphID7 0x00000FDC //
#define WDT_O_PeriphID0 0x00000FE0 //
#define WDT_O_PeriphID1 0x00000FE4 //
#define WDT_O_PeriphID2 0x00000FE8 //
#define WDT_O_PeriphID3 0x00000FEC //
#define WDT_O_PCellID0 0x00000FF0 //
#define WDT_O_PCellID1 0x00000FF4 //
#define WDT_O_PCellID2 0x00000FF8 //
#define WDT_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// The following define the bit fields in the WDT_CTL register.
//
//*****************************************************************************
#define WDT_CTL_RESEN 0x00000002 // Enable reset output
#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int
//*****************************************************************************
//
// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS
// registers.
//
//*****************************************************************************
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
//*****************************************************************************
//
// The following define the bit fields in the WDT_TEST register.
//
//*****************************************************************************
#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable
#ifndef DEPRECATED
#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
#endif
//*****************************************************************************
//
// The following define the bit fields in the WDT_LOCK register.
//
//*****************************************************************************
#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked
#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
//*****************************************************************************
//
// The following define the reset values for the WDT registers.
//
//*****************************************************************************
#define WDT_RV_LOAD 0xFFFFFFFF // Load register
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
#define WDT_RV_CTL 0x00000000 // Control register
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
#define WDT_RV_LOCK 0x00000000 // Lock register
#define WDT_RV_PeriphID4 0x00000000 //
#define WDT_RV_PeriphID5 0x00000000 //
#define WDT_RV_PeriphID6 0x00000000 //
#define WDT_RV_PeriphID7 0x00000000 //
#define WDT_RV_PeriphID0 0x00000005 //
#define WDT_RV_PeriphID1 0x00000018 //
#define WDT_RV_PeriphID2 0x00000018 //
#define WDT_RV_PeriphID3 0x00000001 //
#define WDT_RV_PCellID0 0x0000000D //
#define WDT_RV_PCellID1 0x000000F0 //
#define WDT_RV_PCellID2 0x00000005 //
#define WDT_RV_PCellID3 0x000000B1 //
#endif // __HW_WATCHDOG_H__

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//*****************************************************************************
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __I2C_H__
#define __I2C_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND 0x00000007
#define I2C_MASTER_CMD_SINGLE_RECEIVE 0x00000007
#define I2C_MASTER_CMD_BURST_SEND_START 0x00000003
#define I2C_MASTER_CMD_BURST_SEND_CONT 0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH 0x00000005
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP 0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START 0x0000000b
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT 0x00000009
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH 0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000005
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
//*****************************************************************************
//
// Miscellaneous I2C driver definitions.
//
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
extern void I2CIntUnregister(unsigned long ulBase);
extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
extern tBoolean I2CMasterBusy(unsigned long ulBase);
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
extern unsigned long I2CMasterDataGet(unsigned long ulBase);
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CMasterDisable(unsigned long ulBase);
extern void I2CMasterEnable(unsigned long ulBase);
extern unsigned long I2CMasterErr(unsigned long ulBase);
extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
tBoolean bFast);
extern void I2CMasterIntClear(unsigned long ulBase);
extern void I2CMasterIntDisable(unsigned long ulBase);
extern void I2CMasterIntEnable(unsigned long ulBase);
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
unsigned char ucSlaveAddr,
tBoolean bReceive);
extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CSlaveDisable(unsigned long ulBase);
extern void I2CSlaveEnable(unsigned long ulBase);
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
extern void I2CSlaveIntClear(unsigned long ulBase);
extern void I2CSlaveIntDisable(unsigned long ulBase);
extern void I2CSlaveIntEnable(unsigned long ulBase);
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
extern unsigned long I2CSlaveStatus(unsigned long ulBase);
//*****************************************************************************
//
// Several I2C APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define I2CMasterInit(a, b) \
I2CMasterInitExpClk(a, SysCtlClockGet(), b)
#endif
#ifdef __cplusplus
}
#endif
#endif // __I2C_H__

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//*****************************************************************************
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void IntMasterEnable(void);
extern void IntMasterDisable(void);
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
extern void IntUnregister(unsigned long ulInterrupt);
extern void IntPriorityGroupingSet(unsigned long ulBits);
extern unsigned long IntPriorityGroupingGet(void);
extern void IntPrioritySet(unsigned long ulInterrupt,
unsigned char ucPriority);
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__

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//*****************************************************************************
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __FLASH_H__
#define __FLASH_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FlashProtectSet(), and returned by
// FlashProtectGet().
//
//*****************************************************************************
typedef enum
{
FlashReadWrite, // Flash can be read and written
FlashReadOnly, // Flash can only be read
FlashExecuteOnly // Flash can only be executed
}
tFlashProtection;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long FlashUsecGet(void);
extern void FlashUsecSet(unsigned long ulClocks);
extern long FlashErase(unsigned long ulAddress);
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
extern long FlashProtectSet(unsigned long ulAddress,
tFlashProtection eProtect);
extern long FlashProtectSave(void);
extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);
extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);
extern long FlashUserSave(void);
extern void FlashIntRegister(void (*pfnHandler)(void));
extern void FlashIntUnregister(void);
extern void FlashIntEnable(unsigned long ulIntFlags);
extern void FlashIntDisable(unsigned long ulIntFlags);
extern unsigned long FlashIntGetStatus(tBoolean bMasked);
extern void FlashIntClear(unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __FLASH_H__

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//*****************************************************************************
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
tBoolean bEnable);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerRTCEnable(unsigned long ulBase);
extern void TimerRTCDisable(unsigned long ulBase);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerQuiesce(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__

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//*****************************************************************************
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __PWM_H__
#define __PWM_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are passed to PWMGenConfigure() as the ulConfig
// parameter and specify the configuration of the PWM generator.
//
//*****************************************************************************
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM generator interrupts and
// triggers.
//
//*****************************************************************************
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM interrupts.
//
//*****************************************************************************
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
#define PWM_INT_FAULT 0x00010000 // Fault interrupt
//*****************************************************************************
//
// Defines to identify the generators within a module.
//
//*****************************************************************************
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
//*****************************************************************************
//
// Defines to identify the outputs within a module.
//
//*****************************************************************************
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulConfig);
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulPeriod);
extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
unsigned long ulGen);
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
unsigned long ulWidth);
extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
unsigned long ulPWMOut);
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
unsigned short usRise, unsigned short usFall);
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bEnable);
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bInvert);
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bFaultKill);
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
void (*pfnIntHandler)(void));
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
extern void PWMFaultIntRegister(unsigned long ulBase,
void (*pfnIntHandler)(void));
extern void PWMFaultIntUnregister(unsigned long ulBase);
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
tBoolean bMasked);
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulInts);
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMFaultIntClear(unsigned long ulBase);
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
#ifdef __cplusplus
}
#endif
#endif // __PWM_H__

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//*****************************************************************************
//
// qei.h - Prototypes for the Quadrature Encoder Driver.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __QEI_H__
#define __QEI_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to QEIConfigure as the ulConfig paramater.
//
//*****************************************************************************
#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only
#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges
#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse
#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse
#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature
#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir
#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB
#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB
//*****************************************************************************
//
// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.
//
//*****************************************************************************
#define QEI_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_VELDIV_128 0x000001C0 // Predivide by 128
//*****************************************************************************
//
// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
// as the ulIntFlags parameter, and returned by QEIGetIntStatus.
//
//*****************************************************************************
#define QEI_INTERROR 0x00000008 // Phase error detected
#define QEI_INTDIR 0x00000004 // Direction change
#define QEI_INTTIMER 0x00000002 // Velocity timer expired
#define QEI_INTINDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void QEIEnable(unsigned long ulBase);
extern void QEIDisable(unsigned long ulBase);
extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxPosition);
extern unsigned long QEIPositionGet(unsigned long ulBase);
extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);
extern long QEIDirectionGet(unsigned long ulBase);
extern tBoolean QEIErrorGet(unsigned long ulBase);
extern void QEIVelocityEnable(unsigned long ulBase);
extern void QEIVelocityDisable(unsigned long ulBase);
extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
unsigned long ulPeriod);
extern unsigned long QEIVelocityGet(unsigned long ulBase);
extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void QEIIntUnregister(unsigned long ulBase);
extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __QEI_H__

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//*****************************************************************************
//
// rit128x96x4.h - Prototypes for the driver for the RITEK 128x96x4 graphical
// OLED display.
//
// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __RIT128X96X4_H__
#define __RIT128X96X4_H__
//*****************************************************************************
//
// Prototypes for the driver APIs.
//
//*****************************************************************************
extern void RIT128x96x4Clear(void);
extern void RIT128x96x4StringDraw(const char *pcStr,
unsigned long ulX,
unsigned long ulY,
unsigned char ucLevel);
extern void RIT128x96x4ImageDraw(const unsigned char *pucImage,
unsigned long ulX,
unsigned long ulY,
unsigned long ulWidth,
unsigned long ulHeight);
extern void RIT128x96x4Init(unsigned long ulFrequency);
extern void RIT128x96x4Enable(unsigned long ulFrequency);
extern void RIT128x96x4Disable(void);
extern void RIT128x96x4DisplayOn(void);
extern void RIT128x96x4DisplayOff(void);
#endif // __RIT128X96X4_H__

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//*****************************************************************************
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SSI_H__
#define __SSI_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
// as the ulIntFlags parameter, and returned by SSIIntStatus.
//
//*****************************************************************************
#define SSI_TXFF 0x00000008 // TX FIFO half empty or less
#define SSI_RXFF 0x00000004 // RX FIFO half full or less
#define SSI_RXTO 0x00000002 // RX timeout
#define SSI_RXOR 0x00000001 // RX overrun
//*****************************************************************************
//
// Values that can be passed to SSIConfigSetExpClk.
//
//*****************************************************************************
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
#define SSI_FRF_TI 0x00000010 // TI frame format
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
#define SSI_MODE_MASTER 0x00000000 // SSI master
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
unsigned long ulProtocol, unsigned long ulMode,
unsigned long ulBitRate,
unsigned long ulDataWidth);
extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
extern long SSIDataGetNonBlocking(unsigned long ulBase,
unsigned long *pulData);
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
extern void SSIDisable(unsigned long ulBase);
extern void SSIEnable(unsigned long ulBase);
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SSIIntUnregister(unsigned long ulBase);
//*****************************************************************************
//
// Several SSI APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define SSIConfig(a, b, c, d, e) \
SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
#define SSIDataNonBlockingGet(a, b) \
SSIDataGetNonBlocking(a, b)
#define SSIDataNonBlockingPut(a, b) \
SSIDataPutNonBlocking(a, b)
#endif
#ifdef __cplusplus
}
#endif
#endif // __SSI_H__

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//*****************************************************************************
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following are values that can be passed to the
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
#define SYSCTL_PERIPH_ETH 0x20105000 // ETH
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPinPresent() API
// as the ulPin parameter.
//
//*****************************************************************************
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOSet() API as
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
//
//*****************************************************************************
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
//
//*****************************************************************************
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlIntEnable(),
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
// by the SysCtlIntStatus() API.
//
//*****************************************************************************
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlResetCauseClear()
// API or returned by the SysCtlResetCauseGet() API.
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPWMClockSet() API
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
// API.
//
//*****************************************************************************
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlADCSpeedSet() API
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
// API.
//
//*****************************************************************************
#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second
#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second
#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
extern void SysCtlIntRegister(void (*pfnHandler)(void));
extern void SysCtlIntUnregister(void);
extern void SysCtlIntEnable(unsigned long ulInts);
extern void SysCtlIntDisable(unsigned long ulInts);
extern void SysCtlIntClear(unsigned long ulInts);
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
extern void SysCtlLDOSet(unsigned long ulVoltage);
extern unsigned long SysCtlLDOGet(void);
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
extern void SysCtlReset(void);
extern void SysCtlSleep(void);
extern void SysCtlDeepSleep(void);
extern unsigned long SysCtlResetCauseGet(void);
extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
extern unsigned long SysCtlADCSpeedGet(void);
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
extern void SysCtlClkVerificationClear(void);
#ifdef __cplusplus
}
#endif
#endif // __SYSCTL_H__

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//*****************************************************************************
//
// systick.h - Prototypes for the SysTick driver.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SysTickEnable(void);
extern void SysTickDisable(void);
extern void SysTickIntRegister(void (*pfnHandler)(void));
extern void SysTickIntUnregister(void);
extern void SysTickIntEnable(void);
extern void SysTickIntDisable(void);
extern void SysTickPeriodSet(unsigned long ulPeriod);
extern unsigned long SysTickPeriodGet(void);
extern unsigned long SysTickValueGet(void);
#ifdef __cplusplus
}
#endif
#endif // __SYSTICK_H__

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//*****************************************************************************
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
tBoolean bEnable);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerRTCEnable(unsigned long ulBase);
extern void TimerRTCDisable(unsigned long ulBase);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerQuiesce(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__

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//*****************************************************************************
//
// uart.h - Defines and Macros for the UART.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __UART_H__
#define __UART_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
#define UART_INT_RX 0x010 // Receive Interrupt Mask
//*****************************************************************************
//
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
// and returned by UARTConfigGetExpClk in the pulConfig parameter.
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
// UARTParityModeSet as the ulParity parameter, and are returned by
// UARTParityModeGet.
//
//*****************************************************************************
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one
#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
// returned by UARTFIFOLevelGet in the pulTxLevel.
//
//*****************************************************************************
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
// returned by UARTFIFOLevelGet in the pulRxLevel.
//
//*****************************************************************************
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
extern unsigned long UARTParityModeGet(unsigned long ulBase);
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel);
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel);
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long ulBaud, unsigned long ulConfig);
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long *pulBaud,
unsigned long *pulConfig);
extern void UARTEnable(unsigned long ulBase);
extern void UARTDisable(unsigned long ulBase);
extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
extern void UARTDisableSIR(unsigned long ulBase);
extern tBoolean UARTCharsAvail(unsigned long ulBase);
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
extern long UARTCharGetNonBlocking(unsigned long ulBase);
extern long UARTCharGet(unsigned long ulBase);
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
unsigned char ucData);
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void UARTIntUnregister(unsigned long ulBase);
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
//*****************************************************************************
//
// Several UART APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define UARTConfigSet(a, b, c) \
UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
#define UARTConfigGet(a, b, c) \
UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
#define UARTCharNonBlockingGet(a) \
UARTCharGetNonBlocking(a)
#define UARTCharNonBlockingPut(a, b) \
UARTCharPutNonBlocking(a, b)
#endif
#ifdef __cplusplus
}
#endif
#endif // __UART_H__

670
20080212/Demo/Common/drivers/LuminaryMicro/ustdlib.c Normal file
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//*****************************************************************************
//
// ustdlib.c - Simple standard library functions.
//
// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
//*****************************************************************************
#include <stdarg.h>
#include <string.h>
#include "debug.h"
//*****************************************************************************
//
//! \addtogroup utilities_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// A mapping from an integer between 0 and 15 to its ASCII character
// equivalent.
//
//*****************************************************************************
static const char * const g_pcHex = "0123456789abcdef";
//*****************************************************************************
//
//! A simple vsnprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.
//!
//! \param pcBuf points to the buffer where the converted string is stored.
//! \param ulSize is the size of the buffer.
//! \param pcString is the format string.
//! \param vaArgP is the list of optional arguments, which depend on the
//! contents of the format string.
//!
//! This function is very similar to the C library <tt>vsnprintf()</tt>
//! function. Only the following formatting characters are supported:
//!
//! - \%c to print a character
//! - \%d to print a decimal value
//! - \%s to print a string
//! - \%u to print an unsigned decimal value
//! - \%x to print a hexadecimal value using lower case letters
//! - \%X to print a hexadecimal value using lower case letters (not upper case
//! letters as would typically be used)
//! - \%\% to print out a \% character
//!
//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%
//! and the format character, which specifies the minimum number of characters
//! to use for that value; if preceeded by a 0 then the extra characters will
//! be filled with zeros instead of spaces. For example, ``\%8d'' will use
//! eight characters to print the decimal value with spaces added to reach
//! eight; ``\%08d'' will use eight characters as well but will add zeros
//! instead of spaces.
//!
//! The type of the arguments after \b pcString must match the requirements of
//! the format string. For example, if an integer was passed where a string
//! was expected, an error of some kind will most likely occur.
//!
//! The \b ulSize parameter limits the number of characters that will be
//! stored in the buffer pointed to by \b pcBuf to prevent the possibility
//! of a buffer overflow. The buffer size should be large enough to hold
//! the expected converted output string, including the null termination
//! character.
//!
//! The function will return the number of characters that would be
//! converted as if there were no limit on the buffer size. Therefore
//! it is possible for the function to return a count that is greater than
//! the specified buffer size. If this happens, it means that the output
//! was truncated.
//!
//! \return the number of characters that were to be stored, not including
//! the NULL termination character, regardless of space in the buffer.
//
//*****************************************************************************
int
uvsnprintf(char *pcBuf, unsigned long ulSize, const char *pcString,
va_list vaArgP)
{
unsigned long ulIdx, ulValue, ulCount, ulBase;
char *pcStr, cFill;
int iConvertCount = 0;
//
// Check the arguments.
//
ASSERT(pcString != 0);
ASSERT(pcBuf != 0);
ASSERT(ulSize != 0);
//
// Adjust buffer size limit to allow one space for null termination.
//
if(ulSize)
{
ulSize--;
}
//
// Initialize the count of characters converted.
//
iConvertCount = 0;
//
// Loop while there are more characters in the format string.
//
while(*pcString)
{
//
// Find the first non-% character, or the end of the string.
//
for(ulIdx = 0; (pcString[ulIdx] != '%') && (pcString[ulIdx] != '\0');
ulIdx++)
{
}
//
// Write this portion of the string to the output buffer. If
// there are more characters to write than there is space in the
// buffer, then only write as much as will fit in the buffer.
//
if(ulIdx > ulSize)
{
strncpy(pcBuf, pcString, ulSize);
pcBuf += ulSize;
ulSize = 0;
}
else
{
strncpy(pcBuf, pcString, ulIdx);
pcBuf += ulIdx;
ulSize -= ulIdx;
}
//
// Update the conversion count. This will be the number of
// characters that should have been written, even if there was
// not room in the buffer.
//
iConvertCount += ulIdx;
//
// Skip the portion of the format string that was written.
//
pcString += ulIdx;
//
// See if the next character is a %.
//
if(*pcString == '%')
{
//
// Skip the %.
//
pcString++;
//
// Set the digit count to zero, and the fill character to space
// (i.e. to the defaults).
//
ulCount = 0;
cFill = ' ';
//
// It may be necessary to get back here to process more characters.
// Goto's aren't pretty, but effective. I feel extremely dirty for
// using not one but two of the beasts.
//
again:
//
// Determine how to handle the next character.
//
switch(*pcString++)
{
//
// Handle the digit characters.
//
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
{
//
// If this is a zero, and it is the first digit, then the
// fill character is a zero instead of a space.
//
if((pcString[-1] == '0') && (ulCount == 0))
{
cFill = '0';
}
//
// Update the digit count.
//
ulCount *= 10;
ulCount += pcString[-1] - '0';
//
// Get the next character.
//
goto again;
}
//
// Handle the %c command.
//
case 'c':
{
//
// Get the value from the varargs.
//
ulValue = va_arg(vaArgP, unsigned long);
//
// Copy the character to the output buffer, if
// there is room. Update the buffer size remaining.
//
if(ulSize != 0)
{
*pcBuf++ = (char)ulValue;
ulSize--;
}
//
// Update the conversion count.
//
iConvertCount++;
//
// This command has been handled.
//
break;
}
//
// Handle the %d command.
//
case 'd':
{
//
// Get the value from the varargs.
//
ulValue = va_arg(vaArgP, unsigned long);
//
// If the value is negative, make it positive and stick a
// minus sign in the beginning of the buffer.
//
if((long)ulValue < 0)
{
ulValue = -(long)ulValue;
if(ulSize != 0)
{
*pcBuf++ = '-';
ulSize--;
}
//
// Update the conversion count.
//
iConvertCount++;
}
//
// Set the base to 10.
//
ulBase = 10;
//
// Convert the value to ASCII.
//
goto convert;
}
//
// Handle the %s command.
//
case 's':
{
//
// Get the string pointer from the varargs.
//
pcStr = va_arg(vaArgP, char *);
//
// Determine the length of the string.
//
for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++)
{
}
//
// Copy the string to the output buffer. Only copy
// as much as will fit in the buffer. Update the
// output buffer pointer and the space remaining.
//
if(ulIdx > ulSize)
{
strncpy(pcBuf, pcStr, ulSize);
pcBuf += ulSize;
ulSize = 0;
}
else
{
strncpy(pcBuf, pcStr, ulIdx);
pcBuf += ulIdx;
ulSize -= ulIdx;
}
//
// Update the conversion count. This will be the number of
// characters that should have been written, even if there
// was not room in the buffer.
//
iConvertCount += ulIdx;
//
//
// This command has been handled.
//
break;
}
//
// Handle the %u command.
//
case 'u':
{
//
// Get the value from the varargs.
//
ulValue = va_arg(vaArgP, unsigned long);
//
// Set the base to 10.
//
ulBase = 10;
//
// Convert the value to ASCII.
//
goto convert;
}
//
// Handle the %x and %X commands. Note that they are treated
// identically; i.e. %X will use lower case letters for a-f
// instead of the upper case letters is should use.
//
case 'x':
case 'X':
{
//
// Get the value from the varargs.
//
ulValue = va_arg(vaArgP, unsigned long);
//
// Set the base to 16.
//
ulBase = 16;
//
// Determine the number of digits in the string version of
// the value.
//
convert:
for(ulIdx = 1;
(((ulIdx * ulBase) <= ulValue) &&
(((ulIdx * ulBase) / ulBase) == ulIdx));
ulIdx *= ulBase, ulCount--)
{
}
//
// Provide additional padding at the beginning of the
// string conversion if needed.
//
if((ulCount > 1) && (ulCount < 16))
{
for(ulCount--; ulCount; ulCount--)
{
//
// Copy the character to the output buffer if
// there is room.
//
if(ulSize != 0)
{
*pcBuf++ = cFill;
ulSize--;
}
//
// Update the conversion count.
//
iConvertCount++;
}
}
//
// Convert the value into a string.
//
for(; ulIdx; ulIdx /= ulBase)
{
//
// Copy the character to the output buffer if
// there is room.
//
if(ulSize != 0)
{
*pcBuf++ = g_pcHex[(ulValue / ulIdx) % ulBase];
ulSize--;
}
//
// Update the conversion count.
//
iConvertCount++;
}
//
// This command has been handled.
//
break;
}
//
// Handle the %% command.
//
case '%':
{
//
// Simply write a single %.
//
if(ulSize != 0)
{
*pcBuf++ = pcString[-1];
ulSize--;
}
//
// Update the conversion count.
//
iConvertCount++;
//
// This command has been handled.
//
break;
}
//
// Handle all other commands.
//
default:
{
//
// Indicate an error.
//
if(ulSize >= 5)
{
strncpy(pcBuf, "ERROR", 5);
pcBuf += 5;
ulSize -= 5;
}
else
{
strncpy(pcBuf, "ERROR", ulSize);
pcBuf += ulSize;
ulSize = 0;
}
//
// Update the conversion count.
//
iConvertCount += 5;
//
// This command has been handled.
//
break;
}
}
}
}
//
// Null terminate the string in the buffer.
//
*pcBuf = 0;
return(iConvertCount);
}
//*****************************************************************************
//
//! A simple sprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.
//!
//! \param pcBuf is the buffer where the converted string is stored.
//! \param pcString is the format string.
//! \param ... are the optional arguments, which depend on the contents of the
//! format string.
//!
//! This function is very similar to the C library <tt>sprintf()</tt> function.
//! Only the following formatting characters are supported:
//!
//! - \%c to print a character
//! - \%d to print a decimal value
//! - \%s to print a string
//! - \%u to print an unsigned decimal value
//! - \%x to print a hexadecimal value using lower case letters
//! - \%X to print a hexadecimal value using lower case letters (not upper case
//! letters as would typically be used)
//! - \%\% to print out a \% character
//!
//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%
//! and the format character, which specifies the minimum number of characters
//! to use for that value; if preceeded by a 0 then the extra characters will
//! be filled with zeros instead of spaces. For example, ``\%8d'' will use
//! eight characters to print the decimal value with spaces added to reach
//! eight; ``\%08d'' will use eight characters as well but will add zeros
//! instead of spaces.
//!
//! The type of the arguments after \b pcString must match the requirements of
//! the format string. For example, if an integer was passed where a string
//! was expected, an error of some kind will most likely occur.
//!
//! The caller must ensure that the buffer pcBuf is large enough to hold the
//! entire converted string, including the null termination character.
//!
//! \return The count of characters that were written to the output buffer,
//! not including the NULL termination character.
//
//*****************************************************************************
int
usprintf(char *pcBuf, const char *pcString, ...)
{
va_list vaArgP;
int iRet;
//
// Start the varargs processing.
//
va_start(vaArgP, pcString);
//
// Call vsnprintf to perform the conversion. Use a
// large number for the buffer size.
//
iRet = uvsnprintf(pcBuf, 0xffff, pcString, vaArgP);
//
// End the varargs processing.
//
va_end(vaArgP);
//
// Return the conversion count.
//
return(iRet);
}
//*****************************************************************************
//
//! A simple snprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.
//!
//! \param pcBuf is the buffer where the converted string is stored.
//! \param ulSize is the size of the buffer.
//! \param pcString is the format string.
//! \param ... are the optional arguments, which depend on the contents of the
//! format string.
//!
//! This function is very similar to the C library <tt>sprintf()</tt> function.
//! Only the following formatting characters are supported:
//!
//! - \%c to print a character
//! - \%d to print a decimal value
//! - \%s to print a string
//! - \%u to print an unsigned decimal value
//! - \%x to print a hexadecimal value using lower case letters
//! - \%X to print a hexadecimal value using lower case letters (not upper case
//! letters as would typically be used)
//! - \%\% to print out a \% character
//!
//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%
//! and the format character, which specifies the minimum number of characters
//! to use for that value; if preceeded by a 0 then the extra characters will
//! be filled with zeros instead of spaces. For example, ``\%8d'' will use
//! eight characters to print the decimal value with spaces added to reach
//! eight; ``\%08d'' will use eight characters as well but will add zeros
//! instead of spaces.
//!
//! The type of the arguments after \b pcString must match the requirements of
//! the format string. For example, if an integer was passed where a string
//! was expected, an error of some kind will most likely occur.
//!
//! The function will copy at most \b ulSize - 1 characters into the
//! buffer \b pcBuf. One space is reserved in the buffer for the null
//! termination character.
//!
//! The function will return the number of characters that would be
//! converted as if there were no limit on the buffer size. Therefore
//! it is possible for the function to return a count that is greater than
//! the specified buffer size. If this happens, it means that the output
//! was truncated.
//!
//! \return the number of characters that were to be stored, not including
//! the NULL termination character, regardless of space in the buffer.
//
//*****************************************************************************
int
usnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, ...)
{
int iRet;
va_list vaArgP;
//
// Start the varargs processing.
//
va_start(vaArgP, pcString);
//
// Call vsnprintf to perform the conversion.
//
iRet = uvsnprintf(pcBuf, ulSize, pcString, vaArgP);
//
// End the varargs processing.
//
va_end(vaArgP);
//
// Return the conversion count.
//
return(iRet);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

63
20080212/Demo/Common/drivers/LuminaryMicro/watchdog.h Normal file
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//*****************************************************************************
//
// watchdog.h - Prototypes for the Watchdog Timer API
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean WatchdogRunning(unsigned long ulBase);
extern void WatchdogEnable(unsigned long ulBase);
extern void WatchdogResetEnable(unsigned long ulBase);
extern void WatchdogResetDisable(unsigned long ulBase);
extern void WatchdogLock(unsigned long ulBase);
extern void WatchdogUnlock(unsigned long ulBase);
extern tBoolean WatchdogLockState(unsigned long ulBase);
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
extern unsigned long WatchdogValueGet(unsigned long ulBase);
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void WatchdogIntUnregister(unsigned long ulBase);
extern void WatchdogIntEnable(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogStallEnable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __WATCHDOG_H__

6
20080212/Demo/Common/drivers/OpenOCD/license.txt Normal file
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OpenOCD is open source software that is covered by the GNU General Public
License (GPL).
Instructions on obtaining/downloading the source code along with the relevant
Copyright information can be obtained from: http://openocd.berlios.de/web/

BIN
20080212/Demo/Common/drivers/OpenOCD/openocd-pp.exe Normal file
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BIN
20080212/Demo/Common/drivers/OpenOCD/openocd_ftdi.exe Normal file
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13
20080212/Demo/Common/ethernet/lwIP/FILES Normal file
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api/ - The code for the high-level wrapper API. Not needed if
you use the lowel-level call-back/raw API.
core/ - The core of the TPC/IP stack; protocol implementations,
memory and buffer management, and the low-level raw API.
include/ - lwIP include files.
netif/ - Generic network interface device drivers are kept here,
as well as the ARP module.
For more information on the various subdirectories, check the FILES
file in each directory.

722
20080212/Demo/Common/ethernet/lwIP/api/api_lib.c Normal file
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/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
/* This is the part of the API that is linked with
the application */
#include "lwip/opt.h"
#include "lwip/api.h"
#include "lwip/api_msg.h"
#include "lwip/memp.h"
struct
netbuf *netbuf_new(void)
{
struct netbuf *buf;
buf = memp_malloc(MEMP_NETBUF);
if (buf != NULL) {
buf->p = NULL;
buf->ptr = NULL;
return buf;
} else {
return NULL;
}
}
void
netbuf_delete(struct netbuf *buf)
{
if (buf != NULL) {
if (buf->p != NULL) {
pbuf_free(buf->p);
buf->p = buf->ptr = NULL;
}
memp_free(MEMP_NETBUF, buf);
}
}
void *
netbuf_alloc(struct netbuf *buf, u16_t size)
{
/* Deallocate any previously allocated memory. */
if (buf->p != NULL) {
pbuf_free(buf->p);
}
buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
if (buf->p == NULL) {
return NULL;
}
buf->ptr = buf->p;
return buf->p->payload;
}
void
netbuf_free(struct netbuf *buf)
{
if (buf->p != NULL) {
pbuf_free(buf->p);
}
buf->p = buf->ptr = NULL;
}
void
netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size)
{
if (buf->p != NULL) {
pbuf_free(buf->p);
}
buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
buf->p->payload = dataptr;
buf->p->len = buf->p->tot_len = size;
buf->ptr = buf->p;
}
void
netbuf_chain(struct netbuf *head, struct netbuf *tail)
{
pbuf_chain(head->p, tail->p);
head->ptr = head->p;
memp_free(MEMP_NETBUF, tail);
}
u16_t
netbuf_len(struct netbuf *buf)
{
return buf->p->tot_len;
}
err_t
netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
{
if (buf->ptr == NULL) {
return ERR_BUF;
}
*dataptr = buf->ptr->payload;
*len = buf->ptr->len;
return ERR_OK;
}
s8_t
netbuf_next(struct netbuf *buf)
{
if (buf->ptr->next == NULL) {
return -1;
}
buf->ptr = buf->ptr->next;
if (buf->ptr->next == NULL) {
return 1;
}
return 0;
}
void
netbuf_first(struct netbuf *buf)
{
buf->ptr = buf->p;
}
void
netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset)
{
struct pbuf *p;
u16_t i, left;
left = 0;
if(buf == NULL || dataptr == NULL) {
return;
}
/* This implementation is bad. It should use bcopy
instead. */
for(p = buf->p; left < len && p != NULL; p = p->next) {
if (offset != 0 && offset >= p->len) {
offset -= p->len;
} else {
for(i = offset; i < p->len; ++i) {
((u8_t *)dataptr)[left] = ((u8_t *)p->payload)[i];
if (++left >= len) {
return;
}
}
offset = 0;
}
}
}
void
netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len)
{
netbuf_copy_partial(buf, dataptr, len, 0);
}
struct ip_addr *
netbuf_fromaddr(struct netbuf *buf)
{
return buf->fromaddr;
}
u16_t
netbuf_fromport(struct netbuf *buf)
{
return buf->fromport;
}
struct
netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
{
struct netconn *conn;
struct api_msg *msg;
conn = memp_malloc(MEMP_NETCONN);
if (conn == NULL) {
return NULL;
}
conn->err = ERR_OK;
conn->type = t;
conn->pcb.tcp = NULL;
if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) {
memp_free(MEMP_NETCONN, conn);
return NULL;
}
conn->recvmbox = SYS_MBOX_NULL;
conn->acceptmbox = SYS_MBOX_NULL;
conn->sem = sys_sem_new(0);
if (conn->sem == SYS_SEM_NULL) {
memp_free(MEMP_NETCONN, conn);
return NULL;
}
conn->state = NETCONN_NONE;
conn->socket = 0;
conn->callback = callback;
conn->recv_avail = 0;
if((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
memp_free(MEMP_NETCONN, conn);
return NULL;
}
msg->type = API_MSG_NEWCONN;
msg->msg.msg.bc.port = proto; /* misusing the port field */
msg->msg.conn = conn;
api_msg_post(msg);
sys_mbox_fetch(conn->mbox, NULL);
memp_free(MEMP_API_MSG, msg);
if ( conn->err != ERR_OK ) {
memp_free(MEMP_NETCONN, conn);
return NULL;
}
return conn;
}
struct
netconn *netconn_new(enum netconn_type t)
{
return netconn_new_with_proto_and_callback(t,0,NULL);
}
struct
netconn *netconn_new_with_callback(enum netconn_type t,
void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
{
return netconn_new_with_proto_and_callback(t,0,callback);
}
err_t
netconn_delete(struct netconn *conn)
{
struct api_msg *msg;
void *mem;
if (conn == NULL) {
return ERR_OK;
}
if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
return ERR_MEM;
}
msg->type = API_MSG_DELCONN;
msg->msg.conn = conn;
api_msg_post(msg);
sys_mbox_fetch(conn->mbox, NULL);
memp_free(MEMP_API_MSG, msg);
/* Drain the recvmbox. */
if (conn->recvmbox != SYS_MBOX_NULL) {
while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
if (conn->type == NETCONN_TCP) {
if(mem != NULL)
pbuf_free((struct pbuf *)mem);
} else {
netbuf_delete((struct netbuf *)mem);
}
}
sys_mbox_free(conn->recvmbox);
conn->recvmbox = SYS_MBOX_NULL;
}
/* Drain the acceptmbox. */
if (conn->acceptmbox != SYS_MBOX_NULL) {
while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
netconn_delete((struct netconn *)mem);
}
sys_mbox_free(conn->acceptmbox);
conn->acceptmbox = SYS_MBOX_NULL;
}
sys_mbox_free(conn->mbox);
conn->mbox = SYS_MBOX_NULL;
if (conn->sem != SYS_SEM_NULL) {
sys_sem_free(conn->sem);
}
/* conn->sem = SYS_SEM_NULL;*/
memp_free(MEMP_NETCONN, conn);
return ERR_OK;
}
enum netconn_type
netconn_type(struct netconn *conn)
{
return conn->type;
}
err_t
netconn_peer(struct netconn *conn, struct ip_addr *addr,
u16_t *port)
{
switch (conn->type) {
case NETCONN_RAW:
/* return an error as connecting is only a helper for upper layers */
return ERR_CONN;
case NETCONN_UDPLITE:
case NETCONN_UDPNOCHKSUM:
case NETCONN_UDP:
if (conn->pcb.udp == NULL ||
((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0))
return ERR_CONN;
*addr = (conn->pcb.udp->remote_ip);
*port = conn->pcb.udp->remote_port;
break;
case NETCONN_TCP:
if (conn->pcb.tcp == NULL)
return ERR_CONN;
*addr = (conn->pcb.tcp->remote_ip);
*port = conn->pcb.tcp->remote_port;
break;
}
return (conn->err = ERR_OK);
}
err_t
netconn_addr(struct netconn *conn, struct ip_addr **addr,
u16_t *port)
{
switch (conn->type) {
case NETCONN_RAW:
*addr = &(conn->pcb.raw->local_ip);
*port = conn->pcb.raw->protocol;
break;
case NETCONN_UDPLITE:
case NETCONN_UDPNOCHKSUM:
case NETCONN_UDP:
*addr = &(conn->pcb.udp->local_ip);
*port = conn->pcb.udp->local_port;
break;
case NETCONN_TCP:
*addr = &(conn->pcb.tcp->local_ip);
*port = conn->pcb.tcp->local_port;
break;
}
return (conn->err = ERR_OK);
}
err_t
netconn_bind(struct netconn *conn, struct ip_addr *addr,
u16_t port)
{
struct api_msg *msg;
if (conn == NULL) {
return ERR_VAL;
}
if (conn->type != NETCONN_TCP &&
conn->recvmbox == SYS_MBOX_NULL) {
if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
return ERR_MEM;
}
}
if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
return (conn->err = ERR_MEM);
}
msg->type = API_MSG_BIND;
msg->msg.conn = conn;
msg->msg.msg.bc.ipaddr = addr;
msg->msg.msg.bc.port = port;
api_msg_post(msg);
sys_mbox_fetch(conn->mbox, NULL);
memp_free(MEMP_API_MSG, msg);
return conn->err;
}
err_t
netconn_connect(struct netconn *conn, struct ip_addr *addr,
u16_t port)
{
struct api_msg *msg;
if (conn == NULL) {
return ERR_VAL;
}
if (conn->recvmbox == SYS_MBOX_NULL) {
if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
return ERR_MEM;
}
}
if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
return ERR_MEM;
}
msg->type = API_MSG_CONNECT;
msg->msg.conn = conn;
msg->msg.msg.bc.ipaddr = addr;
msg->msg.msg.bc.port = port;
api_msg_post(msg);
sys_mbox_fetch(conn->mbox, NULL);
memp_free(MEMP_API_MSG, msg);
return conn->err;
}
err_t
netconn_disconnect(struct netconn *conn)
{
struct api_msg *msg;
if (conn == NULL) {
return ERR_VAL;
}
if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
return ERR_MEM;
}
msg->type = API_MSG_DISCONNECT;
msg->msg.conn = conn;
api_msg_post(msg);
sys_mbox_fetch(conn->mbox, NULL);
memp_free(MEMP_API_MSG, msg);
return conn->err;
}
err_t
netconn_listen(struct netconn *conn)
{
struct api_msg *msg;
if (conn == NULL) {
return ERR_VAL;
}
if (conn->acceptmbox == SYS_MBOX_NULL) {
conn->acceptmbox = sys_mbox_new();
if (conn->acceptmbox == SYS_MBOX_NULL) {
return ERR_MEM;
}
}
if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
return (conn->err = ERR_MEM);
}
msg->type = API_MSG_LISTEN;
msg->msg.conn = conn;
api_msg_post(msg);
sys_mbox_fetch(conn->mbox, NULL);
memp_free(MEMP_API_MSG, msg);
return conn->err;
}
struct netconn *
netconn_accept(struct netconn *conn)
{
struct netconn *newconn;
if (conn == NULL) {
return NULL;
}
sys_mbox_fetch(conn->acceptmbox, (void *)&newconn);
/* Register event with callback */
if (conn->callback)
(*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0);
return newconn;
}
struct netbuf *
netconn_recv(struct netconn *conn)
{
struct api_msg *msg;
struct netbuf *buf;
struct pbuf *p;
u16_t len;
if (conn == NULL) {
return NULL;
}
if (conn->recvmbox == SYS_MBOX_NULL) {
conn->err = ERR_CONN;
return NULL;
}
if (conn->err != ERR_OK) {
return NULL;
}
if (conn->type == NETCONN_TCP) {
if (conn->pcb.tcp->state == LISTEN) {
conn->err = ERR_CONN;
return NULL;
}
buf = memp_malloc(MEMP_NETBUF);
if (buf == NULL) {
conn->err = ERR_MEM;
return NULL;
}
sys_mbox_fetch(conn->recvmbox, (void *)&p);
if (p != NULL)
{
len = p->tot_len;
conn->recv_avail -= len;
}
else
len = 0;
/* Register event with callback */
if (conn->callback)
(*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len);
/* If we are closed, we indicate that we no longer wish to receive
data by setting conn->recvmbox to SYS_MBOX_NULL. */
if (p == NULL) {
memp_free(MEMP_NETBUF, buf);
sys_mbox_free(conn->recvmbox);
conn->recvmbox = SYS_MBOX_NULL;
return NULL;
}
buf->p = p;
buf->ptr = p;
buf->fromport = 0;
buf->fromaddr = NULL;
/* Let the stack know that we have taken the data. */
if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
conn->err = ERR_MEM;
return buf;
}
msg->type = API_MSG_RECV;
msg->msg.conn = conn;
if (buf != NULL) {
msg->msg.msg.len = buf->p->tot_len;
} else {
msg->msg.msg.len = 1;
}
api_msg_post(msg);
sys_mbox_fetch(conn->mbox, NULL);
memp_free(MEMP_API_MSG, msg);
} else {
sys_mbox_fetch(conn->recvmbox, (void *)&buf);
conn->recv_avail -= buf->p->tot_len;
/* Register event with callback */
if (conn->callback)
(*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len);
}
LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err));
return buf;
}
err_t
netconn_send(struct netconn *conn, struct netbuf *buf)
{
struct api_msg *msg;
if (conn == NULL) {
return ERR_VAL;
}
if (conn->err != ERR_OK) {
return conn->err;
}
if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
return (conn->err = ERR_MEM);
}
LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len));
msg->type = API_MSG_SEND;
msg->msg.conn = conn;
msg->msg.msg.p = buf->p;
api_msg_post(msg);
sys_mbox_fetch(conn->mbox, NULL);
memp_free(MEMP_API_MSG, msg);
return conn->err;
}
err_t
netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy)
{
struct api_msg *msg;
u16_t len;
if (conn == NULL) {
return ERR_VAL;
}
if (conn->err != ERR_OK) {
return conn->err;
}
if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
return (conn->err = ERR_MEM);
}
msg->type = API_MSG_WRITE;
msg->msg.conn = conn;
conn->state = NETCONN_WRITE;
while (conn->err == ERR_OK && size > 0) {
msg->msg.msg.w.dataptr = dataptr;
msg->msg.msg.w.copy = copy;
if (conn->type == NETCONN_TCP) {
if (tcp_sndbuf(conn->pcb.tcp) == 0) {
sys_sem_wait(conn->sem);
if (conn->err != ERR_OK) {
goto ret;
}
}
if (size > tcp_sndbuf(conn->pcb.tcp)) {
/* We cannot send more than one send buffer's worth of data at a
time. */
len = tcp_sndbuf(conn->pcb.tcp);
} else {
len = size;
}
} else {
len = size;
}
LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy));
msg->msg.msg.w.len = len;
api_msg_post(msg);
sys_mbox_fetch(conn->mbox, NULL);
if (conn->err == ERR_OK) {
dataptr = (void *)((u8_t *)dataptr + len);
size -= len;
} else if (conn->err == ERR_MEM) {
conn->err = ERR_OK;
sys_sem_wait(conn->sem);
} else {
goto ret;
}
}
ret:
memp_free(MEMP_API_MSG, msg);
conn->state = NETCONN_NONE;
return conn->err;
}
err_t
netconn_close(struct netconn *conn)
{
struct api_msg *msg;
if (conn == NULL) {
return ERR_VAL;
}
if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
return (conn->err = ERR_MEM);
}
conn->state = NETCONN_CLOSE;
again:
msg->type = API_MSG_CLOSE;
msg->msg.conn = conn;
api_msg_post(msg);
sys_mbox_fetch(conn->mbox, NULL);
if (conn->err == ERR_MEM &&
conn->sem != SYS_SEM_NULL) {
sys_sem_wait(conn->sem);
goto again;
}
conn->state = NETCONN_NONE;
memp_free(MEMP_API_MSG, msg);
return conn->err;
}
err_t
netconn_err(struct netconn *conn)
{
return conn->err;
}

807
20080212/Demo/Common/ethernet/lwIP/api/api_msg.c Normal file
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@ -0,0 +1,807 @@
/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#include "lwip/opt.h"
#include "lwip/arch.h"
#include "lwip/api_msg.h"
#include "lwip/memp.h"
#include "lwip/sys.h"
#include "lwip/tcpip.h"
#if LWIP_RAW
static u8_t
recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
struct ip_addr *addr)
{
struct netbuf *buf;
struct netconn *conn;
conn = arg;
if (!conn) return 0;
if (conn->recvmbox != SYS_MBOX_NULL) {
if (!(buf = memp_malloc(MEMP_NETBUF))) {
return 0;
}
pbuf_ref(p);
buf->p = p;
buf->ptr = p;
buf->fromaddr = addr;
buf->fromport = pcb->protocol;
conn->recv_avail += p->tot_len;
/* Register event with callback */
if (conn->callback)
(*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
sys_mbox_post(conn->recvmbox, buf);
}
return 0; /* do not eat the packet */
}
#endif
#if LWIP_UDP
static void
recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
struct ip_addr *addr, u16_t port)
{
struct netbuf *buf;
struct netconn *conn;
conn = arg;
if (conn == NULL) {
pbuf_free(p);
return;
}
if (conn->recvmbox != SYS_MBOX_NULL) {
buf = memp_malloc(MEMP_NETBUF);
if (buf == NULL) {
pbuf_free(p);
return;
} else {
buf->p = p;
buf->ptr = p;
buf->fromaddr = addr;
buf->fromport = port;
}
conn->recv_avail += p->tot_len;
/* Register event with callback */
if (conn->callback)
(*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
sys_mbox_post(conn->recvmbox, buf);
}
}
#endif /* LWIP_UDP */
#if LWIP_TCP
static err_t
recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
{
struct netconn *conn;
u16_t len;
conn = arg;
if (conn == NULL) {
pbuf_free(p);
return ERR_VAL;
}
if (conn->recvmbox != SYS_MBOX_NULL) {
conn->err = err;
if (p != NULL) {
len = p->tot_len;
conn->recv_avail += len;
}
else
len = 0;
/* Register event with callback */
if (conn->callback)
(*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len);
sys_mbox_post(conn->recvmbox, p);
}
return ERR_OK;
}
static err_t
poll_tcp(void *arg, struct tcp_pcb *pcb)
{
struct netconn *conn;
conn = arg;
if (conn != NULL &&
(conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) &&
conn->sem != SYS_SEM_NULL) {
sys_sem_signal(conn->sem);
}
return ERR_OK;
}
static err_t
sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
{
struct netconn *conn;
conn = arg;
if (conn != NULL && conn->sem != SYS_SEM_NULL) {
sys_sem_signal(conn->sem);
}
if (conn && conn->callback)
if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT)
(*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len);
return ERR_OK;
}
static void
err_tcp(void *arg, err_t err)
{
struct netconn *conn;
conn = arg;
conn->pcb.tcp = NULL;
conn->err = err;
if (conn->recvmbox != SYS_MBOX_NULL) {
/* Register event with callback */
if (conn->callback)
(*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
sys_mbox_post(conn->recvmbox, NULL);
}
if (conn->mbox != SYS_MBOX_NULL) {
sys_mbox_post(conn->mbox, NULL);
}
if (conn->acceptmbox != SYS_MBOX_NULL) {
/* Register event with callback */
if (conn->callback)
(*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
sys_mbox_post(conn->acceptmbox, NULL);
}
if (conn->sem != SYS_SEM_NULL) {
sys_sem_signal(conn->sem);
}
}
static void
setup_tcp(struct netconn *conn)
{
struct tcp_pcb *pcb;
pcb = conn->pcb.tcp;
tcp_arg(pcb, conn);
tcp_recv(pcb, recv_tcp);
tcp_sent(pcb, sent_tcp);
tcp_poll(pcb, poll_tcp, 4);
tcp_err(pcb, err_tcp);
}
static err_t
accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)
{
sys_mbox_t mbox;
struct netconn *newconn;
struct netconn *conn;
#if API_MSG_DEBUG
#if TCP_DEBUG
tcp_debug_print_state(newpcb->state);
#endif /* TCP_DEBUG */
#endif /* API_MSG_DEBUG */
conn = (struct netconn *)arg;
mbox = conn->acceptmbox;
newconn = memp_malloc(MEMP_NETCONN);
if (newconn == NULL) {
return ERR_MEM;
}
newconn->recvmbox = sys_mbox_new();
if (newconn->recvmbox == SYS_MBOX_NULL) {
memp_free(MEMP_NETCONN, newconn);
return ERR_MEM;
}
newconn->mbox = sys_mbox_new();
if (newconn->mbox == SYS_MBOX_NULL) {
sys_mbox_free(newconn->recvmbox);
memp_free(MEMP_NETCONN, newconn);
return ERR_MEM;
}
newconn->sem = sys_sem_new(0);
if (newconn->sem == SYS_SEM_NULL) {
sys_mbox_free(newconn->recvmbox);
sys_mbox_free(newconn->mbox);
memp_free(MEMP_NETCONN, newconn);
return ERR_MEM;
}
/* Allocations were OK, setup the PCB etc */
newconn->type = NETCONN_TCP;
newconn->pcb.tcp = newpcb;
setup_tcp(newconn);
newconn->acceptmbox = SYS_MBOX_NULL;
newconn->err = err;
/* Register event with callback */
if (conn->callback)
{
(*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
}
/* We have to set the callback here even though
* the new socket is unknown. Mark the socket as -1. */
newconn->callback = conn->callback;
newconn->socket = -1;
newconn->recv_avail = 0;
sys_mbox_post(mbox, newconn);
return ERR_OK;
}
#endif /* LWIP_TCP */
static void
do_newconn(struct api_msg_msg *msg)
{
if(msg->conn->pcb.tcp != NULL) {
/* This "new" connection already has a PCB allocated. */
/* Is this an error condition? Should it be deleted?
We currently just are happy and return. */
sys_mbox_post(msg->conn->mbox, NULL);
return;
}
msg->conn->err = ERR_OK;
/* Allocate a PCB for this connection */
switch(msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */
raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
msg->conn->pcb.udp = udp_new();
if(msg->conn->pcb.udp == NULL) {
msg->conn->err = ERR_MEM;
break;
}
udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
break;
case NETCONN_UDPNOCHKSUM:
msg->conn->pcb.udp = udp_new();
if(msg->conn->pcb.udp == NULL) {
msg->conn->err = ERR_MEM;
break;
}
udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
break;
case NETCONN_UDP:
msg->conn->pcb.udp = udp_new();
if(msg->conn->pcb.udp == NULL) {
msg->conn->err = ERR_MEM;
break;
}
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
break;
#endif /* LWIP_UDP */
#if LWIP_TCP
case NETCONN_TCP:
msg->conn->pcb.tcp = tcp_new();
if(msg->conn->pcb.tcp == NULL) {
msg->conn->err = ERR_MEM;
break;
}
setup_tcp(msg->conn);
break;
#endif
}
sys_mbox_post(msg->conn->mbox, NULL);
}
static void
do_delconn(struct api_msg_msg *msg)
{
if (msg->conn->pcb.tcp != NULL) {
switch (msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
raw_remove(msg->conn->pcb.raw);
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
msg->conn->pcb.udp->recv_arg = NULL;
udp_remove(msg->conn->pcb.udp);
break;
#endif /* LWIP_UDP */
#if LWIP_TCP
case NETCONN_TCP:
if (msg->conn->pcb.tcp->state == LISTEN) {
tcp_arg(msg->conn->pcb.tcp, NULL);
tcp_accept(msg->conn->pcb.tcp, NULL);
tcp_close(msg->conn->pcb.tcp);
} else {
tcp_arg(msg->conn->pcb.tcp, NULL);
tcp_sent(msg->conn->pcb.tcp, NULL);
tcp_recv(msg->conn->pcb.tcp, NULL);
tcp_poll(msg->conn->pcb.tcp, NULL, 0);
tcp_err(msg->conn->pcb.tcp, NULL);
if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) {
tcp_abort(msg->conn->pcb.tcp);
}
}
#endif
default:
break;
}
}
/* Trigger select() in socket layer */
if (msg->conn->callback)
{
(*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0);
(*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0);
}
if (msg->conn->mbox != SYS_MBOX_NULL) {
sys_mbox_post(msg->conn->mbox, NULL);
}
}
static void
do_bind(struct api_msg_msg *msg)
{
if (msg->conn->pcb.tcp == NULL) {
switch (msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
msg->conn->pcb.udp = udp_new();
udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
break;
case NETCONN_UDPNOCHKSUM:
msg->conn->pcb.udp = udp_new();
udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
break;
case NETCONN_UDP:
msg->conn->pcb.udp = udp_new();
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
break;
#endif /* LWIP_UDP */
#if LWIP_TCP
case NETCONN_TCP:
msg->conn->pcb.tcp = tcp_new();
setup_tcp(msg->conn);
#endif /* LWIP_TCP */
default:
break;
}
}
switch (msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr);
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
break;
#endif /* LWIP_UDP */
#if LWIP_TCP
case NETCONN_TCP:
msg->conn->err = tcp_bind(msg->conn->pcb.tcp,
msg->msg.bc.ipaddr, msg->msg.bc.port);
#endif /* LWIP_TCP */
default:
break;
}
sys_mbox_post(msg->conn->mbox, NULL);
}
#if LWIP_TCP
static err_t
do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
{
struct netconn *conn;
conn = arg;
if (conn == NULL) {
return ERR_VAL;
}
conn->err = err;
if (conn->type == NETCONN_TCP && err == ERR_OK) {
setup_tcp(conn);
}
sys_mbox_post(conn->mbox, NULL);
return ERR_OK;
}
#endif
static void
do_connect(struct api_msg_msg *msg)
{
if (msg->conn->pcb.tcp == NULL) {
switch (msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
msg->conn->pcb.udp = udp_new();
if (msg->conn->pcb.udp == NULL) {
msg->conn->err = ERR_MEM;
sys_mbox_post(msg->conn->mbox, NULL);
return;
}
udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
break;
case NETCONN_UDPNOCHKSUM:
msg->conn->pcb.udp = udp_new();
if (msg->conn->pcb.udp == NULL) {
msg->conn->err = ERR_MEM;
sys_mbox_post(msg->conn->mbox, NULL);
return;
}
udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
break;
case NETCONN_UDP:
msg->conn->pcb.udp = udp_new();
if (msg->conn->pcb.udp == NULL) {
msg->conn->err = ERR_MEM;
sys_mbox_post(msg->conn->mbox, NULL);
return;
}
udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
break;
#endif /* LWIP_UDP */
#if LWIP_TCP
case NETCONN_TCP:
msg->conn->pcb.tcp = tcp_new();
if (msg->conn->pcb.tcp == NULL) {
msg->conn->err = ERR_MEM;
sys_mbox_post(msg->conn->mbox, NULL);
return;
}
#endif
default:
break;
}
}
switch (msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
sys_mbox_post(msg->conn->mbox, NULL);
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
sys_mbox_post(msg->conn->mbox, NULL);
break;
#endif
#if LWIP_TCP
case NETCONN_TCP:
/* tcp_arg(msg->conn->pcb.tcp, msg->conn);*/
setup_tcp(msg->conn);
tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port,
do_connected);
/*tcp_output(msg->conn->pcb.tcp);*/
#endif
default:
break;
}
}
static void
do_disconnect(struct api_msg_msg *msg)
{
switch (msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
/* Do nothing as connecting is only a helper for upper lwip layers */
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
udp_disconnect(msg->conn->pcb.udp);
break;
#endif
case NETCONN_TCP:
break;
}
sys_mbox_post(msg->conn->mbox, NULL);
}
static void
do_listen(struct api_msg_msg *msg)
{
if (msg->conn->pcb.tcp != NULL) {
switch (msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n"));
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n"));
break;
#endif /* LWIP_UDP */
#if LWIP_TCP
case NETCONN_TCP:
msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp);
if (msg->conn->pcb.tcp == NULL) {
msg->conn->err = ERR_MEM;
} else {
if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
msg->conn->acceptmbox = sys_mbox_new();
if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
msg->conn->err = ERR_MEM;
break;
}
}
tcp_arg(msg->conn->pcb.tcp, msg->conn);
tcp_accept(msg->conn->pcb.tcp, accept_function);
}
#endif
default:
break;
}
}
sys_mbox_post(msg->conn->mbox, NULL);
}
static void
do_accept(struct api_msg_msg *msg)
{
if (msg->conn->pcb.tcp != NULL) {
switch (msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n"));
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n"));
break;
#endif /* LWIP_UDP */
case NETCONN_TCP:
break;
}
}
}
static void
do_send(struct api_msg_msg *msg)
{
if (msg->conn->pcb.tcp != NULL) {
switch (msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
raw_send(msg->conn->pcb.raw, msg->msg.p);
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
udp_send(msg->conn->pcb.udp, msg->msg.p);
break;
#endif /* LWIP_UDP */
case NETCONN_TCP:
break;
}
}
sys_mbox_post(msg->conn->mbox, NULL);
}
static void
do_recv(struct api_msg_msg *msg)
{
#if LWIP_TCP
if (msg->conn->pcb.tcp != NULL) {
if (msg->conn->type == NETCONN_TCP) {
tcp_recved(msg->conn->pcb.tcp, msg->msg.len);
}
}
#endif
sys_mbox_post(msg->conn->mbox, NULL);
}
static void
do_write(struct api_msg_msg *msg)
{
#if LWIP_TCP
err_t err;
#endif
if (msg->conn->pcb.tcp != NULL) {
switch (msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
msg->conn->err = ERR_VAL;
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
msg->conn->err = ERR_VAL;
break;
#endif /* LWIP_UDP */
#if LWIP_TCP
case NETCONN_TCP:
err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr,
msg->msg.w.len, msg->msg.w.copy);
/* This is the Nagle algorithm: inhibit the sending of new TCP
segments when new outgoing data arrives from the user if any
previously transmitted data on the connection remains
unacknowledged. */
if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL ||
(msg->conn->pcb.tcp->flags & TF_NODELAY) ||
(msg->conn->pcb.tcp->snd_queuelen) > 1)) {
tcp_output(msg->conn->pcb.tcp);
}
msg->conn->err = err;
if (msg->conn->callback)
if (err == ERR_OK)
{
if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT)
(*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len);
}
#endif
default:
break;
}
}
sys_mbox_post(msg->conn->mbox, NULL);
}
static void
do_close(struct api_msg_msg *msg)
{
err_t err;
err = ERR_OK;
if (msg->conn->pcb.tcp != NULL) {
switch (msg->conn->type) {
#if LWIP_RAW
case NETCONN_RAW:
break;
#endif
#if LWIP_UDP
case NETCONN_UDPLITE:
/* FALLTHROUGH */
case NETCONN_UDPNOCHKSUM:
/* FALLTHROUGH */
case NETCONN_UDP:
break;
#endif /* LWIP_UDP */
#if LWIP_TCP
case NETCONN_TCP:
if (msg->conn->pcb.tcp->state == LISTEN) {
err = tcp_close(msg->conn->pcb.tcp);
}
else if (msg->conn->pcb.tcp->state == CLOSE_WAIT) {
err = tcp_output(msg->conn->pcb.tcp);
}
msg->conn->err = err;
#endif
default:
break;
}
}
sys_mbox_post(msg->conn->mbox, NULL);
}
typedef void (* api_msg_decode)(struct api_msg_msg *msg);
static api_msg_decode decode[API_MSG_MAX] = {
do_newconn,
do_delconn,
do_bind,
do_connect,
do_disconnect,
do_listen,
do_accept,
do_send,
do_recv,
do_write,
do_close
};
void
api_msg_input(struct api_msg *msg)
{
decode[msg->type](&(msg->msg));
}
void
api_msg_post(struct api_msg *msg)
{
tcpip_apimsg(msg);
}

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/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#include "lwip/err.h"
#ifdef LWIP_DEBUG
static char *err_strerr[] = {"Ok.",
"Out of memory error.",
"Buffer error.",
"Connection aborted.",
"Connection reset.",
"Connection closed.",
"Not connected.",
"Illegal value.",
"Illegal argument.",
"Routing problem.",
"Address in use."
};
char *
lwip_strerr(err_t err)
{
return err_strerr[-err];
}
#endif /* LWIP_DEBUG */

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/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#include "lwip/opt.h"
#include "lwip/sys.h"
#include "lwip/memp.h"
#include "lwip/pbuf.h"
#include "lwip/ip.h"
#include "lwip/ip_frag.h"
#include "lwip/udp.h"
#include "lwip/tcp.h"
#include "lwip/tcpip.h"
static void (* tcpip_init_done)(void *arg) = NULL;
static void *tcpip_init_done_arg;
static sys_mbox_t mbox;
#if LWIP_TCP
static int tcpip_tcp_timer_active = 0;
static void
tcpip_tcp_timer(void *arg)
{
(void)arg;
/* call TCP timer handler */
tcp_tmr();
/* timer still needed? */
if (tcp_active_pcbs || tcp_tw_pcbs) {
/* restart timer */
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
} else {
/* disable timer */
tcpip_tcp_timer_active = 0;
}
}
#if !NO_SYS
void
tcp_timer_needed(void)
{
/* timer is off but needed again? */
if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
/* enable and start timer */
tcpip_tcp_timer_active = 1;
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
}
}
#endif /* !NO_SYS */
#endif /* LWIP_TCP */
#if IP_REASSEMBLY
static void
ip_timer(void *data)
{
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n"));
ip_reass_tmr();
sys_timeout(1000, ip_timer, NULL);
}
#endif
static void
tcpip_thread(void *arg)
{
struct tcpip_msg *msg;
(void)arg;
ip_init();
#if LWIP_UDP
udp_init();
#endif
#if LWIP_TCP
tcp_init();
#endif
#if IP_REASSEMBLY
sys_timeout(1000, ip_timer, NULL);
#endif
if (tcpip_init_done != NULL) {
tcpip_init_done(tcpip_init_done_arg);
}
while (1) { /* MAIN Loop */
sys_mbox_fetch(mbox, (void *)&msg);
switch (msg->type) {
case TCPIP_MSG_API:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
api_msg_input(msg->msg.apimsg);
break;
case TCPIP_MSG_INPUT:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg));
ip_input(msg->msg.inp.p, msg->msg.inp.netif);
break;
case TCPIP_MSG_CALLBACK:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
msg->msg.cb.f(msg->msg.cb.ctx);
break;
default:
break;
}
memp_free(MEMP_TCPIP_MSG, msg);
}
}
err_t
tcpip_input(struct pbuf *p, struct netif *inp)
{
struct tcpip_msg *msg;
msg = memp_malloc(MEMP_TCPIP_MSG);
if (msg == NULL) {
pbuf_free(p);
return ERR_MEM;
}
msg->type = TCPIP_MSG_INPUT;
msg->msg.inp.p = p;
msg->msg.inp.netif = inp;
sys_mbox_post(mbox, msg);
return ERR_OK;
}
err_t
tcpip_callback(void (*f)(void *ctx), void *ctx)
{
struct tcpip_msg *msg;
msg = memp_malloc(MEMP_TCPIP_MSG);
if (msg == NULL) {
return ERR_MEM;
}
msg->type = TCPIP_MSG_CALLBACK;
msg->msg.cb.f = f;
msg->msg.cb.ctx = ctx;
sys_mbox_post(mbox, msg);
return ERR_OK;
}
void
tcpip_apimsg(struct api_msg *apimsg)
{
struct tcpip_msg *msg;
msg = memp_malloc(MEMP_TCPIP_MSG);
if (msg == NULL) {
memp_free(MEMP_API_MSG, apimsg);
return;
}
msg->type = TCPIP_MSG_API;
msg->msg.apimsg = apimsg;
sys_mbox_post(mbox, msg);
}
void
tcpip_init(void (* initfunc)(void *), void *arg)
{
tcpip_init_done = initfunc;
tcpip_init_done_arg = arg;
mbox = sys_mbox_new();
sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO);
}

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/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
/* inet.c
*
* Functions common to all TCP/IP modules, such as the Internet checksum and the
* byte order functions.
*
*/
#include "lwip/opt.h"
#include "lwip/arch.h"
#include "lwip/def.h"
#include "lwip/inet.h"
#include "lwip/sys.h"
/* These are some reference implementations of the checksum algorithm, with the
* aim of being simple, correct and fully portable. Checksumming is the
* first thing you would want to optimize for your platform. If you create
* your own version, link it in and in your sys_arch.h put:
*
* #define LWIP_CHKSUM <your_checksum_routine>
*/
#ifndef LWIP_CHKSUM
#define LWIP_CHKSUM lwip_standard_chksum
#if 1 /* Version A */
/**
* lwip checksum
*
* @param dataptr points to start of data to be summed at any boundary
* @param len length of data to be summed
* @return host order (!) lwip checksum (non-inverted Internet sum)
*
* @note accumulator size limits summable length to 64k
* @note host endianess is irrelevant (p3 RFC1071)
*/
static u16_t
lwip_standard_chksum(void *dataptr, u16_t len)
{
u32_t acc;
u16_t src;
u8_t *octetptr;
acc = 0;
/* dataptr may be at odd or even addresses */
octetptr = (u8_t*)dataptr;
while (len > 1)
{
/* declare first octet as most significant
thus assume network order, ignoring host order */
src = (*octetptr) << 8;
octetptr++;
/* declare second octet as least significant */
src |= (*octetptr);
octetptr++;
acc += src;
len -= 2;
}
if (len > 0)
{
/* accumulate remaining octet */
src = (*octetptr) << 8;
acc += src;
}
/* add deferred carry bits */
acc = (acc >> 16) + (acc & 0x0000ffffUL);
if ((acc & 0xffff0000) != 0) {
acc = (acc >> 16) + (acc & 0x0000ffffUL);
}
/* This maybe a little confusing: reorder sum using htons()
instead of ntohs() since it has a little less call overhead.
The caller must invert bits for Internet sum ! */
return htons((u16_t)acc);
}
#endif
#if 0 /* Version B */
/*
* Curt McDowell
* Broadcom Corp.
* csm@broadcom.com
*
* IP checksum two bytes at a time with support for
* unaligned buffer.
* Works for len up to and including 0x20000.
* by Curt McDowell, Broadcom Corp. 12/08/2005
*/
static u16_t
lwip_standard_chksum(void *dataptr, int len)
{
u8_t *pb = dataptr;
u16_t *ps, t = 0;
u32_t sum = 0;
int odd = ((u32_t)pb & 1);
/* Get aligned to u16_t */
if (odd && len > 0) {
((u8_t *)&t)[1] = *pb++;
len--;
}
/* Add the bulk of the data */
ps = (u16_t *)pb;
while (len > 1) {
sum += *ps++;
len -= 2;
}
/* Consume left-over byte, if any */
if (len > 0)
((u8_t *)&t)[0] = *(u8_t *)ps;;
/* Add end bytes */
sum += t;
/* Fold 32-bit sum to 16 bits */
while (sum >> 16)
sum = (sum & 0xffff) + (sum >> 16);
/* Swap if alignment was odd */
if (odd)
sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
return sum;
}
#endif
#if 0 /* Version C */
/**
* An optimized checksum routine. Basically, it uses loop-unrolling on
* the checksum loop, treating the head and tail bytes specially, whereas
* the inner loop acts on 8 bytes at a time.
*
* @arg start of buffer to be checksummed. May be an odd byte address.
* @len number of bytes in the buffer to be checksummed.
*
* by Curt McDowell, Broadcom Corp. December 8th, 2005
*/
static u16_t
lwip_standard_chksum(void *dataptr, int len)
{
u8_t *pb = dataptr;
u16_t *ps, t = 0;
u32_t *pl;
u32_t sum = 0, tmp;
/* starts at odd byte address? */
int odd = ((u32_t)pb & 1);
if (odd && len > 0) {
((u8_t *)&t)[1] = *pb++;
len--;
}
ps = (u16_t *)pb;
if (((u32_t)ps & 3) && len > 1) {
sum += *ps++;
len -= 2;
}
pl = (u32_t *)ps;
while (len > 7) {
tmp = sum + *pl++; /* ping */
if (tmp < sum)
tmp++; /* add back carry */
sum = tmp + *pl++; /* pong */
if (sum < tmp)
sum++; /* add back carry */
len -= 8;
}
/* make room in upper bits */
sum = (sum >> 16) + (sum & 0xffff);
ps = (u16_t *)pl;
/* 16-bit aligned word remaining? */
while (len > 1) {
sum += *ps++;
len -= 2;
}
/* dangling tail byte remaining? */
if (len > 0) /* include odd byte */
((u8_t *)&t)[0] = *(u8_t *)ps;
sum += t; /* add end bytes */
while (sum >> 16) /* combine halves */
sum = (sum >> 16) + (sum & 0xffff);
if (odd)
sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
return sum;
}
#endif
#endif /* LWIP_CHKSUM */
/* inet_chksum_pseudo:
*
* Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
*/
u16_t
inet_chksum_pseudo(struct pbuf *p,
struct ip_addr *src, struct ip_addr *dest,
u8_t proto, u16_t proto_len)
{
u32_t acc;
struct pbuf *q;
u8_t swapped;
acc = 0;
swapped = 0;
/* iterate through all pbuf in chain */
for(q = p; q != NULL; q = q->next) {
LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
(void *)q, (void *)q->next));
acc += LWIP_CHKSUM(q->payload, q->len);
/*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
while (acc >> 16) {
acc = (acc & 0xffffUL) + (acc >> 16);
}
if (q->len % 2 != 0) {
swapped = 1 - swapped;
acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
}
/*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
}
if (swapped) {
acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
}
acc += (src->addr & 0xffffUL);
acc += ((src->addr >> 16) & 0xffffUL);
acc += (dest->addr & 0xffffUL);
acc += ((dest->addr >> 16) & 0xffffUL);
acc += (u32_t)htons((u16_t)proto);
acc += (u32_t)htons(proto_len);
while (acc >> 16) {
acc = (acc & 0xffffUL) + (acc >> 16);
}
LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
return (u16_t)~(acc & 0xffffUL);
}
/* inet_chksum:
*
* Calculates the Internet checksum over a portion of memory. Used primarily for IP
* and ICMP.
*/
u16_t
inet_chksum(void *dataptr, u16_t len)
{
u32_t acc;
acc = LWIP_CHKSUM(dataptr, len);
while (acc >> 16) {
acc = (acc & 0xffff) + (acc >> 16);
}
return (u16_t)~(acc & 0xffff);
}
u16_t
inet_chksum_pbuf(struct pbuf *p)
{
u32_t acc;
struct pbuf *q;
u8_t swapped;
acc = 0;
swapped = 0;
for(q = p; q != NULL; q = q->next) {
acc += LWIP_CHKSUM(q->payload, q->len);
while (acc >> 16) {
acc = (acc & 0xffffUL) + (acc >> 16);
}
if (q->len % 2 != 0) {
swapped = 1 - swapped;
acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8);
}
}
if (swapped) {
acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8);
}
return (u16_t)~(acc & 0xffffUL);
}
/* Here for now until needed in other places in lwIP */
#ifndef isprint
#define in_range(c, lo, up) ((u8_t)c >= lo && (u8_t)c <= up)
#define isprint(c) in_range(c, 0x20, 0x7f)
#define isdigit(c) in_range(c, '0', '9')
#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
#define islower(c) in_range(c, 'a', 'z')
#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
#endif
/*
* Ascii internet address interpretation routine.
* The value returned is in network order.
*/
u32_t
inet_addr(const char *cp)
{
struct in_addr val;
if (inet_aton(cp, &val)) {
return (val.s_addr);
}
return (INADDR_NONE);
}
/*
* Check whether "cp" is a valid ascii representation
* of an Internet address and convert to a binary address.
* Returns 1 if the address is valid, 0 if not.
* This replaces inet_addr, the return value from which
* cannot distinguish between failure and a local broadcast address.
*/
int
inet_aton(const char *cp, struct in_addr *addr)
{
u32_t val;
int base, n, c;
u32_t parts[4];
u32_t *pp = parts;
c = *cp;
for (;;) {
/*
* Collect number up to ``.''.
* Values are specified as for C:
* 0x=hex, 0=octal, 1-9=decimal.
*/
if (!isdigit(c))
return (0);
val = 0;
base = 10;
if (c == '0') {
c = *++cp;
if (c == 'x' || c == 'X') {
base = 16;
c = *++cp;
} else
base = 8;
}
for (;;) {
if (isdigit(c)) {
val = (val * base) + (int)(c - '0');
c = *++cp;
} else if (base == 16 && isxdigit(c)) {
val = (val << 4) | (int)(c + 10 - (islower(c) ? 'a' : 'A'));
c = *++cp;
} else
break;
}
if (c == '.') {
/*
* Internet format:
* a.b.c.d
* a.b.c (with c treated as 16 bits)
* a.b (with b treated as 24 bits)
*/
if (pp >= parts + 3)
return (0);
*pp++ = val;
c = *++cp;
} else
break;
}
/*
* Check for trailing characters.
*/
if (c != '\0' && (!isprint(c) || !isspace(c)))
return (0);
/*
* Concoct the address according to
* the number of parts specified.
*/
n = pp - parts + 1;
switch (n) {
case 0:
return (0); /* initial nondigit */
case 1: /* a -- 32 bits */
break;
case 2: /* a.b -- 8.24 bits */
if (val > 0xffffff)
return (0);
val |= parts[0] << 24;
break;
case 3: /* a.b.c -- 8.8.16 bits */
if (val > 0xffff)
return (0);
val |= (parts[0] << 24) | (parts[1] << 16);
break;
case 4: /* a.b.c.d -- 8.8.8.8 bits */
if (val > 0xff)
return (0);
val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
break;
}
if (addr)
addr->s_addr = htonl(val);
return (1);
}
/* Convert numeric IP address into decimal dotted ASCII representation.
* returns ptr to static buffer; not reentrant!
*/
char *
inet_ntoa(struct in_addr addr)
{
static char str[16];
u32_t s_addr = addr.s_addr;
char inv[3];
char *rp;
u8_t *ap;
u8_t rem;
u8_t n;
u8_t i;
rp = str;
ap = (u8_t *)&s_addr;
for(n = 0; n < 4; n++) {
i = 0;
do {
rem = *ap % (u8_t)10;
*ap /= (u8_t)10;
inv[i++] = '0' + rem;
} while(*ap);
while(i--)
*rp++ = inv[i];
*rp++ = '.';
ap++;
}
*--rp = 0;
return str;
}
/*
* These are reference implementations of the byte swapping functions.
* Again with the aim of being simple, correct and fully portable.
* Byte swapping is the second thing you would want to optimize. You will
* need to port it to your architecture and in your cc.h:
*
* #define LWIP_PLATFORM_BYTESWAP 1
* #define LWIP_PLATFORM_HTONS(x) <your_htons>
* #define LWIP_PLATFORM_HTONL(x) <your_htonl>
*
* Note ntohs() and ntohl() are merely references to the htonx counterparts.
*/
#ifndef BYTE_ORDER
#error BYTE_ORDER is not defined
#endif
#if (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN)
u16_t
htons(u16_t n)
{
return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
}
u16_t
ntohs(u16_t n)
{
return htons(n);
}
u32_t
htonl(u32_t n)
{
return ((n & 0xff) << 24) |
((n & 0xff00) << 8) |
((n & 0xff0000) >> 8) |
((n & 0xff000000) >> 24);
}
u32_t
ntohl(u32_t n)
{
return htonl(n);
}
#endif /* (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) */

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/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
/* inet6.c
*
* Functions common to all TCP/IP modules, such as the Internet checksum and the
* byte order functions.
*
*/
#include "lwip/opt.h"
#include "lwip/def.h"
#include "lwip/inet.h"
/* chksum:
*
* Sums up all 16 bit words in a memory portion. Also includes any odd byte.
* This function is used by the other checksum functions.
*
* For now, this is not optimized. Must be optimized for the particular processor
* arcitecture on which it is to run. Preferebly coded in assembler.
*/
static u32_t
chksum(void *dataptr, u16_t len)
{
u16_t *sdataptr = dataptr;
u32_t acc;
for(acc = 0; len > 1; len -= 2) {
acc += *sdataptr++;
}
/* add up any odd byte */
if (len == 1) {
acc += htons((u16_t)(*(u8_t *)dataptr) << 8);
}
return acc;
}
/* inet_chksum_pseudo:
*
* Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
*/
u16_t
inet_chksum_pseudo(struct pbuf *p,
struct ip_addr *src, struct ip_addr *dest,
u8_t proto, u32_t proto_len)
{
u32_t acc;
struct pbuf *q;
u8_t swapped, i;
acc = 0;
swapped = 0;
for(q = p; q != NULL; q = q->next) {
acc += chksum(q->payload, q->len);
while (acc >> 16) {
acc = (acc & 0xffff) + (acc >> 16);
}
if (q->len % 2 != 0) {
swapped = 1 - swapped;
acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
}
}
if (swapped) {
acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
}
for(i = 0; i < 8; i++) {
acc += ((u16_t *)src->addr)[i] & 0xffff;
acc += ((u16_t *)dest->addr)[i] & 0xffff;
while (acc >> 16) {
acc = (acc & 0xffff) + (acc >> 16);
}
}
acc += (u16_t)htons((u16_t)proto);
acc += ((u16_t *)&proto_len)[0] & 0xffff;
acc += ((u16_t *)&proto_len)[1] & 0xffff;
while (acc >> 16) {
acc = (acc & 0xffff) + (acc >> 16);
}
return ~(acc & 0xffff);
}
/* inet_chksum:
*
* Calculates the Internet checksum over a portion of memory. Used primarely for IP
* and ICMP.
*/
u16_t
inet_chksum(void *dataptr, u16_t len)
{
u32_t acc, sum;
acc = chksum(dataptr, len);
sum = (acc & 0xffff) + (acc >> 16);
sum += (sum >> 16);
return ~(sum & 0xffff);
}
u16_t
inet_chksum_pbuf(struct pbuf *p)
{
u32_t acc;
struct pbuf *q;
u8_t swapped;
acc = 0;
swapped = 0;
for(q = p; q != NULL; q = q->next) {
acc += chksum(q->payload, q->len);
while (acc >> 16) {
acc = (acc & 0xffff) + (acc >> 16);
}
if (q->len % 2 != 0) {
swapped = 1 - swapped;
acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8);
}
}
if (swapped) {
acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
}
return ~(acc & 0xffff);
}

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/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
/* Some ICMP messages should be passed to the transport protocols. This
is not implemented. */
#include <string.h>
#include "lwip/opt.h"
#include "lwip/icmp.h"
#include "lwip/inet.h"
#include "lwip/ip.h"
#include "lwip/def.h"
#include "lwip/stats.h"
#include "lwip/snmp.h"
void
icmp_input(struct pbuf *p, struct netif *inp)
{
u8_t type;
u8_t code;
struct icmp_echo_hdr *iecho;
struct ip_hdr *iphdr;
struct ip_addr tmpaddr;
u16_t hlen;
ICMP_STATS_INC(icmp.recv);
snmp_inc_icmpinmsgs();
iphdr = p->payload;
hlen = IPH_HL(iphdr) * 4;
if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) {
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
pbuf_free(p);
ICMP_STATS_INC(icmp.lenerr);
snmp_inc_icmpinerrors();
return;
}
type = *((u8_t *)p->payload);
code = *(((u8_t *)p->payload)+1);
switch (type) {
case ICMP_ECHO:
/* broadcast or multicast destination address? */
if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) {
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n"));
ICMP_STATS_INC(icmp.err);
pbuf_free(p);
return;
}
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
pbuf_free(p);
ICMP_STATS_INC(icmp.lenerr);
snmp_inc_icmpinerrors();
return;
}
iecho = p->payload;
if (inet_chksum_pbuf(p) != 0) {
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
pbuf_free(p);
ICMP_STATS_INC(icmp.chkerr);
snmp_inc_icmpinerrors();
return;
}
tmpaddr.addr = iphdr->src.addr;
iphdr->src.addr = iphdr->dest.addr;
iphdr->dest.addr = tmpaddr.addr;
ICMPH_TYPE_SET(iecho, ICMP_ER);
/* adjust the checksum */
if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) {
iecho->chksum += htons(ICMP_ECHO << 8) + 1;
} else {
iecho->chksum += htons(ICMP_ECHO << 8);
}
ICMP_STATS_INC(icmp.xmit);
/* increase number of messages attempted to send */
snmp_inc_icmpoutmsgs();
/* increase number of echo replies attempted to send */
snmp_inc_icmpoutechoreps();
pbuf_header(p, hlen);
ip_output_if(p, &(iphdr->src), IP_HDRINCL,
IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp);
break;
default:
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", (s16_t)type, (s16_t)code));
ICMP_STATS_INC(icmp.proterr);
ICMP_STATS_INC(icmp.drop);
}
pbuf_free(p);
}
void
icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
{
struct pbuf *q;
struct ip_hdr *iphdr;
struct icmp_dur_hdr *idur;
q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
/* ICMP header + IP header + 8 bytes of data */
iphdr = p->payload;
idur = q->payload;
ICMPH_TYPE_SET(idur, ICMP_DUR);
ICMPH_CODE_SET(idur, t);
memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8);
/* calculate checksum */
idur->chksum = 0;
idur->chksum = inet_chksum(idur, q->len);
ICMP_STATS_INC(icmp.xmit);
/* increase number of messages attempted to send */
snmp_inc_icmpoutmsgs();
/* increase number of destination unreachable messages attempted to send */
snmp_inc_icmpoutdestunreachs();
ip_output(q, NULL, &(iphdr->src),
ICMP_TTL, 0, IP_PROTO_ICMP);
pbuf_free(q);
}
#if IP_FORWARD
void
icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
{
struct pbuf *q;
struct ip_hdr *iphdr;
struct icmp_te_hdr *tehdr;
q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
iphdr = p->payload;
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src));
LWIP_DEBUGF(ICMP_DEBUG, (" to "));
ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest));
LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
tehdr = q->payload;
ICMPH_TYPE_SET(tehdr, ICMP_TE);
ICMPH_CODE_SET(tehdr, t);
/* copy fields from original packet */
memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8);
/* calculate checksum */
tehdr->chksum = 0;
tehdr->chksum = inet_chksum(tehdr, q->len);
ICMP_STATS_INC(icmp.xmit);
/* increase number of messages attempted to send */
snmp_inc_icmpoutmsgs();
/* increase number of destination unreachable messages attempted to send */
snmp_inc_icmpouttimeexcds();
ip_output(q, NULL, &(iphdr->src),
ICMP_TTL, 0, IP_PROTO_ICMP);
pbuf_free(q);
}
#endif /* IP_FORWARD */

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/* @file
*
* This is the IP layer implementation for incoming and outgoing IP traffic.
*
* @see ip_frag.c
*
*/
/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#include "lwip/opt.h"
#include "lwip/def.h"
#include "lwip/mem.h"
#include "lwip/ip.h"
#include "lwip/ip_frag.h"
#include "lwip/inet.h"
#include "lwip/netif.h"
#include "lwip/icmp.h"
#include "lwip/raw.h"
#include "lwip/udp.h"
#include "lwip/tcp.h"
#include "lwip/stats.h"
#include "arch/perf.h"
#include "lwip/snmp.h"
#if LWIP_DHCP
# include "lwip/dhcp.h"
#endif /* LWIP_DHCP */
/**
* Initializes the IP layer.
*/
void
ip_init(void)
{
#if IP_FRAG
ip_frag_init();
#endif
}
/**
* Finds the appropriate network interface for a given IP address. It
* searches the list of network interfaces linearly. A match is found
* if the masked IP address of the network interface equals the masked
* IP address given to the function.
*/
struct netif *
ip_route(struct ip_addr *dest)
{
struct netif *netif;
/* iterate through netifs */
for(netif = netif_list; netif != NULL; netif = netif->next) {
/* network mask matches? */
if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
/* return netif on which to forward IP packet */
return netif;
}
}
/* no matching netif found, use default netif */
return netif_default;
}
#if IP_FORWARD
/**
* Forwards an IP packet. It finds an appropriate route for the
* packet, decrements the TTL value of the packet, adjusts the
* checksum and outputs the packet on the appropriate interface.
*/
static struct netif *
ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
{
struct netif *netif;
PERF_START;
/* Find network interface where to forward this IP packet to. */
netif = ip_route((struct ip_addr *)&(iphdr->dest));
if (netif == NULL) {
LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n",
iphdr->dest.addr));
snmp_inc_ipoutnoroutes();
return (struct netif *)NULL;
}
/* Do not forward packets onto the same network interface on which
* they arrived. */
if (netif == inp) {
LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n"));
snmp_inc_ipoutnoroutes();
return (struct netif *)NULL;
}
/* decrement TTL */
IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
/* send ICMP if TTL == 0 */
if (IPH_TTL(iphdr) == 0) {
snmp_inc_ipinhdrerrors();
/* Don't send ICMP messages in response to ICMP messages */
if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
icmp_time_exceeded(p, ICMP_TE_TTL);
}
return (struct netif *)NULL;
}
/* Incrementally update the IP checksum. */
if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) {
IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1);
} else {
IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100));
}
LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n",
iphdr->dest.addr));
IP_STATS_INC(ip.fw);
IP_STATS_INC(ip.xmit);
snmp_inc_ipforwdatagrams();
PERF_STOP("ip_forward");
/* transmit pbuf on chosen interface */
netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
return netif;
}
#endif /* IP_FORWARD */
/**
* This function is called by the network interface device driver when
* an IP packet is received. The function does the basic checks of the
* IP header such as packet size being at least larger than the header
* size etc. If the packet was not destined for us, the packet is
* forwarded (using ip_forward). The IP checksum is always checked.
*
* Finally, the packet is sent to the upper layer protocol input function.
*
*
*
*/
err_t
ip_input(struct pbuf *p, struct netif *inp) {
struct ip_hdr *iphdr;
struct netif *netif;
u16_t iphdrlen;
IP_STATS_INC(ip.recv);
snmp_inc_ipinreceives();
/* identify the IP header */
iphdr = p->payload;
if (IPH_V(iphdr) != 4) {
LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr)));
ip_debug_print(p);
pbuf_free(p);
IP_STATS_INC(ip.err);
IP_STATS_INC(ip.drop);
snmp_inc_ipinhdrerrors();
return ERR_OK;
}
/* obtain IP header length in number of 32-bit words */
iphdrlen = IPH_HL(iphdr);
/* calculate IP header length in bytes */
iphdrlen *= 4;
/* header length exceeds first pbuf length? */
if (iphdrlen > p->len) {
LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet droppped.\n",
iphdrlen, p->len));
/* free (drop) packet pbufs */
pbuf_free(p);
IP_STATS_INC(ip.lenerr);
IP_STATS_INC(ip.drop);
snmp_inc_ipindiscards();
return ERR_OK;
}
/* verify checksum */
#if CHECKSUM_CHECK_IP
if (inet_chksum(iphdr, iphdrlen) != 0) {
LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen)));
ip_debug_print(p);
pbuf_free(p);
IP_STATS_INC(ip.chkerr);
IP_STATS_INC(ip.drop);
snmp_inc_ipinhdrerrors();
return ERR_OK;
}
#endif
/* Trim pbuf. This should have been done at the netif layer,
* but we'll do it anyway just to be sure that its done. */
pbuf_realloc(p, ntohs(IPH_LEN(iphdr)));
/* match packet against an interface, i.e. is this packet for us? */
for (netif = netif_list; netif != NULL; netif = netif->next) {
LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n",
iphdr->dest.addr, netif->ip_addr.addr,
iphdr->dest.addr & netif->netmask.addr,
netif->ip_addr.addr & netif->netmask.addr,
iphdr->dest.addr & ~(netif->netmask.addr)));
/* interface is up and configured? */
if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr))))
{
/* unicast to this interface address? */
if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) ||
/* or broadcast on this interface network address? */
ip_addr_isbroadcast(&(iphdr->dest), netif)) {
LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n",
netif->name[0], netif->name[1]));
/* break out of for loop */
break;
}
}
}
#if LWIP_DHCP
/* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
* using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
* According to RFC 1542 section 3.1.1, referred by RFC 2131).
*/
if (netif == NULL) {
/* remote port is DHCP server? */
if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %"U16_F"\n",
ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest)));
if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) {
LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n"));
netif = inp;
}
}
}
#endif /* LWIP_DHCP */
/* packet not for us? */
if (netif == NULL) {
/* packet not for us, route or discard */
LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n"));
#if IP_FORWARD
/* non-broadcast packet? */
if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) {
/* try to forward IP packet on (other) interfaces */
ip_forward(p, iphdr, inp);
}
else
#endif /* IP_FORWARD */
{
snmp_inc_ipinaddrerrors();
snmp_inc_ipindiscards();
}
pbuf_free(p);
return ERR_OK;
}
/* packet consists of multiple fragments? */
if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) {
#if IP_REASSEMBLY /* packet fragment reassembly code present? */
LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n",
ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8));
/* reassemble the packet*/
p = ip_reass(p);
/* packet not fully reassembled yet? */
if (p == NULL) {
return ERR_OK;
}
iphdr = p->payload;
#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
pbuf_free(p);
LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n",
ntohs(IPH_OFFSET(iphdr))));
IP_STATS_INC(ip.opterr);
IP_STATS_INC(ip.drop);
/* unsupported protocol feature */
snmp_inc_ipinunknownprotos();
return ERR_OK;
#endif /* IP_REASSEMBLY */
}
#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */
if (iphdrlen > IP_HLEN) {
LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n"));
pbuf_free(p);
IP_STATS_INC(ip.opterr);
IP_STATS_INC(ip.drop);
/* unsupported protocol feature */
snmp_inc_ipinunknownprotos();
return ERR_OK;
}
#endif /* IP_OPTIONS == 0 */
/* send to upper layers */
LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n"));
ip_debug_print(p);
LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
#if LWIP_RAW
/* raw input did not eat the packet? */
if (raw_input(p, inp) == 0) {
#endif /* LWIP_RAW */
switch (IPH_PROTO(iphdr)) {
#if LWIP_UDP
case IP_PROTO_UDP:
case IP_PROTO_UDPLITE:
snmp_inc_ipindelivers();
udp_input(p, inp);
break;
#endif /* LWIP_UDP */
#if LWIP_TCP
case IP_PROTO_TCP:
snmp_inc_ipindelivers();
tcp_input(p, inp);
break;
#endif /* LWIP_TCP */
case IP_PROTO_ICMP:
snmp_inc_ipindelivers();
icmp_input(p, inp);
break;
default:
/* send ICMP destination protocol unreachable unless is was a broadcast */
if (!ip_addr_isbroadcast(&(iphdr->dest), inp) &&
!ip_addr_ismulticast(&(iphdr->dest))) {
p->payload = iphdr;
icmp_dest_unreach(p, ICMP_DUR_PROTO);
}
pbuf_free(p);
LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr)));
IP_STATS_INC(ip.proterr);
IP_STATS_INC(ip.drop);
snmp_inc_ipinunknownprotos();
}
#if LWIP_RAW
} /* LWIP_RAW */
#endif
return ERR_OK;
}
/**
* Sends an IP packet on a network interface. This function constructs
* the IP header and calculates the IP header checksum. If the source
* IP address is NULL, the IP address of the outgoing network
* interface is filled in as source address.
*
* @note ip_id: RFC791 "some host may be able to simply use
* unique identifiers independent of destination"
*/
err_t
ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
u8_t ttl, u8_t tos,
u8_t proto, struct netif *netif)
{
struct ip_hdr *iphdr;
static u16_t ip_id = 0;
snmp_inc_ipoutrequests();
if (dest != IP_HDRINCL) {
if (pbuf_header(p, IP_HLEN)) {
LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n"));
IP_STATS_INC(ip.err);
snmp_inc_ipoutdiscards();
return ERR_BUF;
}
iphdr = p->payload;
IPH_TTL_SET(iphdr, ttl);
IPH_PROTO_SET(iphdr, proto);
ip_addr_set(&(iphdr->dest), dest);
IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos);
IPH_LEN_SET(iphdr, htons(p->tot_len));
IPH_OFFSET_SET(iphdr, htons(IP_DF));
IPH_ID_SET(iphdr, htons(ip_id));
++ip_id;
if (ip_addr_isany(src)) {
ip_addr_set(&(iphdr->src), &(netif->ip_addr));
} else {
ip_addr_set(&(iphdr->src), src);
}
IPH_CHKSUM_SET(iphdr, 0);
#if CHECKSUM_GEN_IP
IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
#endif
} else {
iphdr = p->payload;
dest = &(iphdr->dest);
}
#if IP_FRAG
/* don't fragment if interface has mtu set to 0 [loopif] */
if (netif->mtu && (p->tot_len > netif->mtu))
return ip_frag(p,netif,dest);
#endif
IP_STATS_INC(ip.xmit);
LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num));
ip_debug_print(p);
LWIP_DEBUGF(IP_DEBUG, ("netif->output()"));
return netif->output(netif, p, dest);
}
/**
* Simple interface to ip_output_if. It finds the outgoing network
* interface and calls upon ip_output_if to do the actual work.
*/
err_t
ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
u8_t ttl, u8_t tos, u8_t proto)
{
struct netif *netif;
if ((netif = ip_route(dest)) == NULL) {
LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
IP_STATS_INC(ip.rterr);
snmp_inc_ipoutnoroutes();
return ERR_RTE;
}
return ip_output_if(p, src, dest, ttl, tos, proto, netif);
}
#if IP_DEBUG
void
ip_debug_print(struct pbuf *p)
{
struct ip_hdr *iphdr = p->payload;
u8_t *payload;
payload = (u8_t *)iphdr + IP_HLEN;
LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" | 0x%02"X16_F" | %5"U16_F" | (v, hl, tos, len)\n",
IPH_V(iphdr),
IPH_HL(iphdr),
IPH_TOS(iphdr),
ntohs(IPH_LEN(iphdr))));
LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" |%"U16_F"%"U16_F"%"U16_F"| %4"U16_F" | (id, flags, offset)\n",
ntohs(IPH_ID(iphdr)),
ntohs(IPH_OFFSET(iphdr)) >> 15 & 1,
ntohs(IPH_OFFSET(iphdr)) >> 14 & 1,
ntohs(IPH_OFFSET(iphdr)) >> 13 & 1,
ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK));
LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | 0x%04"X16_F" | (ttl, proto, chksum)\n",
IPH_TTL(iphdr),
IPH_PROTO(iphdr),
ntohs(IPH_CHKSUM(iphdr))));
LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (src)\n",
ip4_addr1(&iphdr->src),
ip4_addr2(&iphdr->src),
ip4_addr3(&iphdr->src),
ip4_addr4(&iphdr->src)));
LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (dest)\n",
ip4_addr1(&iphdr->dest),
ip4_addr2(&iphdr->dest),
ip4_addr3(&iphdr->dest),
ip4_addr4(&iphdr->dest)));
LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
}
#endif /* IP_DEBUG */

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/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#include "lwip/ip_addr.h"
#include "lwip/inet.h"
#include "lwip/netif.h"
#define IP_ADDR_ANY_VALUE 0x00000000UL
#define IP_ADDR_BROADCAST_VALUE 0xffffffffUL
/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
const struct ip_addr ip_addr_any = { IP_ADDR_ANY_VALUE };
const struct ip_addr ip_addr_broadcast = { IP_ADDR_BROADCAST_VALUE };
/* Determine if an address is a broadcast address on a network interface
*
* @param addr address to be checked
* @param netif the network interface against which the address is checked
* @return returns non-zero if the address is a broadcast address
*
*/
u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif)
{
u32_t addr2test;
addr2test = addr->addr;
/* all ones (broadcast) or all zeroes (old skool broadcast) */
if ((~addr2test == IP_ADDR_ANY_VALUE) ||
(addr2test == IP_ADDR_ANY_VALUE))
return 1;
/* no broadcast support on this network interface? */
else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0)
/* the given address cannot be a broadcast address
* nor can we check against any broadcast addresses */
return 0;
/* address matches network interface address exactly? => no broadcast */
else if (addr2test == netif->ip_addr.addr)
return 0;
/* on the same (sub) network... */
else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask))
/* ...and host identifier bits are all ones? =>... */
&& ((addr2test & ~netif->netmask.addr) ==
(IP_ADDR_BROADCAST_VALUE & ~netif->netmask.addr)))
/* => network broadcast address */
return 1;
else
return 0;
}

388
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/* @file
*
* This is the IP packet segmentation and reassembly implementation.
*
*/
/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Jani Monoses <jani@iv.ro>
* original reassembly code by Adam Dunkels <adam@sics.se>
*
*/
#include <string.h>
#include "lwip/opt.h"
#include "lwip/ip.h"
#include "lwip/ip_frag.h"
#include "lwip/netif.h"
#include "lwip/snmp.h"
#include "lwip/stats.h"
static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE];
static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8) + 1];
static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f,
0x0f, 0x07, 0x03, 0x01
};
static u16_t ip_reasslen;
static u8_t ip_reassflags;
#define IP_REASS_FLAG_LASTFRAG 0x01
static u8_t ip_reasstmr;
/*
* Copy len bytes from offset in pbuf to buffer
*
* helper used by both ip_reass and ip_frag
*/
static struct pbuf *
copy_from_pbuf(struct pbuf *p, u16_t * offset,
u8_t * buffer, u16_t len)
{
u16_t l;
p->payload = (u8_t *)p->payload + *offset;
p->len -= *offset;
while (len) {
l = len < p->len ? len : p->len;
memcpy(buffer, p->payload, l);
buffer += l;
len -= l;
if (len)
p = p->next;
else
*offset = l;
}
return p;
}
/**
* Initializes IP reassembly and fragmentation states.
*/
void
ip_frag_init(void)
{
ip_reasstmr = 0;
ip_reassflags = 0;
ip_reasslen = 0;
memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap));
}
/**
* Reassembly timer base function
* for both NO_SYS == 0 and 1 (!).
*
* Should be called every 1000 msec.
*/
void
ip_reass_tmr(void)
{
if (ip_reasstmr > 0) {
ip_reasstmr--;
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n",(u16_t)ip_reasstmr));
if (ip_reasstmr == 0) {
/* reassembly timed out */
snmp_inc_ipreasmfails();
}
}
}
/**
* Reassembles incoming IP fragments into an IP datagram.
*
* @param p points to a pbuf chain of the fragment
* @return NULL if reassembly is incomplete, ? otherwise
*/
struct pbuf *
ip_reass(struct pbuf *p)
{
struct pbuf *q;
struct ip_hdr *fraghdr, *iphdr;
u16_t offset, len;
u16_t i;
IPFRAG_STATS_INC(ip_frag.recv);
snmp_inc_ipreasmreqds();
iphdr = (struct ip_hdr *) ip_reassbuf;
fraghdr = (struct ip_hdr *) p->payload;
/* If ip_reasstmr is zero, no packet is present in the buffer, so we
write the IP header of the fragment into the reassembly
buffer. The timer is updated with the maximum age. */
if (ip_reasstmr == 0) {
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n"));
memcpy(iphdr, fraghdr, IP_HLEN);
ip_reasstmr = IP_REASS_MAXAGE;
ip_reassflags = 0;
/* Clear the bitmap. */
memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap));
}
/* Check if the incoming fragment matches the one currently present
in the reasembly buffer. If so, we proceed with copying the
fragment into the buffer. */
if (ip_addr_cmp(&iphdr->src, &fraghdr->src) &&
ip_addr_cmp(&iphdr->dest, &fraghdr->dest) &&
IPH_ID(iphdr) == IPH_ID(fraghdr)) {
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n",
ntohs(IPH_ID(fraghdr))));
IPFRAG_STATS_INC(ip_frag.cachehit);
/* Find out the offset in the reassembly buffer where we should
copy the fragment. */
len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
/* If the offset or the offset + fragment length overflows the
reassembly buffer, we discard the entire packet. */
if ((offset > IP_REASS_BUFSIZE) || ((offset + len) > IP_REASS_BUFSIZE)) {
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip_reass: fragment outside of buffer (%"S16_F":%"S16_F"/%"S16_F").\n", offset,
offset + len, IP_REASS_BUFSIZE));
ip_reasstmr = 0;
snmp_inc_ipreasmfails();
goto nullreturn;
}
/* Copy the fragment into the reassembly buffer, at the right
offset. */
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip_reass: copying with offset %"S16_F" into %"S16_F":%"S16_F"\n", offset,
IP_HLEN + offset, IP_HLEN + offset + len));
i = IPH_HL(fraghdr) * 4;
copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len);
/* Update the bitmap. */
if (offset / (8 * 8) == (offset + len) / (8 * 8)) {
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip_reass: updating single byte in bitmap.\n"));
/* If the two endpoints are in the same byte, we only update that byte. */
LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)",
offset / (8 * 8) < sizeof(ip_reassbitmap));
ip_reassbitmap[offset / (8 * 8)] |=
bitmap_bits[(offset / 8) & 7] &
~bitmap_bits[((offset + len) / 8) & 7];
} else {
/* If the two endpoints are in different bytes, we update the
bytes in the endpoints and fill the stuff inbetween with
0xff. */
LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)",
offset / (8 * 8) < sizeof(ip_reassbitmap));
ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7];
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip_reass: updating many bytes in bitmap (%"S16_F":%"S16_F").\n",
1 + offset / (8 * 8), (offset + len) / (8 * 8)));
for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
ip_reassbitmap[i] = 0xff;
}
LWIP_ASSERT("(offset + len) / (8 * 8) < sizeof(ip_reassbitmap)",
(offset + len) / (8 * 8) < sizeof(ip_reassbitmap));
ip_reassbitmap[(offset + len) / (8 * 8)] |=
~bitmap_bits[((offset + len) / 8) & 7];
}
/* If this fragment has the More Fragments flag set to zero, we
know that this is the last fragment, so we can calculate the
size of the entire packet. We also set the
IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
the final fragment. */
if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) {
ip_reassflags |= IP_REASS_FLAG_LASTFRAG;
ip_reasslen = offset + len;
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip_reass: last fragment seen, total len %"S16_F"\n",
ip_reasslen));
}
/* Finally, we check if we have a full packet in the buffer. We do
this by checking if we have the last fragment and if all bits
in the bitmap are set. */
if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) {
/* Check all bytes up to and including all but the last byte in
the bitmap. */
LWIP_ASSERT("ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)",
ip_reasslen / (8 * 8) - 1 < ((u16_t) sizeof(ip_reassbitmap)));
for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) {
if (ip_reassbitmap[i] != 0xff) {
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip_reass: last fragment seen, bitmap %"S16_F"/%"S16_F" failed (%"X16_F")\n",
i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i]));
goto nullreturn;
}
}
/* Check the last byte in the bitmap. It should contain just the
right amount of bits. */
LWIP_ASSERT("ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)",
ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap));
if (ip_reassbitmap[ip_reasslen / (8 * 8)] !=
(u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) {
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip_reass: last fragment seen, bitmap %"S16_F" didn't contain %"X16_F" (%"X16_F")\n",
ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7],
ip_reassbitmap[ip_reasslen / (8 * 8)]));
goto nullreturn;
}
/* Pretend to be a "normal" (i.e., not fragmented) IP packet
from now on. */
ip_reasslen += IP_HLEN;
IPH_LEN_SET(iphdr, htons(ip_reasslen));
IPH_OFFSET_SET(iphdr, 0);
IPH_CHKSUM_SET(iphdr, 0);
IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
/* If we have come this far, we have a full packet in the
buffer, so we allocate a pbuf and copy the packet into it. We
also reset the timer. */
ip_reasstmr = 0;
pbuf_free(p);
p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL);
if (p != NULL) {
i = 0;
for (q = p; q != NULL; q = q->next) {
/* Copy enough bytes to fill this pbuf in the chain. The
available data in the pbuf is given by the q->len variable. */
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip_reass: memcpy from %p (%"S16_F") to %p, %"S16_F" bytes\n",
(void *)&ip_reassbuf[i], i, q->payload,
q->len > ip_reasslen - i ? ip_reasslen - i : q->len));
memcpy(q->payload, &ip_reassbuf[i],
q->len > ip_reasslen - i ? ip_reasslen - i : q->len);
i += q->len;
}
IPFRAG_STATS_INC(ip_frag.fw);
snmp_inc_ipreasmoks();
} else {
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip_reass: pbuf_alloc(PBUF_LINK, ip_reasslen=%"U16_F", PBUF_POOL) failed\n", ip_reasslen));
IPFRAG_STATS_INC(ip_frag.memerr);
snmp_inc_ipreasmfails();
}
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p));
return p;
}
}
nullreturn:
IPFRAG_STATS_INC(ip_frag.drop);
pbuf_free(p);
return NULL;
}
static u8_t buf[MEM_ALIGN_SIZE(IP_FRAG_MAX_MTU)];
/**
* Fragment an IP datagram if too large for the netif.
*
* Chop the datagram in MTU sized chunks and send them in order
* by using a fixed size static memory buffer (PBUF_ROM)
*/
err_t
ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest)
{
struct pbuf *rambuf;
struct pbuf *header;
struct ip_hdr *iphdr;
u16_t nfb = 0;
u16_t left, cop;
u16_t mtu = netif->mtu;
u16_t ofo, omf;
u16_t last;
u16_t poff = IP_HLEN;
u16_t tmp;
/* Get a RAM based MTU sized pbuf */
rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF);
if (rambuf == NULL) {
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc(PBUF_LINK, 0, PBUF_REF) failed\n"));
return ERR_MEM;
}
rambuf->tot_len = rambuf->len = mtu;
rambuf->payload = MEM_ALIGN((void *)buf);
/* Copy the IP header in it */
iphdr = rambuf->payload;
memcpy(iphdr, p->payload, IP_HLEN);
/* Save original offset */
tmp = ntohs(IPH_OFFSET(iphdr));
ofo = tmp & IP_OFFMASK;
omf = tmp & IP_MF;
left = p->tot_len - IP_HLEN;
while (left) {
last = (left <= mtu - IP_HLEN);
/* Set new offset and MF flag */
ofo += nfb;
tmp = omf | (IP_OFFMASK & (ofo));
if (!last)
tmp = tmp | IP_MF;
IPH_OFFSET_SET(iphdr, htons(tmp));
/* Fill this fragment */
nfb = (mtu - IP_HLEN) / 8;
cop = last ? left : nfb * 8;
p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop);
/* Correct header */
IPH_LEN_SET(iphdr, htons(cop + IP_HLEN));
IPH_CHKSUM_SET(iphdr, 0);
IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
if (last)
pbuf_realloc(rambuf, left + IP_HLEN);
/* This part is ugly: we alloc a RAM based pbuf for
* the link level header for each chunk and then
* free it.A PBUF_ROM style pbuf for which pbuf_header
* worked would make things simpler.
*/
header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM);
if (header != NULL) {
pbuf_chain(header, rambuf);
netif->output(netif, header, dest);
IPFRAG_STATS_INC(ip_frag.xmit);
snmp_inc_ipfragcreates();
pbuf_free(header);
} else {
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc() for header failed\n"));
pbuf_free(rambuf);
return ERR_MEM;
}
left -= cop;
}
pbuf_free(rambuf);
snmp_inc_ipfragoks();
return ERR_OK;
}

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/** @file
*
* Dynamic memory manager
*
*/
/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#include <string.h>
#include "lwip/arch.h"
#include "lwip/opt.h"
#include "lwip/def.h"
#include "lwip/mem.h"
#include "lwip/sys.h"
#include "lwip/stats.h"
#if (MEM_LIBC_MALLOC == 0)
/* lwIP replacement for your libc malloc() */
struct mem {
mem_size_t next, prev;
#if MEM_ALIGNMENT == 1
u8_t used;
#elif MEM_ALIGNMENT == 2
u16_t used;
#elif MEM_ALIGNMENT == 4
u32_t used;
#elif MEM_ALIGNMENT == 8
u64_t used;
#else
#error "unhandled MEM_ALIGNMENT size"
#endif /* MEM_ALIGNMENT */
};
static struct mem *ram_end;
#if 1
/* Adam original */
static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT];
#else
/* Christiaan alignment fix */
static u8_t *ram;
static struct mem ram_heap[1 + ( (MEM_SIZE + sizeof(struct mem) - 1) / sizeof(struct mem))];
#endif
#define MIN_SIZE 12
#if 0 /* this one does not align correctly for some, resulting in crashes */
#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem))
#else
#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \
(((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \
(4 - (sizeof(struct mem) % MEM_ALIGNMENT))))
#endif
static struct mem *lfree; /* pointer to the lowest free block */
static sys_sem_t mem_sem;
static void
plug_holes(struct mem *mem)
{
struct mem *nmem;
struct mem *pmem;
LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
/* plug hole forward */
LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE);
nmem = (struct mem *)&ram[mem->next];
if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
if (lfree == nmem) {
lfree = mem;
}
mem->next = nmem->next;
((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram;
}
/* plug hole backward */
pmem = (struct mem *)&ram[mem->prev];
if (pmem != mem && pmem->used == 0) {
if (lfree == mem) {
lfree = pmem;
}
pmem->next = mem->next;
((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram;
}
}
void
mem_init(void)
{
struct mem *mem;
#if 1
/* Adam original */
#else
/* Christiaan alignment fix */
ram = (u8_t*)ram_heap;
#endif
memset(ram, 0, MEM_SIZE);
mem = (struct mem *)ram;
mem->next = MEM_SIZE;
mem->prev = 0;
mem->used = 0;
ram_end = (struct mem *)&ram[MEM_SIZE];
ram_end->used = 1;
ram_end->next = MEM_SIZE;
ram_end->prev = MEM_SIZE;
mem_sem = sys_sem_new(1);
lfree = (struct mem *)ram;
#if MEM_STATS
lwip_stats.mem.avail = MEM_SIZE;
#endif /* MEM_STATS */
}
void
mem_free(void *rmem)
{
struct mem *mem;
if (rmem == NULL) {
LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n"));
return;
}
sys_sem_wait(mem_sem);
LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
(u8_t *)rmem < (u8_t *)ram_end);
if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n"));
#if MEM_STATS
++lwip_stats.mem.err;
#endif /* MEM_STATS */
sys_sem_signal(mem_sem);
return;
}
mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
LWIP_ASSERT("mem_free: mem->used", mem->used);
mem->used = 0;
if (mem < lfree) {
lfree = mem;
}
#if MEM_STATS
lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram);
#endif /* MEM_STATS */
plug_holes(mem);
sys_sem_signal(mem_sem);
}
void *
mem_realloc(void *rmem, mem_size_t newsize)
{
mem_size_t size;
mem_size_t ptr, ptr2;
struct mem *mem, *mem2;
/* Expand the size of the allocated memory region so that we can
adjust for alignment. */
if ((newsize % MEM_ALIGNMENT) != 0) {
newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
}
if (newsize > MEM_SIZE) {
return NULL;
}
sys_sem_wait(mem_sem);
LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
(u8_t *)rmem < (u8_t *)ram_end);
if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n"));
return rmem;
}
mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
ptr = (u8_t *)mem - ram;
size = mem->next - ptr - SIZEOF_STRUCT_MEM;
#if MEM_STATS
lwip_stats.mem.used -= (size - newsize);
#endif /* MEM_STATS */
if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) {
ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
mem2 = (struct mem *)&ram[ptr2];
mem2->used = 0;
mem2->next = mem->next;
mem2->prev = ptr;
mem->next = ptr2;
if (mem2->next != MEM_SIZE) {
((struct mem *)&ram[mem2->next])->prev = ptr2;
}
plug_holes(mem2);
}
sys_sem_signal(mem_sem);
return rmem;
}
#if 1
/**
* Adam's mem_malloc(), suffers from bug #17922
* Set if to 0 for alternative mem_malloc().
*/
void *
mem_malloc(mem_size_t size)
{
mem_size_t ptr, ptr2;
struct mem *mem, *mem2;
if (size == 0) {
return NULL;
}
/* Expand the size of the allocated memory region so that we can
adjust for alignment. */
if ((size % MEM_ALIGNMENT) != 0) {
size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
}
if (size > MEM_SIZE) {
return NULL;
}
sys_sem_wait(mem_sem);
for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) {
mem = (struct mem *)&ram[ptr];
if (!mem->used &&
mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) {
ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
mem2 = (struct mem *)&ram[ptr2];
mem2->prev = ptr;
mem2->next = mem->next;
mem->next = ptr2;
if (mem2->next != MEM_SIZE) {
((struct mem *)&ram[mem2->next])->prev = ptr2;
}
mem2->used = 0;
mem->used = 1;
#if MEM_STATS
lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM);
/* if (lwip_stats.mem.max < lwip_stats.mem.used) {
lwip_stats.mem.max = lwip_stats.mem.used;
} */
if (lwip_stats.mem.max < ptr2) {
lwip_stats.mem.max = ptr2;
}
#endif /* MEM_STATS */
if (mem == lfree) {
/* Find next free block after mem */
while (lfree->used && lfree != ram_end) {
lfree = (struct mem *)&ram[lfree->next];
}
LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used);
}
sys_sem_signal(mem_sem);
LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
(mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
(unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
return (u8_t *)mem + SIZEOF_STRUCT_MEM;
}
}
LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
#if MEM_STATS
++lwip_stats.mem.err;
#endif /* MEM_STATS */
sys_sem_signal(mem_sem);
return NULL;
}
#else
/**
* Adam's mem_malloc() plus solution for bug #17922
*/
void *
mem_malloc(mem_size_t size)
{
mem_size_t ptr, ptr2;
struct mem *mem, *mem2;
if (size == 0) {
return NULL;
}
/* Expand the size of the allocated memory region so that we can
adjust for alignment. */
if ((size % MEM_ALIGNMENT) != 0) {
size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
}
if (size > MEM_SIZE) {
return NULL;
}
sys_sem_wait(mem_sem);
for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE - size; ptr = ((struct mem *)&ram[ptr])->next) {
mem = (struct mem *)&ram[ptr];
if (!mem->used) {
ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
if (mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) >= size) {
/* split large block, create empty remainder */
mem->next = ptr2;
mem->used = 1;
/* create mem2 struct */
mem2 = (struct mem *)&ram[ptr2];
mem2->used = 0;
mem2->next = mem->next;
mem2->prev = ptr;
if (mem2->next != MEM_SIZE) {
((struct mem *)&ram[mem2->next])->prev = ptr2;
}
}
else if (mem->next - (ptr + SIZEOF_STRUCT_MEM) > size) {
/* near fit, no split, no mem2 creation,
round up to mem->next */
ptr2 = mem->next;
mem->used = 1;
}
else if (mem->next - (ptr + SIZEOF_STRUCT_MEM) == size) {
/* exact fit, do not split, no mem2 creation */
mem->next = ptr2;
mem->used = 1;
}
if (mem->used) {
#if MEM_STATS
lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM);
if (lwip_stats.mem.max < ptr2) {
lwip_stats.mem.max = ptr2;
}
#endif /* MEM_STATS */
if (mem == lfree) {
/* Find next free block after mem */
while (lfree->used && lfree != ram_end) {
lfree = (struct mem *)&ram[lfree->next];
}
LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used);
}
sys_sem_signal(mem_sem);
LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
(mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
(unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
return (u8_t *)mem + SIZEOF_STRUCT_MEM;
}
}
}
LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
#if MEM_STATS
++lwip_stats.mem.err;
#endif /* MEM_STATS */
sys_sem_signal(mem_sem);
return NULL;
}
#endif
#endif /* MEM_LIBC_MALLOC == 0 */

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/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#include "lwip/opt.h"
#include "lwip/memp.h"
#include "lwip/pbuf.h"
#include "lwip/udp.h"
#include "lwip/raw.h"
#include "lwip/tcp.h"
#include "lwip/api.h"
#include "lwip/api_msg.h"
#include "lwip/tcpip.h"
#include "lwip/sys.h"
#include "lwip/stats.h"
struct memp {
struct memp *next;
};
#define MEMP_SIZE MEM_ALIGN_SIZE(sizeof(struct memp))
static struct memp *memp_tab[MEMP_MAX];
static const u16_t memp_sizes[MEMP_MAX] = {
MEM_ALIGN_SIZE(sizeof(struct pbuf)),
MEM_ALIGN_SIZE(sizeof(struct raw_pcb)),
MEM_ALIGN_SIZE(sizeof(struct udp_pcb)),
MEM_ALIGN_SIZE(sizeof(struct tcp_pcb)),
MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen)),
MEM_ALIGN_SIZE(sizeof(struct tcp_seg)),
MEM_ALIGN_SIZE(sizeof(struct netbuf)),
MEM_ALIGN_SIZE(sizeof(struct netconn)),
MEM_ALIGN_SIZE(sizeof(struct api_msg)),
MEM_ALIGN_SIZE(sizeof(struct tcpip_msg)),
MEM_ALIGN_SIZE(sizeof(struct sys_timeo))
};
static const u16_t memp_num[MEMP_MAX] = {
MEMP_NUM_PBUF,
MEMP_NUM_RAW_PCB,
MEMP_NUM_UDP_PCB,
MEMP_NUM_TCP_PCB,
MEMP_NUM_TCP_PCB_LISTEN,
MEMP_NUM_TCP_SEG,
MEMP_NUM_NETBUF,
MEMP_NUM_NETCONN,
MEMP_NUM_API_MSG,
MEMP_NUM_TCPIP_MSG,
MEMP_NUM_SYS_TIMEOUT
};
#define MEMP_TYPE_SIZE(qty, type) \
((qty) * (MEMP_SIZE + MEM_ALIGN_SIZE(sizeof(type))))
static u8_t memp_memory[MEM_ALIGNMENT - 1 +
MEMP_TYPE_SIZE(MEMP_NUM_PBUF, struct pbuf) +
MEMP_TYPE_SIZE(MEMP_NUM_RAW_PCB, struct raw_pcb) +
MEMP_TYPE_SIZE(MEMP_NUM_UDP_PCB, struct udp_pcb) +
MEMP_TYPE_SIZE(MEMP_NUM_TCP_PCB, struct tcp_pcb) +
MEMP_TYPE_SIZE(MEMP_NUM_TCP_PCB_LISTEN, struct tcp_pcb_listen) +
MEMP_TYPE_SIZE(MEMP_NUM_TCP_SEG, struct tcp_seg) +
MEMP_TYPE_SIZE(MEMP_NUM_NETBUF, struct netbuf) +
MEMP_TYPE_SIZE(MEMP_NUM_NETCONN, struct netconn) +
MEMP_TYPE_SIZE(MEMP_NUM_API_MSG, struct api_msg) +
MEMP_TYPE_SIZE(MEMP_NUM_TCPIP_MSG, struct tcpip_msg) +
MEMP_TYPE_SIZE(MEMP_NUM_SYS_TIMEOUT, struct sys_timeo)];
#if !SYS_LIGHTWEIGHT_PROT
static sys_sem_t mutex;
#endif
#if MEMP_SANITY_CHECK
static int
memp_sanity(void)
{
s16_t i, c;
struct memp *m, *n;
for (i = 0; i < MEMP_MAX; i++) {
for (m = memp_tab[i]; m != NULL; m = m->next) {
c = 1;
for (n = memp_tab[i]; n != NULL; n = n->next) {
if (n == m && --c < 0) {
return 0; /* LW was: abort(); */
}
}
}
}
return 1;
}
#endif /* MEMP_SANITY_CHECK*/
void
memp_init(void)
{
struct memp *memp;
u16_t i, j;
#if MEMP_STATS
for (i = 0; i < MEMP_MAX; ++i) {
lwip_stats.memp[i].used = lwip_stats.memp[i].max =
lwip_stats.memp[i].err = 0;
lwip_stats.memp[i].avail = memp_num[i];
}
#endif /* MEMP_STATS */
memp = MEM_ALIGN(memp_memory);
for (i = 0; i < MEMP_MAX; ++i) {
memp_tab[i] = NULL;
for (j = 0; j < memp_num[i]; ++j) {
memp->next = memp_tab[i];
memp_tab[i] = memp;
memp = (struct memp *)((u8_t *)memp + MEMP_SIZE + memp_sizes[i]);
}
}
#if !SYS_LIGHTWEIGHT_PROT
mutex = sys_sem_new(1);
#endif
}
void *
memp_malloc(memp_t type)
{
struct memp *memp;
void *mem;
#if SYS_LIGHTWEIGHT_PROT
SYS_ARCH_DECL_PROTECT(old_level);
#endif
LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX);
#if SYS_LIGHTWEIGHT_PROT
SYS_ARCH_PROTECT(old_level);
#else /* SYS_LIGHTWEIGHT_PROT */
sys_sem_wait(mutex);
#endif /* SYS_LIGHTWEIGHT_PROT */
memp = memp_tab[type];
if (memp != NULL) {
memp_tab[type] = memp->next;
memp->next = NULL;
#if MEMP_STATS
++lwip_stats.memp[type].used;
if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) {
lwip_stats.memp[type].max = lwip_stats.memp[type].used;
}
#endif /* MEMP_STATS */
mem = (u8_t *)memp + MEMP_SIZE;
LWIP_ASSERT("memp_malloc: memp properly aligned",
((mem_ptr_t)memp % MEM_ALIGNMENT) == 0);
} else {
LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %"S16_F"\n", type));
#if MEMP_STATS
++lwip_stats.memp[type].err;
#endif /* MEMP_STATS */
mem = NULL;
}
#if SYS_LIGHTWEIGHT_PROT
SYS_ARCH_UNPROTECT(old_level);
#else /* SYS_LIGHTWEIGHT_PROT */
sys_sem_signal(mutex);
#endif /* SYS_LIGHTWEIGHT_PROT */
return mem;
}
void
memp_free(memp_t type, void *mem)
{
struct memp *memp;
#if SYS_LIGHTWEIGHT_PROT
SYS_ARCH_DECL_PROTECT(old_level);
#endif /* SYS_LIGHTWEIGHT_PROT */
if (mem == NULL) {
return;
}
memp = (struct memp *)((u8_t *)mem - MEMP_SIZE);
#if SYS_LIGHTWEIGHT_PROT
SYS_ARCH_PROTECT(old_level);
#else /* SYS_LIGHTWEIGHT_PROT */
sys_sem_wait(mutex);
#endif /* SYS_LIGHTWEIGHT_PROT */
#if MEMP_STATS
lwip_stats.memp[type].used--;
#endif /* MEMP_STATS */
memp->next = memp_tab[type];
memp_tab[type] = memp;
#if MEMP_SANITY_CHECK
LWIP_ASSERT("memp sanity", memp_sanity());
#endif
#if SYS_LIGHTWEIGHT_PROT
SYS_ARCH_UNPROTECT(old_level);
#else /* SYS_LIGHTWEIGHT_PROT */
sys_sem_signal(mutex);
#endif /* SYS_LIGHTWEIGHT_PROT */
}

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/**
* @file
*
* lwIP network interface abstraction
*/
/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#include "lwip/opt.h"
#include "lwip/def.h"
#include "lwip/ip_addr.h"
#include "lwip/netif.h"
#include "lwip/tcp.h"
#include "lwip/snmp.h"
struct netif *netif_list = NULL;
struct netif *netif_default = NULL;
/**
* Add a network interface to the list of lwIP netifs.
*
* @param netif a pre-allocated netif structure
* @param ipaddr IP address for the new netif
* @param netmask network mask for the new netif
* @param gw default gateway IP address for the new netif
* @param state opaque data passed to the new netif
* @param init callback function that initializes the interface
* @param input callback function that is called to pass
* ingress packets up in the protocol layer stack.
*
* @return netif, or NULL if failed.
*/
struct netif *
netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
struct ip_addr *gw,
void *state,
err_t (* init)(struct netif *netif),
err_t (* input)(struct pbuf *p, struct netif *netif))
{
static s16_t netifnum = 0;
/* reset new interface configuration state */
netif->ip_addr.addr = 0;
netif->netmask.addr = 0;
netif->gw.addr = 0;
netif->flags = 0;
#if LWIP_DHCP
/* netif not under DHCP control by default */
netif->dhcp = NULL;
#endif
/* remember netif specific state information data */
netif->state = state;
netif->num = netifnum++;
netif->input = input;
netif_set_addr(netif, ipaddr, netmask, gw);
/* call user specified initialization function for netif */
if (init(netif) != ERR_OK) {
return NULL;
}
/* add this netif to the list */
netif->next = netif_list;
netif_list = netif;
snmp_inc_iflist();
LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ",
netif->name[0], netif->name[1]));
ip_addr_debug_print(NETIF_DEBUG, ipaddr);
LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
ip_addr_debug_print(NETIF_DEBUG, netmask);
LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
ip_addr_debug_print(NETIF_DEBUG, gw);
LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
return netif;
}
void
netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
struct ip_addr *gw)
{
netif_set_ipaddr(netif, ipaddr);
netif_set_netmask(netif, netmask);
netif_set_gw(netif, gw);
}
void netif_remove(struct netif * netif)
{
if ( netif == NULL ) return;
snmp_delete_ipaddridx_tree(netif);
/* is it the first netif? */
if (netif_list == netif) {
netif_list = netif->next;
snmp_dec_iflist();
}
else {
/* look for netif further down the list */
struct netif * tmpNetif;
for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) {
if (tmpNetif->next == netif) {
tmpNetif->next = netif->next;
snmp_dec_iflist();
break;
}
}
if (tmpNetif == NULL)
return; /* we didn't find any netif today */
}
/* this netif is default? */
if (netif_default == netif)
/* reset default netif */
netif_default = NULL;
LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
}
struct netif *
netif_find(char *name)
{
struct netif *netif;
u8_t num;
if (name == NULL) {
return NULL;
}
num = name[2] - '0';
for(netif = netif_list; netif != NULL; netif = netif->next) {
if (num == netif->num &&
name[0] == netif->name[0] &&
name[1] == netif->name[1]) {
LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
return netif;
}
}
LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
return NULL;
}
void
netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr)
{
/* TODO: Handling of obsolete pcbs */
/* See: http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */
#if LWIP_TCP
struct tcp_pcb *pcb;
struct tcp_pcb_listen *lpcb;
/* address is actually being changed? */
if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0)
{
/* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */
LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n"));
pcb = tcp_active_pcbs;
while (pcb != NULL) {
/* PCB bound to current local interface address? */
if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
/* this connection must be aborted */
struct tcp_pcb *next = pcb->next;
LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
tcp_abort(pcb);
pcb = next;
} else {
pcb = pcb->next;
}
}
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
/* PCB bound to current local interface address? */
if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) {
/* The PCB is listening to the old ipaddr and
* is set to listen to the new one instead */
ip_addr_set(&(lpcb->local_ip), ipaddr);
}
}
}
#endif
snmp_delete_ipaddridx_tree(netif);
snmp_delete_iprteidx_tree(0,netif);
/* set new IP address to netif */
ip_addr_set(&(netif->ip_addr), ipaddr);
snmp_insert_ipaddridx_tree(netif);
snmp_insert_iprteidx_tree(0,netif);
#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */
/** For Ethernet network interfaces, we would like to send a
* "gratuitous ARP"; this is an ARP packet sent by a node in order
* to spontaneously cause other nodes to update an entry in their
* ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6.
*/
etharp_query(netif, ipaddr, NULL);
#endif
LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
netif->name[0], netif->name[1],
ip4_addr1(&netif->ip_addr),
ip4_addr2(&netif->ip_addr),
ip4_addr3(&netif->ip_addr),
ip4_addr4(&netif->ip_addr)));
}
void
netif_set_gw(struct netif *netif, struct ip_addr *gw)
{
ip_addr_set(&(netif->gw), gw);
LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
netif->name[0], netif->name[1],
ip4_addr1(&netif->gw),
ip4_addr2(&netif->gw),
ip4_addr3(&netif->gw),
ip4_addr4(&netif->gw)));
}
void
netif_set_netmask(struct netif *netif, struct ip_addr *netmask)
{
snmp_delete_iprteidx_tree(0, netif);
/* set new netmask to netif */
ip_addr_set(&(netif->netmask), netmask);
snmp_insert_iprteidx_tree(0, netif);
LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
netif->name[0], netif->name[1],
ip4_addr1(&netif->netmask),
ip4_addr2(&netif->netmask),
ip4_addr3(&netif->netmask),
ip4_addr4(&netif->netmask)));
}
void
netif_set_default(struct netif *netif)
{
if (netif == NULL)
{
/* remove default route */
snmp_delete_iprteidx_tree(1, netif);
}
else
{
/* install default route */
snmp_insert_iprteidx_tree(1, netif);
}
netif_default = netif;
LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
}
/**
* Bring an interface up, available for processing
* traffic.
*
* @note: Enabling DHCP on a down interface will make it come
* up once configured.
*
* @see dhcp_start()
*/
void netif_set_up(struct netif *netif)
{
netif->flags |= NETIF_FLAG_UP;
#if LWIP_SNMP
snmp_get_sysuptime(&netif->ts);
#endif
}
/**
* Ask if an interface is up
*/
u8_t netif_is_up(struct netif *netif)
{
return (netif->flags & NETIF_FLAG_UP)?1:0;
}
/**
* Bring an interface down, disabling any traffic processing.
*
* @note: Enabling DHCP on a down interface will make it come
* up once configured.
*
* @see dhcp_start()
*/
void netif_set_down(struct netif *netif)
{
netif->flags &= ~NETIF_FLAG_UP;
#if LWIP_SNMP
snmp_get_sysuptime(&netif->ts);
#endif
}
void
netif_init(void)
{
netif_list = netif_default = NULL;
}

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@ -0,0 +1,964 @@
/**
* @file
* Packet buffer management
*
* Packets are built from the pbuf data structure. It supports dynamic
* memory allocation for packet contents or can reference externally
* managed packet contents both in RAM and ROM. Quick allocation for
* incoming packets is provided through pools with fixed sized pbufs.
*
* A packet may span over multiple pbufs, chained as a singly linked
* list. This is called a "pbuf chain".
*
* Multiple packets may be queued, also using this singly linked list.
* This is called a "packet queue".
*
* So, a packet queue consists of one or more pbuf chains, each of
* which consist of one or more pbufs. Currently, queues are only
* supported in a limited section of lwIP, this is the etharp queueing
* code. Outside of this section no packet queues are supported yet.
*
* The differences between a pbuf chain and a packet queue are very
* precise but subtle.
*
* The last pbuf of a packet has a ->tot_len field that equals the
* ->len field. It can be found by traversing the list. If the last
* pbuf of a packet has a ->next field other than NULL, more packets
* are on the queue.
*
* Therefore, looping through a pbuf of a single packet, has an
* loop end condition (tot_len == p->len), NOT (next == NULL).
*/
/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#include <string.h>
#include "lwip/opt.h"
#include "lwip/stats.h"
#include "lwip/def.h"
#include "lwip/mem.h"
#include "lwip/memp.h"
#include "lwip/pbuf.h"
#include "lwip/sys.h"
#include "arch/perf.h"
static u8_t pbuf_pool_memory[MEM_ALIGNMENT - 1 + PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf))];
#if !SYS_LIGHTWEIGHT_PROT
static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock;
static sys_sem_t pbuf_pool_free_sem;
#endif
static struct pbuf *pbuf_pool = NULL;
/**
* Initializes the pbuf module.
*
* A large part of memory is allocated for holding the pool of pbufs.
* The size of the individual pbufs in the pool is given by the size
* parameter, and the number of pbufs in the pool by the num parameter.
*
* After the memory has been allocated, the pbufs are set up. The
* ->next pointer in each pbuf is set up to point to the next pbuf in
* the pool.
*
*/
void
pbuf_init(void)
{
struct pbuf *p, *q = NULL;
u16_t i;
pbuf_pool = (struct pbuf *)MEM_ALIGN(pbuf_pool_memory);
#if PBUF_STATS
lwip_stats.pbuf.avail = PBUF_POOL_SIZE;
#endif /* PBUF_STATS */
/* Set up ->next pointers to link the pbufs of the pool together */
p = pbuf_pool;
for(i = 0; i < PBUF_POOL_SIZE; ++i) {
p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf));
p->len = p->tot_len = PBUF_POOL_BUFSIZE;
p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf)));
p->flags = PBUF_FLAG_POOL;
q = p;
p = p->next;
}
/* The ->next pointer of last pbuf is NULL to indicate that there
are no more pbufs in the pool */
q->next = NULL;
#if !SYS_LIGHTWEIGHT_PROT
pbuf_pool_alloc_lock = 0;
pbuf_pool_free_lock = 0;
pbuf_pool_free_sem = sys_sem_new(1);
#endif
}
/**
* @internal only called from pbuf_alloc()
*/
static struct pbuf *
pbuf_pool_alloc(void)
{
struct pbuf *p = NULL;
SYS_ARCH_DECL_PROTECT(old_level);
SYS_ARCH_PROTECT(old_level);
#if !SYS_LIGHTWEIGHT_PROT
/* Next, check the actual pbuf pool, but if the pool is locked, we
pretend to be out of buffers and return NULL. */
if (pbuf_pool_free_lock) {
#if PBUF_STATS
++lwip_stats.pbuf.alloc_locked;
#endif /* PBUF_STATS */
return NULL;
}
pbuf_pool_alloc_lock = 1;
if (!pbuf_pool_free_lock) {
#endif /* SYS_LIGHTWEIGHT_PROT */
p = pbuf_pool;
if (p) {
pbuf_pool = p->next;
}
#if !SYS_LIGHTWEIGHT_PROT
#if PBUF_STATS
} else {
++lwip_stats.pbuf.alloc_locked;
#endif /* PBUF_STATS */
}
pbuf_pool_alloc_lock = 0;
#endif /* SYS_LIGHTWEIGHT_PROT */
#if PBUF_STATS
if (p != NULL) {
++lwip_stats.pbuf.used;
if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) {
lwip_stats.pbuf.max = lwip_stats.pbuf.used;
}
}
#endif /* PBUF_STATS */
SYS_ARCH_UNPROTECT(old_level);
return p;
}
/**
* Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).
*
* The actual memory allocated for the pbuf is determined by the
* layer at which the pbuf is allocated and the requested size
* (from the size parameter).
*
* @param flag this parameter decides how and where the pbuf
* should be allocated as follows:
*
* - PBUF_RAM: buffer memory for pbuf is allocated as one large
* chunk. This includes protocol headers as well.
* - PBUF_ROM: no buffer memory is allocated for the pbuf, even for
* protocol headers. Additional headers must be prepended
* by allocating another pbuf and chain in to the front of
* the ROM pbuf. It is assumed that the memory used is really
* similar to ROM in that it is immutable and will not be
* changed. Memory which is dynamic should generally not
* be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
* - PBUF_REF: no buffer memory is allocated for the pbuf, even for
* protocol headers. It is assumed that the pbuf is only
* being used in a single thread. If the pbuf gets queued,
* then pbuf_take should be called to copy the buffer.
* - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from
* the pbuf pool that is allocated during pbuf_init().
*
* @return the allocated pbuf. If multiple pbufs where allocated, this
* is the first pbuf of a pbuf chain.
*/
struct pbuf *
pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag)
{
struct pbuf *p, *q, *r;
u16_t offset;
s32_t rem_len; /* remaining length */
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F")\n", length));
/* determine header offset */
offset = 0;
switch (l) {
case PBUF_TRANSPORT:
/* add room for transport (often TCP) layer header */
offset += PBUF_TRANSPORT_HLEN;
/* FALLTHROUGH */
case PBUF_IP:
/* add room for IP layer header */
offset += PBUF_IP_HLEN;
/* FALLTHROUGH */
case PBUF_LINK:
/* add room for link layer header */
offset += PBUF_LINK_HLEN;
break;
case PBUF_RAW:
break;
default:
LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0);
return NULL;
}
switch (flag) {
case PBUF_POOL:
/* allocate head of pbuf chain into p */
p = pbuf_pool_alloc();
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p));
if (p == NULL) {
#if PBUF_STATS
++lwip_stats.pbuf.err;
#endif /* PBUF_STATS */
return NULL;
}
p->next = NULL;
/* make the payload pointer point 'offset' bytes into pbuf data memory */
p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset)));
LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned",
((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
/* the total length of the pbuf chain is the requested size */
p->tot_len = length;
/* set the length of the first pbuf in the chain */
p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length;
/* set reference count (needed here in case we fail) */
p->ref = 1;
/* now allocate the tail of the pbuf chain */
/* remember first pbuf for linkage in next iteration */
r = p;
/* remaining length to be allocated */
rem_len = length - p->len;
/* any remaining pbufs to be allocated? */
while (rem_len > 0) {
q = pbuf_pool_alloc();
if (q == NULL) {
LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n"));
#if PBUF_STATS
++lwip_stats.pbuf.err;
#endif /* PBUF_STATS */
/* free chain so far allocated */
pbuf_free(p);
/* bail out unsuccesfully */
return NULL;
}
q->next = NULL;
/* make previous pbuf point to this pbuf */
r->next = q;
/* set total length of this pbuf and next in chain */
q->tot_len = rem_len;
/* this pbuf length is pool size, unless smaller sized tail */
q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len;
q->payload = (void *)((u8_t *)q + sizeof(struct pbuf));
LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
q->ref = 1;
/* calculate remaining length to be allocated */
rem_len -= q->len;
/* remember this pbuf for linkage in next iteration */
r = q;
}
/* end of chain */
/*r->next = NULL;*/
break;
case PBUF_RAM:
/* If pbuf is to be allocated in RAM, allocate memory for it. */
p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length));
if (p == NULL) {
return NULL;
}
/* Set up internal structure of the pbuf. */
p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset));
p->len = p->tot_len = length;
p->next = NULL;
p->flags = PBUF_FLAG_RAM;
LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
break;
/* pbuf references existing (non-volatile static constant) ROM payload? */
case PBUF_ROM:
/* pbuf references existing (externally allocated) RAM payload? */
case PBUF_REF:
/* only allocate memory for the pbuf structure */
p = memp_malloc(MEMP_PBUF);
if (p == NULL) {
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF"));
return NULL;
}
/* caller must set this field properly, afterwards */
p->payload = NULL;
p->len = p->tot_len = length;
p->next = NULL;
p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF);
break;
default:
LWIP_ASSERT("pbuf_alloc: erroneous flag", 0);
return NULL;
}
/* set reference count */
p->ref = 1;
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
return p;
}
#if PBUF_STATS
#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0)
#else /* PBUF_STATS */
#define DEC_PBUF_STATS
#endif /* PBUF_STATS */
#define PBUF_POOL_FAST_FREE(p) do { \
p->next = pbuf_pool; \
pbuf_pool = p; \
DEC_PBUF_STATS; \
} while (0)
#if SYS_LIGHTWEIGHT_PROT
#define PBUF_POOL_FREE(p) do { \
SYS_ARCH_DECL_PROTECT(old_level); \
SYS_ARCH_PROTECT(old_level); \
PBUF_POOL_FAST_FREE(p); \
SYS_ARCH_UNPROTECT(old_level); \
} while (0)
#else /* SYS_LIGHTWEIGHT_PROT */
#define PBUF_POOL_FREE(p) do { \
sys_sem_wait(pbuf_pool_free_sem); \
PBUF_POOL_FAST_FREE(p); \
sys_sem_signal(pbuf_pool_free_sem); \
} while (0)
#endif /* SYS_LIGHTWEIGHT_PROT */
/**
* Shrink a pbuf chain to a desired length.
*
* @param p pbuf to shrink.
* @param new_len desired new length of pbuf chain
*
* Depending on the desired length, the first few pbufs in a chain might
* be skipped and left unchanged. The new last pbuf in the chain will be
* resized, and any remaining pbufs will be freed.
*
* @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.
* @note May not be called on a packet queue.
*
* @bug Cannot grow the size of a pbuf (chain) (yet).
*/
void
pbuf_realloc(struct pbuf *p, u16_t new_len)
{
struct pbuf *q;
u16_t rem_len; /* remaining length */
s16_t grow;
LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL ||
p->flags == PBUF_FLAG_ROM ||
p->flags == PBUF_FLAG_RAM ||
p->flags == PBUF_FLAG_REF);
/* desired length larger than current length? */
if (new_len >= p->tot_len) {
/* enlarging not yet supported */
return;
}
/* the pbuf chain grows by (new_len - p->tot_len) bytes
* (which may be negative in case of shrinking) */
grow = new_len - p->tot_len;
/* first, step over any pbufs that should remain in the chain */
rem_len = new_len;
q = p;
/* should this pbuf be kept? */
while (rem_len > q->len) {
/* decrease remaining length by pbuf length */
rem_len -= q->len;
/* decrease total length indicator */
q->tot_len += grow;
/* proceed to next pbuf in chain */
q = q->next;
}
/* we have now reached the new last pbuf (in q) */
/* rem_len == desired length for pbuf q */
/* shrink allocated memory for PBUF_RAM */
/* (other types merely adjust their length fields */
if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) {
/* reallocate and adjust the length of the pbuf that will be split */
mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len);
}
/* adjust length fields for new last pbuf */
q->len = rem_len;
q->tot_len = q->len;
/* any remaining pbufs in chain? */
if (q->next != NULL) {
/* free remaining pbufs in chain */
pbuf_free(q->next);
}
/* q is last packet in chain */
q->next = NULL;
}
/**
* Adjusts the payload pointer to hide or reveal headers in the payload.
*
* Adjusts the ->payload pointer so that space for a header
* (dis)appears in the pbuf payload.
*
* The ->payload, ->tot_len and ->len fields are adjusted.
*
* @param hdr_size_inc Number of bytes to increment header size which
* increases the size of the pbuf. New space is on the front.
* (Using a negative value decreases the header size.)
* If hdr_size_inc is 0, this function does nothing and returns succesful.
*
* PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
* the call will fail. A check is made that the increase in header size does
* not move the payload pointer in front of the start of the buffer.
* @return non-zero on failure, zero on success.
*
*/
u8_t
pbuf_header(struct pbuf *p, s16_t header_size_increment)
{
u16_t flags;
void *payload;
LWIP_ASSERT("p != NULL", p != NULL);
if ((header_size_increment == 0) || (p == NULL)) return 0;
flags = p->flags;
/* remember current payload pointer */
payload = p->payload;
/* pbuf types containing payloads? */
if (flags == PBUF_FLAG_RAM || flags == PBUF_FLAG_POOL) {
/* set new payload pointer */
p->payload = (u8_t *)p->payload - header_size_increment;
/* boundary check fails? */
if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) {
LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n",
(void *)p->payload,
(void *)(p + 1)));\
/* restore old payload pointer */
p->payload = payload;
/* bail out unsuccesfully */
return 1;
}
/* pbuf types refering to external payloads? */
} else if (flags == PBUF_FLAG_REF || flags == PBUF_FLAG_ROM) {
/* hide a header in the payload? */
if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) {
/* increase payload pointer */
p->payload = (u8_t *)p->payload - header_size_increment;
} else {
/* cannot expand payload to front (yet!)
* bail out unsuccesfully */
return 1;
}
}
/* modify pbuf length fields */
p->len += header_size_increment;
p->tot_len += header_size_increment;
LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%"S16_F")\n",
(void *)payload, (void *)p->payload, header_size_increment));
return 0;
}
/**
* Dereference a pbuf chain or queue and deallocate any no-longer-used
* pbufs at the head of this chain or queue.
*
* Decrements the pbuf reference count. If it reaches zero, the pbuf is
* deallocated.
*
* For a pbuf chain, this is repeated for each pbuf in the chain,
* up to the first pbuf which has a non-zero reference count after
* decrementing. So, when all reference counts are one, the whole
* chain is free'd.
*
* @param pbuf The pbuf (chain) to be dereferenced.
*
* @return the number of pbufs that were de-allocated
* from the head of the chain.
*
* @note MUST NOT be called on a packet queue (Not verified to work yet).
* @note the reference counter of a pbuf equals the number of pointers
* that refer to the pbuf (or into the pbuf).
*
* @internal examples:
*
* Assuming existing chains a->b->c with the following reference
* counts, calling pbuf_free(a) results in:
*
* 1->2->3 becomes ...1->3
* 3->3->3 becomes 2->3->3
* 1->1->2 becomes ......1
* 2->1->1 becomes 1->1->1
* 1->1->1 becomes .......
*
*/
u8_t
pbuf_free(struct pbuf *p)
{
u16_t flags;
struct pbuf *q;
u8_t count;
SYS_ARCH_DECL_PROTECT(old_level);
LWIP_ASSERT("p != NULL", p != NULL);
/* if assertions are disabled, proceed with debug output */
if (p == NULL) {
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n"));
return 0;
}
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p));
PERF_START;
LWIP_ASSERT("pbuf_free: sane flags",
p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM ||
p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL);
count = 0;
/* Since decrementing ref cannot be guaranteed to be a single machine operation
* we must protect it. Also, the later test of ref must be protected.
*/
SYS_ARCH_PROTECT(old_level);
/* de-allocate all consecutive pbufs from the head of the chain that
* obtain a zero reference count after decrementing*/
while (p != NULL) {
/* all pbufs in a chain are referenced at least once */
LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
/* decrease reference count (number of pointers to pbuf) */
p->ref--;
/* this pbuf is no longer referenced to? */
if (p->ref == 0) {
/* remember next pbuf in chain for next iteration */
q = p->next;
LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p));
flags = p->flags;
/* is this a pbuf from the pool? */
if (flags == PBUF_FLAG_POOL) {
p->len = p->tot_len = PBUF_POOL_BUFSIZE;
p->payload = (void *)((u8_t *)p + sizeof(struct pbuf));
PBUF_POOL_FREE(p);
/* is this a ROM or RAM referencing pbuf? */
} else if (flags == PBUF_FLAG_ROM || flags == PBUF_FLAG_REF) {
memp_free(MEMP_PBUF, p);
/* flags == PBUF_FLAG_RAM */
} else {
mem_free(p);
}
count++;
/* proceed to next pbuf */
p = q;
/* p->ref > 0, this pbuf is still referenced to */
/* (and so the remaining pbufs in chain as well) */
} else {
LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)p->ref));
/* stop walking through the chain */
p = NULL;
}
}
SYS_ARCH_UNPROTECT(old_level);
PERF_STOP("pbuf_free");
/* return number of de-allocated pbufs */
return count;
}
/**
* Count number of pbufs in a chain
*
* @param p first pbuf of chain
* @return the number of pbufs in a chain
*/
u8_t
pbuf_clen(struct pbuf *p)
{
u8_t len;
len = 0;
while (p != NULL) {
++len;
p = p->next;
}
return len;
}
/**
* Increment the reference count of the pbuf.
*
* @param p pbuf to increase reference counter of
*
*/
void
pbuf_ref(struct pbuf *p)
{
SYS_ARCH_DECL_PROTECT(old_level);
/* pbuf given? */
if (p != NULL) {
SYS_ARCH_PROTECT(old_level);
++(p->ref);
SYS_ARCH_UNPROTECT(old_level);
}
}
/**
* Concatenate two pbufs (each may be a pbuf chain) and take over
* the caller's reference of the tail pbuf.
*
* @note The caller MAY NOT reference the tail pbuf afterwards.
* Use pbuf_chain() for that purpose.
*
* @see pbuf_chain()
*/
void
pbuf_cat(struct pbuf *h, struct pbuf *t)
{
struct pbuf *p;
LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL);
LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL);
if ((h == NULL) || (t == NULL)) return;
/* proceed to last pbuf of chain */
for (p = h; p->next != NULL; p = p->next) {
/* add total length of second chain to all totals of first chain */
p->tot_len += t->tot_len;
}
/* { p is last pbuf of first h chain, p->next == NULL } */
LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
LWIP_ASSERT("p->next == NULL", p->next == NULL);
/* add total length of second chain to last pbuf total of first chain */
p->tot_len += t->tot_len;
/* chain last pbuf of head (p) with first of tail (t) */
p->next = t;
/* p->next now references t, but the caller will drop its reference to t,
* so netto there is no change to the reference count of t.
*/
}
/**
* Chain two pbufs (or pbuf chains) together.
*
* The caller MUST call pbuf_free(t) once it has stopped
* using it. Use pbuf_cat() instead if you no longer use t.
*
* @param h head pbuf (chain)
* @param t tail pbuf (chain)
* @note The pbufs MUST belong to the same packet.
* @note MAY NOT be called on a packet queue.
*
* The ->tot_len fields of all pbufs of the head chain are adjusted.
* The ->next field of the last pbuf of the head chain is adjusted.
* The ->ref field of the first pbuf of the tail chain is adjusted.
*
*/
void
pbuf_chain(struct pbuf *h, struct pbuf *t)
{
pbuf_cat(h, t);
/* t is now referenced by h */
pbuf_ref(t);
LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
}
/* For packet queueing. Note that queued packets MUST be dequeued first
* using pbuf_dequeue() before calling other pbuf_() functions. */
#if ARP_QUEUEING
/**
* Add a packet to the end of a queue.
*
* @param q pointer to first packet on the queue
* @param n packet to be queued
*
* Both packets MUST be given, and must be different.
*/
void
pbuf_queue(struct pbuf *p, struct pbuf *n)
{
#if PBUF_DEBUG /* remember head of queue */
struct pbuf *q = p;
#endif
/* programmer stupidity checks */
LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL);
LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL);
LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n);
if ((p == NULL) || (n == NULL) || (p == n)){
LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n"));
return;
}
/* iterate through all packets on queue */
while (p->next != NULL) {
/* be very picky about pbuf chain correctness */
#if PBUF_DEBUG
/* iterate through all pbufs in packet */
while (p->tot_len != p->len) {
/* make sure invariant condition holds */
LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
/* make sure each packet is complete */
LWIP_ASSERT("p->next != NULL", p->next != NULL);
p = p->next;
/* { p->tot_len == p->len => p is last pbuf of a packet } */
}
/* { p is last pbuf of a packet } */
/* proceed to next packet on queue */
#endif
/* proceed to next pbuf */
if (p->next != NULL) p = p->next;
}
/* { p->tot_len == p->len and p->next == NULL } ==>
* { p is last pbuf of last packet on queue } */
/* chain last pbuf of queue with n */
p->next = n;
/* n is now referenced to by the (packet p in the) queue */
pbuf_ref(n);
#if PBUF_DEBUG
LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2,
("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n",
(void *)n, (void *)p, (void *)q));
#endif
}
/**
* Remove a packet from the head of a queue.
*
* The caller MUST reference the remainder of the queue (as returned). The
* caller MUST NOT call pbuf_ref() as it implicitly takes over the reference
* from p.
*
* @param p pointer to first packet on the queue which will be dequeued.
* @return first packet on the remaining queue (NULL if no further packets).
*
*/
struct pbuf *
pbuf_dequeue(struct pbuf *p)
{
struct pbuf *q;
LWIP_ASSERT("p != NULL", p != NULL);
/* iterate through all pbufs in packet p */
while (p->tot_len != p->len) {
/* make sure invariant condition holds */
LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
/* make sure each packet is complete */
LWIP_ASSERT("p->next != NULL", p->next != NULL);
p = p->next;
}
/* { p->tot_len == p->len } => p is the last pbuf of the first packet */
/* remember next packet on queue in q */
q = p->next;
/* dequeue packet p from queue */
p->next = NULL;
/* any next packet on queue? */
if (q != NULL) {
/* although q is no longer referenced by p, it MUST be referenced by
* the caller, who is maintaining this packet queue. So, we do not call
* pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */
LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q));
} else {
LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n"));
}
return q;
}
#endif
/**
*
* Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs.
*
* Used to queue packets on behalf of the lwIP stack, such as
* ARP based queueing.
*
* Go through a pbuf chain and replace any PBUF_REF buffers
* with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of
* the referenced data.
*
* @note You MUST explicitly use p = pbuf_take(p);
* The pbuf you give as argument, may have been replaced
* by a (differently located) copy through pbuf_take()!
*
* @note Any replaced pbufs will be freed through pbuf_free().
* This may deallocate them if they become no longer referenced.
*
* @param p Head of pbuf chain to process
*
* @return Pointer to head of pbuf chain
*/
struct pbuf *
pbuf_take(struct pbuf *p)
{
struct pbuf *q , *prev, *head;
LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL);
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p));
prev = NULL;
head = p;
/* iterate through pbuf chain */
do
{
/* pbuf is of type PBUF_REF? */
if (p->flags == PBUF_FLAG_REF) {
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p));
/* allocate a pbuf (w/ payload) fully in RAM */
/* PBUF_POOL buffers are faster if we can use them */
if (p->len <= PBUF_POOL_BUFSIZE) {
q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL);
if (q == NULL) {
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n"));
}
} else {
/* no replacement pbuf yet */
q = NULL;
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n"));
}
/* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */
if (q == NULL) {
q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM);
if (q == NULL) {
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n"));
}
}
/* replacement pbuf could be allocated? */
if (q != NULL)
{
/* copy p to q */
/* copy successor */
q->next = p->next;
/* remove linkage from original pbuf */
p->next = NULL;
/* remove linkage to original pbuf */
if (prev != NULL) {
/* prev->next == p at this point */
LWIP_ASSERT("prev->next == p", prev->next == p);
/* break chain and insert new pbuf instead */
prev->next = q;
/* prev == NULL, so we replaced the head pbuf of the chain */
} else {
head = q;
}
/* copy pbuf payload */
memcpy(q->payload, p->payload, p->len);
q->tot_len = p->tot_len;
q->len = p->len;
/* in case p was the first pbuf, it is no longer refered to by
* our caller, as the caller MUST do p = pbuf_take(p);
* in case p was not the first pbuf, it is no longer refered to
* by prev. we can safely free the pbuf here.
* (note that we have set p->next to NULL already so that
* we will not free the rest of the chain by accident.)
*/
pbuf_free(p);
/* do not copy ref, since someone else might be using the old buffer */
LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q));
p = q;
} else {
/* deallocate chain */
pbuf_free(head);
LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p));
return NULL;
}
/* p->flags != PBUF_FLAG_REF */
} else {
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n"));
}
/* remember this pbuf */
prev = p;
/* proceed to next pbuf in original chain */
p = p->next;
} while (p);
LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n"));
return head;
}
/**
* Dechains the first pbuf from its succeeding pbufs in the chain.
*
* Makes p->tot_len field equal to p->len.
* @param p pbuf to dechain
* @return remainder of the pbuf chain, or NULL if it was de-allocated.
* @note May not be called on a packet queue.
*/
struct pbuf *
pbuf_dechain(struct pbuf *p)
{
struct pbuf *q;
u8_t tail_gone = 1;
/* tail */
q = p->next;
/* pbuf has successor in chain? */
if (q != NULL) {
/* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);
/* enforce invariant if assertion is disabled */
q->tot_len = p->tot_len - p->len;
/* decouple pbuf from remainder */
p->next = NULL;
/* total length of pbuf p is its own length only */
p->tot_len = p->len;
/* q is no longer referenced by p, free it */
LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q));
tail_gone = pbuf_free(q);
if (tail_gone > 0) {
LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE,
("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));
}
/* return remaining tail or NULL if deallocated */
}
/* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);
return (tail_gone > 0? NULL: q);
}

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@ -0,0 +1,326 @@
/**
* @file
*
* Implementation of raw protocol PCBs for low-level handling of
* different types of protocols besides (or overriding) those
* already available in lwIP.
*
*/
/*
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#include <string.h>
#include "lwip/opt.h"
#include "lwip/def.h"
#include "lwip/memp.h"
#include "lwip/inet.h"
#include "lwip/ip_addr.h"
#include "lwip/netif.h"
#include "lwip/raw.h"
#include "lwip/stats.h"
#include "arch/perf.h"
#include "lwip/snmp.h"
#if LWIP_RAW
/** The list of RAW PCBs */
static struct raw_pcb *raw_pcbs = NULL;
void
raw_init(void)
{
raw_pcbs = NULL;
}
/**
* Determine if in incoming IP packet is covered by a RAW PCB
* and if so, pass it to a user-provided receive callback function.
*
* Given an incoming IP datagram (as a chain of pbufs) this function
* finds a corresponding RAW PCB and calls the corresponding receive
* callback function.
*
* @param pbuf pbuf to be demultiplexed to a RAW PCB.
* @param netif network interface on which the datagram was received.
* @Return - 1 if the packet has been eaten by a RAW PCB receive
* callback function. The caller MAY NOT not reference the
* packet any longer, and MAY NOT call pbuf_free().
* @return - 0 if packet is not eaten (pbuf is still referenced by the
* caller).
*
*/
u8_t
raw_input(struct pbuf *p, struct netif *inp)
{
struct raw_pcb *pcb;
struct ip_hdr *iphdr;
s16_t proto;
u8_t eaten = 0;
iphdr = p->payload;
proto = IPH_PROTO(iphdr);
pcb = raw_pcbs;
/* loop through all raw pcbs until the packet is eaten by one */
/* this allows multiple pcbs to match against the packet by design */
while ((eaten == 0) && (pcb != NULL)) {
if (pcb->protocol == proto) {
/* receive callback function available? */
if (pcb->recv != NULL) {
/* the receive callback function did not eat the packet? */
if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0)
{
/* receive function ate the packet */
p = NULL;
eaten = 1;
}
}
/* no receive callback function was set for this raw PCB */
/* drop the packet */
}
pcb = pcb->next;
}
return eaten;
}
/**
* Bind a RAW PCB.
*
* @param pcb RAW PCB to be bound with a local address ipaddr.
* @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
* bind to all local interfaces.
*
* @return lwIP error code.
* - ERR_OK. Successful. No error occured.
* - ERR_USE. The specified IP address is already bound to by
* another RAW PCB.
*
* @see raw_disconnect()
*/
err_t
raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr)
{
ip_addr_set(&pcb->local_ip, ipaddr);
return ERR_OK;
}
/**
* Connect an RAW PCB. This function is required by upper layers
* of lwip. Using the raw api you could use raw_sendto() instead
*
* This will associate the RAW PCB with the remote address.
*
* @param pcb RAW PCB to be connected with remote address ipaddr and port.
* @param ipaddr remote IP address to connect with.
*
* @return lwIP error code
*
* @see raw_disconnect() and raw_sendto()
*/
err_t
raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr)
{
ip_addr_set(&pcb->remote_ip, ipaddr);
return ERR_OK;
}
/**
* Set the callback function for received packets that match the
* raw PCB's protocol and binding.
*
* The callback function MUST either
* - eat the packet by calling pbuf_free() and returning non-zero. The
* packet will not be passed to other raw PCBs or other protocol layers.
* - not free the packet, and return zero. The packet will be matched
* against further PCBs and/or forwarded to another protocol layers.
*
* @return non-zero if the packet was free()d, zero if the packet remains
* available for others.
*/
void
raw_recv(struct raw_pcb *pcb,
u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p,
struct ip_addr *addr),
void *recv_arg)
{
/* remember recv() callback and user data */
pcb->recv = recv;
pcb->recv_arg = recv_arg;
}
/**
* Send the raw IP packet to the given address. Note that actually you cannot
* modify the IP headers (this is inconsistent with the receive callback where
* you actually get the IP headers), you can only specify the IP payload here.
* It requires some more changes in lwIP. (there will be a raw_send() function
* then.)
*
* @param pcb the raw pcb which to send
* @param p the IP payload to send
* @param ipaddr the destination address of the IP packet
*
*/
err_t
raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr)
{
err_t err;
struct netif *netif;
struct ip_addr *src_ip;
struct pbuf *q; /* q will be sent down the stack */
LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n"));
/* not enough space to add an IP header to first pbuf in given p chain? */
if (pbuf_header(p, IP_HLEN)) {
/* allocate header in new pbuf */
q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);
/* new header pbuf could not be allocated? */
if (q == NULL) {
LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n"));
return ERR_MEM;
}
/* chain header q in front of given pbuf p */
pbuf_chain(q, p);
/* { first pbuf q points to header pbuf } */
LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
} else {
/* first pbuf q equals given pbuf */
q = p;
pbuf_header(q, -IP_HLEN);
}
if ((netif = ip_route(ipaddr)) == NULL) {
LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr));
#if RAW_STATS
/* ++lwip_stats.raw.rterr;*/
#endif /* RAW_STATS */
/* free any temporary header pbuf allocated by pbuf_header() */
if (q != p) {
pbuf_free(q);
}
return ERR_RTE;
}
if (ip_addr_isany(&pcb->local_ip)) {
/* use outgoing network interface IP address as source address */
src_ip = &(netif->ip_addr);
} else {
/* use RAW PCB local IP address as source address */
src_ip = &(pcb->local_ip);
}
err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif);
/* did we chain a header earlier? */
if (q != p) {
/* free the header */
pbuf_free(q);
}
return err;
}
/**
* Send the raw IP packet to the address given by raw_connect()
*
* @param pcb the raw pcb which to send
* @param p the IP payload to send
* @param ipaddr the destination address of the IP packet
*
*/
err_t
raw_send(struct raw_pcb *pcb, struct pbuf *p)
{
return raw_sendto(pcb, p, &pcb->remote_ip);
}
/**
* Remove an RAW PCB.
*
* @param pcb RAW PCB to be removed. The PCB is removed from the list of
* RAW PCB's and the data structure is freed from memory.
*
* @see raw_new()
*/
void
raw_remove(struct raw_pcb *pcb)
{
struct raw_pcb *pcb2;
/* pcb to be removed is first in list? */
if (raw_pcbs == pcb) {
/* make list start at 2nd pcb */
raw_pcbs = raw_pcbs->next;
/* pcb not 1st in list */
} else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
/* find pcb in raw_pcbs list */
if (pcb2->next != NULL && pcb2->next == pcb) {
/* remove pcb from list */
pcb2->next = pcb->next;
}
}
memp_free(MEMP_RAW_PCB, pcb);
}
/**
* Create a RAW PCB.
*
* @return The RAW PCB which was created. NULL if the PCB data structure
* could not be allocated.
*
* @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)
*
* @see raw_remove()
*/
struct raw_pcb *
raw_new(u16_t proto) {
struct raw_pcb *pcb;
LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n"));
pcb = memp_malloc(MEMP_RAW_PCB);
/* could allocate RAW PCB? */
if (pcb != NULL) {
/* initialize PCB to all zeroes */
memset(pcb, 0, sizeof(struct raw_pcb));
pcb->protocol = proto;
pcb->ttl = RAW_TTL;
pcb->next = raw_pcbs;
raw_pcbs = pcb;
}
return pcb;
}
#endif /* LWIP_RAW */

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20080212/Demo/Common/ethernet/lwIP/core/snmp/asn1_dec.c Normal file
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@ -0,0 +1,652 @@
/**
* @file
* Abstract Syntax Notation One (ISO 8824, 8825) decoding
*
* @todo not optimised (yet), favor correctness over speed, favor speed over size
*/
/*
* Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* Author: Christiaan Simons <christiaan.simons@axon.tv>
*/
#include "lwip/opt.h"
#if LWIP_SNMP
#include "lwip/snmp_asn1.h"
/**
* Retrieves type field from incoming pbuf chain.
*
* @param p points to a pbuf holding an ASN1 coded type field
* @param ofs points to the offset within the pbuf chain of the ASN1 coded type field
* @param type return ASN1 type
* @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
*/
err_t
snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type)
{
u16_t plen, base;
u8_t *msg_ptr;
plen = 0;
while (p != NULL)
{
base = plen;
plen += p->len;
if (ofs < plen)
{
msg_ptr = p->payload;
msg_ptr += ofs - base;
*type = *msg_ptr;
return ERR_OK;
}
p = p->next;
}
/* p == NULL, ofs >= plen */
return ERR_ARG;
}
/**
* Decodes length field from incoming pbuf chain into host length.
*
* @param p points to a pbuf holding an ASN1 coded length
* @param ofs points to the offset within the pbuf chain of the ASN1 coded length
* @param octets_used returns number of octets used by the length code
* @param length return host order length, upto 64k
* @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
*/
err_t
snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length)
{
u16_t plen, base;
u8_t *msg_ptr;
plen = 0;
while (p != NULL)
{
base = plen;
plen += p->len;
if (ofs < plen)
{
msg_ptr = p->payload;
msg_ptr += ofs - base;
if (*msg_ptr < 0x80)
{
/* primitive definite length format */
*octets_used = 1;
*length = *msg_ptr;
return ERR_OK;
}
else if (*msg_ptr == 0x80)
{
/* constructed indefinite length format, termination with two zero octets */
u8_t zeros;
u8_t i;
*length = 0;
zeros = 0;
while (zeros != 2)
{
i = 2;
while (i > 0)
{
i--;
(*length) += 1;
ofs += 1;
if (ofs >= plen)
{
/* next octet in next pbuf */
p = p->next;
if (p == NULL) { return ERR_ARG; }
msg_ptr = p->payload;
plen += p->len;
}
else
{
/* next octet in same pbuf */
msg_ptr++;
}
if (*msg_ptr == 0)
{
zeros++;
if (zeros == 2)
{
/* stop while (i > 0) */
i = 0;
}
}
else
{
zeros = 0;
}
}
}
*octets_used = 1;
return ERR_OK;
}
else if (*msg_ptr == 0x81)
{
/* constructed definite length format, one octet */
ofs += 1;
if (ofs >= plen)
{
/* next octet in next pbuf */
p = p->next;
if (p == NULL) { return ERR_ARG; }
msg_ptr = p->payload;
}
else
{
/* next octet in same pbuf */
msg_ptr++;
}
*length = *msg_ptr;
*octets_used = 2;
return ERR_OK;
}
else if (*msg_ptr == 0x82)
{
u8_t i;
/* constructed definite length format, two octets */
i = 2;
while (i > 0)
{
i--;
ofs += 1;
if (ofs >= plen)
{
/* next octet in next pbuf */
p = p->next;
if (p == NULL) { return ERR_ARG; }
msg_ptr = p->payload;
plen += p->len;
}
else
{
/* next octet in same pbuf */
msg_ptr++;
}
if (i == 0)
{
/* least significant length octet */
*length |= *msg_ptr;
}
else
{
/* most significant length octet */
*length = (*msg_ptr) << 8;
}
}
*octets_used = 3;
return ERR_OK;
}
else
{
/* constructed definite length format 3..127 octets, this is too big (>64k) */
/** @todo: do we need to accept inefficient codings with many leading zero's? */
*octets_used = 1 + ((*msg_ptr) & 0x7f);
return ERR_ARG;
}
}
p = p->next;
}
/* p == NULL, ofs >= plen */
return ERR_ARG;
}
/**
* Decodes positive integer (counter, gauge, timeticks) into u32_t.
*
* @param p points to a pbuf holding an ASN1 coded integer
* @param ofs points to the offset within the pbuf chain of the ASN1 coded integer
* @param len length of the coded integer field
* @param value return host order integer
* @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
*
* @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded
* as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value
* of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!!
*/
err_t
snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value)
{
u16_t plen, base;
u8_t *msg_ptr;
plen = 0;
while (p != NULL)
{
base = plen;
plen += p->len;
if (ofs < plen)
{
msg_ptr = p->payload;
msg_ptr += ofs - base;
if ((len > 0) && (len < 6))
{
/* start from zero */
*value = 0;
if (*msg_ptr & 0x80)
{
/* negative, expecting zero sign bit! */
return ERR_ARG;
}
else
{
/* positive */
if ((len > 1) && (*msg_ptr == 0))
{
/* skip leading "sign byte" octet 0x00 */
len--;
ofs += 1;
if (ofs >= plen)
{
/* next octet in next pbuf */
p = p->next;
if (p == NULL) { return ERR_ARG; }
msg_ptr = p->payload;
plen += p->len;
}
else
{
/* next octet in same pbuf */
msg_ptr++;
}
}
}
/* OR octets with value */
while (len > 1)
{
len--;
*value |= *msg_ptr;
*value <<= 8;
ofs += 1;
if (ofs >= plen)
{
/* next octet in next pbuf */
p = p->next;
if (p == NULL) { return ERR_ARG; }
msg_ptr = p->payload;
plen += p->len;
}
else
{
/* next octet in same pbuf */
msg_ptr++;
}
}
*value |= *msg_ptr;
return ERR_OK;
}
else
{
return ERR_ARG;
}
}
p = p->next;
}
/* p == NULL, ofs >= plen */
return ERR_ARG;
}
/**
* Decodes integer into s32_t.
*
* @param p points to a pbuf holding an ASN1 coded integer
* @param ofs points to the offset within the pbuf chain of the ASN1 coded integer
* @param len length of the coded integer field
* @param value return host order integer
* @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
*
* @note ASN coded integers are _always_ signed!
*/
err_t
snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value)
{
u16_t plen, base;
u8_t *msg_ptr;
u8_t *lsb_ptr = (u8_t*)value;
u8_t sign;
plen = 0;
while (p != NULL)
{
base = plen;
plen += p->len;
if (ofs < plen)
{
msg_ptr = p->payload;
msg_ptr += ofs - base;
if ((len > 0) && (len < 5))
{
if (*msg_ptr & 0x80)
{
/* negative, start from -1 */
*value = -1;
sign = 1;
}
else
{
/* positive, start from 0 */
*value = 0;
sign = 0;
}
/* OR/AND octets with value */
while (len > 1)
{
len--;
if (sign)
{
*lsb_ptr &= *msg_ptr;
*value <<= 8;
*lsb_ptr |= 255;
}
else
{
*lsb_ptr |= *msg_ptr;
*value <<= 8;
}
ofs += 1;
if (ofs >= plen)
{
/* next octet in next pbuf */
p = p->next;
if (p == NULL) { return ERR_ARG; }
msg_ptr = p->payload;
plen += p->len;
}
else
{
/* next octet in same pbuf */
msg_ptr++;
}
}
if (sign)
{
*lsb_ptr &= *msg_ptr;
}
else
{
*lsb_ptr |= *msg_ptr;
}
return ERR_OK;
}
else
{
return ERR_ARG;
}
}
p = p->next;
}
/* p == NULL, ofs >= plen */
return ERR_ARG;
}
/**
* Decodes object identifier from incoming message into array of s32_t.
*
* @param p points to a pbuf holding an ASN1 coded object identifier
* @param ofs points to the offset within the pbuf chain of the ASN1 coded object identifier
* @param len length of the coded object identifier
* @param oid return object identifier struct
* @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
*/
err_t
snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid)
{
u16_t plen, base;
u8_t *msg_ptr;
s32_t *oid_ptr;
plen = 0;
while (p != NULL)
{
base = plen;
plen += p->len;
if (ofs < plen)
{
msg_ptr = p->payload;
msg_ptr += ofs - base;
oid->len = 0;
oid_ptr = &oid->id[0];
if (len > 0)
{
/* first compressed octet */
if (*msg_ptr == 0x2B)
{
/* (most) common case 1.3 (iso.org) */
*oid_ptr = 1;
oid_ptr++;
*oid_ptr = 3;
oid_ptr++;
}
else if (*msg_ptr < 40)
{
*oid_ptr = 0;
oid_ptr++;
*oid_ptr = *msg_ptr;
oid_ptr++;
}
else if (*msg_ptr < 80)
{
*oid_ptr = 1;
oid_ptr++;
*oid_ptr = (*msg_ptr) - 40;
oid_ptr++;
}
else
{
*oid_ptr = 2;
oid_ptr++;
*oid_ptr = (*msg_ptr) - 80;
oid_ptr++;
}
oid->len = 2;
}
else
{
/* accepting zero length identifiers e.g. for
getnext operation. uncommon but valid */
return ERR_OK;
}
len--;
if (len > 0)
{
ofs += 1;
if (ofs >= plen)
{
/* next octet in next pbuf */
p = p->next;
if (p == NULL) { return ERR_ARG; }
msg_ptr = p->payload;
plen += p->len;
}
else
{
/* next octet in same pbuf */
msg_ptr++;
}
}
while ((len > 0) && (oid->len < LWIP_SNMP_OBJ_ID_LEN))
{
/* sub-identifier uses multiple octets */
if (*msg_ptr & 0x80)
{
s32_t sub_id = 0;
while ((*msg_ptr & 0x80) && (len > 1))
{
len--;
sub_id = (sub_id << 7) + (*msg_ptr & ~0x80);
ofs += 1;
if (ofs >= plen)
{
/* next octet in next pbuf */
p = p->next;
if (p == NULL) { return ERR_ARG; }
msg_ptr = p->payload;
plen += p->len;
}
else
{
/* next octet in same pbuf */
msg_ptr++;
}
}
if (!(*msg_ptr & 0x80) && (len > 0))
{
/* last octet sub-identifier */
len--;
sub_id = (sub_id << 7) + *msg_ptr;
*oid_ptr = sub_id;
}
}
else
{
/* !(*msg_ptr & 0x80) sub-identifier uses single octet */
len--;
*oid_ptr = *msg_ptr;
}
if (len > 0)
{
/* remaining oid bytes available ... */
ofs += 1;
if (ofs >= plen)
{
/* next octet in next pbuf */
p = p->next;
if (p == NULL) { return ERR_ARG; }
msg_ptr = p->payload;
plen += p->len;
}
else
{
/* next octet in same pbuf */
msg_ptr++;
}
}
oid_ptr++;
oid->len++;
}
if (len == 0)
{
/* len == 0, end of oid */
return ERR_OK;
}
else
{
/* len > 0, oid->len == LWIP_SNMP_OBJ_ID_LEN or malformed encoding */
return ERR_ARG;
}
}
p = p->next;
}
/* p == NULL, ofs >= plen */
return ERR_ARG;
}
/**
* Decodes (copies) raw data (ip-addresses, octet strings, opaque encoding)
* from incoming message into array.
*
* @param p points to a pbuf holding an ASN1 coded raw data
* @param ofs points to the offset within the pbuf chain of the ASN1 coded raw data
* @param len length of the coded raw data (zero is valid, e.g. empty string!)
* @param raw_len length of the raw return value
* @param raw return raw bytes
* @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
*/
err_t
snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw)
{
u16_t plen, base;
u8_t *msg_ptr;
if (len > 0)
{
plen = 0;
while (p != NULL)
{
base = plen;
plen += p->len;
if (ofs < plen)
{
msg_ptr = p->payload;
msg_ptr += ofs - base;
if (raw_len >= len)
{
while (len > 1)
{
/* copy len - 1 octets */
len--;
*raw = *msg_ptr;
raw++;
ofs += 1;
if (ofs >= plen)
{
/* next octet in next pbuf */
p = p->next;
if (p == NULL) { return ERR_ARG; }
msg_ptr = p->payload;
plen += p->len;
}
else
{
/* next octet in same pbuf */
msg_ptr++;
}
}
/* copy last octet */
*raw = *msg_ptr;
return ERR_OK;
}
else
{
/* raw_len < len, not enough dst space */
return ERR_ARG;
}
}
p = p->next;
}
/* p == NULL, ofs >= plen */
return ERR_ARG;
}
else
{
/* len == 0, empty string */
return ERR_OK;
}
}
#endif /* LWIP_SNMP */

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