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768
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_can.c
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768
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_can.c
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
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* File Name : 91x_can.c
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* Author : MCD Application Team
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* Date First Issued : 05/18/2006 : Version 1.0
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* Description : This file provides all the CAN software functions.
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********************************************************************************
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* History:
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* 05/24/2006 : Version 1.1
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* 05/18/2006 : Version 1.0
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********************************************************************************
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
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* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Includes ------------------------------------------------------------------*/
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#include "91x_can.h"
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#include "91x_scu.h"
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */
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/* Description : Form the Mask and Arbitration registers value to filter */
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/* a range of identifiers or a fixed identifier, for standard*/
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/* and extended IDs */
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/*----------------------------------------------------------------------------*/
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#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start)))
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#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end))
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#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id))
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#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id))
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#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2))
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#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2))
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#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2))
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#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2))
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#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11))
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#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03)))
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#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11))
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#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03)))
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#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11))
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#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03)))
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#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11))
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#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03)))
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/* macro to format the timing register value from the timing parameters*/
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#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F))
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/* Private variables ---------------------------------------------------------*/
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/* array of pre-defined timing parameters for standard bitrates*/
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u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */
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CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */
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CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */
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CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */
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CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */
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CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */
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};
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/* Private function prototypes -----------------------------------------------*/
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static u32 GetFreeIF(void);
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/* Private functions ---------------------------------------------------------*/
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/*******************************************************************************
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* Function Name : CAN_DeInit
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* Description : Deinitializes the CAN peripheral registers to their default
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* reset values.
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void CAN_DeInit (void)
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{
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/* Reset the CAN registers values*/
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SCU_APBPeriphReset(__CAN,ENABLE); /*CAN peripheral is under Reset */
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SCU_APBPeriphReset(__CAN,DISABLE); /*CAN peripheral Reset off*/
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}
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/*******************************************************************************
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* Function Name : CAN_Init
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* Description : Initializes the CAN peripheral according to the specified
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* parameters in the CAN_InitStruct.
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* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
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* contains the configuration information for the CAN peripheral.
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* Output : None
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* Return : None
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*******************************************************************************/
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void CAN_Init(CAN_InitTypeDef* CAN_InitStruct)
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{
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CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters);
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CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate);
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CAN_LeaveInitMode();
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CAN_LeaveTestMode();
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}
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/*******************************************************************************
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* Function Name : CAN_StructInit
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* Description : Fills each CAN_InitStruct member with its reset value.
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* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which
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* will be initialized.
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* Output : None
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* Return : None.
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*******************************************************************************/
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void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
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{
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/* Reset CAN init structure parameters values */
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CAN_InitStruct->CAN_ConfigParameters = 0x0;
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CAN_InitStruct->CAN_Bitrate = 0x2301;
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}
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/*******************************************************************************
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* Function Name : CAN_SetBitrate
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* Description : Setups a standard CAN bitrate.
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* Input : bitrate: specifies the bit rate.
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* Output : None
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* Return : None
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*******************************************************************************/
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void CAN_SetBitrate(u32 bitrate)
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{
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CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */
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CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */
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}
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/*******************************************************************************
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* Function Name : CAN_SetTiming
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* Description : Setups the CAN timing with specific parameters
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* Input : - tseg1: specifies Time Segment before the sample point.
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* This parameter must be a number between 1 and 16.
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* - tseg2: Time Segment after the sample point. This parameter
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* must be a number between 1 and 8.
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* - sjw: Synchronisation Jump Width. This parameter must be
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* a number between 1 and 4.
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* - brp: Baud Rate Prescaler. This parameter must be a number
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* between 1 and 1024.
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* Output : None
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* Return : None
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*******************************************************************************/
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void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp)
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{
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CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp);
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CAN->BRPR = ((brp-1) >> 6) & 0x0F;
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}
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/*******************************************************************************
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* Function Name : GetFreeIF
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* Description : Searchs the first free message interface, starting from 0.
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* Input : None
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* Output : None
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* Return : A free message interface number (0 or 1) if found, else 2
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*******************************************************************************/
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static u32 GetFreeIF(void)
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{
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if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0)
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return 0;
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else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0)
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return 1;
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else
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return 2;
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}
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/*******************************************************************************
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* Function Name : CAN_SetUnusedMsgObj
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* Description : Configures the message object as unused
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* Input : msgobj: specifies the Message object number, from 0 to 31.
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* Output : None
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* Return : An ErrorStatus enumuration value:
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* - SUCCESS: Interface to treat the message
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* - ERROR: No interface to treat the message
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*******************************************************************************/
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ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj)
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{
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u32 msg_if=0;
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if ((msg_if = GetFreeIF()) == 2)
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{
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return ERROR;
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}
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CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD
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| CAN_CMR_MASK
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| CAN_CMR_ARB
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| CAN_CMR_CONTROL
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| CAN_CMR_DATAA
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| CAN_CMR_DATAB;
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CAN->sMsgObj[msg_if].M1R = 0;
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CAN->sMsgObj[msg_if].M2R = 0;
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CAN->sMsgObj[msg_if].A1R = 0;
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CAN->sMsgObj[msg_if].A2R = 0;
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CAN->sMsgObj[msg_if].MCR = 0;
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CAN->sMsgObj[msg_if].DA1R = 0;
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CAN->sMsgObj[msg_if].DA2R = 0;
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CAN->sMsgObj[msg_if].DB1R = 0;
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CAN->sMsgObj[msg_if].DB2R = 0;
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CAN->sMsgObj[msg_if].CRR = 1 + msgobj;
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return SUCCESS;
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}
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/*******************************************************************************
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* Function Name : CAN_SetTxMsgObj
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* Description : Configures the message object as TX.
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* Input : - msgobj: specifies the Message object number, from 0 to 31.
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* - idType: specifies the identifier type of the frames that
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* will be transmitted using this message object.
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* This parameter can be one of the following values:
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* - CAN_STD_ID (standard ID, 11-bit)
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* - CAN_EXT_ID (extended ID, 29-bit)
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* Output : None
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* Return : An ErrorStatus enumuration value:
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* - SUCCESS: Interface to treat the message
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* - ERROR: No interface to treat the message
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*******************************************************************************/
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ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType)
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{
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u32 msg_if=0;
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if ((msg_if = GetFreeIF()) == 2)
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{
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return ERROR;
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}
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CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD
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| CAN_CMR_MASK
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| CAN_CMR_ARB
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| CAN_CMR_CONTROL
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| CAN_CMR_DATAA
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| CAN_CMR_DATAB;
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CAN->sMsgObj[msg_if].M1R = 0;
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CAN->sMsgObj[msg_if].A1R = 0;
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if (idType == CAN_STD_ID)
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{
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CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR;
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CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR;
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}
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else
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{
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CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD;
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CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD;
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}
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CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB;
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CAN->sMsgObj[msg_if].DA1R = 0;
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CAN->sMsgObj[msg_if].DA2R = 0;
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CAN->sMsgObj[msg_if].DB1R = 0;
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CAN->sMsgObj[msg_if].DB2R = 0;
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CAN->sMsgObj[msg_if].CRR = 1 + msgobj;
|
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return SUCCESS;
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}
|
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/*******************************************************************************
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* Function Name : CAN_SetRxMsgObj
|
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* Description : Configures the message object as RX.
|
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* Input : - msgobj: specifies the Message object number, from 0 to 31.
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* - idType: specifies the identifier type of the frames that
|
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* will be transmitted using this message object.
|
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* This parameter can be one of the following values:
|
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* - CAN_STD_ID (standard ID, 11-bit)
|
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* - CAN_EXT_ID (extended ID, 29-bit)
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* - idLow: specifies the low part of the identifier range used
|
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* for acceptance filtering.
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* - idHigh: specifies the high part of the identifier range
|
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* used for acceptance filtering.
|
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* - singleOrFifoLast: specifies the end-of-buffer indicator.
|
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* This parameter can be one of the following values:
|
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* - TRUE: for a single receive object or a FIFO receive
|
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* object that is the last one of the FIFO.
|
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* - FALSE: for a FIFO receive object that is not the
|
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* last one.
|
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* Output : None
|
||||
* Return : An ErrorStatus enumuration value:
|
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* - SUCCESS: Interface to treat the message
|
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* - ERROR: No interface to treat the message
|
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*******************************************************************************/
|
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ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast)
|
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{
|
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u32 msg_if=0;
|
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|
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if ((msg_if = GetFreeIF()) == 2)
|
||||
{
|
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return ERROR;
|
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}
|
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|
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CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD
|
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| CAN_CMR_MASK
|
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| CAN_CMR_ARB
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| CAN_CMR_CONTROL
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| CAN_CMR_DATAA
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| CAN_CMR_DATAB;
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if (idType == CAN_STD_ID)
|
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{
|
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CAN->sMsgObj[msg_if].M1R = 0;
|
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CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh);
|
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|
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CAN->sMsgObj[msg_if].A1R = 0;
|
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CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh);
|
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}
|
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else
|
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{
|
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CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh);
|
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CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh);
|
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|
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CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh);
|
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CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh);
|
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}
|
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|
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CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0);
|
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|
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CAN->sMsgObj[msg_if].DA1R = 0;
|
||||
CAN->sMsgObj[msg_if].DA2R = 0;
|
||||
CAN->sMsgObj[msg_if].DB1R = 0;
|
||||
CAN->sMsgObj[msg_if].DB2R = 0;
|
||||
|
||||
CAN->sMsgObj[msg_if].CRR = 1 + msgobj;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
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/*******************************************************************************
|
||||
* Function Name : CAN_InvalidateAllMsgObj
|
||||
* Description : Configures all the message objects as unused.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void CAN_InvalidateAllMsgObj(void)
|
||||
{
|
||||
u32 i=0;
|
||||
for (i = 0; i < 32; i++)
|
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CAN_SetUnusedMsgObj(i);
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_ReleaseMessage
|
||||
* Description : Releases the message object
|
||||
* Input : - msgobj: specifies the Message object number, from 0 to 31.
|
||||
* Output : None
|
||||
* Return : An ErrorStatus enumuration value:
|
||||
* - SUCCESS: Interface to treat the message
|
||||
* - ERROR: No interface to treat the message
|
||||
*******************************************************************************/
|
||||
ErrorStatus CAN_ReleaseMessage(u32 msgobj)
|
||||
{
|
||||
u32 msg_if=0;
|
||||
|
||||
if ((msg_if = GetFreeIF()) == 2)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT;
|
||||
CAN->sMsgObj[msg_if].CRR = 1 + msgobj;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_SendMessage
|
||||
* Description : Start transmission of a message
|
||||
* Input : - msgobj: specifies the Message object number, from 0 to 31.
|
||||
* : - pCanMsg: pointer to the message structure containing data
|
||||
* to transmit.
|
||||
* Output : None
|
||||
* Return : An ErrorStatus enumuration value:
|
||||
* - SUCCESS: Transmission OK
|
||||
* - ERROR: No transmission
|
||||
*******************************************************************************/
|
||||
ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg)
|
||||
{
|
||||
if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
CAN->SR &= ~CAN_SR_TXOK;
|
||||
|
||||
/* read the Arbitration and Message Control*/
|
||||
CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL;
|
||||
|
||||
CAN->sMsgObj[0].CRR = 1 + msgobj;
|
||||
|
||||
if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* update the contents needed for transmission*/
|
||||
CAN->sMsgObj[0].CMR = CAN_CMR_WRRD
|
||||
| CAN_CMR_ARB
|
||||
| CAN_CMR_CONTROL
|
||||
| CAN_CMR_DATAA
|
||||
| CAN_CMR_DATAB;
|
||||
|
||||
if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0)
|
||||
{
|
||||
/* standard ID*/
|
||||
CAN->sMsgObj[0].A1R = 0;
|
||||
CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* extended ID*/
|
||||
CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id);
|
||||
CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id);
|
||||
}
|
||||
|
||||
CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc;
|
||||
|
||||
CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0];
|
||||
CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2];
|
||||
CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4];
|
||||
CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6];
|
||||
|
||||
CAN->sMsgObj[0].CRR = 1 + msgobj;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_ReceiveMessage
|
||||
* Description : Gets the message, if received.
|
||||
* Input : - msgobj: specifies the Message object number, from 0 to 31.
|
||||
* - release: specifies the message release indicator.
|
||||
* This parameter can be one of the following values:
|
||||
* - TRUE: the message object is released when getting
|
||||
* the data.
|
||||
* - FALSE: the message object is not released.
|
||||
* - pCanMsg: pointer to the message structure where received
|
||||
* data is copied.
|
||||
* Output : None
|
||||
* Return : An ErrorStatus enumuration value:
|
||||
* - SUCCESS: Reception OK
|
||||
* - ERROR: No message pending
|
||||
*******************************************************************************/
|
||||
ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg)
|
||||
{
|
||||
if (!CAN_IsMessageWaiting(msgobj))
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
CAN->SR &= ~CAN_SR_RXOK;
|
||||
|
||||
/* read the message contents*/
|
||||
CAN->sMsgObj[1].CMR = CAN_CMR_MASK
|
||||
| CAN_CMR_ARB
|
||||
| CAN_CMR_CONTROL
|
||||
| CAN_CMR_CLRINTPND
|
||||
| (release ? CAN_CMR_TXRQSTNEWDAT : 0)
|
||||
| CAN_CMR_DATAA
|
||||
| CAN_CMR_DATAB;
|
||||
|
||||
CAN->sMsgObj[1].CRR = 1 + msgobj;
|
||||
|
||||
if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0)
|
||||
{
|
||||
/* standard ID*/
|
||||
pCanMsg->IdType = CAN_STD_ID;
|
||||
pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* extended ID*/
|
||||
pCanMsg->IdType = CAN_EXT_ID;
|
||||
pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF);
|
||||
pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11);
|
||||
pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27);
|
||||
}
|
||||
|
||||
pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F;
|
||||
|
||||
pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R;
|
||||
pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8);
|
||||
pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R;
|
||||
pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8);
|
||||
pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R;
|
||||
pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8);
|
||||
pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R;
|
||||
pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_WaitEndOfTx
|
||||
* Description : Waits until current transmission is finished.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : An ErrorStatus enumuration value:
|
||||
* - SUCCESS: Transmission ended
|
||||
* - ERROR: Transmission did not occur yet
|
||||
*******************************************************************************/
|
||||
ErrorStatus CAN_WaitEndOfTx(void)
|
||||
{
|
||||
if ((CAN->SR & CAN_SR_TXOK) == 0)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
CAN->SR &= ~CAN_SR_TXOK;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_BasicSendMessage
|
||||
* Description : Starts transmission of a message in BASIC mode. This mode
|
||||
* does not use the message RAM.
|
||||
* Input : pCanMsg: Pointer to the message structure containing data to
|
||||
* transmit.
|
||||
* Output : None
|
||||
* Return : An ErrorStatus enumuration value:
|
||||
* - SUCCESS: Transmission OK
|
||||
* - ERROR: No transmission
|
||||
*******************************************************************************/
|
||||
ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg)
|
||||
{
|
||||
/* clear NewDat bit in IF2 to detect next reception*/
|
||||
CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT;
|
||||
|
||||
CAN->SR &= ~CAN_SR_TXOK;
|
||||
CAN->sMsgObj[0].CMR = CAN_CMR_WRRD
|
||||
| CAN_CMR_ARB
|
||||
| CAN_CMR_CONTROL
|
||||
| CAN_CMR_DATAA
|
||||
| CAN_CMR_DATAB;
|
||||
|
||||
if (pCanMsg->IdType == CAN_STD_ID)
|
||||
{
|
||||
/* standard ID*/
|
||||
CAN->sMsgObj[0].A1R = 0;
|
||||
CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* extended ID*/
|
||||
CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id);
|
||||
CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id);
|
||||
}
|
||||
|
||||
CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc;
|
||||
|
||||
CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0];
|
||||
CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2];
|
||||
CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4];
|
||||
CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6];
|
||||
|
||||
/* request transmission*/
|
||||
if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY )
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_BasicReceiveMessage
|
||||
* Description : Gets the message in BASIC mode, if received. This mode does
|
||||
* not use the message RAM.
|
||||
* Input : pCanMsg: pointer to the message structure where message is copied.
|
||||
* Output : None
|
||||
* Return : An ErrorStatus enumuration value:
|
||||
* - SUCCESS: Reception OK
|
||||
* - ERROR: No message pending
|
||||
*******************************************************************************/
|
||||
ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg)
|
||||
{
|
||||
if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
CAN->SR &= ~CAN_SR_RXOK;
|
||||
|
||||
CAN->sMsgObj[1].CMR = CAN_CMR_ARB
|
||||
| CAN_CMR_CONTROL
|
||||
| CAN_CMR_DATAA
|
||||
| CAN_CMR_DATAB;
|
||||
|
||||
if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0)
|
||||
{
|
||||
/* standard ID*/
|
||||
pCanMsg->IdType = CAN_STD_ID;
|
||||
pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* extended ID*/
|
||||
pCanMsg->IdType = CAN_EXT_ID;
|
||||
pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF);
|
||||
pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11);
|
||||
pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27);
|
||||
}
|
||||
|
||||
pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F;
|
||||
|
||||
pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R;
|
||||
pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8);
|
||||
pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R;
|
||||
pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8);
|
||||
pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R;
|
||||
pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8);
|
||||
pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R;
|
||||
pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_EnterInitMode
|
||||
* Description : Switchs the CAN into initialization mode. This function must
|
||||
* be used in conjunction with CAN_LeaveInitMode().
|
||||
* Input : InitMask: specifies the CAN configuration in normal mode.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void CAN_EnterInitMode(u8 InitMask)
|
||||
{
|
||||
CAN->CR = InitMask | CAN_CR_INIT;
|
||||
CAN->SR = 0; /* reset the status*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_LeaveInitMode
|
||||
* Description : Leaves the initialization mode (switch into normal mode).
|
||||
* This function must be used in conjunction with CAN_EnterInitMode().
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void CAN_LeaveInitMode(void)
|
||||
{
|
||||
CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_EnterTestMode
|
||||
* Description : Switchs the CAN into test mode. This function must be used in
|
||||
* conjunction with CAN_LeaveTestMode().
|
||||
* Input : TestMask: specifies the configuration in test modes.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void CAN_EnterTestMode(u8 TestMask)
|
||||
{
|
||||
CAN->CR |= CAN_CR_TEST;
|
||||
CAN->TESTR |= TestMask;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_LeaveTestMode
|
||||
* Description : Leaves the current test mode (switch into normal mode).
|
||||
* This function must be used in conjunction with CAN_EnterTestMode().
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void CAN_LeaveTestMode(void)
|
||||
{
|
||||
CAN->CR |= CAN_CR_TEST;
|
||||
CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC);
|
||||
CAN->CR &= ~CAN_CR_TEST;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_ReleaseTxMessage
|
||||
* Description : Releases the transmit message object.
|
||||
* Input : - msgobj: specifies the Message object number, from 0 to 31.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void CAN_ReleaseTxMessage(u32 msgobj)
|
||||
{
|
||||
CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT;
|
||||
CAN->sMsgObj[0].CRR = 1 + msgobj;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_ReleaseRxMessage
|
||||
* Description : Releases the receive message object.
|
||||
* Input : - msgobj: specifies the Message object number, from 0 to 31.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void CAN_ReleaseRxMessage(u32 msgobj)
|
||||
{
|
||||
CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT;
|
||||
CAN->sMsgObj[1].CRR = 1 + msgobj;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_IsMessageWaiting
|
||||
* Description : Tests the waiting status of a received message.
|
||||
* Input : - msgobj: specifies the Message object number, from 0 to 31.
|
||||
* Output : None
|
||||
* Return : A non-zero value if the corresponding message object has
|
||||
* received a message waiting to be copied, else 0.
|
||||
*******************************************************************************/
|
||||
u32 CAN_IsMessageWaiting(u32 msgobj)
|
||||
{
|
||||
return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16)));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_IsTransmitRequested
|
||||
* Description : Tests the request status of a transmitted message.
|
||||
* Input : - msgobj: specifies the Message object number, from 0 to 31.
|
||||
* Output : None
|
||||
* Return : A non-zero value if the corresponding message is requested
|
||||
* to transmit, else 0.
|
||||
*******************************************************************************/
|
||||
u32 CAN_IsTransmitRequested(u32 msgobj)
|
||||
{
|
||||
return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16)));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_IsInterruptPending
|
||||
* Description : Tests the interrupt status of a message object.
|
||||
* Input : - msgobj: specifies the Message object number, from 0 to 31.
|
||||
* Output : None
|
||||
* Return : A non-zero value if the corresponding message has an
|
||||
* interrupt pending, else 0.
|
||||
*******************************************************************************/
|
||||
u32 CAN_IsInterruptPending(u32 msgobj)
|
||||
{
|
||||
return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16)));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_IsObjectValid
|
||||
* Description : Tests the validity of a message object (ready to use).
|
||||
* Input : - msgobj: specifies the Message object number, from 0 to 31.
|
||||
* Output : None
|
||||
* Return : A non-zero value if the corresponding message object is
|
||||
* valid, else 0.
|
||||
*******************************************************************************/
|
||||
u32 CAN_IsObjectValid(u32 msgobj)
|
||||
{
|
||||
return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16)));
|
||||
}
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
591
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c
Normal file
591
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c
Normal file
|
@ -0,0 +1,591 @@
|
|||
/********************
|
||||
* Original work (C) COPYRIGHT 2006 STMicroelectronics **************************
|
||||
* Modifications (C) CopyRight 2006 Richard barry
|
||||
* File Name : 91x_enet.c
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : May 2006
|
||||
* Description : ENET library functions
|
||||
********************************************************************************
|
||||
* History:
|
||||
* May 2006: v1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "91x_lib.h"
|
||||
#include "string.h" //include when using memcpy function
|
||||
|
||||
/* Include of other module interface headers ---------------------------------*/
|
||||
/* Local includes ------------------------------------------------------------*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#ifndef NULL
|
||||
#define NULL (0)
|
||||
#endif
|
||||
/* Function return values */
|
||||
#define ENET_OK (1)
|
||||
#define ENET_NOK (0)
|
||||
|
||||
/* PHY interface constants. */
|
||||
#define STE100P_STATUS_REG 0x01
|
||||
#define STE100P_CONTROL_REG 0x00
|
||||
#define STE100P_LINK_ABILITY 0x05
|
||||
#define STE100P_STATUS_LINKED 0x0004
|
||||
#define STE100P_AUTO_NEGOTIATE_ABILITY 0x1000
|
||||
#define STE100P_AUTO_NEGOTIATE_COMPLETE 0x20
|
||||
#define STE100P_10HALF 0x0020
|
||||
#define STE100P_10FULL 0x0040
|
||||
#define STE100P_100HALF 0x0080
|
||||
#define STE100P_100FULL 0x0100
|
||||
#define STE100P_CTRL_FULL 0x0100
|
||||
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
#define ENET_NUM_RX_BUFFERS 8
|
||||
|
||||
static ENET_DMADSCRBase dmaTxDscrBase, dmaRxDscrBase[ ENET_NUM_RX_BUFFERS ];
|
||||
static u8 RxBuff[ ENET_NUM_RX_BUFFERS ][ENET_BUFFER_SIZE];
|
||||
u8 TxBuff[ENET_BUFFER_SIZE];
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
extern MEMCOPY_L2S_BY4();
|
||||
|
||||
/* Interface functions -------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_SetMACConfig(ENET_MACConfig * MAC_Config)
|
||||
* Description : MAC Control Register Configuration
|
||||
* Input : MAC_Config structure
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void ENET_MACControlConfig(ENET_MACConfig *MAC_Config)
|
||||
{
|
||||
/* ReceiveALL bit */
|
||||
if (MAC_Config->ReceiveALL==ENABLE) ENET_MAC->MCR |= MAC_MCR_RA;
|
||||
else ENET_MAC->MCR &=~MAC_MCR_RA;
|
||||
|
||||
/* MIIPrescaler */
|
||||
ENET_MAC->MCR &=~(0x3<<24);
|
||||
if ((MAC_Config->MIIPrescaler) == MIIPrescaler_2)
|
||||
ENET_MAC->MCR |=0x1<<24;
|
||||
|
||||
/* Loopback mode */
|
||||
if (MAC_Config->LoopbackMode==ENABLE)
|
||||
{
|
||||
ENET_MAC->MCR &=~MAC_MCR_LM;
|
||||
ENET_MAC->MCR |=0x1<<21;
|
||||
ENET_MAC->MCR &=~MAC_MCR_DRO; /*enable frame reception during transmission*/
|
||||
}
|
||||
|
||||
/* Address filtering mode */
|
||||
ENET_MAC->MCR &=~MAC_MCR_AFM;
|
||||
ENET_MAC->MCR |= MAC_Config->AddressFilteringMode;
|
||||
|
||||
/* VLAN Filtering Mode */
|
||||
ENET_MAC->MCR |= (MAC_Config->VLANFilteringMode)<<15;
|
||||
|
||||
/*Wrong Frame Pass */
|
||||
if (MAC_Config->PassWrongFrame == ENABLE) ENET_MAC->MCR |=MAC_MCR_PWF;
|
||||
else ENET_MAC->MCR &=~MAC_MCR_PWF;
|
||||
|
||||
/* Late Collision Retransmission*/
|
||||
if (MAC_Config->LateCollision == ENABLE) ENET_MAC->MCR |=MAC_MCR_ELC;
|
||||
else ENET_MAC->MCR &=~MAC_MCR_ELC;
|
||||
|
||||
/* Broadcast Frame Reception */
|
||||
if (MAC_Config->BroadcastFrameReception == ENABLE) ENET_MAC->MCR &=~MAC_MCR_DBF;
|
||||
else ENET_MAC->MCR |=MAC_MCR_DBF;
|
||||
|
||||
/* PacketRetry */
|
||||
if (MAC_Config->PacketRetry == ENABLE) ENET_MAC->MCR &=~MAC_MCR_DPR;
|
||||
else ENET_MAC->MCR |=MAC_MCR_DPR;
|
||||
|
||||
/* RxFrameFiltering */
|
||||
if (MAC_Config->RxFrameFiltering == ENABLE) ENET_MAC->MCR |=MAC_MCR_RVFF;
|
||||
else ENET_MAC->MCR &=~MAC_MCR_RVFF;
|
||||
|
||||
/* AutomaticPadRemoval */
|
||||
if (MAC_Config->AutomaticPadRemoval == ENABLE) ENET_MAC->MCR |=MAC_MCR_APR;
|
||||
else ENET_MAC->MCR &=~MAC_MCR_APR;
|
||||
|
||||
/* DefferalCheck */
|
||||
if (MAC_Config->DeferralCheck == ENABLE) ENET_MAC->MCR |=MAC_MCR_DCE;
|
||||
else ENET_MAC->MCR &=~MAC_MCR_DCE;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_SetOperatingMode
|
||||
* Description : Sets the Operating mode
|
||||
* Input : ENET_OperatingMode:(see ENET_OperatingMode in 91x_enet.h)
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
portBASE_TYPE ENET_SetOperatingMode( void )
|
||||
{
|
||||
unsigned portLONG ulStatusReg, ulControlReg, ulLinkAbilityReg;
|
||||
|
||||
/* Link status is latched, so read twice to get current value */
|
||||
ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG);
|
||||
ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG);
|
||||
|
||||
if( !( ulStatusReg & STE100P_STATUS_LINKED ) )
|
||||
{
|
||||
/* No Link. */
|
||||
return pdFAIL;
|
||||
}
|
||||
|
||||
ulControlReg = ENET_MIIReadReg(0, STE100P_CONTROL_REG);
|
||||
if (ulControlReg & STE100P_AUTO_NEGOTIATE_ABILITY)
|
||||
{
|
||||
/* AutoNegotiation is enabled. */
|
||||
if (!(ulStatusReg & STE100P_AUTO_NEGOTIATE_COMPLETE))
|
||||
{
|
||||
/* Auto-negotiation in progress. */
|
||||
return pdFAIL;
|
||||
}
|
||||
|
||||
ulLinkAbilityReg = ENET_MIIReadReg(0, STE100P_LINK_ABILITY);
|
||||
if( ( ulLinkAbilityReg & STE100P_100FULL ) || ( ulLinkAbilityReg & STE100P_10FULL ) )
|
||||
{
|
||||
ENET_MAC->MCR |=MAC_MCR_FDM; /* full duplex mode */
|
||||
ENET_MAC->MCR &=~MAC_MCR_DRO; /* enable frame reception during transmission */
|
||||
}
|
||||
else
|
||||
{
|
||||
ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */
|
||||
ENET_MAC->MCR |=MAC_MCR_DRO; /* disable frame reception during transmission */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if( ulStatusReg & STE100P_CTRL_FULL )
|
||||
{
|
||||
ENET_MAC->MCR |=MAC_MCR_FDM; /* full duplex mode */
|
||||
ENET_MAC->MCR &=~MAC_MCR_DRO; /* enable frame reception during transmission */
|
||||
}
|
||||
else
|
||||
{
|
||||
ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */
|
||||
ENET_MAC->MCR |=MAC_MCR_DRO; /* disable frame reception during transmission */
|
||||
}
|
||||
}
|
||||
|
||||
return pdPASS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_MIIWriteReg
|
||||
* Description : Writes a value on the PHY registers
|
||||
* Input : phyDev PHY device address
|
||||
: phyReg PHY register to be written
|
||||
* : phyVal PHY register value
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32 phyVal)
|
||||
{
|
||||
|
||||
volatile u32 addr;
|
||||
volatile u32 res; /* temporary result for address register status */
|
||||
volatile u32 timeout;
|
||||
|
||||
/* Prepare the MII register address */
|
||||
addr = 0;
|
||||
addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */
|
||||
addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */
|
||||
addr |= MAC_MII_ADDR_MII_WRITE; /* in write mode */
|
||||
addr |= MAC_MII_ADDR_MII_BUSY;
|
||||
|
||||
/* Check for the Busy flag */
|
||||
timeout=0;
|
||||
do
|
||||
{
|
||||
timeout++;
|
||||
res = ENET_MAC->MIIA;
|
||||
} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO));
|
||||
|
||||
/* Give the value to the MII data register */
|
||||
ENET_MAC->MIID = (phyVal & 0xFFFF);
|
||||
|
||||
/* write the result value into the MII Address register */
|
||||
ENET_MAC->MIIA =addr;
|
||||
|
||||
/* Check for the Busy flag */
|
||||
timeout=0;
|
||||
do
|
||||
{
|
||||
timeout++;
|
||||
res = ENET_MAC->MIIA;
|
||||
} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO));
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_MIIReadReg
|
||||
* Description : Writes a value on the PHY
|
||||
* Input : phyDev PHY device address
|
||||
* : phyReg PHY register to be read
|
||||
* Output : None
|
||||
* Return : The read value (16 bits)
|
||||
*******************************************************************************/
|
||||
u32 ENET_MIIReadReg (u8 phyDev, u32 phyReg )
|
||||
{
|
||||
|
||||
u32 rValue;
|
||||
u32 addr;
|
||||
u32 res; /* temporary result for address register status */
|
||||
u32 timeout; /* timeout value for read process */
|
||||
|
||||
/* prepare the MII register address */
|
||||
addr = 0;
|
||||
addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */
|
||||
addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */
|
||||
addr &= ~(MAC_MII_ADDR_MII_WRITE); /* ... in read mode */
|
||||
addr |= MAC_MII_ADDR_MII_BUSY;
|
||||
|
||||
/* Check for the Busy flag */
|
||||
timeout = 0;
|
||||
|
||||
do
|
||||
{
|
||||
timeout++;
|
||||
res = ENET_MAC->MIIA;
|
||||
} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO));
|
||||
|
||||
/* write the result value into the MII Address register */
|
||||
ENET_MAC->MIIA = addr;
|
||||
|
||||
/* Check for the Busy flag */
|
||||
timeout = 0;
|
||||
|
||||
do
|
||||
{
|
||||
timeout++;
|
||||
res = ENET_MAC->MIIA;
|
||||
} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO));
|
||||
|
||||
/* read the result value from data register*/
|
||||
rValue = ENET_MAC->MIID;
|
||||
|
||||
return (rValue & 0x0000FFFF);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_RxDscrInit
|
||||
* Description : Initializes the Rx ENET descriptor chain. Single Descriptor
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
|
||||
void ENET_RxDscrInit(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for( i = 0; i < ENET_NUM_RX_BUFFERS; i++ )
|
||||
{
|
||||
/* Assign temp Rx array to the ENET buffer */
|
||||
dmaRxDscrBase[ i ].dmaAddr = (u32)&(RxBuff[ i ][ 0 ]);
|
||||
|
||||
/* Initialize RX ENET Status and control */
|
||||
dmaRxDscrBase[ i ].dmaStatCntl = 0x4000;
|
||||
|
||||
/* Initialize the next descriptor- In our case its single descriptor */
|
||||
dmaRxDscrBase[ i ].dmaNext = (u32)&(dmaRxDscrBase[i+1]) | 0x01;
|
||||
|
||||
/* Set the max packet size */
|
||||
dmaRxDscrBase[ i ].dmaStatCntl = ENET_MAX_PACKET_SIZE | ENET_NEXT_ENABLE;
|
||||
|
||||
/* Setting the VALID bit */
|
||||
dmaRxDscrBase[ i ].dmaPackStatus = DMA_DSCR_RX_STATUS_VALID_MSK;
|
||||
}
|
||||
|
||||
dmaRxDscrBase[ ENET_NUM_RX_BUFFERS - 1 ].dmaNext = (u32)&(dmaRxDscrBase[ 0 ]);
|
||||
|
||||
/* Setting the RX NEXT Descriptor Register inside the ENET */
|
||||
ENET_DMA->RXNDAR = (u32)&(dmaRxDscrBase) | 0x01;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_TxDscrInit
|
||||
* Description : Initializes the Tx ENET descriptor chain with single descriptor
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
|
||||
void ENET_TxDscrInit(void)
|
||||
{
|
||||
|
||||
/* ENET Start Address */
|
||||
dmaTxDscrBase.dmaAddr = (u32)TxBuff;
|
||||
|
||||
/* Next Descriptor Address */
|
||||
dmaTxDscrBase.dmaNext = (u32)&(dmaTxDscrBase);
|
||||
|
||||
/* Initialize ENET status and control */
|
||||
dmaTxDscrBase.dmaStatCntl = 0;
|
||||
|
||||
/* Tx next set to Tx decriptor base */
|
||||
ENET_DMA->TXNDAR = (u32)&(dmaTxDscrBase);
|
||||
|
||||
/* Enable next enable */
|
||||
ENET_DMA->TXNDAR |= DMA_DSCR_NXT_NPOL_EN;
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_Init
|
||||
* Description : ENET MAC, PHY and DMA initializations
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void ENET_Init ()
|
||||
{
|
||||
|
||||
vu32 regValue;
|
||||
ENET_MACConfig *MAC_Config;
|
||||
ENET_MACConfig config;
|
||||
|
||||
/* De-assert the SRESET bit of ENET + MAC devices */
|
||||
ENET_DMA->SCR &=~DMA_SCR_SRESET;
|
||||
MAC_Config =&config;
|
||||
/* Initialize MAC control register with common values */
|
||||
MAC_Config->ReceiveALL = DISABLE;
|
||||
if (SCU_GetHCLKFreqValue() > 50000)
|
||||
MAC_Config->MIIPrescaler = MIIPrescaler_2;
|
||||
MAC_Config->LoopbackMode = DISABLE;
|
||||
MAC_Config->AddressFilteringMode = MAC_Perfect_Multicast_Perfect;
|
||||
MAC_Config->VLANFilteringMode = VLANfilter_VLTAG;
|
||||
MAC_Config->PassWrongFrame = DISABLE;
|
||||
MAC_Config->LateCollision = DISABLE;
|
||||
MAC_Config->BroadcastFrameReception = ENABLE;
|
||||
MAC_Config->PacketRetry = ENABLE;
|
||||
MAC_Config->RxFrameFiltering = ENABLE;
|
||||
MAC_Config->AutomaticPadRemoval = ENABLE;
|
||||
MAC_Config->DeferralCheck = ENABLE;
|
||||
|
||||
/* Configure MAC control register */
|
||||
ENET_MACControlConfig(MAC_Config);
|
||||
|
||||
/* DMA initialization */
|
||||
/* Read the ENET DMA Status and Control Register */
|
||||
regValue = ENET_DMA->SCR;
|
||||
|
||||
/* Setup Tx Max burst size */
|
||||
regValue &= ~(u32)DMA_SCR_TX_MAX_BURST_SZ;
|
||||
regValue |= (u32)DMA_SCR_TX_MAX_BURST_SZ_VAL;
|
||||
|
||||
/* Setup Rx Max Burst size */
|
||||
regValue &= ~(u32)DMA_SCR_RX_MAX_BURST_SZ;
|
||||
regValue |= (u32)DMA_SCR_RX_MAX_BURST_SZ_VAL;
|
||||
|
||||
/* Write Tx & Rx burst size to the ENET status and control register */
|
||||
ENET_DMA->SCR = regValue;
|
||||
|
||||
/* Put the PHY in reset mode */
|
||||
ENET_MIIWriteReg(0x0,MAC_MII_REG_XCR, 0x8000);
|
||||
|
||||
/* Delay to assure PHY reset */
|
||||
vTaskDelay( 3000 / portTICK_RATE_MS );
|
||||
|
||||
/* initialize the opearting mode */
|
||||
while( ENET_SetOperatingMode() == pdFAIL )
|
||||
{
|
||||
vTaskDelay( 3000 / portTICK_RATE_MS );
|
||||
}
|
||||
|
||||
/*set MAC physical*/
|
||||
//ENET_MAC->MAH = (MAC_ADDR5<<8) + MAC_ADDR4;
|
||||
//ENET_MAC->MAL = (MAC_ADDR3<<24) + (MAC_ADDR2<<16) + (MAC_ADDR1<<8) + MAC_ADDR0;
|
||||
|
||||
/* Initialize Rx and Tx descriptors in memory */
|
||||
ENET_TxDscrInit();
|
||||
ENET_RxDscrInit();
|
||||
|
||||
// What's happening ???
|
||||
#ifdef DEBUG
|
||||
//int pippo = 1; // Do NOT remove!!!
|
||||
#endif
|
||||
}
|
||||
|
||||
/********************************************************************************
|
||||
* Function Name : ENET_HandleRxPkt
|
||||
* Description : receive a packet and copy it to memory pointed by ppkt.
|
||||
* Input : ppkt: pointer on application receive buffer.
|
||||
* Output : None
|
||||
* Return : ENET_NOK - If there is no packet
|
||||
* : ENET_OK - If there is a packet
|
||||
*******************************************************************************/
|
||||
u32 ENET_HandleRxPkt ( void *ppkt)
|
||||
{
|
||||
ENET_DMADSCRBase *pDescr;
|
||||
u16 size;
|
||||
static int iNextRx = 0;
|
||||
|
||||
if( dmaRxDscrBase[ iNextRx ].dmaPackStatus & DMA_DSCR_RX_STATUS_VALID_MSK )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
pDescr = &dmaRxDscrBase[ iNextRx ];
|
||||
|
||||
/*Get the size of the packet*/
|
||||
size = ((pDescr->dmaPackStatus & 0x7ff) - 4);
|
||||
|
||||
//MEMCOPY_L2S_BY4((u8*)ppkt, RxBuff, size); /*optimized memcopy function*/
|
||||
memcpy(ppkt, RxBuff[iNextRx], size); //string.h library*/
|
||||
|
||||
/* Give the buffer back to ENET */
|
||||
pDescr->dmaPackStatus = DMA_DSCR_RX_STATUS_VALID_MSK;
|
||||
|
||||
iNextRx++;
|
||||
|
||||
if( iNextRx >= ENET_NUM_RX_BUFFERS )
|
||||
{
|
||||
iNextRx = 0;
|
||||
}
|
||||
|
||||
/* Return no error */
|
||||
return size;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_TxPkt
|
||||
* Description : Transmit a packet
|
||||
* Input : ppkt: pointer to application packet Buffer
|
||||
* : size: Tx Packet size
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
|
||||
u8 *pcGetNextBuffer( void )
|
||||
{
|
||||
if( dmaTxDscrBase.dmaPackStatus & DMA_DSCR_TX_STATUS_VALID_MSK )
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
else
|
||||
{
|
||||
return ( unsigned char * ) TxBuff;
|
||||
}
|
||||
}
|
||||
|
||||
void ENET_TxPkt(void *ppkt, u16 size)
|
||||
{
|
||||
/* Setting the Frame Length*/
|
||||
dmaTxDscrBase.dmaStatCntl = (size&0xFFF);
|
||||
|
||||
/* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/
|
||||
dmaTxDscrBase.dmaPackStatus = DMA_DSCR_TX_STATUS_VALID_MSK;
|
||||
|
||||
/* Start the transmit operation */
|
||||
ENET_DMA->TXSTR|= DMA_TX_START_FETCH;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_Start
|
||||
* Description : Enables ENET MAC reception / transmission & starts DMA fetch
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
|
||||
void ENET_Start ( void)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
/* Force a ENET abort by software for the receive block */
|
||||
ENET_DMA->RXSTR &=~ DMA_RX_START_DMA_EN;
|
||||
|
||||
/* Force a ENET abort by software for the transmit block */
|
||||
ENET_DMA->TXSTR &=~DMA_TX_START_DMA_EN;
|
||||
|
||||
/* Reset all interrupts */
|
||||
ENET_DMA->ISR = 0xFFFFFFFF;
|
||||
|
||||
/* Setup Descriptor Fetch ENET_PhyDelay for Receive Block */
|
||||
value = ENET_DMA->RXSTR;
|
||||
value &= ~( DMA_RX_START_DFETCH_DLY );
|
||||
value |= DMA_RX_START_DFETCH_DEFAULT;
|
||||
ENET_DMA->RXSTR= value;
|
||||
|
||||
/* Setup Descriptor Fetch ENET_PhyDelay for Transmit Block */
|
||||
value = ENET_DMA->TXSTR;
|
||||
value &= ~( DMA_TX_START_DFETCH_DLY );
|
||||
value |= DMA_TX_START_DFETCH_DEFAULT;
|
||||
ENET_DMA->TXSTR= value;
|
||||
|
||||
/* Set Tx underrun bit */
|
||||
value &= ~( DMA_TX_START_URUN );
|
||||
value |= DMA_TX_START_URUN;
|
||||
ENET_DMA->TXSTR = value;
|
||||
|
||||
/* Clear the interrupts */
|
||||
ENET_DMA->IER = 0x0;
|
||||
|
||||
/* MAC TX enable */
|
||||
ENET_MAC->MCR|= MAC_MCR_TE;
|
||||
|
||||
/* MAC RX enable */
|
||||
ENET_MAC->MCR|= MAC_MCR_RE;
|
||||
|
||||
/* Start the DMA Fetch */
|
||||
ENET_DMA->RXSTR|= DMA_RX_START_FETCH;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_InitClocksGPIO
|
||||
* Description : Reset, clocks & GPIO Ethernet Pin initializations
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void ENET_InitClocksGPIO(void)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_Struct;
|
||||
|
||||
SCU_AHBPeriphClockConfig(__ENET, ENABLE);
|
||||
SCU_AHBPeriphReset(__ENET,DISABLE);
|
||||
SCU_PHYCLKConfig(ENABLE);
|
||||
|
||||
GPIO_DeInit(GPIO1);
|
||||
GPIO_Struct.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 |GPIO_Pin_3 |GPIO_Pin_4 |GPIO_Pin_7 ;
|
||||
GPIO_Struct.GPIO_Type = GPIO_Type_PushPull;
|
||||
GPIO_Struct.GPIO_Direction = GPIO_PinOutput;
|
||||
GPIO_Struct.GPIO_IPConnected = GPIO_IPConnected_Disable;
|
||||
GPIO_Struct.GPIO_Alternate=GPIO_OutputAlt2;
|
||||
GPIO_Init(GPIO1, &GPIO_Struct);
|
||||
|
||||
|
||||
GPIO_DeInit(GPIO5);
|
||||
GPIO_Struct.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
|
||||
GPIO_Struct.GPIO_Type = GPIO_Type_PushPull;
|
||||
GPIO_Struct.GPIO_Direction = GPIO_PinOutput;
|
||||
GPIO_Struct.GPIO_IPConnected = GPIO_IPConnected_Disable;
|
||||
GPIO_Struct.GPIO_Alternate=GPIO_OutputAlt2;
|
||||
GPIO_Init(GPIO5, &GPIO_Struct);
|
||||
|
||||
}
|
||||
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics *******************/
|
||||
|
||||
|
519
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_fmi.c
Normal file
519
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_fmi.c
Normal file
|
@ -0,0 +1,519 @@
|
|||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_fmi.c
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file provides all the FMI software functions.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* Standard include ----------------------------------------------------------*/
|
||||
#include "91x_fmi.h"
|
||||
|
||||
/* Include of other module interface headers ---------------------------------*/
|
||||
/* Local includes ------------------------------------------------------------*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
#define TIMEOUT 0xFFFFFF /* Timeout value */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Interface functions -------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_BankRemapConfig
|
||||
* Description : Configure the addresses and sizes of bank 0 and bank 1.
|
||||
* Input1 : FMI_BootBankSize: specifies the boot bank size.
|
||||
* This parameter can be one of the following values:
|
||||
* - 0x0: 32KBytes.
|
||||
* - 0x1: 64KBytes.
|
||||
* - 0x2: 128KBytes.
|
||||
* - 0x3: 256KBytes.
|
||||
* - 0x4: 512KBytes.
|
||||
* ....
|
||||
* - 0xB: 64MBytes.
|
||||
* Input2 : FMI_NonBootBankSize: specifies the non boot bank size.
|
||||
* This parameter can be one of the following values:
|
||||
* - 0x0: 8KBytes.
|
||||
* - 0x1: 16KBytes.
|
||||
* - 0x2: 32KBytes.
|
||||
* - 0x3: 64KBytes.
|
||||
* ....
|
||||
* - 0xD: 64MBytes.
|
||||
* Input3 : FMI_BootBankAddress: specifies the address of the boot bank.
|
||||
* Input4 : FMI_NonBootBankAddress: specifies the address of the non
|
||||
* boot bank.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \
|
||||
u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress)
|
||||
{
|
||||
FMI->BBSR = FMI_BootBankSize;
|
||||
FMI->NBBSR = FMI_NonBootBankSize;
|
||||
FMI->BBADR = (FMI_BootBankAddress >> 2);
|
||||
FMI->NBBADR = (FMI_NonBootBankAddress >> 2);
|
||||
FMI->CR |= 0x18; /* Enable bank 1 */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_Config
|
||||
* Description : Configure the FMI.
|
||||
* Input1 : FMI_ReadWaitState: specifies the needed read wait states.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_READ_WAIT_STATE_1: One read wait state.
|
||||
* - FMI_READ_WAIT_STATE_2: Two read wait states.
|
||||
* - FMI_READ_WAIT_STATE_3: Three read wait states.
|
||||
* Input2 : FMI_WriteWaitState: specifies the needed write wait states.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_WRITE_WAIT_STATE_1: One write wait state.
|
||||
* - FMI_WRITE_WAIT_STATE_2: Two write wait states.
|
||||
* Input3 : FMI_PWD: specifies the power down mode status.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_PWD_ENABLE: Enable the PWD.
|
||||
* - FMI_PWD_DISABLE: Disable the PWD.
|
||||
* Input4 : FMI_LVDEN: specifies the low voltage detector status.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_LVD_ENABLE: Enable the LVD.
|
||||
* - FMI_LVD_DISABLE: Disable the LVD.
|
||||
* Input5 : FMI_FreqRange: specifies the working frequency range.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_FREQ_LOW: Low working frequency (up to 66MHz).
|
||||
* - FMI_FREQ_HIGH: High working frequency (above 66MHz) .
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\
|
||||
u16 FMI_LVDEN, u16 FMI_FreqRange)
|
||||
{
|
||||
/* Configure the write wait state value */
|
||||
if (FMI_WriteWaitState == FMI_WRITE_WAIT_STATE_1)
|
||||
{
|
||||
FMI->CR |= FMI_WRITE_WAIT_STATE_1;
|
||||
}
|
||||
else
|
||||
{
|
||||
FMI->CR &= FMI_WRITE_WAIT_STATE_0;
|
||||
}
|
||||
|
||||
/* Write a write flash configuration register command */
|
||||
*(vu16 *)FMI_BANK_1 = 0x60;
|
||||
|
||||
/* Configure the flash configuration register */
|
||||
*(vu16 *)(FMI_BANK_1|FMI_ReadWaitState|FMI_PWD|FMI_LVDEN|FMI_FreqRange) = 0x03;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_EraseSector
|
||||
* Description : Erase the needed sector.
|
||||
* Input : FMI_Sector: specifies the sector to be erased.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_B0S0: FMI bank 0 sector 0.
|
||||
* - FMI_B0S1: FMI bank 0 sector 1.
|
||||
* - FMI_B0S2: FMI bank 0 sector 2.
|
||||
* - FMI_B0S3: FMI bank 0 sector 3.
|
||||
* - FMI_B0S4: FMI bank 0 sector 4.
|
||||
* - FMI_B0S5: FMI bank 0 sector 5.
|
||||
* - FMI_B0S6: FMI bank 0 sector 6.
|
||||
* - FMI_B0S7: FMI bank 0 sector 7.
|
||||
* - FMI_B1S0: FMI bank 1 sector 0.
|
||||
* - FMI_B1S1: FMI bank 1 sector 1.
|
||||
* - FMI_B1S2: FMI bank 1 sector 2.
|
||||
* - FMI_B1S3: FMI bank 1 sector 3.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void FMI_EraseSector(vu32 FMI_Sector)
|
||||
{
|
||||
/* Write an erase set-up command to the sector */
|
||||
*(vu16 *)FMI_Sector = 0x20;
|
||||
|
||||
/* Write an erase confirm command to the sector */
|
||||
*(vu16 *)FMI_Sector = 0xD0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_EraseBank
|
||||
* Description : Erase the needed bank.
|
||||
* Input : FMI_Bank: specifies the bank to be erased.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_BANK_0: FMI bank 0.
|
||||
* - FMI_BANK_1: FMI bank 1.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void FMI_EraseBank(vu32 FMI_Bank)
|
||||
{
|
||||
/* Write a bank erase set-up command to the bank */
|
||||
*(vu16 *)FMI_Bank = 0x80;
|
||||
|
||||
/* Write an erase confirm command to the sector */
|
||||
*(vu16 *)FMI_Bank = 0xD0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_WriteHalfWord
|
||||
* Description : Write a halfword to the needed Flash memory address.
|
||||
* Input 1 : FMI_Address: specifies the address offset where the data will
|
||||
* be written.
|
||||
* Input 2 : FMI_Data: the needed data.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data)
|
||||
{
|
||||
/* Write a program command to the sector to be written */
|
||||
*(vu16 *)(FMI_Address & 0xFFFFFFFC) = 0x40;
|
||||
|
||||
/* Write the halfword to the destination address */
|
||||
*(vu16 *)FMI_Address = FMI_Data;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_WriteOTPHalfWord
|
||||
* Description : Write a halfword to the needed OTP sector address.
|
||||
* Input 1 : FMI_OTPHWAddress: specifies the halfword address offset
|
||||
* where the data will be written.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_OTP_LOW_HALFWORD_0: OTP Low halfword 0.
|
||||
* - FMI_OTP_HIGH_HALFWORD_0: OTP High halfword 0.
|
||||
* - FMI_OTP_LOW_HALFWORD_1: OTP Low halfword 1.
|
||||
* - FMI_OTP_HIGH_HALFWORD_1: OTP High halfword 1.
|
||||
* - FMI_OTP_LOW_HALFWORD_2: OTP Low halfword 2.
|
||||
* - FMI_OTP_HIGH_HALFWORD_2: OTP High halfword 2.
|
||||
* - FMI_OTP_LOW_HALFWORD_3: OTP Low halfword 3.
|
||||
* - FMI_OTP_HIGH_HALFWORD_3: OTP High halfword 3.
|
||||
* - FMI_OTP_LOW_HALFWORD_4: OTP Low halfword 4.
|
||||
* - FMI_OTP_HIGH_HALFWORD_4: OTP High halfword 4.
|
||||
* - FMI_OTP_LOW_HALFWORD_5: OTP Low halfword 5.
|
||||
* - FMI_OTP_HIGH_HALFWORD_5: OTP High halfword 5.
|
||||
* - FMI_OTP_LOW_HALFWORD_6: OTP Low halfword 6.
|
||||
* - FMI_OTP_HIGH_HALFWORD_6: OTP High halfword 6.
|
||||
* - FMI_OTP_LOW_HALFWORD_7: OTP Low halfword 7.
|
||||
* - FMI_OTP_HIGH_HALFWORD_7: OTP High halfword 7.
|
||||
* Input 2 : FMI_OTPData: The needed OTP data.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData)
|
||||
{
|
||||
/* Write a write OTP command to the needed address */
|
||||
*(vu16 *)(FMI_BANK_1) = 0xC0;
|
||||
|
||||
/* Write the halfword to the destination address */
|
||||
*(vu16 *)(FMI_BANK_1 + FMI_OTPHWAddress) = FMI_OTPData;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_ReadWord
|
||||
* Description : Read the correspondent data.
|
||||
* Input : FMI_Address: specifies the needed address.
|
||||
* Output : None
|
||||
* Return : The data contained in the specified address.
|
||||
*******************************************************************************/
|
||||
u32 FMI_ReadWord(u32 FMI_Address)
|
||||
{
|
||||
return(*(u32*)FMI_Address);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_ReadOTPData
|
||||
* Description : Read data from the OTP sector.
|
||||
* Input : FMI_OTPAddress: specifies the address of the data to be read.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_OTP_WORD_0: FMI bank 0 sector 0.
|
||||
* - FMI_OTP_WORD_1: FMI bank 0 sector 1.
|
||||
* - FMI_OTP_WORD_2: FMI bank 0 sector 2.
|
||||
* - FMI_OTP_WORD_3: FMI bank 0 sector 3.
|
||||
* - FMI_OTP_WORD_4: FMI bank 0 sector 4.
|
||||
* - FMI_OTP_WORD_5: FMI bank 0 sector 5.
|
||||
* - FMI_OTP_WORD_6: FMI bank 0 sector 6.
|
||||
* - FMI_OTP_WORD_7: FMI bank 0 sector 7.
|
||||
* Output : None
|
||||
* Return : The needed OTP words.
|
||||
*******************************************************************************/
|
||||
u32 FMI_ReadOTPData(u8 FMI_OTPAddress)
|
||||
{
|
||||
u32 OTP_Data = 0x0;
|
||||
/* write a read OTP sector command */
|
||||
*(vu16 *)(FMI_BANK_1) = 0x98;
|
||||
|
||||
/* Read the correspondent data */
|
||||
OTP_Data = (*(vu32*)(FMI_BANK_1 + FMI_OTPAddress));
|
||||
|
||||
/* Write a read array command */
|
||||
*(vu16 *)(FMI_BANK_1) = 0xFF;
|
||||
|
||||
return OTP_Data;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_GetFlagStatus
|
||||
* Description : Check whether the specified FMI flag is set or not.
|
||||
* Input1 : FMI_Flag: flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_FLAG_SPS: Sector Protection Status Flag.
|
||||
* - FMI_FLAG_PSS: Program Suspend Status Flag.
|
||||
* - FMI_FLAG_PS: Program Status Flag.
|
||||
* - FMI_FLAG_ES: Erase Status Flag.
|
||||
* - FMI_FLAG_ESS: Erase Suspend Status Flag.
|
||||
* - FMI_FLAG_PECS: FPEC Status Flag.
|
||||
* Input2 : FMI_Bank: specifies the needed bank.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_BANK_0: FMI bank 0.
|
||||
* - FMI_BANK_1: FMI bank 1.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank)
|
||||
{
|
||||
u16 FMI_Status_Register = 0;
|
||||
|
||||
/* Write a read status register command */
|
||||
*(vu16 *)FMI_Bank = 0x70;
|
||||
|
||||
/* Wait until operation completion */
|
||||
while(!((*(vu16 *)FMI_Bank) & 0x80));
|
||||
|
||||
/* Read the status register */
|
||||
FMI_Status_Register = *(vu16 *)FMI_Bank;
|
||||
|
||||
/* Write a read array command */
|
||||
*(vu16 *)FMI_Bank = 0xFF;
|
||||
|
||||
if((FMI_Status_Register & FMI_Flag) != RESET)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_GetReadWaitStateValue
|
||||
* Description : Get the current Read wait state value.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : The current read wait states value.
|
||||
*******************************************************************************/
|
||||
u16 FMI_GetReadWaitStateValue(void)
|
||||
{
|
||||
u16 FMI_Configuration_Register = 0;
|
||||
/* Write a read flash configuration register command */
|
||||
*(vu16 *)FMI_BANK_1 = 0x90;
|
||||
|
||||
/* Read the flash configuration register */
|
||||
FMI_Configuration_Register = *(vu16 *)(FMI_BANK_1 + 0x14);
|
||||
|
||||
/* Write a read array command */
|
||||
*(vu16 *)FMI_BANK_1 = 0xFF;
|
||||
|
||||
FMI_Configuration_Register = ((FMI_Configuration_Register>>11) + 1) & 0x3;
|
||||
|
||||
/* Return the wait states value */
|
||||
return FMI_Configuration_Register;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_GetWriteWaitStateValue
|
||||
* Description : Get the current write wait state value.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : The current write wait states value.
|
||||
*******************************************************************************/
|
||||
u16 FMI_GetWriteWaitStateValue(void)
|
||||
{
|
||||
return ((u16)((FMI->CR & 0x100) >> 8));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_SuspendEnable
|
||||
* Description : Suspend command enable.
|
||||
* Input : FMI_Bank: specifies the bank to be suspended.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_BANK_0: FMI bank 0.
|
||||
* - FMI_BANK_1: FMI bank 1.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void FMI_SuspendEnable(vu32 FMI_Bank)
|
||||
{
|
||||
/* Write a suspend command to the bank */
|
||||
*(vu16 *)FMI_Bank = 0xB0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_ResumeEnable
|
||||
* Description : Resume the suspended command.
|
||||
* Input : FMI_Bank: specifies the suspended bank.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_BANK_0: FMI bank 0.
|
||||
* - FMI_BANK_1: FMI bank 1.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void FMI_ResumeEnable(vu32 FMI_Bank)
|
||||
{
|
||||
/* Write a resume command to the bank */
|
||||
*(vu16 *)FMI_Bank = 0xD0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_ClearFlag
|
||||
* Description : Clear the FMI Flags on the correspondent bank.
|
||||
* Input : FMI_Bank: specifies the needed bank.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_BANK_0: FMI bank 0.
|
||||
* - FMI_BANK_1: FMI bank 1.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void FMI_ClearFlag(vu32 FMI_Bank)
|
||||
{
|
||||
/* Write a clear status register command */
|
||||
*(vu16 *)FMI_Bank = 0x50;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_WriteProtectionCmd
|
||||
* Description : Enable or disable the write protection for the needed sector.
|
||||
* Input1 : FMI_Sector: specifies the sector to be protected or
|
||||
* unprotected.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_B0S0: FMI bank 0 sector 0.
|
||||
* - FMI_B0S1: FMI bank 0 sector 1.
|
||||
* - FMI_B0S2: FMI bank 0 sector 2.
|
||||
* - FMI_B0S3: FMI bank 0 sector 3.
|
||||
* - FMI_B0S4: FMI bank 0 sector 4.
|
||||
* - FMI_B0S5: FMI bank 0 sector 5.
|
||||
* - FMI_B0S6: FMI bank 0 sector 6.
|
||||
* - FMI_B0S7: FMI bank 0 sector 7.
|
||||
* - FMI_B1S0: FMI bank 1 sector 0.
|
||||
* - FMI_B1S1: FMI bank 1 sector 1.
|
||||
* - FMI_B1S2: FMI bank 1 sector 2.
|
||||
* - FMI_B1S3: FMI bank 1 sector 3.
|
||||
* Input2 : FMI_NewState: specifies the protection status.
|
||||
* This parameter can be one of the following values:
|
||||
* - ENABLE: Enable the protection.
|
||||
* - DISABLE: Disable the protection.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState)
|
||||
{
|
||||
if (FMI_NewState == ENABLE)
|
||||
{
|
||||
*(vu16*)FMI_Sector = 0x60;
|
||||
*(vu16*)FMI_Sector = 0x01;
|
||||
*(vu16*)FMI_Sector = 0xFF;
|
||||
}
|
||||
else /* DISABLE */
|
||||
{
|
||||
*(vu16*)FMI_Sector = 0x60;
|
||||
*(vu16*)FMI_Sector = 0xD0;
|
||||
*(vu16*)FMI_Sector = 0xFF;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_GetWriteProtectionStatus
|
||||
* Description : Get the write protection status for the needed sector.
|
||||
* Input : FMI_Sector_Mask: specifies the needed sector mask.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_B0S0_MASK: FMI bank 0 sector 0.
|
||||
* - FMI_B0S1_MASK: FMI bank 0 sector 1.
|
||||
* - FMI_B0S2_MASK: FMI bank 0 sector 2.
|
||||
* - FMI_B0S3_MASK: FMI bank 0 sector 3.
|
||||
* - FMI_B0S4_MASK: FMI bank 0 sector 4.
|
||||
* - FMI_B0S5_MASK: FMI bank 0 sector 5.
|
||||
* - FMI_B0S6_MASK: FMI bank 0 sector 6.
|
||||
* - FMI_B0S7_MASK: FMI bank 0 sector 7.
|
||||
* - FMI_B1S0_MASK: FMI bank 1 sector 0.
|
||||
* - FMI_B1S1_MASK: FMI bank 1 sector 1.
|
||||
* - FMI_B1S2_MASK: FMI bank 1 sector 2.
|
||||
* - FMI_B1S3_MASK: FMI bank 1 sector 3.
|
||||
* Output : None
|
||||
* Return : The Protection Status of the needed sector.
|
||||
* - RESET: The needed sector is not write protected.
|
||||
* - SET : The needed sector is write protected.
|
||||
*******************************************************************************/
|
||||
FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Mask)
|
||||
{
|
||||
u16 Protection_Level_1_Register = 0;
|
||||
/* Write a read flash protection level 1 register command */
|
||||
*(vu16 *)FMI_BANK_1 = 0x90;
|
||||
|
||||
/* Read the flash protection level 1 register */
|
||||
Protection_Level_1_Register = *(vu16 *)(FMI_BANK_1 + 0x10);
|
||||
|
||||
/* Write a read array command */
|
||||
*(vu16 *)FMI_BANK_1 = 0xFF;
|
||||
|
||||
if (Protection_Level_1_Register &= FMI_Sector_Mask)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : FMI_WaitForLastOperation
|
||||
* Description : Wait until the last operation (Write halfword, Write OTP
|
||||
* halfword, Erase sector and Erase bank) completion.
|
||||
* Input : FMI_Bank: specifies the bank where the operation is on going.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_BANK_0: FMI bank 0.
|
||||
* - FMI_BANK_1: FMI bank 1.
|
||||
* Output : None
|
||||
* Return : The timeout status.
|
||||
* This parameter can be one of the following values:
|
||||
* - FMI_TIME_OUT_ERROR: Timeout error occurred.
|
||||
* - FMI_NO_TIME_OUT_ERROR: No timeout error.
|
||||
*******************************************************************************/
|
||||
u8 FMI_WaitForLastOperation(vu32 FMI_Bank)
|
||||
{
|
||||
u32 Time_Out = 0;
|
||||
|
||||
/* Write a read status register command */
|
||||
*(vu16 *)(FMI_Bank) = 0x70;
|
||||
|
||||
/* Wait until operation compeletion */
|
||||
while((!((*(vu16 *)FMI_Bank) & 0x80))&&(Time_Out < TIMEOUT ))
|
||||
{
|
||||
Time_Out ++; /* Time Out */
|
||||
}
|
||||
|
||||
/* Write a read array command */
|
||||
*(vu16 *)FMI_Bank = 0xFF;
|
||||
|
||||
if (Time_Out == TIMEOUT)
|
||||
{
|
||||
return FMI_TIME_OUT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return FMI_NO_TIME_OUT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
407
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_gpio.c
Normal file
407
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_gpio.c
Normal file
|
@ -0,0 +1,407 @@
|
|||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_gpio.c
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file provides all the GPIO software functions.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "91x_gpio.h"
|
||||
#include "91x_scu.h"
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : GPIO_DeInit
|
||||
* Description : Deinitializes the GPIOx peripheral registers to their default
|
||||
* reset values.
|
||||
* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
|
||||
/* Reset the GPIO registers values */
|
||||
if(GPIOx == GPIO0)
|
||||
{
|
||||
SCU_APBPeriphReset(__GPIO0,ENABLE);
|
||||
SCU_APBPeriphReset(__GPIO0,DISABLE);
|
||||
SCU->GPIOTYPE[0x00] = 0x0000 ;
|
||||
SCU->GPIOOUT[0x00] = 0x0000;
|
||||
SCU->GPIOIN[0x00] = 0x0000;
|
||||
}
|
||||
|
||||
if(GPIOx == GPIO1)
|
||||
{
|
||||
SCU_APBPeriphReset(__GPIO1,ENABLE);
|
||||
SCU_APBPeriphReset(__GPIO1,DISABLE);
|
||||
SCU->GPIOTYPE[0x01] = 0x0000 ;
|
||||
SCU->GPIOOUT[0x01] = 0x0000;
|
||||
SCU->GPIOIN[0x01] = 0x0000;
|
||||
}
|
||||
|
||||
if(GPIOx == GPIO2)
|
||||
{
|
||||
SCU_APBPeriphReset(__GPIO2,ENABLE);
|
||||
SCU_APBPeriphReset(__GPIO2,DISABLE);
|
||||
SCU->GPIOTYPE[0x02] = 0x0000 ;
|
||||
SCU->GPIOOUT[0x02] = 0x0000;
|
||||
SCU->GPIOIN[0x02] = 0x0000;
|
||||
}
|
||||
|
||||
if(GPIOx == GPIO3)
|
||||
{
|
||||
SCU_APBPeriphReset(__GPIO3,ENABLE);
|
||||
SCU_APBPeriphReset(__GPIO3,DISABLE);
|
||||
SCU->GPIOTYPE[0x03] = 0x0000 ;
|
||||
SCU->GPIOOUT[0x03] = 0x0000;
|
||||
SCU->GPIOIN[0x03] = 0x0000;
|
||||
}
|
||||
|
||||
if(GPIOx == GPIO4)
|
||||
{
|
||||
SCU_APBPeriphReset(__GPIO4,ENABLE);
|
||||
SCU_APBPeriphReset(__GPIO4,DISABLE);
|
||||
SCU->GPIOTYPE[0x04] = 0x0000 ;
|
||||
SCU->GPIOOUT[0x04] = 0x0000;
|
||||
SCU->GPIOIN[0x04] = 0x0000;
|
||||
SCU->GPIOANA = 0x00;
|
||||
}
|
||||
|
||||
if(GPIOx == GPIO5)
|
||||
{
|
||||
SCU_APBPeriphReset(__GPIO5,ENABLE);
|
||||
SCU_APBPeriphReset(__GPIO5,DISABLE);
|
||||
SCU->GPIOTYPE[0x05] = 0x0000 ;
|
||||
SCU->GPIOOUT[0x05] = 0x0000;
|
||||
SCU->GPIOIN[0x05] = 0x0000;
|
||||
}
|
||||
|
||||
if(GPIOx == GPIO6)
|
||||
{
|
||||
SCU_APBPeriphReset(__GPIO6,ENABLE);
|
||||
SCU_APBPeriphReset(__GPIO6,DISABLE);
|
||||
SCU->GPIOTYPE[0x06] = 0x0000 ;
|
||||
SCU->GPIOOUT[0x06] = 0x0000;
|
||||
SCU->GPIOIN[0x06] = 0x0000;
|
||||
}
|
||||
|
||||
if(GPIOx == GPIO7)
|
||||
{
|
||||
SCU_APBPeriphReset(__GPIO7,ENABLE);
|
||||
SCU_APBPeriphReset(__GPIO7,DISABLE);
|
||||
SCU->GPIOOUT[0x07] = 0xAAAA;
|
||||
SCU->GPIOOUT[0x07] = 0x0000;
|
||||
SCU->GPIOIN[0x07] = 0x0000;
|
||||
}
|
||||
|
||||
if(GPIOx == GPIO8)
|
||||
{
|
||||
SCU_APBPeriphReset(__GPIO8,ENABLE);
|
||||
SCU_APBPeriphReset(__GPIO8,DISABLE);
|
||||
SCU->GPIOEMI = 0x00;
|
||||
}
|
||||
|
||||
if(GPIOx == GPIO9)
|
||||
{
|
||||
SCU_APBPeriphReset(__GPIO9,ENABLE);
|
||||
SCU_APBPeriphReset(__GPIO9,DISABLE);
|
||||
SCU->GPIOEMI = 0x00;
|
||||
}
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : GPIO_Init
|
||||
* Description : Initializes the GPIOx peripheral according to the specified
|
||||
* parameters in the GPIO_InitStruct .
|
||||
* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral.
|
||||
* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
|
||||
* contains the configuration information for the specified GPIO
|
||||
* peripheral.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Select pin direction */
|
||||
u8 PinNumber = 0;
|
||||
u8 Counter = 0;
|
||||
u8 GPIO_Number = 0;
|
||||
|
||||
GPIO_Number = GPIO_GetGPIONumber(GPIOx);
|
||||
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Direction == GPIO_PinOutput)
|
||||
{
|
||||
GPIOx->DDR |= GPIO_InitStruct->GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->DDR &= ~GPIO_InitStruct->GPIO_Pin;
|
||||
}
|
||||
|
||||
for (Counter = 0; Counter < 8;Counter++)
|
||||
{
|
||||
/*Search pin number*/
|
||||
PinNumber = (GPIO_InitStruct->GPIO_Pin & (1 <<Counter));
|
||||
if((PinNumber >> Counter) == 1)
|
||||
{
|
||||
/*Output ALternate 0*/
|
||||
SCU->GPIOOUT[GPIO_Number] &= ~(0x3 <<(Counter *2));
|
||||
if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt1)
|
||||
{
|
||||
/*Output ALternate 1*/
|
||||
SCU->GPIOOUT[GPIO_Number] |= 1 << (Counter *2);
|
||||
}
|
||||
if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt2)
|
||||
{
|
||||
/*Output ALternate 2*/
|
||||
SCU->GPIOOUT[GPIO_Number] |= 0x2 << (Counter *2);
|
||||
}
|
||||
if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt3)
|
||||
{
|
||||
/*Output ALternate 3*/
|
||||
SCU->GPIOOUT[GPIO_Number] |= 0x3 << (Counter *2);
|
||||
}
|
||||
|
||||
/*Type configuration: PushPull or Open Collector*/
|
||||
SCU->GPIOTYPE[GPIO_Number] &= ~(0x1 << Counter) ;
|
||||
if(GPIO_InitStruct->GPIO_Type == GPIO_Type_OpenCollector)
|
||||
{
|
||||
/*Open Drain configuration*/
|
||||
SCU->GPIOTYPE[GPIO_Number] |= 0x1 << Counter;
|
||||
}
|
||||
|
||||
/*IP Connected disable*/
|
||||
SCU->GPIOIN[GPIO_Number] &= ~(0x1 << Counter) ;
|
||||
if(GPIO_InitStruct->GPIO_IPConnected == GPIO_IPConnected_Enable)
|
||||
{
|
||||
/*IP Connected enable*/
|
||||
SCU->GPIOIN[GPIO_Number] |= 0x1 << Counter;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : GPIO_StructInit
|
||||
* Description : Initialize the GPIO Init Structure parameters
|
||||
* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
|
||||
* which will be initialized.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Direction = GPIO_PinInput;
|
||||
GPIO_InitStruct->GPIO_Type = GPIO_Type_PushPull;
|
||||
GPIO_InitStruct->GPIO_IPConnected = GPIO_IPConnected_Disable;
|
||||
GPIO_InitStruct->GPIO_Alternate = GPIO_InputAlt1;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : GPIO_ReadBit
|
||||
* Description : Reads the specified port pin
|
||||
* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
|
||||
* : - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x
|
||||
* where x can be (0..7).
|
||||
* Output : None
|
||||
* Return : The port pin value
|
||||
*******************************************************************************/
|
||||
u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin)
|
||||
{
|
||||
if ((((GPIOx->DR[GPIO_Pin<<2])) & GPIO_Pin) != Bit_RESET )
|
||||
{
|
||||
return Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return Bit_RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : GPIO_Read
|
||||
* Description : Reads the specified GPIO data port
|
||||
* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
|
||||
* Output : None
|
||||
* Return : GPIO data port word value.
|
||||
*******************************************************************************/
|
||||
u8 GPIO_Read(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
return (GPIOx->DR[0x3FC]);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : GPIO_WriteBit
|
||||
* Description : Sets or clears the selected data port bit.
|
||||
* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
|
||||
* - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x
|
||||
* where x can be (0..7).
|
||||
* - BitVal: this parameter specifies the value to be written
|
||||
* to the selected bit.
|
||||
* BitVal must be one of the BitAction enum values:
|
||||
* - Bit_RESET: to clear the port pin
|
||||
* - Bit_SET: to set the port pin
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
if(BitVal == Bit_SET)
|
||||
{
|
||||
GPIOx->DR[GPIO_Pin <<2] = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->DR[GPIO_Pin <<2] = 0x00;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : GPIO_Write
|
||||
* Description : Writes the passed value in the selected data GPIOx port
|
||||
* register.
|
||||
* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral.
|
||||
* - PortVal: the value to be written to the data port register.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal)
|
||||
{
|
||||
GPIOx->DR[0x3FC] = PortVal;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : GPIO_EMIConfig
|
||||
* Description : Enables or disables GPIO 8 and 9 in EMI mode.
|
||||
* Input : - NewState: new state of the EMI.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void GPIO_EMIConfig(FunctionalState NewState)
|
||||
{
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
SCU->GPIOEMI = 0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCU->GPIOEMI = 0x00;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : GPIO_ANAPinConfig
|
||||
* Description : Enables or disables pins from GPIO 4 in Analogue mode.
|
||||
* Input :- GPIO_ANAChannel: selects the ADC channel pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_ANAChannel0
|
||||
* GPIO_ANAChannel1
|
||||
* GPIO_ANAChannel2
|
||||
* GPIO_ANAChannel3
|
||||
* GPIO_ANAChannel4
|
||||
* GPIO_ANAChannel5
|
||||
* GPIO_ANAChannel6
|
||||
* GPIO_ANAChannel7
|
||||
* GPIO_ANAChannelALL
|
||||
* - NewState: new state of the port pin.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState)
|
||||
{
|
||||
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
if(GPIO_ANAChannel == GPIO_ANAChannelALL)
|
||||
{
|
||||
SCU->GPIOOUT[4] = 0x0000;
|
||||
SCU->GPIOIN[4] = 0x00;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCU->GPIOOUT[4] &= ~(0x3<<(GPIO_ANAChannel-1));
|
||||
SCU->GPIOIN[4] &= ~GPIO_ANAChannel;
|
||||
}
|
||||
SCU->GPIOANA |= GPIO_ANAChannel;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
SCU->GPIOANA &= ~GPIO_ANAChannel;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : GPIO_GetGPIONumber
|
||||
* Description : searche the GPIO number.
|
||||
* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral.
|
||||
* Output : None
|
||||
* Return : GPIO number
|
||||
*******************************************************************************/
|
||||
u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
|
||||
if(GPIOx == GPIO1)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
if(GPIOx == GPIO2)
|
||||
{
|
||||
return 2;
|
||||
}
|
||||
if(GPIOx == GPIO3)
|
||||
{
|
||||
return 3;
|
||||
}
|
||||
if(GPIOx == GPIO4)
|
||||
{
|
||||
return 4;
|
||||
}
|
||||
if(GPIOx == GPIO5)
|
||||
{
|
||||
return 5;
|
||||
}
|
||||
if(GPIOx == GPIO6)
|
||||
{
|
||||
return 6;
|
||||
}
|
||||
if(GPIOx == GPIO7)
|
||||
{
|
||||
return 7;
|
||||
}
|
||||
if(GPIOx == GPIO8)
|
||||
{
|
||||
return 8;
|
||||
}
|
||||
if(GPIOx == GPIO9)
|
||||
{
|
||||
return 9;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
387
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_it.c
Normal file
387
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_it.c
Normal file
|
@ -0,0 +1,387 @@
|
|||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_it.c
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 03/31/2006 : Beta Version V0.1
|
||||
* Description : Main Interrupt Service Routines.
|
||||
********************************************************************************
|
||||
* This file can be used to describe all the exceptions subroutines
|
||||
* that may occur within user application.
|
||||
* When an interrupt happens, the software will branch automatically
|
||||
* to the corresponding routine according to the interrupt vector
|
||||
* loaded in the PC register.
|
||||
* The following routines are all empty, user can write code for
|
||||
* exceptions handlers and peripherals IRQ interrupts.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 03/31/2006 : Beta Version V0.1
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
#include "FreeRTOSConfig.h"
|
||||
#include "91x_it.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Undefined_Handler
|
||||
* Description : This function Undefined instruction exception.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Undefined_Handler(void)
|
||||
{
|
||||
// NOT USED.
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : SWI_Handler
|
||||
* Description : This function handles SW exception.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SWI_Handler(void)
|
||||
{
|
||||
// NOT USED.
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : Prefetch_Handler
|
||||
* Description : This function handles preftetch abort exception.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Prefetch_Handler(void)
|
||||
{
|
||||
// NOT USED.
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : Abort_Handler
|
||||
* Description : This function handles data abort exception.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Abort_Handler(void)
|
||||
{
|
||||
// NOT USED.
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : FIQ_Handler
|
||||
* Description : This function handles FIQ exception.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void FIQ_Handler(void)
|
||||
{
|
||||
// NOT USED.
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : SW_IRQHandler
|
||||
* Description : This function handles the SW interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SW_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : ARMRX_IRQHandler
|
||||
* Description : This function handles the ARMRX interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void ARMRX_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : ARMTX_IRQHandler
|
||||
* Description : This function handles the ARMTX interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void ARMTX_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM0_IRQHandler
|
||||
* Description : This function handles the TIM0 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void TIM0_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM1_IRQHandler
|
||||
* Description : This function handles the TIM1 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void TIM1_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM2_IRQHandler
|
||||
* Description : This function handles the TIM2 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
//void TIM2_IRQHandler(void)
|
||||
//{
|
||||
//}
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM3_IRQHandler
|
||||
* Description : This function handles the TIM3 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void TIM3_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : USBHP_IRQHandler
|
||||
* Description : This function handles the USBHP interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void USBHP_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : USBLP_IRQHandler
|
||||
* Description : This function handles the USBLP interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void USBLP_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_IRQHandler
|
||||
* Description : This function handles the SCU interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : DMA_IRQHandler
|
||||
* Description : This function handles the DMA interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void DMA_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : CAN_IRQHandler
|
||||
* Description : This function handles the CAN interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void CAN_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : MC_IRQHandler
|
||||
* Description : This function handles the MC interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void MC_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : ADC_IRQHandler
|
||||
* Description : This function handles the ADC interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void ADC_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : UART0_IRQHandler
|
||||
* Description : This function handles the UART0 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART0_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : UART2_IRQHandler
|
||||
* Description : This function handles the UART2 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART2_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : I2C0_IRQHandler
|
||||
* Description : This function handles the I2C0 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void I2C0_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : I2C1_IRQHandler
|
||||
* Description : This function handles the I2C1 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void I2C1_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : SSP0_IRQHandler
|
||||
* Description : This function handles the SSP0 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SSP0_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : SSP1_IRQHandler
|
||||
* Description : This function handles the SSP1 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SSP1_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : LVD_IRQHandler
|
||||
* Description : This function handles the LVD interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void LVD_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : RTC_IRQHandler
|
||||
* Description : This function handles the RTC interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void RTC_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : WIU_IRQHandler
|
||||
* Description : This function handles the WIU interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void WIU_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : EXTIT0_IRQHandler
|
||||
* Description : This function handles the EXTIT0 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void EXTIT0_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : EXTIT1_IRQHandler
|
||||
* Description : This function handles the EXTIT1 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void EXTIT1_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : EXTIT2_IRQHandler
|
||||
* Description : This function handles the EXTIT2 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void EXTIT2_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : EXTIT3_IRQHandler
|
||||
* Description : This function handles the EXTIT3 interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void EXTIT3_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : USBWU_IRQHandler
|
||||
* Description : This function handles the USBWU interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void USBWU_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : PFQBC_IRQHandler
|
||||
* Description : This function handles the PFQBC interrupt request
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void PFQBC_IRQHandler(void)
|
||||
{
|
||||
}
|
||||
|
||||
#if configUSE_WATCHDOG_TICK == 0
|
||||
/* The kernel is not using the watchdog interrupt so it can be defined here. */
|
||||
void WDG_IRQHandler( void )
|
||||
{
|
||||
}
|
||||
#else
|
||||
/* The kernel is not using the timer 2 interrupt so it can be defined here. */
|
||||
void TIM2_IRQHandler( void )
|
||||
{
|
||||
}
|
||||
#endif /* configUSE_WATCHDOG_TICK */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
281
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_lib.c
Normal file
281
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_lib.c
Normal file
|
@ -0,0 +1,281 @@
|
|||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_lib.c
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file provides all peripherals pointers
|
||||
: initialization.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
#define EXT
|
||||
|
||||
/* Standard include ----------------------------------------------------------*/
|
||||
#include "91x_map.h"
|
||||
|
||||
/* Include of other module interface headers ---------------------------------*/
|
||||
/* Local includes ------------------------------------------------------------*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Interface functions -------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
#ifdef DEBUG
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : debug
|
||||
* Description : this function initialize peripherals pointers
|
||||
* Input : no one
|
||||
* Output : no one
|
||||
* Return : no one
|
||||
*******************************************************************************/
|
||||
void debug(void)
|
||||
{
|
||||
|
||||
|
||||
/************************* DMA *************************/
|
||||
|
||||
#ifdef _DMA
|
||||
DMA = (DMA_TypeDef *)DMA_BASE;
|
||||
#endif /* _DMA */
|
||||
|
||||
/************************* DMA *************************/
|
||||
|
||||
|
||||
#ifdef _DMA_Channel0
|
||||
DMA_Channel0= (DMA_Channel_TypeDef *)DMA_Channel0_BASE;
|
||||
#endif /* _DMA_Channel0 */
|
||||
|
||||
#ifdef _DMA_Channel1
|
||||
DMA_Channel1= (DMA_Channel_TypeDef *)DMA_Channel1_BASE;
|
||||
#endif /* _DMA_Channel1 */
|
||||
|
||||
#ifdef _DMA_Channel2
|
||||
DMA_Channel2 = (DMA_Channel_TypeDef *)DMA_Channel2_BASE;
|
||||
#endif /* _DMA_Channel2 */
|
||||
|
||||
#ifdef _DMA_Channel3
|
||||
DMA_Channel3 = (DMA_Channel_TypeDef *)DMA_Channel3_BASE;
|
||||
#endif /* _DMA_Channel3 */
|
||||
|
||||
#ifdef _DMA_Channel4
|
||||
DMA_Channel4 = (DMA_Channel_TypeDef *)DMA_Channel4_BASE;
|
||||
#endif /* _DMA_Channel4 */
|
||||
|
||||
#ifdef _DMA_Channel5
|
||||
DMA_Channel5= (DMA_Channel_TypeDef *)DMA_Channel5_BASE;
|
||||
#endif /* _DMA_Channel5*/
|
||||
|
||||
|
||||
#ifdef _DMA_Channel6
|
||||
DMA_Channel6 = (DMA_Channel_TypeDef *)DMA_Channel6_BASE;
|
||||
#endif /* _DMA_Channel6 */
|
||||
|
||||
#ifdef _DMA_Channel7
|
||||
DMA_Channel7 = (DMA_Channel_TypeDef *)DMA_Channel7_BASE;
|
||||
#endif /* _DMA_Channel7 */
|
||||
|
||||
|
||||
|
||||
/************************* EMI *************************/
|
||||
|
||||
#ifdef _EMI_Bank0
|
||||
EMI_Bank0= (EMI_Bank_TypeDef *)EMI_Bank0_BASE;
|
||||
#endif /* _EMI_Bank0 */
|
||||
|
||||
#ifdef _EMI_Bank1
|
||||
EMI_Bank1= (EMI_Bank_TypeDef *)EMI_Bank1_BASE;
|
||||
#endif /* _EMI_Bank1 */
|
||||
|
||||
#ifdef _EMI_Bank2
|
||||
EMI_Bank2 = (EMI_Bank_TypeDef *)EMI_Bank2_BASE;
|
||||
#endif /* _EMI_Bank2 */
|
||||
|
||||
#ifdef _EMI_Bank3
|
||||
EMI_Bank3 = (EMI_Bank_TypeDef *)EMI_Bank3_BASE;
|
||||
#endif /* _EMI_Bank3 */
|
||||
|
||||
|
||||
|
||||
/************************* AHBAPB *************************/
|
||||
|
||||
#ifdef _AHBAPB0
|
||||
AHBAPB0 = (AHBAPB_TypeDef *)AHBAPB0_BASE;
|
||||
#endif /* _AHBAPB0 */
|
||||
|
||||
#ifdef _AHBAPB1
|
||||
AHBAPB1 = (AHBAPB_TypeDef *)AHBAPB1_BASE;
|
||||
#endif /*_AHBAPB1 */
|
||||
|
||||
|
||||
|
||||
/************************* FMI *************************/
|
||||
|
||||
#ifdef _FMI
|
||||
FMI = (FMI_TypeDef *)FMI_BASE;
|
||||
#endif /* _FMI */
|
||||
|
||||
/************************* VIC *************************/
|
||||
|
||||
#ifdef _VIC0
|
||||
VIC0 = (VIC_TypeDef *)VIC0_BASE;
|
||||
#endif /* _VIC0 */
|
||||
|
||||
#ifdef _VIC1
|
||||
VIC1 = (VIC_TypeDef *)VIC1_BASE;
|
||||
#endif /* _VIC1 */
|
||||
|
||||
/************************* WIU *************************/
|
||||
|
||||
#ifdef _WIU
|
||||
WIU = (WIU_TypeDef *)WIU_BASE;
|
||||
#endif /* _WIU */
|
||||
|
||||
/************************* TIM *************************/
|
||||
|
||||
#ifdef _TIM0
|
||||
TIM0 = (TIM_TypeDef *)TIM0_BASE;
|
||||
#endif /* _TIM0 */
|
||||
|
||||
#ifdef _TIM1
|
||||
TIM1 = (TIM_TypeDef *)TIM1_BASE;
|
||||
#endif /* _TIM1 */
|
||||
|
||||
#ifdef _TIM2
|
||||
TIM2 = (TIM_TypeDef *)TIM2_BASE;
|
||||
#endif /* _TIM2 */
|
||||
|
||||
#ifdef _TIM3
|
||||
TIM3 = (TIM_TypeDef *)TIM3_BASE;
|
||||
#endif /* _TIM3 */
|
||||
|
||||
/************************* GPIO ************************/
|
||||
|
||||
#ifdef _GPIO0
|
||||
GPIO0 = (GPIO_TypeDef *)GPIO0_BASE;
|
||||
#endif /* _GPIO0 */
|
||||
|
||||
#ifdef _GPIO1
|
||||
GPIO1 = (GPIO_TypeDef *)GPIO1_BASE;
|
||||
#endif /* _GPIO1 */
|
||||
|
||||
#ifdef _GPIO2
|
||||
GPIO2 = (GPIO_TypeDef *)GPIO2_BASE;
|
||||
#endif /* _GPIO2 */
|
||||
|
||||
#ifdef _GPIO3
|
||||
GPIO3 = (GPIO_TypeDef *)GPIO3_BASE;
|
||||
#endif /* _GPIO3 */
|
||||
|
||||
#ifdef _GPIO4
|
||||
GPIO4 = (GPIO_TypeDef *)GPIO4_BASE;
|
||||
#endif /* _GPIO4 */
|
||||
|
||||
#ifdef _GPIO5
|
||||
GPIO5 = (GPIO_TypeDef *)GPIO5_BASE;
|
||||
#endif /* _GPIO5 */
|
||||
|
||||
#ifdef _GPIO6
|
||||
GPIO6 = (GPIO_TypeDef *)GPIO6_BASE;
|
||||
#endif /* _GPIO6 */
|
||||
|
||||
#ifdef _GPIO7
|
||||
GPIO7 = (GPIO_TypeDef *)GPIO7_BASE;
|
||||
#endif /* _GPIO7 */
|
||||
|
||||
#ifdef _GPIO8
|
||||
GPIO8 = (GPIO_TypeDef *)GPIO8_BASE;
|
||||
#endif /* _GPIO8 */
|
||||
|
||||
#ifdef _GPIO9
|
||||
GPIO9 = (GPIO_TypeDef *)GPIO9_BASE;
|
||||
#endif /* _GPIO9 */
|
||||
|
||||
/************************* RTC *************************/
|
||||
|
||||
#ifdef _RTC
|
||||
RTC = (RTC_TypeDef *)RTC_BASE;
|
||||
#endif /* _RTC */
|
||||
|
||||
/************************* PRCCU ***********************/
|
||||
|
||||
#ifdef _SCU
|
||||
SCU = (SCU_TypeDef *)SCU_BASE;
|
||||
#endif /* _PRCCU */
|
||||
|
||||
/************************** MC *************************/
|
||||
|
||||
#ifdef _MC
|
||||
MC = (MC_TypeDef *)MC_BASE;
|
||||
#endif /* _MC */
|
||||
|
||||
/************************* UART ************************/
|
||||
|
||||
#ifdef _UART0
|
||||
UART0 = (UART_TypeDef *)UART0_BASE;
|
||||
#endif /* _UART0 */
|
||||
|
||||
#ifdef _UART1
|
||||
UART1 = (UART_TypeDef *)UART1_BASE;
|
||||
#endif /* _UART1 */
|
||||
|
||||
#ifdef _UART2
|
||||
UART2 = (UART_TypeDef *)UART2_BASE;
|
||||
#endif /* _UART2 */
|
||||
|
||||
/************************* SSP *************************/
|
||||
|
||||
#ifdef _SSP0
|
||||
SSP0 = (SSP_TypeDef *)SSP0_BASE;
|
||||
#endif /* _SSP0 */
|
||||
|
||||
#ifdef _SSP1
|
||||
SSP1 = (SSP_TypeDef *)SSP1_BASE;
|
||||
#endif /* _SSP1 */
|
||||
|
||||
/************************* CAN *************************/
|
||||
|
||||
#ifdef _CAN
|
||||
CAN = (CAN_TypeDef *)CAN_BASE;
|
||||
#endif /* _CAN */
|
||||
|
||||
/************************* ADC *************************/
|
||||
|
||||
#ifdef _ADC
|
||||
ADC = (ADC_TypeDef *)ADC_BASE;
|
||||
#endif /* _ADC */
|
||||
|
||||
/************************* WDG *************************/
|
||||
|
||||
#ifdef _WDG
|
||||
WDG = (WDG_TypeDef *)WDG_BASE;
|
||||
#endif /* _WDG */
|
||||
|
||||
/************************* I2C *************************/
|
||||
|
||||
#ifdef _I2C0
|
||||
I2C0 = (I2C_TypeDef *)I2C0_BASE;
|
||||
#endif /* _I2C0 */
|
||||
|
||||
#ifdef _I2C1
|
||||
I2C1 = (I2C_TypeDef *)I2C1_BASE;
|
||||
#endif /* _I2C1 */
|
||||
/********************** ENET **************************/
|
||||
#ifdef _ENET
|
||||
ENET_MAC = (ENET_MAC_TypeDef *)ENET_MAC_BASE;
|
||||
ENET_DMA = (ENET_DMA_TypeDef *)ENET_DMA_BASE;
|
||||
#endif /* _ENET */
|
||||
}
|
||||
#endif /* DEBUG */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
661
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_scu.c
Normal file
661
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_scu.c
Normal file
|
@ -0,0 +1,661 @@
|
|||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_scu.c
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file provides the SCU library software functions
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "91x_scu.h"
|
||||
|
||||
/* Include of other module interface headers ---------------------------------*/
|
||||
/* Local includes ------------------------------------------------------------*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define SCU_PLLEN 0x80000
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Interface functions -------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_MCLKSourceConfig
|
||||
* Description : Configures the MCLK source clock
|
||||
* Input : MCLK_Source = SCU_MCLK_OSC, SCU_MCLK_PLL or SCU_MCLK_RTC
|
||||
* Output : None
|
||||
* Return : ErrorStatus: SUCCESS or ERROR
|
||||
* Note : this function returns ERROR if trying to select the PLL as
|
||||
* clock source while the PLL is disabled or not locked.
|
||||
*******************************************************************************/
|
||||
ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source)
|
||||
{
|
||||
u32 CLKCNTR_Value;
|
||||
|
||||
CLKCNTR_Value = SCU->CLKCNTR; /*get CLKCNTR register value*/
|
||||
CLKCNTR_Value &=~0x3; /*clear field MCLKSEL*/
|
||||
if (MCLK_Source == SCU_MCLK_PLL) /*PLL selected as clock source*/
|
||||
{
|
||||
/*check if PLL enabled & locked*/
|
||||
if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK)))
|
||||
return ERROR;
|
||||
}
|
||||
else CLKCNTR_Value |=MCLK_Source; /*OSC or RTC selected as clock source*/
|
||||
SCU->CLKCNTR = CLKCNTR_Value; /*Update CLKCNTR register value*/
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_PLLFactorsConfig
|
||||
* Description : Sets the PLL factors
|
||||
* Input : PLLN, PLLM and PLLP
|
||||
* Output : None
|
||||
* Return : ErrorStatus: ERROR or SUCCESS
|
||||
* Notes : -The PLL factors must respect the PLL specification requirements
|
||||
* -The function returns ERROR if trying to change PLL
|
||||
* factors while PLL is selected as Main Clock source (MCLK)
|
||||
* -This function disables the PLL, to enable the PLL use
|
||||
* function" SCU_PLLCmd(ENABLE)" after setting the PLL factors
|
||||
******************************************************************************/
|
||||
ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP)
|
||||
{
|
||||
if (SCU_PLLCmd(DISABLE)==SUCCESS) /*Disable PLL*/
|
||||
{
|
||||
SCU->PLLCONF =0; /*clear PLLCONF register*/
|
||||
SCU->PLLCONF |=(PLLN<<8); /*update PLLN field*/
|
||||
SCU->PLLCONF |=PLLM; /*update PLLM field*/
|
||||
SCU->PLLCONF |=PLLP<<16; /*update PLLP field*/
|
||||
return SUCCESS;
|
||||
}
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_PLLCmd
|
||||
* Description : Enable or Disable the PLL
|
||||
* Input : NewState = ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : ErrorStatus: SUCCESS or ERROR
|
||||
* Note : -The function returns ERROR if:
|
||||
* *trying to disable the PLL while it is selected as the MCLK
|
||||
* *trying to enable the PLL while it is already enabled and
|
||||
* locked
|
||||
*******************************************************************************/
|
||||
ErrorStatus SCU_PLLCmd(FunctionalState NewState)
|
||||
{
|
||||
vu32 i;
|
||||
if (NewState==ENABLE)
|
||||
{
|
||||
if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK)))
|
||||
{
|
||||
SCU->SYSSTATUS|=SCU_FLAG_LOCK; /*clear LOCK bit*/
|
||||
SCU->PLLCONF |=SCU_PLLEN; /*PLL Enable*/
|
||||
while(!SCU->SYSSTATUS&SCU_FLAG_LOCK); /*Wait PLL to lock*/
|
||||
return SUCCESS;
|
||||
}
|
||||
else return ERROR;
|
||||
}
|
||||
else /*NewState = DISABLE*/
|
||||
{
|
||||
if(SCU->CLKCNTR&0x3) /*check if PLL not sys CLK*/
|
||||
{
|
||||
for(i=10;i>0;i--); /*delay before PLL disabling*/
|
||||
SCU->PLLCONF &=~SCU_PLLEN; /*PLL Disable*/
|
||||
return SUCCESS;
|
||||
}
|
||||
else return ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_RCLKDivisorConfig
|
||||
* Description : Sets the RCLK divisor value
|
||||
* Input : RCLK_Divisor
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_RCLKDivisorConfig(u32 RCLK_Divisor)
|
||||
{
|
||||
SCU->CLKCNTR &=SCU_RCLK_Div1; /*clear RCLKDIV[2:0] field*/
|
||||
if (RCLK_Divisor!=SCU_RCLK_Div1)
|
||||
SCU->CLKCNTR |= RCLK_Divisor; /*update field with RCLK divisor*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_HCLKDivisorConfig
|
||||
* Description : Sets the HCLK divisor value
|
||||
* Input : HCLK_Divisor
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_HCLKDivisorConfig(u32 HCLK_Divisor)
|
||||
{
|
||||
SCU->CLKCNTR &=SCU_HCLK_Div1; /*clear AHBDIV[1:0] field*/
|
||||
if (HCLK_Divisor!=SCU_HCLK_Div1)
|
||||
SCU->CLKCNTR |= HCLK_Divisor; /*update field with HCLK divisor*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_PCLKDivisorConfig
|
||||
* Description : Sets the PCLK divisor value
|
||||
* Input : PCLK_Divisor
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_PCLKDivisorConfig(u32 PCLK_Divisor)
|
||||
{
|
||||
SCU->CLKCNTR &=SCU_PCLK_Div1; /*clear APBDIV[1:0] field*/
|
||||
if (PCLK_Divisor!=SCU_PCLK_Div1)
|
||||
SCU->CLKCNTR |= PCLK_Divisor; /*update field with PCLK Divisor*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_APBPeriphClockConfig
|
||||
* Description : Enable the clock for an APB peripheral
|
||||
* Input : -APBPerip : APB peripherals(__RTC, __ADC ,...)
|
||||
* -NewState : ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState==ENABLE) /*Enable clock for APB peripheral*/
|
||||
SCU->PCGR1 |=APBPeriph;
|
||||
else
|
||||
SCU->PCGR1 &=~APBPeriph; /*Disable clock for APB peripheral*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_AHBPeriphClockConfig
|
||||
* Description : Enable the clock for an AHB peripheral
|
||||
* Input : -AHBPerip: AHB peripherals(__USB, __DMA,...)
|
||||
* -NewState : ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState==ENABLE) /*Enable clock for AHB peripheral*/
|
||||
SCU->PCGRO |=AHBPeriph;
|
||||
else
|
||||
SCU->PCGRO &=~AHBPeriph; /*Disable clock for AHB peripheral*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_APBPeriphReset
|
||||
* Description : Assert or deassert Reset on APB peripheral
|
||||
* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
|
||||
-NewState : ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState==DISABLE) /*APB peripheral not held in Reset*/
|
||||
SCU->PRR1 |=APBPeriph;
|
||||
else
|
||||
SCU->PRR1 &=~APBPeriph; /*APB peripheral held in Reset*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_AHBPeriphReset
|
||||
* Description : Assert or deassert Reset on AHB peripheral
|
||||
* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
|
||||
-NewState : ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState==DISABLE)
|
||||
SCU->PRR0 |=AHBPeriph; /*AHB peripheral not held in Reset*/
|
||||
else
|
||||
SCU->PRR0 &=~AHBPeriph; /*AHB peripheral held in Reset*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_APBPeriphIdleConfig
|
||||
* Description : Enable or Disable Periph Clock during Idle mode
|
||||
* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
|
||||
-NewState : ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState==ENABLE)
|
||||
SCU->MGR1 |=APBPeriph; /*APB peripheral clock enabled during Idle mode*/
|
||||
else
|
||||
SCU->MGR1 &=~APBPeriph; /*APB peripheral clock disabled during Idle mode*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_AHBPeriphIdleConfig
|
||||
* Description : Enable or Disable Periph Clock during Idle mode
|
||||
* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
|
||||
-NewState : ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState==ENABLE)
|
||||
SCU->MGR0 |=AHBPeriph; /*AHB peripheral clock enabled during Idle mode*/
|
||||
else
|
||||
SCU->MGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during Idle mode*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_APBPeriphDebugConfig
|
||||
* Description : Enable or Disable Periph Clock during ARM debug state
|
||||
* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
|
||||
-NewState : ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState==ENABLE)
|
||||
SCU->PECGR1 |=APBPeriph; /*APB peripheral clock enabled during ARM debug state*/
|
||||
else
|
||||
SCU->PECGR1 &=~APBPeriph; /*APB peripheral clock disabled during ARM debug state*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_AHBPeriphDebugConfig
|
||||
* Description : Enable or Disable Periph Clock during ARM debug state
|
||||
* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
|
||||
-NewState : ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState==ENABLE)
|
||||
SCU->PECGR0 |=AHBPeriph; /*AHB peripheral clock enabled during ARM debug state*/
|
||||
else
|
||||
SCU->PECGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during ARM debug state*/
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_BRCLKDivisorConfig
|
||||
* Description : Sets the BRCLK divisor value
|
||||
* Input : BRCLK_Divisor
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor)
|
||||
{
|
||||
SCU->CLKCNTR &=SCU_BRCLK_Div1; /*Clear BRSEL bit*/
|
||||
if (BRCLK_Divisor!=SCU_BRCLK_Div1)
|
||||
SCU->CLKCNTR |= SCU_BRCLK_Div2; /*set bit BRSEL*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_TIMCLKSourceConfig
|
||||
* Description : Sets the TIMx clock source
|
||||
* Input : - TIMx : SCU_TIM01 or SCU_TIM23
|
||||
* - TIMCLK_Source = SCU_TIMCLK_EXT or SCU_TIMCLK_INT
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source)
|
||||
{
|
||||
if (TIMx== SCU_TIM01) /*TIM01 clock source configuration*/
|
||||
{
|
||||
SCU->CLKCNTR &=0xFFFFDFFF;
|
||||
if (TIMCLK_Source == SCU_TIMCLK_EXT)
|
||||
SCU->CLKCNTR |=0x2000;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCU->CLKCNTR &=0xFFFFBFFF; /*TIM23 clock source configuration*/
|
||||
if (TIMCLK_Source == SCU_TIMCLK_EXT)
|
||||
SCU->CLKCNTR |=0x4000;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_TIMPresConfig
|
||||
* Description : Sets the TIMx Prescaler Value
|
||||
* Input : - TIMx : SCU_TIM01 or SCU_TIM23
|
||||
* - Prescaler (16 bit value)
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler)
|
||||
{
|
||||
if (TIMx==SCU_TIM01) /*TIM01 Prescaler configuration*/
|
||||
SCU->SCR1 = Prescaler&0xFFFF;
|
||||
else
|
||||
SCU->SCR2 = Prescaler&0xFFFF; /*TIM23 Prescaler configuration*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_USBCLKConfig
|
||||
* Description : Configures the clock source for the 48MHz USBCLK
|
||||
* Input : USBCLK_Source: SCU_USBCLK_MCLK,SCU_USBCLK_MCLK2 or SCU_USBCLK_EXT
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_USBCLKConfig(u32 USBCLK_Source)
|
||||
{
|
||||
SCU->CLKCNTR &=SCU_USBCLK_MCLK; /*clear USBSEL[1:0] field*/
|
||||
if (USBCLK_Source!=SCU_USBCLK_MCLK)
|
||||
SCU->CLKCNTR |= USBCLK_Source; /*update field with USBCLK_Source*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_PHYCLKConfig
|
||||
* Description : Enable or Disable PHY clock output
|
||||
* Input : NewState : ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_PHYCLKConfig(FunctionalState NewState)
|
||||
{
|
||||
if (NewState==ENABLE)
|
||||
SCU->CLKCNTR |= 0x1000; /*enable MIIPHY clock*/
|
||||
else
|
||||
SCU->CLKCNTR &=~0x1000; /*disable MIIPHY clock*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_FMICLKDivisorConfig
|
||||
* Description : Set the FMI clock divisor
|
||||
* Input : FMICLK_Divisor: SCU_FMICLK_Div1 or SCU_FMICLK_DIV2
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor)
|
||||
{
|
||||
SCU->CLKCNTR &=SCU_FMICLK_Div1; /*FMICLK = RCLK*/
|
||||
if (FMICLK_Divisor!=SCU_FMICLK_Div1)
|
||||
SCU->CLKCNTR |=SCU_FMICLK_Div2; /*FMICLK = RCLK/2 */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_EMIBCLKDivisorConfig
|
||||
* Description : Set the EMI Bus clock divisor: EMIBCLK = HCLK or HCLK/2
|
||||
* Input : SCU_EMICLK: SCU_EMIBCLK_Div1 , SCU_EMIBCLK_Div2
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK)
|
||||
{
|
||||
SCU->CLKCNTR &=SCU_EMIBCLK_Div1; /*EMIBCLK = HCLK */
|
||||
if (SCU_EMIBCLK!=SCU_EMIBCLK_Div1)
|
||||
SCU->CLKCNTR |= SCU_EMIBCLK_Div2; /*EMIBCLK = HCLK/2 */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_EMIModeConfig
|
||||
* Description : Configure the EMI as Multiplexed or Demultiplexed
|
||||
* Input : SCU_EMIMODE : SCU_EMI_MUX or SCU_EMI_DEMUX
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_EMIModeConfig(u32 SCU_EMIMODE)
|
||||
{
|
||||
SCU->SCR0 &=SCU_EMI_MUX; /*EMI mode = Multiplexed*/
|
||||
if (SCU_EMIMODE!=SCU_EMI_MUX)
|
||||
SCU->SCR0 |= SCU_EMI_DEMUX; /*EMI mode = Demultiplexed*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_EMIALEConfig
|
||||
* Description : Configure the ALE signal (length & polarity)
|
||||
* Input : -SCU_EMIALE_LEN : SCU_EMIALE_LEN1 or SCU_EMIALE_LEN2
|
||||
* -SCU_EMIALE_POL : SCU_EMIALE_POLLow or SCU_EMI_POLHigh
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL)
|
||||
{
|
||||
/*Configure EMI ALE Length*/
|
||||
SCU->SCR0 &=SCU_EMIALE_LEN1;
|
||||
if (SCU_EMIALE_LEN!=SCU_EMIALE_LEN1)
|
||||
SCU->SCR0 |= SCU_EMIALE_LEN2;
|
||||
|
||||
/*Configure EMI ALE POL*/
|
||||
SCU->SCR0 &=SCU_EMIALE_POLLow;
|
||||
if (SCU_EMIALE_POL!=SCU_EMIALE_POLLow)
|
||||
SCU->SCR0 |= SCU_EMIALE_POLHigh;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_ITConfig
|
||||
* Description : ENBALE or DISABLE an SCU interrupt
|
||||
* Input : -SCU_IT: interrupt mask
|
||||
* -NewState: ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState)
|
||||
{
|
||||
if (NewState==ENABLE)
|
||||
SCU->ITCMSK&=~SCU_IT; /*IT enable */
|
||||
else
|
||||
SCU->ITCMSK|=SCU_IT; /*IT disable( mask)*/
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_GetFlagStatus
|
||||
* Description : Returns flag status
|
||||
* Input : SCU_Flag
|
||||
* Output : NONE
|
||||
* Return : SET or RESET
|
||||
*******************************************************************************/
|
||||
FlagStatus SCU_GetFlagStatus(u32 SCU_Flag)
|
||||
{
|
||||
if (SCU->SYSSTATUS&SCU_Flag)
|
||||
return SET;
|
||||
else return RESET;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_ClearFlag
|
||||
* Description : Clears a SYSTATUS Flag
|
||||
* Input : SCU_Flag
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_ClearFlag(u32 SCU_Flag)
|
||||
{
|
||||
SCU->SYSSTATUS = SCU_Flag;
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_GetPLLfreqValue
|
||||
* Description : Gets the current PLL frequency
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : PLL frequency (KHz)
|
||||
*******************************************************************************/
|
||||
u32 SCU_GetPLLFreqValue(void)
|
||||
{
|
||||
u8 PLL_M;
|
||||
u8 PLL_N;
|
||||
u8 PLL_P;
|
||||
|
||||
PLL_M = SCU->PLLCONF&0xFF;
|
||||
PLL_N = (SCU->PLLCONF&0xFF00)>>8;
|
||||
PLL_P = (SCU->PLLCONF&0x70000)>>16;
|
||||
|
||||
if ((PLL_M>0)&&(PLL_N>0))
|
||||
return (u32)(((_Main_Crystal*2)*PLL_N)/(PLL_M<<PLL_P));
|
||||
|
||||
else return 0;
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_GetMCLKFreqValue
|
||||
* Description : Gets the current MCLK frequency
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : MCLK frequency (KHz)
|
||||
*******************************************************************************/
|
||||
u32 SCU_GetMCLKFreqValue(void)
|
||||
{
|
||||
if ((SCU->CLKCNTR&0x3) == 0x2) return (u32)(_Main_Crystal);
|
||||
if ((SCU->CLKCNTR&0x3) == 0x1) return (u32)(32);
|
||||
else return (SCU_GetPLLFreqValue());
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_GetRCLKFreqValue
|
||||
* Description : Gets the current RCLK frequency
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : RCLK frequency (KHz)
|
||||
*******************************************************************************/
|
||||
u32 SCU_GetRCLKFreqValue(void)
|
||||
{
|
||||
u8 RCLK_Div;
|
||||
RCLK_Div = (SCU->CLKCNTR&0x1C)>>2;
|
||||
if (RCLK_Div==0x5) RCLK_Div=10;
|
||||
return (u32)(SCU_GetMCLKFreqValue() >>RCLK_Div);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_GetHCLKFreqValue
|
||||
* Description : Gets the current PCLK frequency
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : HCLK frequency (KHz)
|
||||
*******************************************************************************/
|
||||
u32 SCU_GetHCLKFreqValue(void)
|
||||
{
|
||||
u8 HCLK_Div;
|
||||
HCLK_Div = (SCU->CLKCNTR&0x60)>>5;
|
||||
return (u32)(SCU_GetRCLKFreqValue() >>HCLK_Div);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_GetPCLKFreqValue
|
||||
* Description : Gets the current HCLK frequency
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : PCLK frequency (KHz)
|
||||
*******************************************************************************/
|
||||
u32 SCU_GetPCLKFreqValue(void)
|
||||
{
|
||||
u8 PCLK_Div;
|
||||
PCLK_Div = (SCU->CLKCNTR&0x180)>>7;
|
||||
return (u32)(SCU_GetRCLKFreqValue() >>PCLK_Div);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_WakeUpLineConfig
|
||||
* Description : Configures an External interrupt as WakeUp line
|
||||
* Input : EXTint : 0 -> 31
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_WakeUpLineConfig(u8 EXTint)
|
||||
{
|
||||
if (EXTint < 8)
|
||||
{
|
||||
SCU->WKUPSEL&=~0x7;
|
||||
SCU->WKUPSEL|=EXTint;
|
||||
}
|
||||
else if (EXTint<16)
|
||||
{
|
||||
SCU->WKUPSEL&=~0x38;
|
||||
SCU->WKUPSEL|=(EXTint-8)<<3;
|
||||
}
|
||||
else if (EXTint<24)
|
||||
{
|
||||
SCU->WKUPSEL&=~0x1C0;
|
||||
SCU->WKUPSEL|=(EXTint-16)<<6;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCU->WKUPSEL&=~0xE00;
|
||||
SCU->WKUPSEL|=(EXTint-24)<<9;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_SpecIntRunModeConfig
|
||||
* Description : Enables or Disables the Special Run mode
|
||||
* Input : newstate = ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_SpecIntRunModeConfig(FunctionalState NewState)
|
||||
{
|
||||
if (NewState == ENABLE)
|
||||
SCU->PWRMNG |=0x8;
|
||||
else
|
||||
SCU->PWRMNG &=~0x8;
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_EnterIdleMode
|
||||
* Description : Enters in Idle mode
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_EnterIdleMode(void)
|
||||
{
|
||||
SCU->PWRMNG |=0x1;
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_EnterSleepMode
|
||||
* Description : Enters in Sleep mode
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_EnterSleepMode(void)
|
||||
{
|
||||
SCU->PWRMNG |=0x2;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_UARTIrDAConfig
|
||||
* Description : Enable or Disable the Irda mode for UARTx
|
||||
* Input : - UARTx :x=0,1 or 2
|
||||
* - UART_IrDA_Mode : SCU_UARTMode_IrDA or SCU_UARTMode_UART
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode)
|
||||
{
|
||||
if (UART_IrDA_Mode == SCU_UARTMode_IrDA)
|
||||
{
|
||||
if (UARTx== UART0) SCU->SCR0 |=0x400;
|
||||
else if (UARTx==UART1) SCU->SCR0 |=0x800;
|
||||
else SCU->SCR0 |=0x1000;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (UARTx== UART0) SCU->SCR0 &=~0x400;
|
||||
else if (UARTx==UART1) SCU->SCR0 &=~0x800;
|
||||
else SCU->SCR0 &=~0x1000;
|
||||
}
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : SCU_PFQBCCmd
|
||||
* Description : Enable or Disable PFQBC
|
||||
* Input : NewState : ENABLE or DISABLE
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SCU_PFQBCCmd(FunctionalState NewState)
|
||||
{
|
||||
if (NewState==ENABLE)
|
||||
SCU->SCR0 |=0x1;
|
||||
else SCU->SCR0 &=~0x1;
|
||||
}
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
692
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_tim.c
Normal file
692
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_tim.c
Normal file
|
@ -0,0 +1,692 @@
|
|||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_tim.c
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file provides all the TIM software functions.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/22/2007 : Version 1.2
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "91x_tim.h"
|
||||
|
||||
/* Include of other module interface headers ---------------------------------*/
|
||||
/* Local includes ------------------------------------------------------------*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* TIM Bits Masks */
|
||||
|
||||
#define TIM_PWM_MASK 0x0010
|
||||
#define TIM_OPM_MASK 0x0020
|
||||
#define TIM_OC1_ENABLE_MASK 0x0040
|
||||
#define TIM_OC1_DISABLE_MASK 0xFFBF
|
||||
#define TIM_OC2_ENABLE_MASK 0x0080
|
||||
#define TIM_OC2_DISABLE_MASK 0xFF7F
|
||||
|
||||
#define TIM_OLVL1_SET_MASK 0x0100
|
||||
#define TIM_OLVL1_RESET_MASK 0xFEFF
|
||||
|
||||
#define TIM_OLVL2_SET_MASK 0x0200
|
||||
#define TIM_OLVL2_RESET_MASK 0xFDFF
|
||||
|
||||
#define TIM_ENABLE_MASK 0x8000
|
||||
#define TIM_DISABLE_MASK 0x7FFF
|
||||
|
||||
#define TIM_DMA_CLEAR_MASK 0xCFFF
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Interface functions -------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_DeInit
|
||||
* Description : Initializes TIM peripheral control and registers to their
|
||||
* : default reset values.
|
||||
* Input : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void TIM_DeInit(TIM_TypeDef *TIMx)
|
||||
{
|
||||
if((TIMx == TIM0)||(TIMx == TIM1))
|
||||
{
|
||||
SCU_APBPeriphReset(__TIM01, DISABLE); /* TIM0 & TIM1 Reset's off */
|
||||
}
|
||||
else
|
||||
{
|
||||
SCU_APBPeriphReset(__TIM23, DISABLE); /* TIM2 & TIM3 Reset's off */
|
||||
}
|
||||
|
||||
/* Set all the TIMx registers to thier default values */
|
||||
TIMx->OC1R = 0x8000;
|
||||
TIMx->OC2R = 0x8000;
|
||||
TIMx->CR1 = 0x0;
|
||||
TIMx->CR2 = 0x1;
|
||||
TIMx->CNTR = 0x1234;
|
||||
TIMx->SR = 0x0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_StructInit
|
||||
* Description : Fills in a TIM_InitTypeDef structure with the reset value of
|
||||
* each parameter.
|
||||
* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure
|
||||
which will be initialized.
|
||||
* Output : None
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct)
|
||||
{
|
||||
TIM_InitStruct->TIM_Mode = 0x0000;
|
||||
TIM_InitStruct->TIM_OC1_Modes = 0x0000;
|
||||
TIM_InitStruct->TIM_OC2_Modes = 0x0000;
|
||||
TIM_InitStruct->TIM_Clock_Source = 0x0000;
|
||||
TIM_InitStruct->TIM_Clock_Edge = 0x0000;
|
||||
TIM_InitStruct->TIM_OPM_INPUT_Edge = 0x0000;
|
||||
TIM_InitStruct->TIM_ICAP1_Edge = 0x0000;
|
||||
TIM_InitStruct->TIM_ICAP2_Edge = 0x0000;
|
||||
TIM_InitStruct->TIM_Prescaler = 0x0000;
|
||||
TIM_InitStruct->TIM_Pulse_Level_1 = 0x0000;
|
||||
TIM_InitStruct->TIM_Pulse_Level_2 = 0x0000;
|
||||
TIM_InitStruct->TIM_Period_Level = 0x0000;
|
||||
TIM_InitStruct->TIM_Pulse_Length_1 = 0x0000;
|
||||
TIM_InitStruct->TIM_Pulse_Length_2 = 0x0000;
|
||||
TIM_InitStruct->TIM_Full_Period = 0x0000;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_Init
|
||||
* Description : Initializes TIM peripheral according to the specified
|
||||
* parameters in the TIM_InitTypeDef structure.
|
||||
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Input2 : TIM_InitStruct: pointer to a TIM_InitTypeDef structure that
|
||||
* contains the configuration information for the specified
|
||||
* TIM peripheral.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
|
||||
void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct)
|
||||
{
|
||||
/***************************** Clock configuration ****************************/
|
||||
|
||||
if (TIM_InitStruct->TIM_Clock_Source == TIM_CLK_APB)
|
||||
{
|
||||
/* APB clock */
|
||||
TIMx->CR1 &= TIM_CLK_APB;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* External/SCU clock */
|
||||
TIMx->CR1 |= TIM_CLK_EXTERNAL;
|
||||
if (TIM_InitStruct->TIM_Clock_Edge == TIM_CLK_EDGE_RISING)
|
||||
{
|
||||
/* Clock rising edge */
|
||||
TIMx->CR1 |= TIM_CLK_EDGE_RISING;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clock falling edge */
|
||||
TIMx->CR1 &= TIM_CLK_EDGE_FALLING;
|
||||
}
|
||||
}
|
||||
|
||||
/************************** Prescaler configuration ***************************/
|
||||
|
||||
TIMx->CR2 =( TIMx->CR2 & 0xFF00 )|TIM_InitStruct->TIM_Prescaler ;
|
||||
|
||||
/********************************** TIM Modes *********************************/
|
||||
|
||||
switch ( TIM_InitStruct->TIM_Mode)
|
||||
{
|
||||
/******************************* PWM Input mode *******************************/
|
||||
|
||||
case TIM_PWMI:
|
||||
|
||||
/* Set the PWMI Bit */
|
||||
TIMx->CR1 |= TIM_PWMI;
|
||||
|
||||
/* Set the first edge Level */
|
||||
if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING)
|
||||
{
|
||||
TIMx->CR1 |= TIM_ICAP1_EDGE_RISING;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING;
|
||||
}
|
||||
|
||||
/* Set the Second edge Level ( Opposite of the first level ) */
|
||||
if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING)
|
||||
{
|
||||
TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 |= TIM_ICAP2_EDGE_RISING;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
/************************** Output compare channel 1 **************************/
|
||||
|
||||
case TIM_OCM_CHANNEL_1:
|
||||
|
||||
if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH)
|
||||
{
|
||||
TIMx->CR1 |= TIM_OLVL1_SET_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 &= TIM_OLVL1_RESET_MASK;
|
||||
}
|
||||
|
||||
TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1;
|
||||
|
||||
if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING)
|
||||
{
|
||||
TIMx->CR1 &= TIM_OC1_DISABLE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 |= TIM_OC1_ENABLE_MASK;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
/************************** Output compare channel 2 **************************/
|
||||
|
||||
case TIM_OCM_CHANNEL_2:
|
||||
|
||||
if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH)
|
||||
{
|
||||
TIMx->CR1 |= TIM_OLVL2_SET_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 &= TIM_OLVL2_RESET_MASK;
|
||||
}
|
||||
|
||||
TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2;
|
||||
|
||||
if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING)
|
||||
{
|
||||
TIMx->CR1 &= TIM_OC2_DISABLE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 |= TIM_OC2_ENABLE_MASK;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
/************************ Output compare channel 1 & 2 ************************/
|
||||
|
||||
case TIM_OCM_CHANNEL_12:
|
||||
|
||||
TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2;
|
||||
TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1;
|
||||
|
||||
if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING)
|
||||
{
|
||||
TIMx->CR1 &= TIM_OC2_DISABLE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 |= TIM_OC2_ENABLE_MASK;
|
||||
}
|
||||
|
||||
if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING)
|
||||
{
|
||||
TIMx->CR1 &= TIM_OC1_DISABLE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 |= TIM_OC1_ENABLE_MASK;
|
||||
}
|
||||
|
||||
if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH)
|
||||
{
|
||||
TIMx->CR1 |= TIM_OLVL1_SET_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 &= TIM_OLVL1_RESET_MASK;
|
||||
}
|
||||
|
||||
if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH)
|
||||
{
|
||||
TIMx->CR1 |= TIM_OLVL2_SET_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 &= TIM_OLVL2_RESET_MASK;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
/********************************** PWM mode **********************************/
|
||||
|
||||
case TIM_PWM:
|
||||
|
||||
/* Set the Level During the pulse */
|
||||
if ( TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH)
|
||||
{
|
||||
TIMx->CR1 |= TIM_OLVL2_SET_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 &= TIM_OLVL2_RESET_MASK;
|
||||
}
|
||||
|
||||
/* Set the Level after the pulse */
|
||||
if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH)
|
||||
{
|
||||
TIMx->CR1 |= TIM_OLVL1_SET_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 &= TIM_OLVL1_RESET_MASK;
|
||||
}
|
||||
|
||||
/* Set the OCAE */
|
||||
TIMx->CR1 |= TIM_OC1_ENABLE_MASK;
|
||||
|
||||
/* Set the PWM Bit */
|
||||
TIMx->CR1 |= TIM_PWM_MASK;
|
||||
|
||||
/* Set the Duty Cycle value */
|
||||
|
||||
TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1 ;
|
||||
|
||||
/* Set the Full Period */
|
||||
|
||||
TIMx->OC2R = TIM_InitStruct->TIM_Full_Period ;
|
||||
|
||||
break;
|
||||
|
||||
/******************************* One pulse mode *******************************/
|
||||
|
||||
case TIM_OPM:
|
||||
|
||||
/* Set the Level During the pulse */
|
||||
if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH)
|
||||
{
|
||||
TIMx->CR1 |= TIM_OLVL2_SET_MASK;
|
||||
}
|
||||
|
||||
/* Set the Level after the pulse */
|
||||
if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH)
|
||||
{
|
||||
TIMx->CR1 |= TIM_OLVL1_SET_MASK;
|
||||
}
|
||||
|
||||
/* Set the Activation Edge on the ICAP 1 */
|
||||
if (TIM_InitStruct->TIM_OPM_INPUT_Edge == TIM_OPM_EDGE_RISING)
|
||||
{
|
||||
TIMx->CR1 |= TIM_OPM_EDGE_RISING;
|
||||
}
|
||||
|
||||
/* Set the Output Compare Function */
|
||||
TIMx->CR1 |= TIM_OC1_ENABLE_MASK;
|
||||
|
||||
/* Set the One pulse mode */
|
||||
TIMx->CR1 |= TIM_OPM_MASK;
|
||||
|
||||
/* Set the Pulse length */
|
||||
TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1;
|
||||
|
||||
break;
|
||||
|
||||
/*************************** Input capture channel 1 **************************/
|
||||
|
||||
case TIM_ICAP_CHANNEL_1:
|
||||
|
||||
if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING)
|
||||
{
|
||||
TIMx->CR1 |= TIM_ICAP1_EDGE_RISING;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
/*************************** Input capture channel 2 **************************/
|
||||
|
||||
case TIM_ICAP_CHANNEL_2:
|
||||
|
||||
if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING)
|
||||
{
|
||||
TIMx->CR1 |= TIM_ICAP2_EDGE_RISING;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
/************************* Input capture channel 1 & 2 ************************/
|
||||
|
||||
case TIM_ICAP_CHANNEL_12:
|
||||
if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING)
|
||||
{
|
||||
TIMx->CR1 |= TIM_ICAP2_EDGE_RISING;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING;
|
||||
}
|
||||
|
||||
if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING)
|
||||
{
|
||||
TIMx->CR1 |= TIM_ICAP1_EDGE_RISING;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_CounterCmd
|
||||
* Description : Enables or disables TIMx Counter peripheral.
|
||||
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Input2 : TIM_operation: specifies the new state of the TIMx Counter.
|
||||
* This parameter can be one of the following values:
|
||||
* - TIM_START: Start the timer counter.
|
||||
* - TIM_STOP : Stop the timer counter.
|
||||
* - TIM_CLEAR: Clear the timer counter.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation)
|
||||
{
|
||||
switch (TIM_operation)
|
||||
{
|
||||
case TIM_START:
|
||||
TIMx->CR1 |= TIM_ENABLE_MASK;
|
||||
break;
|
||||
|
||||
case TIM_STOP:
|
||||
TIMx->CR1 &= TIM_DISABLE_MASK;
|
||||
break;
|
||||
|
||||
case TIM_CLEAR:
|
||||
TIMx->CNTR = 0x1234;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_PrescalerConfig
|
||||
* Description : This routine is used to configure the TIMx prescaler value
|
||||
* (when using the APB clock).
|
||||
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Input2 : TIM_Prescaler: specifies the prescaler value. This parameter
|
||||
* can be a value from 0x0 to 0xFF.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler)
|
||||
{
|
||||
TIMx->CR2 &= 0xFF00;
|
||||
TIMx->CR2 |= TIM_Prescaler;
|
||||
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_GetPrescalerValue
|
||||
* Description : This routine is used to get the TIMx prescaler value
|
||||
* (when using the APB clock).
|
||||
* Input : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Output : None
|
||||
* Return : The prescaler value.
|
||||
*******************************************************************************/
|
||||
u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx)
|
||||
{
|
||||
return TIMx->CR2 & 0x00FF;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_GetCounterValue
|
||||
* Description : This routine is used to get the TIMx counter value.
|
||||
* Input : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Output : None
|
||||
* Return : The counter value.
|
||||
*******************************************************************************/
|
||||
u16 TIM_GetCounterValue(TIM_TypeDef *TIMx)
|
||||
{
|
||||
return TIMx->CNTR;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_GetICAP1Value
|
||||
* Description : This routine is used to get the Input Capture 1 value.
|
||||
* Input : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Output : None
|
||||
* Return : The Input Capture 1 value.
|
||||
*******************************************************************************/
|
||||
u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx)
|
||||
{
|
||||
return TIMx->IC1R;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_GetICAP2Value
|
||||
* Description : This routine is used to get the Input Capture 2 value.
|
||||
* Input : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Output : None
|
||||
* Return : The Input Capture 2 value.
|
||||
*******************************************************************************/
|
||||
u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx)
|
||||
{
|
||||
return TIMx->IC2R;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_SetPulse
|
||||
* Description : This routine is used to set the pulse value.
|
||||
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Input2 : TIM_Channel: specifies the needed channel.
|
||||
* This parameter can be one of the following values:
|
||||
* - TIM_PWM_OC1_Channel: PWM/Output Compare 1 Channel
|
||||
* - TIM_OC2_Channel : Output Compare 2 Channel
|
||||
* Input3 : TIM_Pulse: specifies the new pulse value.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse)
|
||||
{
|
||||
if (TIM_Channel == TIM_PWM_OC1_Channel)
|
||||
{
|
||||
TIMx->OC1R = TIM_Pulse;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->OC2R = TIM_Pulse;
|
||||
}
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_GetFlagStatus
|
||||
* Description : Checks whether the specified TIMx flag is set or not.
|
||||
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Input2 : TIM_Flag: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* - TIM_FLAG_IC1: Input Capture Channel 1 Flag
|
||||
* - TIM_FLAG_IC2: Input Capture Channel 2 Flag
|
||||
* - TIM_FLAG_TO : Timer Overflow Flag
|
||||
* - TIM_FLAG_OC1: Output Compare Channel 1 Flag
|
||||
* - TIM_FLAG_OC2: Output Compare Channel 2 Flag
|
||||
* Output : None
|
||||
* Return : The NewState of the TIM_Flag (SET or RESET).
|
||||
*******************************************************************************/
|
||||
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag)
|
||||
{
|
||||
if((TIMx->SR & TIM_Flag) == RESET)
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_ClearFlag
|
||||
* Description : Clears the TIM Flag passed as a parameter.
|
||||
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Input2 : TIM_Flag: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* - TIM_FLAG_IC1: Input Capture Channel 1 Flag
|
||||
* - TIM_FLAG_IC2: Input Capture Channel 2 Flag
|
||||
* - TIM_FLAG_TO : Timer Overflow Flag
|
||||
* - TIM_FLAG_OC1: Output Compare Channel 1 Flag
|
||||
* - TIM_FLAG_OC2: Output Compare Channel 2 Flag
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag)
|
||||
{
|
||||
/* Clear TIM_Flag */
|
||||
TIMx->SR &= ~TIM_Flag;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_GetPWMIPulse
|
||||
* Description : This routine is used to get the Pulse value in PWMI Mode.
|
||||
* Input : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Output : None
|
||||
* Return : The pulse value.
|
||||
*******************************************************************************/
|
||||
u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx)
|
||||
{
|
||||
return TIMx->IC2R;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_GetPWMIPeriod
|
||||
* Description : This routine is used to get the Period value in PWMI Mode.
|
||||
* Input : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Output : None
|
||||
* Return : The period value.
|
||||
*******************************************************************************/
|
||||
u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx)
|
||||
{
|
||||
return TIMx->IC1R;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_ITConfig
|
||||
* Description : Configures the Timer interrupt source.
|
||||
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Input2 : TIM_IT: specifies the TIM interrupt source to be enabled.
|
||||
* This parameter can be one of the following values:
|
||||
* - TIM_IT_IC1: Input Capture 1 Interrupt source.
|
||||
* - TIM_IT_OC1: Output Compare 1 Interrupt source.
|
||||
* - TIM_IT_TO : Timer Overflow Interrupt source.
|
||||
* - TIM_IT_IC2: Input Capture 2 Interrupt source.
|
||||
* - TIM_IT_OC2: Output Compare 2 Interrupt source.
|
||||
* Input3 : TIM_Newstate: specifies the new state of the TIMx IT.
|
||||
* This parameter can be one of the following values:
|
||||
* - ENABLE : Enable the needed interrupt.
|
||||
* - DISABLE: Disable the needed interrupt.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate)
|
||||
{
|
||||
if(TIM_Newstate == ENABLE)
|
||||
{
|
||||
TIMx->CR2 = (TIMx->CR2 & 0x00FF) | TIM_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR2 &= ~TIM_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_DMAConfig
|
||||
* Description : Configures the Timer DMA source.
|
||||
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Input2 : TIM_DMA_Souces: specifies the TIM DMA source to be selected.
|
||||
* This parameter can be one of the following values:
|
||||
* - TIM_DMA_IC1: Input Capture 1 DMA source.
|
||||
* - TIM_DMA_OCA1 Output Compare 1 DMA source.
|
||||
* - TIM_DMA_TO: Timer Overflow DMA source.
|
||||
* - TIM_DMA_IC2: Input Capture 2 DMA source.
|
||||
* - TIM_DMA_OC2: Output Compare 2 DMA source.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources)
|
||||
{
|
||||
/* Reset the DMAS[1:0] bits */
|
||||
TIMx->CR1 &= TIM_DMA_CLEAR_MASK;
|
||||
/* Set the DMAS[1:0] bits according to TIM_DMA_Sources parameter */
|
||||
TIMx->CR1 |= TIM_DMA_Sources;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : TIM_DMACmd
|
||||
* Description : Enables or disables TIMx DMA peripheral.
|
||||
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
|
||||
* peripheral.
|
||||
* Input2 : TIM_Newstate: new state of the TIMx DMA peripheral
|
||||
* This parameter can be one of the following values:
|
||||
* - ENABLE : Enable the TIMx DMA.
|
||||
* - DISABLE: Disable the TIMx DMA.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate)
|
||||
{
|
||||
if (TIM_Newstate == ENABLE)
|
||||
{
|
||||
TIMx->CR2 |= TIM_DMA_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIMx->CR2 &= TIM_DMA_DISABLE;
|
||||
}
|
||||
}
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
658
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_uart.c
Normal file
658
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_uart.c
Normal file
|
@ -0,0 +1,658 @@
|
|||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_uart.c
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file provides all the UART software functions.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "91x_uart.h"
|
||||
#include "91x_scu.h"
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* UART IrDA Mask */
|
||||
#define UART_IrDA_Disable_Mask 0xFFFD /* IrDA Disable Mask */
|
||||
#define UART_IrDA_Enable_Mask 0x0002 /* IrDA Enable Mask */
|
||||
#define IrDA_LowPower_Enable_Mask 0x0004 /*IrDA lower power mode enable*/
|
||||
#define IrDA_LowPower_Disable_Mask 0xFFFB /*IrDA lower power mode enable*/
|
||||
|
||||
/* UART Mask */
|
||||
#define UART_Enable_Mask 0x0001 /* UART Enable Mask */
|
||||
#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */
|
||||
|
||||
/* UART LoopBack */
|
||||
#define UART_LoopBack_Disable_Mask 0xFF7F /* LoopBack Disable Mask */
|
||||
#define UART_LoopBack_Enable_Mask 0x0080 /* LoopBack Enable Mask */
|
||||
|
||||
#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */
|
||||
#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */
|
||||
#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */
|
||||
#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */
|
||||
#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask*/
|
||||
#define UART_FLAG_Mask 0x1F /* UART Flag Mask */
|
||||
#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */
|
||||
#define UART_RTS_LowLevel_Mask 0x0800 /* RTS signal is low */
|
||||
#define UART_RTS_HighLevel_Mask 0xF7FF /* RTS signal is High */
|
||||
#define UART_DTR_LowLevel_Mask 0x0400 /* DTR signal is low */
|
||||
#define UART_DTR_HighLevel_Mask 0xFBFF /* DTR signal is High */
|
||||
#define UART_ClearFlag_Mask 0xAA /* Clear Flag Mask */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_DeInit
|
||||
* Description : Deinitializes the UARTx peripheral registers
|
||||
* to their default reset values.
|
||||
* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_DeInit(UART_TypeDef* UARTx)
|
||||
{
|
||||
/* Reset the UARTx registers values */
|
||||
if(UARTx == UART0)
|
||||
{
|
||||
SCU_APBPeriphReset(__UART0,ENABLE);
|
||||
SCU_APBPeriphReset(__UART0,DISABLE);
|
||||
}
|
||||
else if(UARTx == UART1)
|
||||
{
|
||||
SCU_APBPeriphReset(__UART1,ENABLE);
|
||||
SCU_APBPeriphReset(__UART1,DISABLE);
|
||||
}
|
||||
else if(UARTx == UART2)
|
||||
{
|
||||
SCU_APBPeriphReset(__UART2,ENABLE);
|
||||
SCU_APBPeriphReset(__UART2,DISABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_Init
|
||||
* Description : Initializes the UARTx peripheral according to the specified
|
||||
* parameters in the UART_InitStruct .
|
||||
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
|
||||
* - UART_InitStruct: pointer to a UART_InitTypeDef structure
|
||||
* that contains the configuration information for the
|
||||
* specified UART peripheral.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct)
|
||||
{
|
||||
|
||||
u64 UART_MainClock = 0;
|
||||
u32 IntegerDivider = 0;
|
||||
u32 FractionalDivider = 0;
|
||||
|
||||
/* Clear the LCR[6:5] bits */
|
||||
UARTx->LCR &= UART_WordLength_Mask;
|
||||
/* Set the LCR[6:5] bits according to UART_WordLength value */
|
||||
UARTx->LCR |= UART_InitStruct->UART_WordLength;
|
||||
|
||||
/* Choose Stop Bits */
|
||||
if(UART_InitStruct->UART_StopBits == UART_StopBits_2)
|
||||
{
|
||||
/* 2 Stop Bit */
|
||||
UARTx->LCR |= UART_StopBits_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* One Stop Bits */
|
||||
UARTx->LCR &= UART_StopBits_1;
|
||||
}
|
||||
|
||||
/* Configure the Parity */
|
||||
/* Clear the LCR[7]and LCR[2:1] bits */
|
||||
UARTx->LCR &= UART_Parity_Mask;
|
||||
/* Set the LCR[7]and LCR[2:1] bits according to UART_Parity value */
|
||||
UARTx->LCR |= UART_InitStruct->UART_Parity;
|
||||
|
||||
/* Configure the BaudRate */
|
||||
UART_MainClock = (SCU_GetMCLKFreqValue())*1000;
|
||||
if((SCU->CLKCNTR & 0x200) != 0x200)
|
||||
{
|
||||
UART_MainClock = UART_MainClock/2;
|
||||
}
|
||||
/* Determine the integer part */
|
||||
IntegerDivider = ((100) * (UART_MainClock) / (16 * (UART_InitStruct->UART_BaudRate)));
|
||||
UARTx->IBRD = IntegerDivider / 100;
|
||||
|
||||
/* Determine the fractional part */
|
||||
FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD));
|
||||
UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100));
|
||||
|
||||
/* Choose the Hardware Flow Control */
|
||||
/* Clear the CR[15:14] bits */
|
||||
UARTx->CR &= UART_HardwareFlowControl_Mask;
|
||||
/* Set the CR[15:14] bits according to UART_HardwareFlowControl value */
|
||||
UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl;
|
||||
|
||||
/* Configure the UART mode */
|
||||
/* Clear the CR[9:8] bits */
|
||||
UARTx->CR &= UART_Mode_Mask;
|
||||
/* Set the CR[9:8] bits according to UART_Mode value */
|
||||
UARTx->CR |= UART_InitStruct->UART_Mode;
|
||||
|
||||
/* Enable or disable the FIFOs */
|
||||
/* Set the FIFOs Levels */
|
||||
if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable)
|
||||
{
|
||||
/* Enable the FIFOs */
|
||||
UARTx->LCR |= UART_FIFO_Enable;
|
||||
|
||||
/* Clear TXIFLSEL and RXIFLSEL bits */
|
||||
UARTx->IFLS &= UART_TxRxFIFOLevel_Mask;
|
||||
|
||||
/* Set RXIFLSEL bits according to UART_RxFIFOLevel value */
|
||||
UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3);
|
||||
|
||||
/* Set TXIFLSEL bits according to UART_TxFIFOLevel value */
|
||||
UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the FIFOs */
|
||||
UARTx->LCR &= UART_FIFO_Disable;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_StructInit
|
||||
* Description : Fills each UART_InitStruct member with its reset value.
|
||||
* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which
|
||||
* will be initialized.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_StructInit(UART_InitTypeDef* UART_InitStruct)
|
||||
{
|
||||
/* Reset the UART_InitStruct members */
|
||||
UART_InitStruct->UART_WordLength = UART_WordLength_8D;
|
||||
UART_InitStruct->UART_StopBits = UART_StopBits_1;
|
||||
UART_InitStruct->UART_Parity = UART_Parity_Odd ;
|
||||
UART_InitStruct->UART_BaudRate = 9600;
|
||||
UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None;
|
||||
UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx;
|
||||
UART_InitStruct->UART_FIFO = UART_FIFO_Enable;
|
||||
UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2;
|
||||
UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_Cmd
|
||||
* Description : Enables or disables the specified UART peripheral.
|
||||
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
|
||||
* - NewState: new state of the UARTx peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState == ENABLE)
|
||||
{
|
||||
/* Enable the selected UART by setting the UARTEN bit in the CR register */
|
||||
UARTx->CR |= UART_Enable_Mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected UART by clearing the UARTEN bit in the CR register */
|
||||
UARTx->CR &= UART_Disable_Mask;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_ITConfig
|
||||
* Description : Enables or disables the specified UART interrupts.
|
||||
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
|
||||
* - UART_IT: specifies the UART interrupts sources to be
|
||||
* enabled or disabled. This parameter can be any combination
|
||||
* of the following values:
|
||||
* - UART_IT_OverrunError: Overrun Error interrupt
|
||||
* - UART_IT_BreakError: Break Error interrupt
|
||||
* - UART_IT_ParityError: Parity Error interrupt
|
||||
* - UART_IT_FrameError: Frame Error interrupt
|
||||
* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt
|
||||
* - UART_IT_Transmit: Transmit interrupt
|
||||
* - UART_IT_Receive: Receive interrupt
|
||||
* - UART_IT_DSR: DSR interrupt
|
||||
* - UART_IT_DCD: DCD interrupt
|
||||
* - UART_IT_CTS: CTS interrupt
|
||||
* - UART_IT_RI: RI interrupt
|
||||
* - NewState: new state of the UARTx peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState)
|
||||
{
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
/* Enables the selected interrupts */
|
||||
UARTx->IMSC |= UART_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disables the selected interrupts */
|
||||
UARTx->IMSC &= ~UART_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_DMAConfig
|
||||
* Description : Configures the UARTx’s DMA interface.
|
||||
* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral
|
||||
* - UART_DMAOnError: specifies the DMA on error request.
|
||||
* This parameter can be:
|
||||
* - UART_DMAOnError_Enable: DMA receive request enabled
|
||||
* when the UART error interrupt is asserted.
|
||||
* - UART_DMAOnError_Disable: DMA receive request disabled
|
||||
* when the UART error interrupt is asserted.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError)
|
||||
{
|
||||
if(UART_DMAOnError == UART_DMAOnError_Enable)
|
||||
{
|
||||
UARTx->DMACR &= UART_DMAOnError_Enable;
|
||||
}
|
||||
else
|
||||
{
|
||||
UARTx->DMACR |= UART_DMAOnError_Disable;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_DMACmd
|
||||
* Description : Enables or disables the UARTx’s DMA interface.
|
||||
* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral
|
||||
* - UART_DMAReq: enables or disables the request of DMA from UART.
|
||||
* This parameter can be:
|
||||
* - UART_DMAReq_Tx: Transmit DMA Enable
|
||||
* - UART_DMAReq_Rx: Receive DMA Enable
|
||||
* - NewState: new state of the UARTx peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState)
|
||||
{
|
||||
if(UART_DMAReq == UART_DMAReq_Tx)
|
||||
{
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
UARTx->DMACR |= UART_DMAReq_Tx;
|
||||
}
|
||||
else
|
||||
{
|
||||
UARTx->DMACR &= ~UART_DMAReq_Tx;
|
||||
}
|
||||
}
|
||||
|
||||
if(UART_DMAReq == UART_DMAReq_Rx)
|
||||
{
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
UARTx->DMACR |= UART_DMAReq_Rx;
|
||||
}
|
||||
else
|
||||
{
|
||||
UARTx->DMACR &= ~UART_DMAReq_Rx;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_LoopBackConfig
|
||||
* Description : Enables or disables the LoopBack mode.
|
||||
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
|
||||
* - NewState: new state of the UARTx peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState == ENABLE)
|
||||
{
|
||||
/* Enable the LoopBack mode of the specified UART */
|
||||
UARTx->CR |= UART_LoopBack_Enable_Mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the LoopBack mode of the specified UART */
|
||||
UARTx->CR &= UART_LoopBack_Disable_Mask;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_GetFlagStatus
|
||||
* Description : Checks whether the specified UART flag is set or not.
|
||||
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
|
||||
* - UART_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* - UART_FLAG_OverrunError: Overrun error flag
|
||||
* - UART_FLAG_Break: break error flag
|
||||
* - UART_FLAG_ParityError: parity error flag
|
||||
* - UART_FLAG_FrameError: frame error flag
|
||||
* - UART_FLAG_RI: RI flag
|
||||
* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag
|
||||
* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag
|
||||
* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag
|
||||
* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag
|
||||
* - UART_FLAG_Busy: UART Busy flag
|
||||
* - UART_FLAG_CTS: CTS flag
|
||||
* - UART_FLAG_DCD: DCD flag
|
||||
* - UART_FLAG_DSR: DSR flag
|
||||
* - UART_RawIT_OverrunError: Overrun Error interrupt flag
|
||||
* - UART_RawIT_BreakError: Break Error interrupt flag
|
||||
* - UART_RawIT_ParityError: Parity Error interrupt flag
|
||||
* - UART_RawIT_FrameError: Frame Error interrupt flag
|
||||
* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag
|
||||
* - UART_RawIT_Transmit: Transmit interrupt flag
|
||||
* - UART_RawIT_Receive: Receive interrupt flag
|
||||
* - UART_RawIT_DSR: DSR interrupt flag
|
||||
* - UART_RawIT_DCD: DCD interrupt flag
|
||||
* - UART_RawIT_CTS: CTS interrupt flag
|
||||
* - UART_RawIT_RI: RI interrupt flag
|
||||
* Output : None
|
||||
* Return : The new state of UART_FLAG (SET or RESET).
|
||||
*******************************************************************************/
|
||||
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG)
|
||||
{
|
||||
|
||||
u32 UARTReg = 0, FlagPos = 0;
|
||||
u32 StatusReg = 0;
|
||||
|
||||
/* Get the UART register index */
|
||||
UARTReg = UART_FLAG >> 5;
|
||||
|
||||
/* Get the flag position */
|
||||
FlagPos = UART_FLAG & UART_FLAG_Mask;
|
||||
|
||||
if(UARTReg == 1) /* The flag to check is in RSR register */
|
||||
{
|
||||
StatusReg = UARTx->RSECR;
|
||||
}
|
||||
else if (UARTReg == 2) /* The flag to check is in FR register */
|
||||
{
|
||||
StatusReg = UARTx->FR;
|
||||
}
|
||||
else if(UARTReg == 3) /* The flag to check is in RIS register */
|
||||
{
|
||||
StatusReg = UARTx->RIS;
|
||||
}
|
||||
|
||||
if((StatusReg & (1 << FlagPos))!= RESET)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_ClearFlag
|
||||
* Description : Clears the UARTx’s flags(Frame, Parity, Break, Overrun error).
|
||||
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_ClearFlag(UART_TypeDef* UARTx)
|
||||
{
|
||||
/* Clear the flag */
|
||||
UARTx->RSECR = UART_ClearFlag_Mask;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_GetITStatus
|
||||
* Description : Checks whether the specified UART interrupt has occured or not.
|
||||
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
|
||||
* - UART_IT: specifies the interrupt pending bit to be checked.
|
||||
* This parameter can be one of the following values:
|
||||
* - UART_IT_OverrunError: Overrun Error interrupt
|
||||
* - UART_IT_BreakError: Break Error interrupt
|
||||
* - UART_IT_ParityError: Parity Error interrupt
|
||||
* - UART_IT_FrameError: Frame Error interrupt
|
||||
* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt
|
||||
* - UART_IT_Transmit: Transmit interrupt
|
||||
* - UART_IT_Receive: Receive interrupt
|
||||
* - UART_IT_DSR: DSR interrupt
|
||||
* - UART_IT_DCD: DCD interrupt
|
||||
* - UART_IT_CTS: CTS interrupt
|
||||
* - UART_IT_RI: RI interrupt
|
||||
* Output : None
|
||||
* Return : The new state of UART_IT (SET or RESET).
|
||||
*******************************************************************************/
|
||||
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT)
|
||||
{
|
||||
if((UARTx->MIS & UART_IT) != RESET)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_ClearITPendingBit
|
||||
* Description : Clears the UARTx’s interrupt pending bits.
|
||||
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
|
||||
* - UART_IT: specifies the interrupt pending bit to clear.
|
||||
* More than one interrupt can be cleared using the “|” operator.
|
||||
* This parameter can be:
|
||||
* - UART_IT_OverrunError: Overrun Error interrupt
|
||||
* - UART_IT_BreakError: Break Error interrupt
|
||||
* - UART_IT_ParityError: Parity Error interrupt
|
||||
* - UART_IT_FrameError: Frame Error interrupt
|
||||
* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt
|
||||
* - UART_IT_Transmit: Transmit interrupt
|
||||
* - UART_IT_Receive: Receive interrupt
|
||||
* - UART_IT_DSR: DSR interrupt
|
||||
* - UART_IT_DCD: DCD interrupt
|
||||
* - UART_IT_CTS: CTS interrupt
|
||||
* - UART_IT_RI: RI interrupt
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT)
|
||||
{
|
||||
/* Clear the specified interrupt */
|
||||
UARTx->ICR &= UART_IT;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_IrDALowPowerConfig
|
||||
* Description : Sets the IrDA low power mode
|
||||
* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral.
|
||||
* - NewState: new state of the UARTIrDA peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState)
|
||||
{
|
||||
UART_TypeDef* UARTx;
|
||||
|
||||
switch(IrDAx)
|
||||
{
|
||||
case IrDA0: UARTx = UART0;
|
||||
break;
|
||||
case IrDA1: UARTx = UART1;
|
||||
break;
|
||||
case IrDA2: UARTx = UART2;
|
||||
break;
|
||||
}
|
||||
|
||||
if (NewState == ENABLE)
|
||||
{
|
||||
UARTx->CR |= IrDA_LowPower_Enable_Mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
UARTx->CR &= IrDA_LowPower_Disable_Mask;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_IrDASetCounter
|
||||
* Description : Sets the IrDA counter divisor value.
|
||||
* Input : - UARTx: where x can be 0,1 or 2 to select the UART/IrDA peripheral.
|
||||
* - IrDA_Counter: IrDA counter divisor new value n low power mode(Hz).
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter)
|
||||
{
|
||||
UART_TypeDef* UARTx;
|
||||
u32 APBClock;
|
||||
switch(IrDAx)
|
||||
{
|
||||
case IrDA0: UARTx = UART0;
|
||||
break;
|
||||
case IrDA1: UARTx = UART1;
|
||||
break;
|
||||
case IrDA2: UARTx = UART2;
|
||||
break;
|
||||
}
|
||||
/* Get the APB frequency */
|
||||
APBClock = (SCU_GetPCLKFreqValue())*1000;
|
||||
/* Determine the Counter Divisor part */
|
||||
UARTx->ILPR = (((APBClock*10) / ( IrDA_Counter)) + 5 )/10;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_IrDACmd
|
||||
* Description : Enables or disables the UARTx’s IrDA interface.
|
||||
* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral
|
||||
* - NewState: new state of the UARTx peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_IrDACmd(u8 IrDAx, FunctionalState NewState)
|
||||
{
|
||||
UART_TypeDef* UARTx;
|
||||
|
||||
switch(IrDAx)
|
||||
{
|
||||
case IrDA0: UARTx = UART0;
|
||||
break;
|
||||
case IrDA1: UARTx = UART1;
|
||||
break;
|
||||
case IrDA2: UARTx = UART2;
|
||||
break;
|
||||
}
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
/* Enable the IrDA mode of the specified UART */
|
||||
UARTx->CR |= UART_IrDA_Enable_Mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the IrDA mode of the specified UART */
|
||||
UARTx->CR &= UART_IrDA_Disable_Mask;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_SendData
|
||||
* Description : Transmits signle Byte of data through the UARTx peripheral.
|
||||
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral.
|
||||
* - Data: the byte to transmit
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_SendData(UART_TypeDef* UARTx, u8 Data)
|
||||
{
|
||||
/* Transmit one byte */
|
||||
UARTx->DR = Data;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_ReceiveData
|
||||
* Description : Returns the most recent received Byte by the UARTx peripheral.
|
||||
* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.
|
||||
* Output : None
|
||||
* Return : The received data
|
||||
*******************************************************************************/
|
||||
u8 UART_ReceiveData(UART_TypeDef* UARTx)
|
||||
{
|
||||
/* Receive one byte */
|
||||
return ((u8)UARTx->DR);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_SendBreak
|
||||
* Description : Transmits break characters.
|
||||
* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_SendBreak(UART_TypeDef* UARTx)
|
||||
{
|
||||
/* Send break characters */
|
||||
UARTx->LCR |= UART_BreakChar_Mask;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_RTSConfig
|
||||
* Description : Sets or Resets the RTS signal
|
||||
* Input : - LevelState: new state of the RTS signal for UART0 only.
|
||||
* This parameter can be: LowLevel or HighLevel
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_RTSConfig(UART_LevelTypeDef LevelState)
|
||||
{
|
||||
if(LevelState == LowLevel)
|
||||
{
|
||||
UART0->CR |= UART_RTS_LowLevel_Mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
UART0->CR &= UART_RTS_HighLevel_Mask;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UART_DTRConfig
|
||||
* Description : Sets or Resets the DTR signal for UART0 only
|
||||
* Input : - LevelState: new state of the DTR signal.
|
||||
* This parameter can be: LowLevel or HighLevel
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void UART_DTRConfig(UART_LevelTypeDef LevelState)
|
||||
{
|
||||
if(LevelState == LowLevel)
|
||||
{
|
||||
UART0->CR |= UART_DTR_LowLevel_Mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
UART0->CR &= UART_DTR_HighLevel_Mask;
|
||||
}
|
||||
}
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
830
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_vic.c
Normal file
830
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_vic.c
Normal file
|
@ -0,0 +1,830 @@
|
|||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_vic.c
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file provides all the VIC software functions.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* Standard include ----------------------------------------------------------*/
|
||||
#include "91x_vic.h"
|
||||
|
||||
/* Include of other module interface headers ---------------------------------*/
|
||||
/* Local includes ------------------------------------------------------------*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
#define VIC_REGISTER_NUMBER 16
|
||||
#define VIC_PROTECTION_ENABLE_MASK 0x1
|
||||
#define VIC_PROTECTION_DISABLE_MASK 0xFFFFFFFE
|
||||
#define VIC_VECTOR_ENABLE_MASK 0x20
|
||||
#define VIC_IT_SOURCE_MASK 0xFFFFFFE0
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode);
|
||||
static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \
|
||||
void (*VIC_VectAddress)(void));
|
||||
static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority);
|
||||
static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority);
|
||||
|
||||
/* Interface functions -------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_DeInit
|
||||
* Description : Deinitialize the VIC module registers to their default reset
|
||||
* values.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void VIC_DeInit(void)
|
||||
{
|
||||
SCU_AHBPeriphReset(__VIC, ENABLE); /* VIC peripheral is under Reset */
|
||||
SCU_AHBPeriphReset(__VIC, DISABLE); /* VIC peripheral Reset off */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_GetIRQStatus
|
||||
* Description : Get the status of interrupts after IRQ masking.
|
||||
* Input : VIC_Source: specifies the number of the source line.
|
||||
* This parameter can be one of the following values:
|
||||
* - WDG_ITLine : VIC source 0
|
||||
* - SW_ITLine : VIC source 1
|
||||
* - ARMRX_ITLine : VIC source 2
|
||||
* - ARMTX_ITLine : VIC source 3
|
||||
* - TIM0_ITLine : VIC source 4
|
||||
* - TIM1_ITLine : VIC source 5
|
||||
* - TIM2_ITLine : VIC source 6
|
||||
* - TIM3_ITLine : VIC source 7
|
||||
* - USBHP_ITLine : VIC source 8
|
||||
* - USBLP_ITLine : VIC source 9
|
||||
* - SCU_ITLine : VIC source 10
|
||||
* - ENET_ITLine : VIC source 11
|
||||
* - DMA_ITLine : VIC source 12
|
||||
* - CAN_ITLine : VIC source 13
|
||||
* - MC_ITLine : VIC source 14
|
||||
* - ADC_ITLine : VIC source 15
|
||||
* - UART0_ITLine : VIC source 16
|
||||
* - UART1_ITLine : VIC source 17
|
||||
* - UART2_ITLine : VIC source 18
|
||||
* - I2C0_ITLine : VIC source 19
|
||||
* - I2C1_ITLine : VIC source 20
|
||||
* - SSP0_ITLine : VIC source 21
|
||||
* - SSP1_ITLine : VIC source 22
|
||||
* - LVD_ITLine : VIC source 23
|
||||
* - RTC_ITLine : VIC source 24
|
||||
* - WIU_ITLine : VIC source 25
|
||||
* - EXTIT0_ITLine: VIC source 26
|
||||
* - EXTIT1_ITLine: VIC source 27
|
||||
* - EXTIT2_ITLine: VIC source 28
|
||||
* - EXTIT3_ITLine: VIC source 29
|
||||
* - USBWU_ITLine : VIC source 30
|
||||
* - PFQBC_ITLine : VIC source 31
|
||||
* Output : None
|
||||
* Return : The status of the IRQ interrupt after masking (SET or RESET).
|
||||
*******************************************************************************/
|
||||
FlagStatus VIC_GetIRQStatus(u16 VIC_Source)
|
||||
{
|
||||
u32 VIC_Mask = 1;
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER)
|
||||
{
|
||||
if ((VIC0->ISR | VIC_Mask << VIC_Source) != RESET)
|
||||
return SET;
|
||||
else
|
||||
return RESET;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((VIC1->ISR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET)
|
||||
return SET;
|
||||
else
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_GetFIQStatus
|
||||
* Description : Get the status of interrupts after FIQ masking
|
||||
* Input : VIC_Source: specifies the number of the source line.
|
||||
* This parameter can be one of the following values:
|
||||
* - WDG_ITLine : VIC source 0
|
||||
* - SW_ITLine : VIC source 1
|
||||
* - ARMRX_ITLine : VIC source 2
|
||||
* - ARMTX_ITLine : VIC source 3
|
||||
* - TIM0_ITLine : VIC source 4
|
||||
* - TIM1_ITLine : VIC source 5
|
||||
* - TIM2_ITLine : VIC source 6
|
||||
* - TIM3_ITLine : VIC source 7
|
||||
* - USBHP_ITLine : VIC source 8
|
||||
* - USBLP_ITLine : VIC source 9
|
||||
* - SCU_ITLine : VIC source 10
|
||||
* - ENET_ITLine : VIC source 11
|
||||
* - DMA_ITLine : VIC source 12
|
||||
* - CAN_ITLine : VIC source 13
|
||||
* - MC_ITLine : VIC source 14
|
||||
* - ADC_ITLine : VIC source 15
|
||||
* - UART0_ITLine : VIC source 16
|
||||
* - UART1_ITLine : VIC source 17
|
||||
* - UART2_ITLine : VIC source 18
|
||||
* - I2C0_ITLine : VIC source 19
|
||||
* - I2C1_ITLine : VIC source 20
|
||||
* - SSP0_ITLine : VIC source 21
|
||||
* - SSP1_ITLine : VIC source 22
|
||||
* - LVD_ITLine : VIC source 23
|
||||
* - RTC_ITLine : VIC source 24
|
||||
* - WIU_ITLine : VIC source 25
|
||||
* - EXTIT0_ITLine: VIC source 26
|
||||
* - EXTIT1_ITLine: VIC source 27
|
||||
* - EXTIT2_ITLine: VIC source 28
|
||||
* - EXTIT3_ITLine: VIC source 29
|
||||
* - USBWU_ITLine : VIC source 30
|
||||
* - PFQBC_ITLine : VIC source 31
|
||||
* Output : None
|
||||
* Return : The status of the FIQ interrupt after masking (SET or RESET)
|
||||
*******************************************************************************/
|
||||
FlagStatus VIC_GetFIQStatus(u16 VIC_Source)
|
||||
{
|
||||
u32 VIC_Mask = 1;
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER)
|
||||
{
|
||||
if ((VIC0->RINTSR | VIC_Mask << VIC_Source) != RESET)
|
||||
return SET;
|
||||
else
|
||||
return RESET;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((VIC1->RINTSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET)
|
||||
return SET;
|
||||
else
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_GetSourceITStatus
|
||||
* Description : Get the status of the source interrupts before masking.
|
||||
* Input : VIC_Source: specifies the number of the source line.
|
||||
* This parameter can be one of the following values:
|
||||
* - WDG_ITLine : VIC source 0
|
||||
* - SW_ITLine : VIC source 1
|
||||
* - ARMRX_ITLine : VIC source 2
|
||||
* - ARMTX_ITLine : VIC source 3
|
||||
* - TIM0_ITLine : VIC source 4
|
||||
* - TIM1_ITLine : VIC source 5
|
||||
* - TIM2_ITLine : VIC source 6
|
||||
* - TIM3_ITLine : VIC source 7
|
||||
* - USBHP_ITLine : VIC source 8
|
||||
* - USBLP_ITLine : VIC source 9
|
||||
* - SCU_ITLine : VIC source 10
|
||||
* - ENET_ITLine : VIC source 11
|
||||
* - DMA_ITLine : VIC source 12
|
||||
* - CAN_ITLine : VIC source 13
|
||||
* - MC_ITLine : VIC source 14
|
||||
* - ADC_ITLine : VIC source 15
|
||||
* - UART0_ITLine : VIC source 16
|
||||
* - UART1_ITLine : VIC source 17
|
||||
* - UART2_ITLine : VIC source 18
|
||||
* - I2C0_ITLine : VIC source 19
|
||||
* - I2C1_ITLine : VIC source 20
|
||||
* - SSP0_ITLine : VIC source 21
|
||||
* - SSP1_ITLine : VIC source 22
|
||||
* - LVD_ITLine : VIC source 23
|
||||
* - RTC_ITLine : VIC source 24
|
||||
* - WIU_ITLine : VIC source 25
|
||||
* - EXTIT0_ITLine: VIC source 26
|
||||
* - EXTIT1_ITLine: VIC source 27
|
||||
* - EXTIT2_ITLine: VIC source 28
|
||||
* - EXTIT3_ITLine: VIC source 29
|
||||
* - USBWU_ITLine : VIC source 30
|
||||
* - PFQBC_ITLine : VIC source 31
|
||||
* Output : None
|
||||
* Return : The status of the source interrupt before masking
|
||||
*******************************************************************************/
|
||||
FlagStatus VIC_GetSourceITStatus(u16 VIC_Source)
|
||||
{
|
||||
u32 VIC_Mask = 1;
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER)
|
||||
{
|
||||
if ((VIC0->FSR | VIC_Mask << VIC_Source) != RESET)
|
||||
return SET;
|
||||
else
|
||||
return RESET;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((VIC1->FSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET)
|
||||
return SET;
|
||||
else
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_ITModeConfig
|
||||
* Description : Select the type of interrupt (IRQ or FIQ)
|
||||
* Input1 : VIC_Source: specifies the number of the source line.
|
||||
* This parameter can be one of the following values:
|
||||
* - WDG_ITLine : VIC source 0
|
||||
* - SW_ITLine : VIC source 1
|
||||
* - ARMRX_ITLine : VIC source 2
|
||||
* - ARMTX_ITLine : VIC source 3
|
||||
* - TIM0_ITLine : VIC source 4
|
||||
* - TIM1_ITLine : VIC source 5
|
||||
* - TIM2_ITLine : VIC source 6
|
||||
* - TIM3_ITLine : VIC source 7
|
||||
* - USBHP_ITLine : VIC source 8
|
||||
* - USBLP_ITLine : VIC source 9
|
||||
* - SCU_ITLine : VIC source 10
|
||||
* - ENET_ITLine : VIC source 11
|
||||
* - DMA_ITLine : VIC source 12
|
||||
* - CAN_ITLine : VIC source 13
|
||||
* - MC_ITLine : VIC source 14
|
||||
* - ADC_ITLine : VIC source 15
|
||||
* - UART0_ITLine : VIC source 16
|
||||
* - UART1_ITLine : VIC source 17
|
||||
* - UART2_ITLine : VIC source 18
|
||||
* - I2C0_ITLine : VIC source 19
|
||||
* - I2C1_ITLine : VIC source 20
|
||||
* - SSP0_ITLine : VIC source 21
|
||||
* - SSP1_ITLine : VIC source 22
|
||||
* - LVD_ITLine : VIC source 23
|
||||
* - RTC_ITLine : VIC source 24
|
||||
* - WIU_ITLine : VIC source 25
|
||||
* - EXTIT0_ITLine: VIC source 26
|
||||
* - EXTIT1_ITLine: VIC source 27
|
||||
* - EXTIT2_ITLine: VIC source 28
|
||||
* - EXTIT3_ITLine: VIC source 29
|
||||
* - USBWU_ITLine : VIC source 30
|
||||
* - PFQBC_ITLine : VIC source 31
|
||||
* Input2 : VIC_LineMode :specifies the type of interrupt of the source
|
||||
* line. This parameter can be one of the following values:
|
||||
* - VIC_IRQ: the correspondent line is configured as IRQ.
|
||||
* - VIC_FIQ: the correspondent line is configured as FIQ.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode)
|
||||
{
|
||||
u32 VIC_Mask = 1;
|
||||
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
|
||||
{
|
||||
if (VIC_LineMode == VIC_IRQ)
|
||||
VIC0->INTSR &= ~(VIC_Mask << VIC_Source);
|
||||
else /* VIC_LineMode == VIC_FIQ */
|
||||
VIC0->INTSR |= (VIC_Mask << VIC_Source);
|
||||
}
|
||||
else /* VIC1 */
|
||||
{
|
||||
if (VIC_LineMode == VIC_IRQ)
|
||||
VIC1->INTSR &= ~(VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
|
||||
else /* VIC_LineMode == VIC_FIQ */
|
||||
VIC1->INTSR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_ITCmd
|
||||
* Description : Enable or disable the interrupt request lines.
|
||||
* Input1 : VIC_Source: specifies the number of the source line.
|
||||
* This parameter can be one of the following values:
|
||||
* - WDG_ITLine : VIC source 0
|
||||
* - SW_ITLine : VIC source 1
|
||||
* - ARMRX_ITLine : VIC source 2
|
||||
* - ARMTX_ITLine : VIC source 3
|
||||
* - TIM0_ITLine : VIC source 4
|
||||
* - TIM1_ITLine : VIC source 5
|
||||
* - TIM2_ITLine : VIC source 6
|
||||
* - TIM3_ITLine : VIC source 7
|
||||
* - USBHP_ITLine : VIC source 8
|
||||
* - USBLP_ITLine : VIC source 9
|
||||
* - SCU_ITLine : VIC source 10
|
||||
* - ENET_ITLine : VIC source 11
|
||||
* - DMA_ITLine : VIC source 12
|
||||
* - CAN_ITLine : VIC source 13
|
||||
* - MC_ITLine : VIC source 14
|
||||
* - ADC_ITLine : VIC source 15
|
||||
* - UART0_ITLine : VIC source 16
|
||||
* - UART1_ITLine : VIC source 17
|
||||
* - UART2_ITLine : VIC source 18
|
||||
* - I2C0_ITLine : VIC source 19
|
||||
* - I2C1_ITLine : VIC source 20
|
||||
* - SSP0_ITLine : VIC source 21
|
||||
* - SSP1_ITLine : VIC source 22
|
||||
* - LVD_ITLine : VIC source 23
|
||||
* - RTC_ITLine : VIC source 24
|
||||
* - WIU_ITLine : VIC source 25
|
||||
* - EXTIT0_ITLine: VIC source 26
|
||||
* - EXTIT1_ITLine: VIC source 27
|
||||
* - EXTIT2_ITLine: VIC source 28
|
||||
* - EXTIT3_ITLine: VIC source 29
|
||||
* - USBWU_ITLine : VIC source 30
|
||||
* - PFQBC_ITLine : VIC source 31
|
||||
* Input2 : FMI_NewState: specifies the line status.
|
||||
* This parameter can be one of the following values:
|
||||
* - ENABLE: The line is enabled.
|
||||
* - DISABLE: The line is disabled.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState)
|
||||
{
|
||||
u32 VIC_Mask = 1;
|
||||
|
||||
if (VIC_NewState == ENABLE)
|
||||
{
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
|
||||
VIC0->INTER |= (VIC_Mask << VIC_Source);
|
||||
else /* VIC1 */
|
||||
VIC1->INTER |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
|
||||
}
|
||||
else /* VIC_NewState == DISABLE */
|
||||
{
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
|
||||
VIC0->INTECR |= (VIC_Mask << VIC_Source);
|
||||
else /* VIC1 */
|
||||
VIC1->INTECR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_SWITCmd
|
||||
* Description : Generate a software interrupt for the specific source
|
||||
* interrupt.
|
||||
* Input1 : VIC_Source: specifies the number of the source line.
|
||||
* This parameter can be one of the following values:
|
||||
* - WDG_ITLine : VIC source 0
|
||||
* - SW_ITLine : VIC source 1
|
||||
* - ARMRX_ITLine : VIC source 2
|
||||
* - ARMTX_ITLine : VIC source 3
|
||||
* - TIM0_ITLine : VIC source 4
|
||||
* - TIM1_ITLine : VIC source 5
|
||||
* - TIM2_ITLine : VIC source 6
|
||||
* - TIM3_ITLine : VIC source 7
|
||||
* - USBHP_ITLine : VIC source 8
|
||||
* - USBLP_ITLine : VIC source 9
|
||||
* - SCU_ITLine : VIC source 10
|
||||
* - ENET_ITLine : VIC source 11
|
||||
* - DMA_ITLine : VIC source 12
|
||||
* - CAN_ITLine : VIC source 13
|
||||
* - MC_ITLine : VIC source 14
|
||||
* - ADC_ITLine : VIC source 15
|
||||
* - UART0_ITLine : VIC source 16
|
||||
* - UART1_ITLine : VIC source 17
|
||||
* - UART2_ITLine : VIC source 18
|
||||
* - I2C0_ITLine : VIC source 19
|
||||
* - I2C1_ITLine : VIC source 20
|
||||
* - SSP0_ITLine : VIC source 21
|
||||
* - SSP1_ITLine : VIC source 22
|
||||
* - LVD_ITLine : VIC source 23
|
||||
* - RTC_ITLine : VIC source 24
|
||||
* - WIU_ITLine : VIC source 25
|
||||
* - EXTIT0_ITLine: VIC source 26
|
||||
* - EXTIT1_ITLine: VIC source 27
|
||||
* - EXTIT2_ITLine: VIC source 28
|
||||
* - EXTIT3_ITLine: VIC source 29
|
||||
* - USBWU_ITLine : VIC source 30
|
||||
* - PFQBC_ITLine : VIC source 31
|
||||
* Input2 : FMI_NewState: specifies the software interrupt status.
|
||||
* This parameter can be one of the following values:
|
||||
* - ENABLE: The software interrupt is enabled.
|
||||
* - DISABLE: The software interrupt is disabled.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState)
|
||||
{
|
||||
u32 VIC_Mask = 1;
|
||||
|
||||
if (VIC_NewState == ENABLE)
|
||||
{
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
|
||||
VIC0->SWINTR |= (VIC_Mask << VIC_Source);
|
||||
else /* VIC1 */
|
||||
VIC1->SWINTR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
|
||||
}
|
||||
else /* VIC_NewState == DISABLE */
|
||||
{
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
|
||||
VIC0->SWINTCR = (VIC_Mask << VIC_Source);
|
||||
else /* VIC1 */
|
||||
VIC1->SWINTCR = (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_ProtectionCmd
|
||||
* Description : Enable or Disable the register access protection.
|
||||
* Input : FMI_NewState: specifies the protection status.
|
||||
* This parameter can be one of the following values:
|
||||
* - ENABLE: The protection is enabled.
|
||||
* - DISABLE: The protection is disabled.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void VIC_ProtectionCmd(FunctionalState VIC_NewState)
|
||||
{
|
||||
if (VIC_NewState == ENABLE)
|
||||
{
|
||||
VIC0->PER |= VIC_PROTECTION_ENABLE_MASK;
|
||||
VIC1->PER |= VIC_PROTECTION_ENABLE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
VIC0->PER &= VIC_PROTECTION_DISABLE_MASK;
|
||||
VIC1->PER &= VIC_PROTECTION_DISABLE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_GetCurrentISRAdd
|
||||
* Description : Get the address of the current active ISR.
|
||||
* Input : VICx: specifies the VIC peripheral
|
||||
* This parameter can be one of the following values:
|
||||
* - VIC0: To select VIC0.
|
||||
* - VIC1: To select VIC1.
|
||||
* Output : None
|
||||
* Return : The Address of the active ISR.
|
||||
*******************************************************************************/
|
||||
u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx)
|
||||
{
|
||||
return VICx->VAR;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_ISRVectAddConfig
|
||||
* Description : Configuration of the ISR vector address.
|
||||
* Input1 : VIC_Source: specifies the number of the source line.
|
||||
* This parameter can be one of the following values:
|
||||
* - WDG_ITLine : VIC source 0
|
||||
* - SW_ITLine : VIC source 1
|
||||
* - ARMRX_ITLine : VIC source 2
|
||||
* - ARMTX_ITLine : VIC source 3
|
||||
* - TIM0_ITLine : VIC source 4
|
||||
* - TIM1_ITLine : VIC source 5
|
||||
* - TIM2_ITLine : VIC source 6
|
||||
* - TIM3_ITLine : VIC source 7
|
||||
* - USBHP_ITLine : VIC source 8
|
||||
* - USBLP_ITLine : VIC source 9
|
||||
* - SCU_ITLine : VIC source 10
|
||||
* - ENET_ITLine : VIC source 11
|
||||
* - DMA_ITLine : VIC source 12
|
||||
* - CAN_ITLine : VIC source 13
|
||||
* - MC_ITLine : VIC source 14
|
||||
* - ADC_ITLine : VIC source 15
|
||||
* - UART0_ITLine : VIC source 16
|
||||
* - UART1_ITLine : VIC source 17
|
||||
* - UART2_ITLine : VIC source 18
|
||||
* - I2C0_ITLine : VIC source 19
|
||||
* - I2C1_ITLine : VIC source 20
|
||||
* - SSP0_ITLine : VIC source 21
|
||||
* - SSP1_ITLine : VIC source 22
|
||||
* - LVD_ITLine : VIC source 23
|
||||
* - RTC_ITLine : VIC source 24
|
||||
* - WIU_ITLine : VIC source 25
|
||||
* - EXTIT0_ITLine: VIC source 26
|
||||
* - EXTIT1_ITLine: VIC source 27
|
||||
* - EXTIT2_ITLine: VIC source 28
|
||||
* - EXTIT3_ITLine: VIC source 29
|
||||
* - USBWU_ITLine : VIC source 30
|
||||
* - PFQBC_ITLine : VIC source 31
|
||||
* Input2 : VIC_Priority: specifies the priority of the interrupt.
|
||||
* It can be a value from 0 to 15. 0 is the highest priority.
|
||||
* Input3 : void (*VIC_VectAddress)(void): specifies the ISR vector
|
||||
* address pointer.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \
|
||||
void (*VIC_VectAddress)(void))
|
||||
{
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
|
||||
VIC0->VAiR[VIC_Priority] = (u32)VIC_VectAddress;
|
||||
else /* VIC1 */
|
||||
VIC1->VAiR[VIC_Priority] = (u32)VIC_VectAddress;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_GetISRVectAdd
|
||||
* Description : Get the ISR vector address of the correspondent line.
|
||||
* Input : VIC_Source: specifies the number of the source line.
|
||||
* This parameter can be one of the following values:
|
||||
* - WDG_ITLine : VIC source 0
|
||||
* - SW_ITLine : VIC source 1
|
||||
* - ARMRX_ITLine : VIC source 2
|
||||
* - ARMTX_ITLine : VIC source 3
|
||||
* - TIM0_ITLine : VIC source 4
|
||||
* - TIM1_ITLine : VIC source 5
|
||||
* - TIM2_ITLine : VIC source 6
|
||||
* - TIM3_ITLine : VIC source 7
|
||||
* - USBHP_ITLine : VIC source 8
|
||||
* - USBLP_ITLine : VIC source 9
|
||||
* - SCU_ITLine : VIC source 10
|
||||
* - ENET_ITLine : VIC source 11
|
||||
* - DMA_ITLine : VIC source 12
|
||||
* - CAN_ITLine : VIC source 13
|
||||
* - MC_ITLine : VIC source 14
|
||||
* - ADC_ITLine : VIC source 15
|
||||
* - UART0_ITLine : VIC source 16
|
||||
* - UART1_ITLine : VIC source 17
|
||||
* - UART2_ITLine : VIC source 18
|
||||
* - I2C0_ITLine : VIC source 19
|
||||
* - I2C1_ITLine : VIC source 20
|
||||
* - SSP0_ITLine : VIC source 21
|
||||
* - SSP1_ITLine : VIC source 22
|
||||
* - LVD_ITLine : VIC source 23
|
||||
* - RTC_ITLine : VIC source 24
|
||||
* - WIU_ITLine : VIC source 25
|
||||
* - EXTIT0_ITLine: VIC source 26
|
||||
* - EXTIT1_ITLine: VIC source 27
|
||||
* - EXTIT2_ITLine: VIC source 28
|
||||
* - EXTIT3_ITLine: VIC source 29
|
||||
* - USBWU_ITLine : VIC source 30
|
||||
* - PFQBC_ITLine : VIC source 31
|
||||
* Output : None
|
||||
* Return : The correspondent ISR vector address.
|
||||
*******************************************************************************/
|
||||
u32 VIC_GetISRVectAdd(u16 VIC_Source)
|
||||
{
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
|
||||
return VIC0->VAiR[VIC_Source];
|
||||
else /* VIC1 */
|
||||
return VIC1->VAiR[VIC_Source - VIC_REGISTER_NUMBER];
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_VectEnableConfig
|
||||
* Description : Enable the vector interrupt.
|
||||
* Input1 : VIC_Source: specifies the number of the source line.
|
||||
* This parameter can be one of the following values:
|
||||
* - WDG_ITLine : VIC source 0
|
||||
* - SW_ITLine : VIC source 1
|
||||
* - ARMRX_ITLine : VIC source 2
|
||||
* - ARMTX_ITLine : VIC source 3
|
||||
* - TIM0_ITLine : VIC source 4
|
||||
* - TIM1_ITLine : VIC source 5
|
||||
* - TIM2_ITLine : VIC source 6
|
||||
* - TIM3_ITLine : VIC source 7
|
||||
* - USBHP_ITLine : VIC source 8
|
||||
* - USBLP_ITLine : VIC source 9
|
||||
* - SCU_ITLine : VIC source 10
|
||||
* - ENET_ITLine : VIC source 11
|
||||
* - DMA_ITLine : VIC source 12
|
||||
* - CAN_ITLine : VIC source 13
|
||||
* - MC_ITLine : VIC source 14
|
||||
* - ADC_ITLine : VIC source 15
|
||||
* - UART0_ITLine : VIC source 16
|
||||
* - UART1_ITLine : VIC source 17
|
||||
* - UART2_ITLine : VIC source 18
|
||||
* - I2C0_ITLine : VIC source 19
|
||||
* - I2C1_ITLine : VIC source 20
|
||||
* - SSP0_ITLine : VIC source 21
|
||||
* - SSP1_ITLine : VIC source 22
|
||||
* - LVD_ITLine : VIC source 23
|
||||
* - RTC_ITLine : VIC source 24
|
||||
* - WIU_ITLine : VIC source 25
|
||||
* - EXTIT0_ITLine: VIC source 26
|
||||
* - EXTIT1_ITLine: VIC source 27
|
||||
* - EXTIT2_ITLine: VIC source 28
|
||||
* - EXTIT3_ITLine: VIC source 29
|
||||
* - USBWU_ITLine : VIC source 30
|
||||
* - PFQBC_ITLine : VIC source 31
|
||||
* Input2 : VIC_Priority: specifies the priority of the interrupt.
|
||||
* It can be a value from 0 to 15. 0 is the highest priority.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority)
|
||||
{
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
|
||||
VIC0->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK;
|
||||
else /* VIC1 */
|
||||
VIC1->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_ITSourceConfig
|
||||
* Description : Select the interrupt source.
|
||||
* Input1 : VIC_Source: specifies the number of the source line.
|
||||
* This parameter can be one of the following values:
|
||||
* - WDG_ITLine : VIC source 0
|
||||
* - SW_ITLine : VIC source 1
|
||||
* - ARMRX_ITLine : VIC source 2
|
||||
* - ARMTX_ITLine : VIC source 3
|
||||
* - TIM0_ITLine : VIC source 4
|
||||
* - TIM1_ITLine : VIC source 5
|
||||
* - TIM2_ITLine : VIC source 6
|
||||
* - TIM3_ITLine : VIC source 7
|
||||
* - USBHP_ITLine : VIC source 8
|
||||
* - USBLP_ITLine : VIC source 9
|
||||
* - SCU_ITLine : VIC source 10
|
||||
* - ENET_ITLine : VIC source 11
|
||||
* - DMA_ITLine : VIC source 12
|
||||
* - CAN_ITLine : VIC source 13
|
||||
* - MC_ITLine : VIC source 14
|
||||
* - ADC_ITLine : VIC source 15
|
||||
* - UART0_ITLine : VIC source 16
|
||||
* - UART1_ITLine : VIC source 17
|
||||
* - UART2_ITLine : VIC source 18
|
||||
* - I2C0_ITLine : VIC source 19
|
||||
* - I2C1_ITLine : VIC source 20
|
||||
* - SSP0_ITLine : VIC source 21
|
||||
* - SSP1_ITLine : VIC source 22
|
||||
* - LVD_ITLine : VIC source 23
|
||||
* - RTC_ITLine : VIC source 24
|
||||
* - WIU_ITLine : VIC source 25
|
||||
* - EXTIT0_ITLine: VIC source 26
|
||||
* - EXTIT1_ITLine: VIC source 27
|
||||
* - EXTIT2_ITLine: VIC source 28
|
||||
* - EXTIT3_ITLine: VIC source 29
|
||||
* - USBWU_ITLine : VIC source 30
|
||||
* - PFQBC_ITLine : VIC source 31
|
||||
* Input2 : VIC_Priority: specifies the priority of the interrupt.
|
||||
* It can be a value from 0 to 15. 0 is the highest priority.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority)
|
||||
{
|
||||
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
|
||||
{
|
||||
VIC0->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK;
|
||||
VIC0->VCiR[VIC_Priority] |= VIC_Source;
|
||||
}
|
||||
else /* VIC1 */
|
||||
{
|
||||
VIC1->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK;
|
||||
VIC1->VCiR[VIC_Priority] |= VIC_Source - VIC_REGISTER_NUMBER;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : VIC_Config
|
||||
* Description : Configure the ISR, the line, the mode and the priority for
|
||||
* each interrupt source line.
|
||||
* Input1 : VIC_Source: specifies the number of the source line.
|
||||
* This parameter can be one of the following values:
|
||||
* - WDG_ITLine : VIC source 0
|
||||
* - SW_ITLine : VIC source 1
|
||||
* - ARMRX_ITLine : VIC source 2
|
||||
* - ARMTX_ITLine : VIC source 3
|
||||
* - TIM0_ITLine : VIC source 4
|
||||
* - TIM1_ITLine : VIC source 5
|
||||
* - TIM2_ITLine : VIC source 6
|
||||
* - TIM3_ITLine : VIC source 7
|
||||
* - USBHP_ITLine : VIC source 8
|
||||
* - USBLP_ITLine : VIC source 9
|
||||
* - SCU_ITLine : VIC source 10
|
||||
* - ENET_ITLine : VIC source 11
|
||||
* - DMA_ITLine : VIC source 12
|
||||
* - CAN_ITLine : VIC source 13
|
||||
* - MC_ITLine : VIC source 14
|
||||
* - ADC_ITLine : VIC source 15
|
||||
* - UART0_ITLine : VIC source 16
|
||||
* - UART1_ITLine : VIC source 17
|
||||
* - UART2_ITLine : VIC source 18
|
||||
* - I2C0_ITLine : VIC source 19
|
||||
* - I2C1_ITLine : VIC source 20
|
||||
* - SSP0_ITLine : VIC source 21
|
||||
* - SSP1_ITLine : VIC source 22
|
||||
* - LVD_ITLine : VIC source 23
|
||||
* - RTC_ITLine : VIC source 24
|
||||
* - WIU_ITLine : VIC source 25
|
||||
* - EXTIT0_ITLine: VIC source 26
|
||||
* - EXTIT1_ITLine: VIC source 27
|
||||
* - EXTIT2_ITLine: VIC source 28
|
||||
* - EXTIT3_ITLine: VIC source 29
|
||||
* - USBWU_ITLine : VIC source 30
|
||||
* - PFQBC_ITLine : VIC source 31
|
||||
* Input2 : VIC_LineMode :specifies the type of interrupt of the source
|
||||
* line. This parameter can be one of the following values:
|
||||
* - VIC_IRQ: the correspondent line is configured as IRQ.
|
||||
* - VIC_FIQ: the correspondent line is configured as FIQ.
|
||||
* Input3 : VIC_Priority: specifies the priority of the interrupt.
|
||||
* It can be a value from 0 to 15. 0 is the highest priority.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority)
|
||||
{
|
||||
switch (VIC_Source)
|
||||
{
|
||||
case 0: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WDG_IRQHandler);
|
||||
break;
|
||||
|
||||
case 1: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SW_IRQHandler);
|
||||
break;
|
||||
|
||||
case 2: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMRX_IRQHandler);
|
||||
break;
|
||||
|
||||
case 3: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMTX_IRQHandler);
|
||||
break;
|
||||
|
||||
case 4: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM0_IRQHandler);
|
||||
break;
|
||||
|
||||
case 5: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM1_IRQHandler);
|
||||
break;
|
||||
|
||||
case 6: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM2_IRQHandler);
|
||||
break;
|
||||
|
||||
case 7: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM3_IRQHandler);
|
||||
break;
|
||||
|
||||
case 8: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBHP_IRQHandler);
|
||||
break;
|
||||
|
||||
case 9: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBLP_IRQHandler);
|
||||
break;
|
||||
|
||||
case 10: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SCU_IRQHandler);
|
||||
break;
|
||||
|
||||
case 11: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ENET_IRQHandler);
|
||||
break;
|
||||
|
||||
case 12: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, DMA_IRQHandler);
|
||||
break;
|
||||
|
||||
case 13: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, CAN_IRQHandler);
|
||||
break;
|
||||
|
||||
case 14: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, MC_IRQHandler);
|
||||
break;
|
||||
|
||||
case 15: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ADC_IRQHandler);
|
||||
break;
|
||||
|
||||
case 16: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART0_IRQHandler);
|
||||
break;
|
||||
|
||||
case 17: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART1_IRQHandler);
|
||||
break;
|
||||
|
||||
case 18: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART2_IRQHandler);
|
||||
break;
|
||||
|
||||
case 19: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C0_IRQHandler);
|
||||
break;
|
||||
|
||||
case 20: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C1_IRQHandler);
|
||||
break;
|
||||
|
||||
case 21: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP0_IRQHandler);
|
||||
break;
|
||||
|
||||
case 22: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP1_IRQHandler);
|
||||
break;
|
||||
|
||||
case 23: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, LVD_IRQHandler);
|
||||
break;
|
||||
|
||||
case 24: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, RTC_IRQHandler);
|
||||
break;
|
||||
|
||||
case 25: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WIU_IRQHandler);
|
||||
break;
|
||||
|
||||
case 26: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT0_IRQHandler);
|
||||
break;
|
||||
|
||||
case 27: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT1_IRQHandler);
|
||||
break;
|
||||
|
||||
case 28: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT2_IRQHandler);
|
||||
break;
|
||||
|
||||
case 29: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT3_IRQHandler);
|
||||
break;
|
||||
|
||||
case 30: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBWU_IRQHandler);
|
||||
break;
|
||||
|
||||
case 31: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, PFQBC_IRQHandler);
|
||||
break;
|
||||
|
||||
default: break;
|
||||
}
|
||||
VIC_ITModeConfig(VIC_Source, VIC_LineMode);
|
||||
VIC_VectEnableConfig(VIC_Source, VIC_Priority);
|
||||
VIC_ITSourceConfig(VIC_Source, VIC_Priority);
|
||||
}
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
277
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_wdg.c
Normal file
277
20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_wdg.c
Normal file
|
@ -0,0 +1,277 @@
|
|||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_wdg.c
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file provides all the WDG software functions.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "91x_wdg.h"
|
||||
#include "91x_scu.h"
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* WDG End of Count interrupt Flag */
|
||||
#define WDG_FLAG_EC 0x0001
|
||||
|
||||
|
||||
/* WDG End of Count interrupt request */
|
||||
#define WDG_IT_EC 0x0001
|
||||
|
||||
|
||||
|
||||
/* WDG Start/Stop counter */
|
||||
#define WDG_Counter_Start 0x0002
|
||||
#define WDG_Counter_Stop 0xFFFD
|
||||
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Registers reset value */
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/******************************************************************************
|
||||
* Function Name : WDG_DeInit
|
||||
* Description : Deinitializes the WDG peripheral registers to their default
|
||||
* reset values.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void WDG_DeInit(void)
|
||||
{
|
||||
|
||||
SCU_APBPeriphReset(__WDG, ENABLE); /*WDG peripheral under Reset */
|
||||
SCU_APBPeriphReset(__WDG, DISABLE); /*WDG peripheral Reset off*/
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : WDG_StructInit
|
||||
* Description : Fills the WDG_InitTypeDef structure member with its reset
|
||||
* value.
|
||||
* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure
|
||||
* which will be initialized.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct)
|
||||
{
|
||||
/* Select the Watchdog running mode*/
|
||||
WDG_InitStruct->WDG_Mode = WDG_Mode_Timer;
|
||||
|
||||
/* Select the source clock */
|
||||
WDG_InitStruct-> WDG_ClockSource = WDG_ClockSource_Apb;
|
||||
|
||||
/* Initialize Prescaler */
|
||||
WDG_InitStruct->WDG_Prescaler =0xFF;
|
||||
|
||||
/* Initialize Preload */
|
||||
WDG_InitStruct->WDG_Preload =0xFFFF;
|
||||
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : WDG_Init
|
||||
* Description : Initializes WDG peripheral according to the specified
|
||||
* parameters in the WDG_InitStruct.
|
||||
* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that
|
||||
* contains the configuration information for the WDG peripheral.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void WDG_Init(WDG_InitTypeDef* WDG_InitStruct)
|
||||
{
|
||||
|
||||
|
||||
if(WDG_InitStruct->WDG_ClockSource == WDG_ClockSource_Apb)
|
||||
{
|
||||
/* Select The APB clock as clock source */
|
||||
WDG->CR &= WDG_ClockSource_Apb;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Select the RTC clock as source */
|
||||
WDG->CR |= WDG_ClockSource_Rtc ;
|
||||
}
|
||||
|
||||
|
||||
/* Configure WDG Prescaler register value */
|
||||
WDG->PR = WDG_InitStruct->WDG_Prescaler;
|
||||
|
||||
/* Configure WDG Pre-load register value */
|
||||
WDG->VR = WDG_InitStruct->WDG_Preload ;
|
||||
|
||||
|
||||
if(WDG_InitStruct->WDG_Mode == WDG_Mode_Timer)
|
||||
{
|
||||
/* Select Timer mode */
|
||||
WDG->CR &= WDG_Mode_Timer;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Select WDG mode */
|
||||
WDG->CR |= WDG_Mode_Wdg ;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : WDG_Cmd
|
||||
* Description : Enables or disables the WDG peripheral.
|
||||
* Input : NewState: new state of the WDG peripheral (Newstate can be
|
||||
* ENABLE or DISABLE)
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void WDG_Cmd(FunctionalState NewState )
|
||||
{
|
||||
if((WDG->CR & WDG_Mode_Wdg) == 0)
|
||||
{
|
||||
/* Timer mode */
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
/* Start timer by setting SC bit in Control register */
|
||||
WDG->CR |= WDG_Counter_Start;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Stop timer by clearning SC bit in Control register */
|
||||
WDG->CR &= WDG_Counter_Stop;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Watchdog mode */
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
WDG->KR = WDG_KeyValue1;
|
||||
WDG->KR = WDG_KeyValue2;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : WDG_ITConfig
|
||||
* Description : Enables or disables the WDG End of Count(EC) interrupt.
|
||||
* Input : Newstate: new state of the End of Count(EC) WDG interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void WDG_ITConfig(FunctionalState NewState)
|
||||
{
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
/* Enable the End of Count interrupt */
|
||||
WDG->MR |= WDG_IT_EC;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the End of Count interrupt */
|
||||
WDG->MR &= ~WDG_IT_EC;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : WDG_GetCounter
|
||||
* Description : Gets the WDG’s current counter value.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : The WDG current counter value
|
||||
*******************************************************************************/
|
||||
u16 WDG_GetCounter(void)
|
||||
{
|
||||
return WDG->CNT;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : WDG_GetITStatus
|
||||
* Description : Checks whether the WDG End of Count(EC) interrupt is occured or not.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : The new state of WDG_IT (SET or RESET).
|
||||
*******************************************************************************/
|
||||
ITStatus WDG_GetITStatus(void)
|
||||
{
|
||||
if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET ))
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : WDG_ClearITPendingBit
|
||||
* Description : Clears the WDG's End of Count(EC) interrupt pending bit.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void WDG_ClearITPendingBit(void)
|
||||
{
|
||||
/* Clear the EC pending bit */
|
||||
WDG->SR &= ~WDG_IT_EC;
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : WDG_ClearFlag
|
||||
* Description : Clears the WDG's End of Count(EC) Flag.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void WDG_ClearFlag(void)
|
||||
{
|
||||
/* Clear the EC Flag */
|
||||
|
||||
WDG->SR &= ~WDG_FLAG_EC;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : WDG_GetFlagStatus
|
||||
* Description : Checks whether the WDG End of Count(EC) flag is set or not.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : The new state of the WDG_FLAG (SET or RESET).
|
||||
*******************************************************************************/
|
||||
FlagStatus WDG_GetFlagStatus(void)
|
||||
{
|
||||
if((WDG->SR & WDG_FLAG_EC) != RESET )
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
Loading…
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Reference in a new issue