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Update RSIC-V port layer after testing saving and receiving of chip specific registers.

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This commit is contained in:
Richard Barry 2018-12-30 23:11:40 +00:00
parent 60b133b2c6
commit db750d0c82
2 changed files with 11 additions and 12 deletions
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4
FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h
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@ -75,7 +75,7 @@
/* Save additional registers found on the Pulpino. */
.macro portasmSAVE_ADDITIONAL_REGISTERS
addi sp, sp, -portasmADDITIONAL_CONTEXT_SIZE /* Make room for the additional registers. */
addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
csrr t0, lpstart0 /* Load additional registers into accessable temporary registers. */
csrr t1, lpend0
csrr t2, lpcount0
@ -104,7 +104,7 @@
csrw lpstart1, t3
csrw lpend1, t4
csrw lpcount1, t5
addi sp, sp, -portasmADDITIONAL_CONTEXT_SIZE /* Remove space added for additional registers. */
addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
.endm
#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */