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Provide each Risc V task with an initial mstatus register value.

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This commit is contained in:
Richard Barry 2018-11-20 20:12:35 +00:00
parent 8cef339aec
commit db64297487
2 changed files with 85 additions and 79 deletions
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11
FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
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@ -76,6 +76,8 @@ volatile uint32_t ulx = 0;
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
uint32_t mstatus;
const uint32_t ulMPIE_Bit = 0x80, ulMPP_Bits = 0x1800;
/*
X1 to X31 integer registers for the 'I' profile, X1 to X15 for the 'E' profile.
@ -94,10 +96,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
x28-31 t3-6 Temporaries Caller
*/
/* To ensure alignment. */
//_RB_ pxTopOfStack--;
//_RB_ pxTopOfStack--;
//_RB_pxTopOfStack--;
/* Start task with interrupt enabled. */
__asm volatile ("csrr %0, mstatus" : "=r"(mstatus));
mstatus |= ulMPIE_Bit | ulMPP_Bits;
pxTopOfStack--;
*pxTopOfStack = mstatus;
/* Numbers correspond to the x register number. */
pxTopOfStack--;

17
FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
View file

@ -36,7 +36,7 @@
#error Assembler has not defined __riscv_xlen
#endif
#define CONTEXT_SIZE ( 28 * WORD_SIZE )
#define CONTEXT_SIZE ( 30 * WORD_SIZE )
.global xPortStartFirstTask
.global vPortTrapHandler
@ -81,7 +81,6 @@ xPortStartFirstTask:
lw x31, 28 * WORD_SIZE( sp ) /* t6 */
addi sp, sp, CONTEXT_SIZE
csrs mstatus, 8 /* Enable machine interrupts. */
csrs mie, 8 /* Enable soft interrupt. */
ret
/*-----------------------------------------------------------*/
@ -118,22 +117,22 @@ vPortTrapHandler:
sw x30, 27 * WORD_SIZE( sp )
sw x31, 28 * WORD_SIZE( sp )
csrr t0, mstatus /* Required for MPIE bit. */
sw t0, 29 * WORD_SIZE( sp )
lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
sw sp, 0( t0 ) /* Write sp from first TCB member. */
sw sp, 0( t0 ) /* Write sp to first TCB member. */
csrr a0, mcause
csrr a1, mepc
mv a2, sp
/*_RB_ Does stack need aligning here? */
jal handle_trap
csrw mepc, a0
/* Save exception return address. */
sw a0, 0( sp )
# Remain in M-mode after mret
li t0, 0x00001800 /* MSTATUS MPP */
csrs mstatus, t0
lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
lw sp, 0( sp ) /* Read sp from first TCB member. */
@ -141,6 +140,10 @@ vPortTrapHandler:
lw t0, 0( sp )
csrw mepc, t0
/* Load mstatus with the interrupt enable bits used by the task. */
lw t0, 29 * WORD_SIZE( sp )
csrw mstatus, t0 /* Required for MPIE bit. */
lw x1, 1 * WORD_SIZE( sp )
lw x5, 2 * WORD_SIZE( sp ) /* t0 */
lw x6, 3 * WORD_SIZE( sp ) /* t1 */