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Add trace hook macro for most ports (#794)
Add trace hook macro for most ports In pull request #659 we introduced better support for tracing tools like systemview. This patchset adds support for more ports as requested in the original pull request.
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83861f5b1d
commit
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103 changed files with 1005 additions and 134 deletions
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@ -352,13 +352,19 @@ void xPortSysTickHandler( void )
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uint32_t ulPreviousMask;
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ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
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traceISR_ENTER();
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{
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/* Increment the RTOS tick. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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traceISR_EXIT_TO_SCHEDULER();
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/* Pend a context switch. */
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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}
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else
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{
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traceISR_EXIT();
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}
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}
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portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
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}
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@ -86,9 +86,19 @@ extern void vPortYield( void );
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portYIELD() vPortYield()
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#define portEND_SWITCHING_ISR( xSwitchRequired ) \
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do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
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while( 0 )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) \
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do \
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{ \
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if( xSwitchRequired ) \
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{ \
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traceISR_EXIT_TO_SCHEDULER(); \
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
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} \
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else \
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{ \
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traceISR_EXIT(); \
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} \
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} while( 0 )
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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@ -449,14 +449,21 @@ void xPortSysTickHandler( void )
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* known - therefore the slightly faster vPortRaiseBASEPRI() function is used
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* in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
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vPortRaiseBASEPRI();
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traceISR_ENTER();
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{
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/* Increment the RTOS tick. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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traceISR_EXIT_TO_SCHEDULER();
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/* A context switch is required. Context switching is performed in
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* the PendSV interrupt. Pend the PendSV interrupt. */
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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}
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else
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{
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traceISR_EXIT();
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}
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}
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vPortClearBASEPRIFromISR();
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@ -99,8 +99,20 @@ typedef unsigned long UBaseType_t;
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) \
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do \
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{ \
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if( xSwitchRequired != pdFALSE ) \
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{ \
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traceISR_EXIT_TO_SCHEDULER(); \
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portYIELD(); \
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} \
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else \
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{ \
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traceISR_EXIT(); \
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} \
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} while( 0 )
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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@ -545,14 +545,21 @@ void xPortSysTickHandler( void )
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* known - therefore the slightly faster vPortRaiseBASEPRI() function is used
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* in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
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vPortRaiseBASEPRI();
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traceISR_ENTER();
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{
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/* Increment the RTOS tick. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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traceISR_EXIT_TO_SCHEDULER();
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/* A context switch is required. Context switching is performed in
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* the PendSV interrupt. Pend the PendSV interrupt. */
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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}
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else
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{
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traceISR_EXIT();
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}
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}
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vPortClearBASEPRIFromISR();
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@ -99,8 +99,20 @@ typedef unsigned long UBaseType_t;
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) \
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do \
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{ \
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if( xSwitchRequired != pdFALSE ) \
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{ \
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traceISR_EXIT_TO_SCHEDULER(); \
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portYIELD(); \
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} \
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else \
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{ \
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traceISR_EXIT(); \
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} \
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} while( 0 )
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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@ -1185,13 +1185,19 @@ void xPortSysTickHandler( void )
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uint32_t ulDummy;
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ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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traceISR_ENTER();
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{
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/* Increment the RTOS tick. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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traceISR_EXIT_TO_SCHEDULER();
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/* Pend a context switch. */
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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}
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else
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{
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traceISR_EXIT();
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}
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}
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portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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}
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@ -281,9 +281,19 @@ typedef struct MPU_SETTINGS
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) \
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do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
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while( 0 )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) \
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do \
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{ \
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if( xSwitchRequired ) \
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{ \
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traceISR_EXIT_TO_SCHEDULER(); \
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
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} \
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else \
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{ \
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traceISR_EXIT(); \
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} \
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} while( 0 )
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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@ -531,14 +531,21 @@ void xPortSysTickHandler( void )
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* known - therefore the slightly faster vPortRaiseBASEPRI() function is used
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* in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
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vPortRaiseBASEPRI();
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traceISR_ENTER();
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{
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/* Increment the RTOS tick. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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traceISR_EXIT_TO_SCHEDULER();
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/* A context switch is required. Context switching is performed in
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* the PendSV interrupt. Pend the PendSV interrupt. */
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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}
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else
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{
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traceISR_EXIT();
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}
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}
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vPortClearBASEPRIFromISR();
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@ -99,8 +99,20 @@ typedef unsigned long UBaseType_t;
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) \
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do \
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{ \
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if( xSwitchRequired != pdFALSE ) \
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{ \
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traceISR_EXIT_TO_SCHEDULER(); \
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portYIELD(); \
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} \
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else \
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{ \
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traceISR_EXIT(); \
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} \
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} while( 0 )
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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