Update the Keil XMC4500 demo project to include build configurations for the XMC4200 and XMC4400 application boards.

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h

@@ -89,7 +89,7 @@ extern uint32_t SystemCoreClock;
 #define configTICK_RATE_HZ				( ( portTickType ) 1000 )
 #define configMAX_PRIORITIES			( ( unsigned portBASE_TYPE ) 5 )
 #define configMINIMAL_STACK_SIZE		( ( unsigned short ) 130 )
-#define configTOTAL_HEAP_SIZE			( ( size_t ) ( 40960 ) )
+#define configTOTAL_HEAP_SIZE			( ( size_t ) ( 22800 ) )
 #define configMAX_TASK_NAME_LEN			( 10 )
 #define configUSE_TRACE_FACILITY		1
 #define configUSE_16_BIT_TICKS			0
@@ -158,5 +158,39 @@ standard names. */
 #define xPortPendSVHandler PendSV_Handler
 #define xPortSysTickHandler SysTick_Handler
 
+
+/* Demo application specific settings. */
+#if defined( PART_XMC4500 )
+	/* Hardware includes. */
+	#include "XMC4500.h"
+	#include "System_XMC4500.h"
+
+	/* Configure pin P3.9 for the LED. */
+	#define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 )
+	/* To toggle the single LED */
+	#define configTOGGLE_LED()	( PORT3->OMR =	0x02000200 )
+#elif defined( PART_XMC4400 )
+	/* Hardware includes. */
+	#include "XMC4400.h"
+	#include "System_XMC4200.h"
+
+	/* Configure pin P5.2 for the LED. */
+	#define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 )
+	/* To toggle the single LED */
+	#define configTOGGLE_LED()	( PORT5->OMR =	0x00040004 )
+#elif defined( PART_XMC4200 )
+	/* Hardware includes. */
+	#include "XMC4200.h"
+	#include "System_XMC4200.h"
+
+	/* Configure pin P2.1 for the LED. */
+	#define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL
+	/* To toggle the single LED */
+	#define configTOGGLE_LED()	( PORT2->OMR =	0x00020002 )
+#else
+	#error Part number not specified in project options
+#endif
+
+
 #endif /* FREERTOS_CONFIG_H */
 

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c

@@ -1,47 +1,47 @@
-/******************************************************************************
+/**************************************************************************//**
  * @file     system_XMC4500.c
- * @brief    Device specific initialization for the XMC4500-Series according to CMSIS
+ * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File
- * @version  V2.2
+ *           for the Infineon XMC4500 Device Series
- * @date     20. January 2012
+ * @version  V3.0.1 Alpha
+ * @date     17. September 2012
  *
  * @note
- * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
-
  *
  * @par
- * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.  
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * This file can be freely distributed within development tools that are supporting such microcontrollers. 
+ * processor based microcontrollers.  This file can be freely distributed
-
+ * within development tools that are supporting such ARM based processors.
  *
  * @par
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  *
- *
  ******************************************************************************/
 
-#include "System_XMC4500.h"
+#include "system_XMC4500.h"
 #include <XMC4500.h>
 
-/*----------------------------------------------------------------------------
-  Define clocks	is located in System_XMC4500.h
- *----------------------------------------------------------------------------*/
-
 /*----------------------------------------------------------------------------
   Clock Variable definitions
  *----------------------------------------------------------------------------*/
 /*!< System Clock Frequency (Core Clock)*/
-uint32_t SystemCoreClock = CLOCK_OSC_HP;
+uint32_t SystemCoreClock;
+
+/* clock definitions, do not modify! */
+#define SCU_CLOCK_CRYSTAL              	1
+#define SCU_CLOCK_BACK_UP_FACTORY		   	2
+#define SCU_CLOCK_BACK_UP_AUTOMATIC	   	3
+
+
+#define HIB_CLOCK_FOSI					1
+#define HIB_CLOCK_OSCULP				2
+
+
 
-/*----------------------------------------------------------------------------
-  Keil pragma to prevent warnings
- *----------------------------------------------------------------------------*/
-#if defined(__ARMCC_VERSION)
-#pragma diag_suppress 177
-#endif
 
 /*
 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
@@ -80,8 +80,57 @@ uint32_t SystemCoreClock = CLOCK_OSC_HP;
 #define	SCU_CPUCLKCR_DIV		0x00000000
 #define	SCU_PBCLKCR_DIV		    0x00000000
 #define	SCU_CCUCLKCR_DIV		0x00000000
+/* not avalible in config wizzard*/
+/*
+* mandatory clock parameters **************************************************
+*
+* source for clock generation
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
+*
+**************************************************************************************/
+// Selection of imput lock for PLL
+/*************************************************************************************/
+#define	SCU_PLL_CLOCK_INPUT	SCU_CLOCK_CRYSTAL
+//#define	SCU_PLL_CLOCK_INPUT	SCU_CLOCK_BACK_UP_FACTORY
+//#define	SCU_PLL_CLOCK_INPUT	SCU_CLOCK_BACK_UP_AUTOMATIC
 
+/*************************************************************************************/
+// Standby clock selection for Backup clock source trimming
+/*************************************************************************************/
+#define	SCU_STANDBY_CLOCK  HIB_CLOCK_OSCULP
+//#define	SCU_STANDBY_CLOCK  HIB_CLOCK_FOSI
 
+/*************************************************************************************/
+// Global clock parameters
+/*************************************************************************************/
+#define CLOCK_FSYS							120000000
+#define	CLOCK_CRYSTAL_FREQUENCY	12000000
+#define	CLOCK_BACK_UP						24000000
+
+/*************************************************************************************/
+/* OSC_HP setup parameters */
+/*************************************************************************************/
+#define	SCU_OSC_HP_MODE	0xF0
+#define	SCU_OSCHPWDGDIV	2
+
+/*************************************************************************************/
+/* MAIN PLL setup parameters */
+/*************************************************************************************/
+//Divider settings for external crystal @ 12 MHz
+/*************************************************************************************/
+#define 	SCU_PLL_K1DIV	1
+#define 	SCU_PLL_K2DIV	3
+#define 	SCU_PLL_PDIV	1
+#define 	SCU_PLL_NDIV	79
+
+/*************************************************************************************/
+//Divider settings for use of backup clock source trimmed
+/*************************************************************************************/
+//#define 	SCU_PLL_K1DIV	1
+//#define 	SCU_PLL_K2DIV	3
+//#define 	SCU_PLL_PDIV	3
+//#define 	SCU_PLL_NDIV	79
+/*************************************************************************************/
 
 /*--------------------- USB CLOCK Configuration ---------------------------
 //
@@ -92,6 +141,25 @@ uint32_t SystemCoreClock = CLOCK_OSC_HP;
 */
 
 #define SCU_USB_CLOCK_SETUP              0
+/* not avalible in config wizzard*/
+#define 	SCU_USBPLL_PDIV	0
+#define 	SCU_USBPLL_NDIV	31
+#define 	SCU_USBDIV	3
+
+/*--------------------- Flash Wait State Configuration -------------------------------
+//
+// <e> Flash Wait State Configuration
+//     <o1.0..3>   Flash Wait State
+//                     <0=> 3 WS
+//                     <1=> 4 WS
+//                     <2=> 5 WS
+//										 <3=> 6 WS
+// </e>
+//
+*/
+
+#define PMU_FLASH             1
+#define	PMU_FLASH_WS					0x00000000
 
 
 /*--------------------- CLOCKOUT Configuration -------------------------------
@@ -99,9 +167,10 @@ uint32_t SystemCoreClock = CLOCK_OSC_HP;
 // <e> Clock OUT Configuration
 //     <o1.0..1>   Clockout Source Selection
 //                     <0=> System Clock
-//                     <2=> USB Clock
+//                     <2=> Divided value of USB PLL output
 //                     <3=> Divided value of PLL Clock
-//     <o2.0..1>   Clockout Pin Selection
+//     <o2.0..4>   Clockout divider <1-10><#-1>
+//     <o3.0..1>   Clockout Pin Selection
 //                     <0=> P1.15
 //                     <1=> P0.8
 //
@@ -110,9 +179,20 @@ uint32_t SystemCoreClock = CLOCK_OSC_HP;
 //
 */
 
-#define SCU_CLOCKOUT_SETUP              0  // recommended to keep disabled
+#define SCU_CLOCKOUT_SETUP               0
-#define	SCU_CLOCKOUT_SOURCE		0x00000000
+#define	SCU_CLOCKOUT_SOURCE		0x00000003
-#define	SCU_CLOCKOUT_PIN		0x00000000
+#define	SCU_CLOCKOUT_DIV		0x00000009
+#define	SCU_CLOCKOUT_PIN		0x00000001
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+#if SCU_CLOCK_SETUP
+uint32_t SystemCoreClock = CLOCK_FSYS;
+#else
+uint32_t SystemCoreClock = CLOCK_BACK_UP;
+#endif
 
 /*----------------------------------------------------------------------------
   static functions declarations
@@ -122,9 +202,10 @@ static int SystemClockSetup(void);
 #endif
 
 #if (SCU_USB_CLOCK_SETUP == 1)
-static void USBClockSetup(void);
+static int USBClockSetup(void);
 #endif
 
+
 /**
   * @brief  Setup the microcontroller system.
   *         Initialize the PLL and update the
@@ -134,59 +215,70 @@ static void USBClockSetup(void);
   */
 void SystemInit(void)
 {
-/* Setup the WDT */
+int temp;
-#if (WDT_SETUP == 1)
-WDT->CTR &= ~WDTENB_nVal; 
-#endif
 
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
                (3UL << 11*2)  );               /* set CP11 Full Access */
 #endif
 
-/* Disable branch prediction - PCON.PBS = 1 */
-PREF->PCON |= (PREF_PCON_PBS_Msk);
-
 /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
 SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
 
+/* Setup the WDT */
+#if WDT_SETUP
+
+WDT->CTR &= ~WDTENB_nVal;
+
+#endif
+
+/* Setup the Flash Wait State */
+#if PMU_FLASH
+temp = FLASH0->FCON;
+temp &= ~FLASH_FCON_WSPFLASH_Msk;
+temp |= PMU_FLASH_WS+3;
+FLASH0->FCON = temp;
+#endif
+
+
 /* Setup the clockout */
-/* README README README README README README README README README README */
+#if SCU_CLOCKOUT_SETUP
-/*
+
- * Please use the CLOCKOUT feature with diligence. Use this only if you know
- * what you are doing.
- *
- * You must be aware that the settings below can potentially be in conflict
- * with DAVE code generation engine preferences.
- *
- * Even worse, the setting below configures the ports as output ports while in
- * reality, the board on which this chip is mounted may have a source driving
- * the ports.
- *
- * So use this feature only when you are absolutely sure that the port must 
- * indeed be configured as an output AND you are NOT linking this startup code
- * with code that was generated by DAVE code engine.
- */
-#if (SCU_CLOCKOUT_SETUP == 1)
 SCU_CLK->EXTCLKCR	|= SCU_CLOCKOUT_SOURCE;
+/*set PLL div for clkout */
+SCU_CLK->EXTCLKCR	|= SCU_CLOCKOUT_DIV<<16;
 
 if (SCU_CLOCKOUT_PIN) {
 						PORT0->IOCR8 = 0x00000088;   /*P0.8 --> ALT1 select +  HWSEL */
 					    PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
+					    //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk);  /*set to strong driver */
 						}
-else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
+else {
+		PORT1->IOCR12 = 0x88000000;                    /*P1.15--> ALT1 select */
+	    //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk);  /*set to strong driver */
+		}
+
 #endif
 
+
 /* Setup the System clock */
-#if (SCU_CLOCK_SETUP == 1)
+#if SCU_CLOCK_SETUP
 SystemClockSetup();
 #endif
 
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
+
+
 /* Setup the USB PL */
-#if (SCU_USB_CLOCK_SETUP == 1)
+#if SCU_USB_CLOCK_SETUP
 USBClockSetup();
 #endif
 
+
+
 }
 
 
@@ -198,11 +290,49 @@ USBClockSetup();
   */
 void SystemCoreClockUpdate(void)
 {
+unsigned int PDIV;
+unsigned int NDIV;
+unsigned int K2DIV;
+unsigned int long VCO;
+
 
 /*----------------------------------------------------------------------------
   Clock Variable definitions
  *----------------------------------------------------------------------------*/
-SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/
+if (SCU_CLK->SYSCLKCR ==  0x00010000)
+{
+	if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
+		/* check if PLL is locked */
+		/* read back divider settings */
+		 PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
+		 NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
+		 K2DIV  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
+
+		if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
+		/* the selected clock is the Backup clock fofi */
+		VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
+		SystemCoreClock = VCO/K2DIV;
+		/* in case the sysclock div is used */
+		SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+
+		}
+		else
+		{
+		/* the selected clock is the PLL external oscillator */
+		VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
+		SystemCoreClock = VCO/K2DIV;
+		/* in case the sysclock div is used */
+		SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+		}
+
+
+	}
+}
+else
+{
+SystemCoreClock = CLOCK_BACK_UP;
+}
+
 
 }
 
@@ -216,62 +346,182 @@ SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/
 #if (SCU_CLOCK_SETUP == 1)
 static int SystemClockSetup(void)
 {
+int temp;
+unsigned int long VCO;
+int stepping_K2DIV;
+
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
+
+/* check if PLL is switched on */
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
 /* enable PLL first */
-  SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | 
+  SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
-									                                SCU_PLL_PLLCON0_PLLPWD_Msk);
-
-/* Enable OSC_HP */
-  if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
-  {
-   /* Enable the OSC_HP*/
-   SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4);	 
-   /* Setup OSC WDG devider */
-   SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);         
-   /* Select external OSC as PLL input */
-   SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
-   /* Restart OSC Watchdog */
-   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  
-
-   do 
-   {
-	;  /* here a timeout need to be added */
-   }while(!( (SCU_PLL->PLLSTAT) & 
-					   (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |
-					    SCU_PLL_PLLSTAT_PLLSP_Msk)
-					 )
-         ); 
 
 }
 
-/* Setup Main PLL */
+/* Enable OSC_HP if not already on*/
-   /* Select FOFI as system clock */
+  if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
-   if(SCU_CLK->SYSCLKCR != 0X000000)
+  {
-	  SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/
+	/********************************************************************************************************************/
+	/*   Use external crystal for PLL clock input                                                                            */
+	/********************************************************************************************************************/
 
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
+	   SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);	 /*enable the OSC_HP*/
+	   /* setup OSC WDG devider */
+	   SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
+	   /* select external OSC as PLL input */
+	   SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
+	   /* restart OSC Watchdog */
+	   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
+
+       /* Timeout for wait loop ~150ms */
+	   /********************************/
+	   SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+	   do
+	   {
+       ;/* wait for ~150ms  */
+	   }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
+
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+	   if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+	   return(0);/* Return Error */
+
+    }
+  }
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
+	{
+	/********************************************************************************************************************/
+	/*   Use factory trimming Back-up clock for PLL clock input                                                                            */
+	/********************************************************************************************************************/
+		/* PLL Back up clock selected */
+		SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+	}
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
+  {
+	/********************************************************************************************************************/
+	/*   Use automatic trimming Back-up clock for PLL clock input                                                                            */
+	/********************************************************************************************************************/
+	/* check for HIB Domain enabled  */
+	if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
+		SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
+
+   /* check for HIB Domain is not in reset state  */
+	if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
+	    SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
+
+			/* PLL Back up clock selected */
+		SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+		if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
+			{
+			/****************************************************************************************************************/
+			/*   Use fOSI as source of the standby clock                                                                             */
+			/****************************************************************************************************************/
+			SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+
+			SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+			for(temp=0;temp<=0xFFFF;temp++);
+
+			SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+			}
+		else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
+			{
+			/****************************************************************************************************************/
+			/*   Use fULP as source of the standby clock                                                                            */
+			/****************************************************************************************************************/
+			/*check OSCUL if running correct*/
+			if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
+				{
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
+
+					SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
+					/*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
+					/* select OSCUL clock for RTC*/
+					SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+					/*enable OSCULP WDG Alarm Enable*/
+					SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+					/*wait now for clock is stable */
+					do
+					{
+					SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+					for(temp=0;temp<=0xFFFF;temp++);
+					}
+					while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
+
+					SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+				}
+			// now OSCULP is running and can be used
+			SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+			while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+
+			SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+			/*TRIAL for delay loop*/
+			for(temp=0;temp<=0xFFFF;temp++);
+
+			SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+			/*TRIAL for delay loop*/
+			for(temp=0;temp<=0xFFFF;temp++);
+
+			}
+  }
+
+	/********************************************************************************************************************/
+	/*   Setup and look the main PLL                                                                                    */
+	/********************************************************************************************************************/
+
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
+	/* Systen is still running from internal clock */
+		   /* select FOFI as system clock */
+		   if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
+
+
+			 /*calulation for stepping*/
+			 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+			 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+					VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+			 stepping_K2DIV = (VCO/24000000)-1;
 			 /* Go to bypass the Main PLL */
 		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
-
 		   /* disconnect OSC_HP to PLL */
 		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
-
 		   /* Setup devider settings for main PLL */
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | 
+		   SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
-                                     (PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24));
-
 		   /* we may have to set OSCDISCDIS */
 		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
-
 		   /* connect OSC_HP to PLL */
 		   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
-
 		   /* restart PLL Lock detection */
 		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
-
 		   /* wait for PLL Lock */
-   while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk));
+		   /* setup time out loop */
+	       /* Timeout for wait loo ~150ms */
+		   /********************************/
+		   SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+		   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+		   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+		                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
 
+		   while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
+	       SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+
+		   if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
+		   		{
 				/* Go back to the Main PLL */
 				SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
+				}
+				else return(0);
+
 
 	   /*********************************************************
 	   here we need to setup the system clock divider
@@ -281,81 +531,100 @@ static int SystemClockSetup(void)
 		SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
 		SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
 
+
 		 /* Switch system clock to PLL */
 	   SCU_CLK->SYSCLKCR |=  0x00010000;
 
-   /*********************************************************
+	   /* we may have to reset OSCDISCDIS */
-   here the ramp up of the system clock starts
+	   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
-   *********************************************************/
+
+
+		 /*********************************************************/
 		 /* Delay for next K2 step ~50µs */
-   /********************************/
+		 /*********************************************************/
-   /* Set reload register */
+		 SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
-   SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+		 SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
-
-   /* Load the SysTick Counter Value */
-   SysTick->VAL   = 0;                                         
-
-   /* Enable SysTick IRQ and SysTick Timer */
 		 SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_ENABLE_Msk;                    
+										 SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
 
-	 /* wait for ~50µs  */
+		 while (SysTick->VAL >= 100);								   /* wait for ~50µs  */
-   while (SysTick->VAL >= 100);								   
+		 SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+		 /*********************************************************/
 
-   /* Stop SysTick Timer */
+	   /*********************************************************
-   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 
+	   here the ramp up of the system clock starts FSys < 60MHz
-   /********************************/
+	   *********************************************************/
+		if (CLOCK_FSYS > 60000000){
+			 /*calulation for stepping*/
+			 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+			 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+					VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+			 stepping_K2DIV = (VCO/60000000)-1;
 
 			 /* Setup devider settings for main PLL */
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | 
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
-                                     (PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24));
+		 }
+		 else
+		 {
+				/* Setup devider settings for main PLL */
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+		    SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */
+			  return(1);
+		 }
 
+		 /*********************************************************/
 		 /* Delay for next K2 step ~50µs */
-   /********************************/
+		 /*********************************************************/
 	   SysTick->LOAD  = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
 
-   /* Load the SysTick Counter Value */
+	   while (SysTick->VAL >= 100);								   /* wait for ~50µs  */
-   SysTick->VAL   = 0;
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
-
-   /* Enable SysTick IRQ and SysTick Timer */
-   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
-                                                                   
-   /* Wait for ~50µs  */
-   while (SysTick->VAL >= 100);								   
-
-   /* Stop SysTick Timer */
-   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 
 	   /********************************/
 
-   /* Setup devider settings for main PLL */
+   /*********************************************************
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | 
+	   here the ramp up of the system clock starts FSys < 90MHz
-									                    (PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24));
+	   *********************************************************/
+		if (CLOCK_FSYS > 90000000){
+			 /*calulation for stepping*/
+			 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+			 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+					VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
 
+			 stepping_K2DIV = (VCO/90000000)-1;
+
+			 /* Setup devider settings for main PLL */
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+		 }
+		 else
+		 {
+				/* Setup devider settings for main PLL */
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+	      SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */
+				return(1);
+		 }
+
+		 /*********************************************************/
 		 /* Delay for next K2 step ~50µs */
-   /********************************/
+		 /*********************************************************/
 	   SysTick->LOAD  = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
 
-   /* Load the SysTick Counter Value */
+	   while (SysTick->VAL >= 100);								   /* wait for ~50µs  */
-   SysTick->VAL   = 0;                                         
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
-
-   /* Enable SysTick IRQ and SysTick Timer */
-   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
-                                       
-   /* Wait for ~50µs  */
-   while (SysTick->VAL >= 100);								   
-
-   /* Stop SysTick Timer */
-   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 
 	   /********************************/
 
 	   /* Setup devider settings for main PLL */
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) | 
+	   SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
-                                                               (PLL_PDIV<<24));
-
-	 /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */
-   SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | 
-					                                    SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  
 
+	   SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */
+	}
+ }/* end this weak function enables DAVE3 clock App usage */
    return(1);
 
 }
@@ -368,35 +637,45 @@ static int SystemClockSetup(void)
   * @retval None
   */
 #if (SCU_USB_CLOCK_SETUP == 1)
-static void USBClockSetup(void)
+static int USBClockSetup(void)
 {
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
+
+	/* check if PLL is switched on */
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
 	/* enable PLL first */
-  SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | 
+  SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
-									                               SCU_PLL_USBPLLCON_PLLPWD_Msk);
+}
 
 /* check and if not already running enable OSC_HP */
-  if(!((SCU_PLL->PLLSTAT) & 
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
-			 (SCU_PLL_PLLSTAT_PLLHV_Msk | 
+		 /* check if Main PLL is switched on for OSC WD*/
-        SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)))
+		 if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
-  {
+			/* enable PLL first */
-	  if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
+  			SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
-	  {
+		 }
-	
+	   SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);	 /*enable the OSC_HP*/
-	   SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4);	 /*enable the OSC_HP*/
 	   /* setup OSC WDG devider */
-	   SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);         
+	   SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
-	   /* select external OSC as PLL input */
-	   SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
 	   /* restart OSC Watchdog */
 	   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
 
+       /* Timeout for wait loop ~150ms */
+	   /********************************/
+	   SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
 	   do
 	   {
-		;  /* here a timeout need to be added */
+       ;/* wait for ~150ms  */
-	   }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | 
+	   }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
-               SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))); 
+
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+	   if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+	   return(0);/* Return Error */
 
-	  }
   }
 
 
@@ -406,7 +685,9 @@ static void USBClockSetup(void)
    /* disconnect OSC_FI to PLL */
    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
    /* Setup devider settings for main PLL */
-   SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24));
+   SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
+   /* Setup USBDIV settings USB clock */
+   SCU_CLK->USBCLKCR = SCU_USBDIV;
    /* we may have to set OSCDISCDIS */
    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
    /* connect OSC_FI to PLL */
@@ -415,5 +696,10 @@ static void USBClockSetup(void)
    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
    /* wait for PLL Lock */
    while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
+
+  }/* end this weak function enables DAVE3 clock App usage */
+   return(1);
+
 }
 #endif
+

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.h

@@ -0,0 +1,114 @@
+/**************************************************************************//**
+ * @file     system_XMC4500.h
+ * @brief    Header file for the XMC4500-Series systeminit
+ *           
+ * @version  V1.6
+ * @date     23. October 2012
+ *
+ * @note
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.  
+ * This file can be freely distributed within development tools that are supporting such microcontrollers. 
+
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_XMC4500_H
+#define __SYSTEM_XMC4500_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+extern void SystemInit (void);
+
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/* this weak function enables DAVE3 clock App usage */		
+extern uint32_t AllowPLLInitByStartup(void);				
+
+
+/* clock definitions, do not modify! */
+#define SCU_CLOCK_CRYSTAL              1
+
+				
+				
+/*				
+ * mandatory clock parameters **************************************************				
+ */				
+/* source for clock generation				
+ * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)				
+ * mandatory for old system_xmc4500.c files - please do not remove!!!       				
+ **************************************************************************************/				
+				
+#define	SCU_PLL_CLOCK_INPUT	SCU_CLOCK_CRYSTAL
+#define CLOCK_OSC_HP	24000000
+#define CLOCK_BACK_UP	24000000		 
+#define	CLOCK_CRYSTAL_FREQUENCY	12000000		
+#define	SYSTEM_FREQUENCY	120000000		
+				
+/* OSC_HP setup parameters */				
+#define	OSC_HP_MODE	0		
+#define OSCHPWDGDIV 2
+				
+/* MAIN PLL setup parameters */				
+				
+				
+#define 	PLL_K1DIV	1		
+#define 	PLL_K2DIV	3		
+#define 	PLL_PDIV	1		
+#define 	PLL_NDIV	79
+		
+				
+				
+#define 	PLL_K2DIV_STEP_1	19	//PLL output is 24Mhz	
+#define 	PLL_K2DIV_STEP_2	7	//PLL output to 60Mhz	
+#define 	PLL_K2DIV_STEP_3	4	//PLL output to 96Mhz	
+				
+				
+		
+#define 	USBPLL_PDIV	1		
+#define 	USBPLL_NDIV	15		
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c

@@ -92,13 +92,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* Hardware includes. */
-#include "XMC4500.h"
-#include "System_XMC4500.h"
-
 /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
 or 0 to run the more comprehensive test and demo application. */
-#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY	1
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY	0
 
 /*-----------------------------------------------------------*/
 
@@ -141,12 +137,6 @@ static void prvSetupHardware( void )
 {
 extern void SystemCoreClockUpdate( void );
 
-	/* Ensure SystemCoreClock variable is set. */
-	SystemCoreClockUpdate();
-
-	/* Configure pin P3.9 for the LED. */
-	PORT3->IOCR8 = 0x00008000;
-
 	/* Ensure all priority bits are assigned as preemption priority bits. */
 	NVIC_SetPriorityGrouping( 0 );
 }

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_blinky.c

@@ -107,10 +107,6 @@
 #include "task.h"
 #include "semphr.h"
 
-/* Hardware includes. */
-#include "XMC4500.h"
-#include "System_XMC4500.h"
-
 /* Priorities at which the tasks are created. */
 #define mainQUEUE_RECEIVE_TASK_PRIORITY		( tskIDLE_PRIORITY + 2 )
 #define	mainQUEUE_SEND_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
@@ -129,9 +125,6 @@ functionality. */
 #define mainQUEUE_SEND_PARAMETER			( 0x1111UL )
 #define mainQUEUE_RECEIVE_PARAMETER			( 0x22UL )
 
-/* To toggle the single LED */
-#define mainTOGGLE_LED()					( PORT3->OMR =	0x02000200 )
-
 /*-----------------------------------------------------------*/
 
 /*
@@ -146,11 +139,6 @@ static void prvQueueSendTask( void *pvParameters );
  */
 void main_blinky( void );
 
-/*
- * The hardware only has a single LED.  Simply toggle it.
- */
-extern void vMainToggleLED( void );
-
 /*-----------------------------------------------------------*/
 
 /* The queue used by both tasks. */
@@ -235,7 +223,7 @@ unsigned long ulReceivedValue;
 		is it the expected value?  If it is, toggle the LED. */
 		if( ulReceivedValue == 100UL )
 		{
-			mainTOGGLE_LED();
+			configTOGGLE_LED();
 			ulReceivedValue = 0U;
 		}
 	}

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c

@@ -124,10 +124,6 @@
 #include "recmutex.h"
 #include "death.h"
 
-/* Hardware includes. */
-#include "XMC4500.h"
-#include "System_XMC4500.h"
-
 /* Priorities for the demo application tasks. */
 #define mainQUEUE_POLL_PRIORITY				( tskIDLE_PRIORITY + 2UL )
 #define mainSEM_TEST_PRIORITY				( tskIDLE_PRIORITY + 1UL )
@@ -135,9 +131,6 @@
 #define mainCREATOR_TASK_PRIORITY			( tskIDLE_PRIORITY + 3UL )
 #define mainFLOP_TASK_PRIORITY				( tskIDLE_PRIORITY )
 
-/* To toggle the single LED */
-#define mainTOGGLE_LED()					( PORT3->OMR =	0x02000200 )
-
 /* A block time of zero simply means "don't block". */
 #define mainDONT_BLOCK						( 0UL )
 
@@ -183,14 +176,11 @@ xTimerHandle xCheckTimer = NULL;
 	/* Start all the other standard demo/test tasks.  The have not particular
 	functionality, but do demonstrate how to use the FreeRTOS API and test the
 	kernel port. */
-	vStartIntegerMathTasks( tskIDLE_PRIORITY );
 	vStartDynamicPriorityTasks();
-	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
 	vCreateBlockTimeTasks();
 	vStartCountingSemaphoreTasks();
 	vStartGenericQueueTasks( tskIDLE_PRIORITY );
 	vStartRecursiveMutexTasks();
-	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
 	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
 	vStartMathTasks( mainFLOP_TASK_PRIORITY );
 	
@@ -213,11 +203,6 @@ xTimerHandle xCheckTimer = NULL;
 		xTimerStart( xCheckTimer, mainDONT_BLOCK );
 	}
 
-	/* The set of tasks created by the following function call have to be 
-	created last as they keep account of the number of tasks they expect to see 
-	running. */
-	vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
-
 	/* Start the scheduler. */
 	vTaskStartScheduler();
 	
@@ -244,21 +229,11 @@ unsigned long ulErrorFound = pdFALSE;
 		ulErrorFound = pdTRUE;
 	}
 
-	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
-	{
-		ulErrorFound = pdTRUE;
-	}
-
 	if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
 	{
 		ulErrorFound = pdTRUE;
 	}
 
-	if( xAreBlockingQueuesStillRunning() != pdTRUE )
-	{
-		ulErrorFound = pdTRUE;
-	}
-
 	if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
 	{
 		ulErrorFound = pdTRUE;
@@ -274,16 +249,6 @@ unsigned long ulErrorFound = pdFALSE;
 		ulErrorFound = pdTRUE;
 	}
 
-	if( xIsCreateTaskStillRunning() != pdTRUE )
-	{
-		ulErrorFound = pdTRUE;
-	}
-
-	if( xArePollingQueuesStillRunning() != pdTRUE )
-	{
-		ulErrorFound = pdTRUE;
-	}
-
 	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
 	{
 		ulErrorFound = pdTRUE;
@@ -306,7 +271,7 @@ unsigned long ulErrorFound = pdFALSE;
 	/* Toggle the check LED to give an indication of the system status.  If
 	the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
 	everything is ok.  A faster toggle indicates an error. */
-	mainTOGGLE_LED();	
+	configTOGGLE_LED();	
 	
 	/* Have any errors been latch in ulErrorFound?  If so, shorten the
 	period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4200.s

@@ -0,0 +1,455 @@
+;*****************************************************************************/
+; * @file     startup_XMC4200.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File for
+; *           Infineon XMC4200 Device Series
+; * @version  V1.00
+; * @date     05. February 2013
+; *
+; * @note
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+;/* ********************* Version History *********************************** */
+;/* ***************************************************************************
+; V0.1 , September 2012, First version
+; V1.0 , February 2013, FIX for CPU prefetch bug implemented
+;**************************************************************************** */
+
+
+;*  <<< Use Configuration Wizard in Context Menu >>>
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
+;/*
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
+; * A veneer defined below will first
+; * be executed which in turn branches to the final exception handler.
+; *
+; * In addition to defining the veneers, the vector table must for these buggy
+; * devices contain the veneers.
+; */
+
+;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define
+;or use define below
+              GBLL WORKAROUND_PMU_CM001
+
+;/* A macro to setup a vector table entry based on STEP ID */
+              IF    :DEF:WORKAROUND_PMU_CM001
+                MACRO
+                ExcpVector $Handler
+                  DCD   $Handler._Veneer
+                MEND
+              ELSE
+                MACRO
+                ExcpVector $Handler
+                  DCD   $Handler
+                MEND
+              ENDIF
+
+;/* A macro to ease definition of the various handlers based on STEP ID */
+              IF     :DEF:WORKAROUND_PMU_CM001
+
+                ;/* First define the final exception handler */
+                MACRO
+                ExcpHandler $Handler_Func
+$Handler_Func\
+                  PROC
+                  EXPORT  $Handler_Func            [WEAK]
+                  B       .
+                  ENDP
+
+                ;/* And then define a veneer that will branch to the final excp handler */
+$Handler_Func._Veneer\
+                  PROC
+                  EXPORT  $Handler_Func._Veneer    [WEAK]
+                  LDR     R0, =$Handler_Func
+                  PUSH    {LR}
+                  BLX     R0
+                  POP     {PC}
+                  ALIGN
+                  LTORG
+                  ENDP
+                MEND
+
+              ELSE
+
+                ;/* No prefetch bug, hence define only the final exception handler */
+                MACRO
+                ExcpHandler $Handler_Func
+$Handler_Func\
+                  PROC
+                  EXPORT  $Handler_Func            [WEAK]
+                  B       .
+                  ENDP
+                MEND
+
+              ENDIF
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
+
+
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */
+;* Vector Table - This gets programed into VTOR register */
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+
+
+__Vectors
+    DCD          __initial_sp               ; Top of Stack
+    DCD          Reset_Handler              ; Reset Handler
+
+    ExcpVector   NMI_Handler                ; NMI Handler
+    ExcpVector   HardFault_Handler          ; Hard Fault Handler
+    ExcpVector   MemManage_Handler          ; MPU Fault Handler
+    ExcpVector   BusFault_Handler           ; Bus Fault Handler
+    ExcpVector   UsageFault_Handler         ; Usage Fault Handler
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          SVC_Handler                ; SVCall Handler
+    ExcpVector   DebugMon_Handler           ; Debug Monitor Handler
+    DCD          0                          ; Reserved
+    DCD          PendSV_Handler             ; PendSV Handler
+    DCD          SysTick_Handler            ; SysTick Handler
+
+    ; Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals
+    ExcpVector   SCU_0_IRQHandler           ; Handler name for SR SCU_0
+    ExcpVector   ERU0_0_IRQHandler          ; Handler name for SR ERU0_0
+    ExcpVector   ERU0_1_IRQHandler          ; Handler name for SR ERU0_1
+    ExcpVector   ERU0_2_IRQHandler          ; Handler name for SR ERU0_2
+    ExcpVector   ERU0_3_IRQHandler          ; Handler name for SR ERU0_3
+    ExcpVector   ERU1_0_IRQHandler          ; Handler name for SR ERU1_0
+    ExcpVector   ERU1_1_IRQHandler          ; Handler name for SR ERU1_1
+    ExcpVector   ERU1_2_IRQHandler          ; Handler name for SR ERU1_2
+    ExcpVector   ERU1_3_IRQHandler          ; Handler name for SR ERU1_3
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    ExcpVector   PMU0_0_IRQHandler          ; Handler name for SR PMU0_0
+    DCD          0                          ; Reserved
+    ExcpVector   VADC0_C0_0_IRQHandler      ; Handler name for SR VADC0_C0_0
+    ExcpVector   VADC0_C0_1_IRQHandler      ; Handler name for SR VADC0_C0_1
+    ExcpVector   VADC0_C0_2_IRQHandler      ; Handler name for SR VADC0_C0_1
+    ExcpVector   VADC0_C0_3_IRQHandler      ; Handler name for SR VADC0_C0_3
+    ExcpVector   VADC0_G0_0_IRQHandler      ; Handler name for SR VADC0_G0_0
+    ExcpVector   VADC0_G0_1_IRQHandler      ; Handler name for SR VADC0_G0_1
+    ExcpVector   VADC0_G0_2_IRQHandler      ; Handler name for SR VADC0_G0_2
+    ExcpVector   VADC0_G0_3_IRQHandler      ; Handler name for SR VADC0_G0_3
+    ExcpVector   VADC0_G1_0_IRQHandler      ; Handler name for SR VADC0_G1_0
+    ExcpVector   VADC0_G1_1_IRQHandler      ; Handler name for SR VADC0_G1_1
+    ExcpVector   VADC0_G1_2_IRQHandler      ; Handler name for SR VADC0_G1_2
+    ExcpVector   VADC0_G1_3_IRQHandler      ; Handler name for SR VADC0_G1_3
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    ExcpVector   DAC0_0_IRQHandler          ; Handler name for SR DAC0_0
+    ExcpVector   DAC0_1_IRQHandler          ; Handler name for SR DAC0_1
+    ExcpVector   CCU40_0_IRQHandler         ; Handler name for SR CCU40_0
+    ExcpVector   CCU40_1_IRQHandler         ; Handler name for SR CCU40_1
+    ExcpVector   CCU40_2_IRQHandler         ; Handler name for SR CCU40_2
+    ExcpVector   CCU40_3_IRQHandler         ; Handler name for SR CCU40_3
+    ExcpVector   CCU41_0_IRQHandler         ; Handler name for SR CCU41_0
+    ExcpVector   CCU41_1_IRQHandler         ; Handler name for SR CCU41_1
+    ExcpVector   CCU41_2_IRQHandler         ; Handler name for SR CCU41_2
+    ExcpVector   CCU41_3_IRQHandler         ; Handler name for SR CCU41_3
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    ExcpVector   CCU80_0_IRQHandler         ; Handler name for SR CCU80_0
+    ExcpVector   CCU80_1_IRQHandler         ; Handler name for SR CCU80_1
+    ExcpVector   CCU80_2_IRQHandler         ; Handler name for SR CCU80_2
+    ExcpVector   CCU80_3_IRQHandler         ; Handler name for SR CCU80_3
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    ExcpVector   POSIF0_0_IRQHandler        ; Handler name for SR POSIF0_0
+    ExcpVector   POSIF0_1_IRQHandler        ; Handler name for SR POSIF0_1
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    ExcpVector   HRPWM_0_IRQHandler         ; Handler name for SR HRPWM_0
+    ExcpVector   HRPWM_1_IRQHandler         ; Handler name for SR HRPWM_1
+    ExcpVector   HRPWM_2_IRQHandler         ; Handler name for SR HRPWM_2
+    ExcpVector   HRPWM_3_IRQHandler         ; Handler name for SR HRPWM_3
+    ExcpVector   CAN0_0_IRQHandler          ; Handler name for SR CAN0_0
+    ExcpVector   CAN0_1_IRQHandler          ; Handler name for SR CAN0_1
+    ExcpVector   CAN0_2_IRQHandler          ; Handler name for SR CAN0_2
+    ExcpVector   CAN0_3_IRQHandler          ; Handler name for SR CAN0_3
+    ExcpVector   CAN0_4_IRQHandler          ; Handler name for SR CAN0_4
+    ExcpVector   CAN0_5_IRQHandler          ; Handler name for SR CAN0_5
+    ExcpVector   CAN0_6_IRQHandler          ; Handler name for SR CAN0_6
+    ExcpVector   CAN0_7_IRQHandler          ; Handler name for SR CAN0_7
+    ExcpVector   USIC0_0_IRQHandler         ; Handler name for SR USIC0_0
+    ExcpVector   USIC0_1_IRQHandler         ; Handler name for SR USIC0_1
+    ExcpVector   USIC0_2_IRQHandler         ; Handler name for SR USIC0_2
+    ExcpVector   USIC0_3_IRQHandler         ; Handler name for SR USIC0_3
+    ExcpVector   USIC0_4_IRQHandler         ; Handler name for SR USIC0_4
+    ExcpVector   USIC0_5_IRQHandler         ; Handler name for SR USIC0_5
+    ExcpVector   USIC1_0_IRQHandler         ; Handler name for SR USIC1_0
+    ExcpVector   USIC1_1_IRQHandler         ; Handler name for SR USIC1_1
+    ExcpVector   USIC1_2_IRQHandler         ; Handler name for SR USIC1_2
+    ExcpVector   USIC1_3_IRQHandler         ; Handler name for SR USIC1_3
+    ExcpVector   USIC1_4_IRQHandler         ; Handler name for SR USIC1_4
+    ExcpVector   USIC1_5_IRQHandler         ; Handler name for SR USIC1_5
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    ExcpVector   LEDTS0_0_IRQHandler        ; Handler name for SR LEDTS0_0
+    DCD          0                          ; Reserved
+    ExcpVector   FCE0_0_IRQHandler          ; Handler name for SR FCE0_0
+    ExcpVector   GPDMA0_0_IRQHandler        ; Handler name for SR GPDMA0_0
+    DCD          0                          ; Reserved
+    ExcpVector   USB0_0_IRQHandler          ; Handler name for SR USB0_0
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+;* ================== END OF VECTOR TABLE DEFINITION ======================= */
+
+;* ================== START OF VECTOR ROUTINES ============================= */
+
+                AREA    |.text|, CODE, READONLY
+
+;* Reset Handler */
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+        ; Remap vector table
+        LDR     R0, =__Vectors
+        LDR     R1, =0xE000ED08 ;*VTOR register
+        STR     R0,[R1]
+
+        ;* C routines are likely to be called. Setup the stack now
+        LDR     SP,=__initial_sp
+
+        LDR     R0, = SystemInit
+        BLX     R0
+
+        ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
+        ;weakly defined here though for a potential override.
+
+        LDR     R0, = SystemInit_DAVE3
+        BLX     R0
+
+        ;* Reset stack pointer before zipping off to user application
+        LDR     SP,=__initial_sp
+
+        LDR     R0, =__main
+        BX      R0
+
+        ALIGN
+        ENDP
+
+
+
+
+;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
+
+
+
+;/* Default exception Handlers - Users may override this default functionality by
+;   defining handlers of the same name in their C code */
+
+    ExcpHandler   NMI_Handler
+    ExcpHandler   HardFault_Handler
+    ExcpHandler   MemManage_Handler
+    ExcpHandler   BusFault_Handler
+    ExcpHandler   UsageFault_Handler
+    ExcpHandler   SVC_Handler
+    ExcpHandler   DebugMon_Handler
+    ExcpHandler   PendSV_Handler
+    ExcpHandler   SysTick_Handler
+
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
+
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
+
+;* IRQ Handlers */
+    ExcpHandler   SCU_0_IRQHandler
+    ExcpHandler   ERU0_0_IRQHandler
+    ExcpHandler   ERU0_1_IRQHandler
+    ExcpHandler   ERU0_2_IRQHandler
+    ExcpHandler   ERU0_3_IRQHandler
+    ExcpHandler   ERU1_0_IRQHandler
+    ExcpHandler   ERU1_1_IRQHandler
+    ExcpHandler   ERU1_2_IRQHandler
+    ExcpHandler   ERU1_3_IRQHandler
+    ExcpHandler   PMU0_0_IRQHandler
+    ExcpHandler   VADC0_C0_0_IRQHandler
+    ExcpHandler   VADC0_C0_1_IRQHandler
+    ExcpHandler   VADC0_C0_2_IRQHandler
+    ExcpHandler   VADC0_C0_3_IRQHandler
+    ExcpHandler   VADC0_G0_0_IRQHandler
+    ExcpHandler   VADC0_G0_1_IRQHandler
+    ExcpHandler   VADC0_G0_2_IRQHandler
+    ExcpHandler   VADC0_G0_3_IRQHandler
+    ExcpHandler   VADC0_G1_0_IRQHandler
+    ExcpHandler   VADC0_G1_1_IRQHandler
+    ExcpHandler   VADC0_G1_2_IRQHandler
+    ExcpHandler   VADC0_G1_3_IRQHandler
+    ExcpHandler   DAC0_0_IRQHandler
+    ExcpHandler   DAC0_1_IRQHandler
+    ExcpHandler   CCU40_0_IRQHandler
+    ExcpHandler   CCU40_1_IRQHandler
+    ExcpHandler   CCU40_2_IRQHandler
+    ExcpHandler   CCU40_3_IRQHandler
+    ExcpHandler   CCU41_0_IRQHandler
+    ExcpHandler   CCU41_1_IRQHandler
+    ExcpHandler   CCU41_2_IRQHandler
+    ExcpHandler   CCU41_3_IRQHandler
+    ExcpHandler   CCU80_0_IRQHandler
+    ExcpHandler   CCU80_1_IRQHandler
+    ExcpHandler   CCU80_2_IRQHandler
+    ExcpHandler   CCU80_3_IRQHandler
+    ExcpHandler   POSIF0_0_IRQHandler
+    ExcpHandler   POSIF0_1_IRQHandler
+    ExcpHandler   HRPWM_0_IRQHandler
+    ExcpHandler   HRPWM_1_IRQHandler
+    ExcpHandler   HRPWM_2_IRQHandler
+    ExcpHandler   HRPWM_3_IRQHandler
+    ExcpHandler   CAN0_0_IRQHandler
+    ExcpHandler   CAN0_1_IRQHandler
+    ExcpHandler   CAN0_2_IRQHandler
+    ExcpHandler   CAN0_3_IRQHandler
+    ExcpHandler   CAN0_4_IRQHandler
+    ExcpHandler   CAN0_5_IRQHandler
+    ExcpHandler   CAN0_6_IRQHandler
+    ExcpHandler   CAN0_7_IRQHandler
+    ExcpHandler   USIC0_0_IRQHandler
+    ExcpHandler   USIC0_1_IRQHandler
+    ExcpHandler   USIC0_2_IRQHandler
+    ExcpHandler   USIC0_3_IRQHandler
+    ExcpHandler   USIC0_4_IRQHandler
+    ExcpHandler   USIC0_5_IRQHandler
+    ExcpHandler   USIC1_0_IRQHandler
+    ExcpHandler   USIC1_1_IRQHandler
+    ExcpHandler   USIC1_2_IRQHandler
+    ExcpHandler   USIC1_3_IRQHandler
+    ExcpHandler   USIC1_4_IRQHandler
+    ExcpHandler   USIC1_5_IRQHandler
+    ExcpHandler   LEDTS0_0_IRQHandler
+    ExcpHandler   FCE0_0_IRQHandler
+    ExcpHandler   GPDMA0_0_IRQHandler
+    ExcpHandler   USB0_0_IRQHandler
+
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
+
+;*  Definition of the default weak SystemInit_DAVE3 function.
+;*  This function will be called by the CMSIS SystemInit function.
+;*  If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
+;*  which will overule this weak definition
+SystemInit_DAVE3  PROC
+                  EXPORT  SystemInit_DAVE3             [WEAK]
+                  NOP
+                  BX     LR
+                  ENDP
+
+;*  Definition of the default weak DAVE3 function for clock App usage.
+;* AllowPLLInitByStartup Handler */
+AllowPLLInitByStartup    PROC
+                  EXPORT  AllowPLLInitByStartup        [WEAK]
+                  MOV    R0,#1
+                  BX     LR
+                  ENDP
+
+                  ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4400.s

@@ -0,0 +1,486 @@
+;*****************************************************************************/
+; * @file     startup_XMC4400.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File for
+; *           Infineon XMC4400 Device Series
+; * @version  V1.00
+; * @date     05. February 2013
+; *
+; * @note
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+;/* ********************* Version History *********************************** */
+;/* ***************************************************************************
+; V0.2 , August 2012, First version
+; V1.0 , February 2013, FIX for CPU prefetch bug implemented
+;**************************************************************************** */
+
+
+;*  <<< Use Configuration Wizard in Context Menu >>>
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
+;/*
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
+; * A veneer defined below will first
+; * be executed which in turn branches to the final exception handler.
+; *
+; * In addition to defining the veneers, the vector table must for these buggy
+; * devices contain the veneers.
+; */
+
+;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define
+;or use define below
+              GBLL WORKAROUND_PMU_CM001
+
+;/* A macro to setup a vector table entry based on STEP ID */
+              IF    :DEF:WORKAROUND_PMU_CM001
+                MACRO
+                ExcpVector $Handler
+                  DCD   $Handler._Veneer
+                MEND
+              ELSE
+                MACRO
+                ExcpVector $Handler
+                  DCD   $Handler
+                MEND
+              ENDIF
+
+;/* A macro to ease definition of the various handlers based on STEP ID */
+              IF     :DEF:WORKAROUND_PMU_CM001
+
+                ;/* First define the final exception handler */
+                MACRO
+                ExcpHandler $Handler_Func
+$Handler_Func\
+                  PROC
+                  EXPORT  $Handler_Func            [WEAK]
+                  B       .
+                  ENDP
+
+                ;/* And then define a veneer that will branch to the final excp handler */
+$Handler_Func._Veneer\
+                  PROC
+                  EXPORT  $Handler_Func._Veneer    [WEAK]
+                  LDR     R0, =$Handler_Func
+                  PUSH    {LR}
+                  BLX     R0
+                  POP     {PC}
+                  ALIGN
+                  LTORG
+                  ENDP
+                MEND
+
+              ELSE
+
+                ;/* No prefetch bug, hence define only the final exception handler */
+                MACRO
+                ExcpHandler $Handler_Func
+$Handler_Func\
+                  PROC
+                  EXPORT  $Handler_Func            [WEAK]
+                  B       .
+                  ENDP
+                MEND
+
+              ENDIF
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
+
+
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */
+;* Vector Table - This gets programed into VTOR register */
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+
+
+__Vectors
+    DCD          __initial_sp               ; Top of Stack
+    DCD          Reset_Handler              ; Reset Handler
+
+    ExcpVector   NMI_Handler                ; NMI Handler
+    ExcpVector   HardFault_Handler          ; Hard Fault Handler
+    ExcpVector   MemManage_Handler          ; MPU Fault Handler
+    ExcpVector   BusFault_Handler           ; Bus Fault Handler
+    ExcpVector   UsageFault_Handler         ; Usage Fault Handler
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          SVC_Handler                ; SVCall Handler
+    ExcpVector   DebugMon_Handler           ; Debug Monitor Handler
+    DCD          0                          ; Reserved
+    DCD          PendSV_Handler             ; PendSV Handler
+    DCD          SysTick_Handler            ; SysTick Handler
+
+    ; Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals
+    ExcpVector   SCU_0_IRQHandler           ; Handler name for SR SCU_0
+    ExcpVector   ERU0_0_IRQHandler          ; Handler name for SR ERU0_0
+    ExcpVector   ERU0_1_IRQHandler          ; Handler name for SR ERU0_1
+    ExcpVector   ERU0_2_IRQHandler          ; Handler name for SR ERU0_2
+    ExcpVector   ERU0_3_IRQHandler          ; Handler name for SR ERU0_3
+    ExcpVector   ERU1_0_IRQHandler          ; Handler name for SR ERU1_0
+    ExcpVector   ERU1_1_IRQHandler          ; Handler name for SR ERU1_1
+    ExcpVector   ERU1_2_IRQHandler          ; Handler name for SR ERU1_2
+    ExcpVector   ERU1_3_IRQHandler          ; Handler name for SR ERU1_3
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    ExcpVector   PMU0_0_IRQHandler          ; Handler name for SR PMU0_0
+    DCD          0                          ; Reserved
+    ExcpVector   VADC0_C0_0_IRQHandler      ; Handler name for SR VADC0_C0_0
+    ExcpVector   VADC0_C0_1_IRQHandler      ; Handler name for SR VADC0_C0_1
+    ExcpVector   VADC0_C0_2_IRQHandler      ; Handler name for SR VADC0_C0_1
+    ExcpVector   VADC0_C0_3_IRQHandler      ; Handler name for SR VADC0_C0_3
+    ExcpVector   VADC0_G0_0_IRQHandler      ; Handler name for SR VADC0_G0_0
+    ExcpVector   VADC0_G0_1_IRQHandler      ; Handler name for SR VADC0_G0_1
+    ExcpVector   VADC0_G0_2_IRQHandler      ; Handler name for SR VADC0_G0_2
+    ExcpVector   VADC0_G0_3_IRQHandler      ; Handler name for SR VADC0_G0_3
+    ExcpVector   VADC0_G1_0_IRQHandler      ; Handler name for SR VADC0_G1_0
+    ExcpVector   VADC0_G1_1_IRQHandler      ; Handler name for SR VADC0_G1_1
+    ExcpVector   VADC0_G1_2_IRQHandler      ; Handler name for SR VADC0_G1_2
+    ExcpVector   VADC0_G1_3_IRQHandler      ; Handler name for SR VADC0_G1_3
+    ExcpVector   VADC0_G2_0_IRQHandler      ; Handler name for SR VADC0_G2_0
+    ExcpVector   VADC0_G2_1_IRQHandler      ; Handler name for SR VADC0_G2_1
+    ExcpVector   VADC0_G2_2_IRQHandler      ; Handler name for SR VADC0_G2_2
+    ExcpVector   VADC0_G2_3_IRQHandler      ; Handler name for SR VADC0_G2_3
+    ExcpVector   VADC0_G3_0_IRQHandler      ; Handler name for SR VADC0_G3_0
+    ExcpVector   VADC0_G3_1_IRQHandler      ; Handler name for SR VADC0_G3_1
+    ExcpVector   VADC0_G3_2_IRQHandler      ; Handler name for SR VADC0_G3_2
+    ExcpVector   VADC0_G3_3_IRQHandler      ; Handler name for SR VADC0_G3_3
+    ExcpVector   DSD0_0_IRQHandler          ; Handler name for SR DSD0_0
+    ExcpVector   DSD0_1_IRQHandler          ; Handler name for SR DSD0_1
+    ExcpVector   DSD0_2_IRQHandler          ; Handler name for SR DSD0_2
+    ExcpVector   DSD0_3_IRQHandler          ; Handler name for SR DSD0_3
+    ExcpVector   DSD0_4_IRQHandler          ; Handler name for SR DSD0_4
+    ExcpVector   DSD0_5_IRQHandler          ; Handler name for SR DSD0_5
+    ExcpVector   DSD0_6_IRQHandler          ; Handler name for SR DSD0_6
+    ExcpVector   DSD0_7_IRQHandler          ; Handler name for SR DSD0_7
+    ExcpVector   DAC0_0_IRQHandler          ; Handler name for SR DAC0_0
+    ExcpVector   DAC0_1_IRQHandler          ; Handler name for SR DAC0_1
+    ExcpVector   CCU40_0_IRQHandler         ; Handler name for SR CCU40_0
+    ExcpVector   CCU40_1_IRQHandler         ; Handler name for SR CCU40_1
+    ExcpVector   CCU40_2_IRQHandler         ; Handler name for SR CCU40_2
+    ExcpVector   CCU40_3_IRQHandler         ; Handler name for SR CCU40_3
+    ExcpVector   CCU41_0_IRQHandler         ; Handler name for SR CCU41_0
+    ExcpVector   CCU41_1_IRQHandler         ; Handler name for SR CCU41_1
+    ExcpVector   CCU41_2_IRQHandler         ; Handler name for SR CCU41_2
+    ExcpVector   CCU41_3_IRQHandler         ; Handler name for SR CCU41_3
+    ExcpVector   CCU42_0_IRQHandler         ; Handler name for SR CCU42_0
+    ExcpVector   CCU42_1_IRQHandler         ; Handler name for SR CCU42_1
+    ExcpVector   CCU42_2_IRQHandler         ; Handler name for SR CCU42_2
+    ExcpVector   CCU42_3_IRQHandler         ; Handler name for SR CCU42_3
+    ExcpVector   CCU43_0_IRQHandler         ; Handler name for SR CCU43_0
+    ExcpVector   CCU43_1_IRQHandler         ; Handler name for SR CCU43_1
+    ExcpVector   CCU43_2_IRQHandler         ; Handler name for SR CCU43_2
+    ExcpVector   CCU43_3_IRQHandler         ; Handler name for SR CCU43_3
+    ExcpVector   CCU80_0_IRQHandler         ; Handler name for SR CCU80_0
+    ExcpVector   CCU80_1_IRQHandler         ; Handler name for SR CCU80_1
+    ExcpVector   CCU80_2_IRQHandler         ; Handler name for SR CCU80_2
+    ExcpVector   CCU80_3_IRQHandler         ; Handler name for SR CCU80_3
+    ExcpVector   CCU81_0_IRQHandler         ; Handler name for SR CCU81_0
+    ExcpVector   CCU81_1_IRQHandler         ; Handler name for SR CCU81_1
+    ExcpVector   CCU81_2_IRQHandler         ; Handler name for SR CCU81_2
+    ExcpVector   CCU81_3_IRQHandler         ; Handler name for SR CCU81_3
+    ExcpVector   POSIF0_0_IRQHandler        ; Handler name for SR POSIF0_0
+    ExcpVector   POSIF0_1_IRQHandler        ; Handler name for SR POSIF0_1
+    ExcpVector   POSIF1_0_IRQHandler        ; Handler name for SR POSIF1_0
+    ExcpVector   POSIF1_1_IRQHandler        ; Handler name for SR POSIF1_1
+    ExcpVector   HRPWM_0_IRQHandler         ; Handler name for SR HRPWM_0
+    ExcpVector   HRPWM_1_IRQHandler         ; Handler name for SR HRPWM_1
+    ExcpVector   HRPWM_2_IRQHandler         ; Handler name for SR HRPWM_2
+    ExcpVector   HRPWM_3_IRQHandler         ; Handler name for SR HRPWM_3
+    ExcpVector   CAN0_0_IRQHandler          ; Handler name for SR CAN0_0
+    ExcpVector   CAN0_1_IRQHandler          ; Handler name for SR CAN0_1
+    ExcpVector   CAN0_2_IRQHandler          ; Handler name for SR CAN0_2
+    ExcpVector   CAN0_3_IRQHandler          ; Handler name for SR CAN0_3
+    ExcpVector   CAN0_4_IRQHandler          ; Handler name for SR CAN0_4
+    ExcpVector   CAN0_5_IRQHandler          ; Handler name for SR CAN0_5
+    ExcpVector   CAN0_6_IRQHandler          ; Handler name for SR CAN0_6
+    ExcpVector   CAN0_7_IRQHandler          ; Handler name for SR CAN0_7
+    ExcpVector   USIC0_0_IRQHandler         ; Handler name for SR USIC0_0
+    ExcpVector   USIC0_1_IRQHandler         ; Handler name for SR USIC0_1
+    ExcpVector   USIC0_2_IRQHandler         ; Handler name for SR USIC0_2
+    ExcpVector   USIC0_3_IRQHandler         ; Handler name for SR USIC0_3
+    ExcpVector   USIC0_4_IRQHandler         ; Handler name for SR USIC0_4
+    ExcpVector   USIC0_5_IRQHandler         ; Handler name for SR USIC0_5
+    ExcpVector   USIC1_0_IRQHandler         ; Handler name for SR USIC1_0
+    ExcpVector   USIC1_1_IRQHandler         ; Handler name for SR USIC1_1
+    ExcpVector   USIC1_2_IRQHandler         ; Handler name for SR USIC1_2
+    ExcpVector   USIC1_3_IRQHandler         ; Handler name for SR USIC1_3
+    ExcpVector   USIC1_4_IRQHandler         ; Handler name for SR USIC1_4
+    ExcpVector   USIC1_5_IRQHandler         ; Handler name for SR USIC1_5
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    ExcpVector   LEDTS0_0_IRQHandler        ; Handler name for SR LEDTS0_0
+    DCD          0                          ; Reserved
+    ExcpVector   FCE0_0_IRQHandler          ; Handler name for SR FCE0_0
+    ExcpVector   GPDMA0_0_IRQHandler        ; Handler name for SR GPDMA0_0
+    DCD          0                          ; Reserved
+    ExcpVector   USB0_0_IRQHandler          ; Handler name for SR USB0_0
+    ExcpVector   ETH0_0_IRQHandler          ; Handler name for SR ETH0_0
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+    DCD          0                          ; Reserved
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+;* ================== END OF VECTOR TABLE DEFINITION ======================= */
+
+;* ================== START OF VECTOR ROUTINES ============================= */
+
+                AREA    |.text|, CODE, READONLY
+
+;* Reset Handler */
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+        ; Remap vector table
+        LDR     R0, =__Vectors
+        LDR     R1, =0xE000ED08 ;*VTOR register
+        STR     R0,[R1]
+
+        ;* C routines are likely to be called. Setup the stack now
+        LDR     SP,=__initial_sp
+
+        LDR     R0, = SystemInit
+        BLX     R0
+
+        ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
+        ;weakly defined here though for a potential override.
+
+        LDR     R0, = SystemInit_DAVE3
+        BLX     R0
+
+        ;* Reset stack pointer before zipping off to user application
+        LDR     SP,=__initial_sp
+
+        LDR     R0, =__main
+        BX      R0
+
+        ALIGN
+        ENDP
+
+
+
+
+;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
+
+
+
+;/* Default exception Handlers - Users may override this default functionality by
+;   defining handlers of the same name in their C code */
+
+    ExcpHandler   NMI_Handler
+    ExcpHandler   HardFault_Handler
+    ExcpHandler   MemManage_Handler
+    ExcpHandler   BusFault_Handler
+    ExcpHandler   UsageFault_Handler
+    ExcpHandler   SVC_Handler
+    ExcpHandler   DebugMon_Handler
+    ExcpHandler   PendSV_Handler
+    ExcpHandler   SysTick_Handler
+
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
+
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
+
+;* IRQ Handlers */
+    ExcpHandler   SCU_0_IRQHandler
+    ExcpHandler   ERU0_0_IRQHandler
+    ExcpHandler   ERU0_1_IRQHandler
+    ExcpHandler   ERU0_2_IRQHandler
+    ExcpHandler   ERU0_3_IRQHandler
+    ExcpHandler   ERU1_0_IRQHandler
+    ExcpHandler   ERU1_1_IRQHandler
+    ExcpHandler   ERU1_2_IRQHandler
+    ExcpHandler   ERU1_3_IRQHandler
+    ExcpHandler   PMU0_0_IRQHandler
+    ExcpHandler   VADC0_C0_0_IRQHandler
+    ExcpHandler   VADC0_C0_1_IRQHandler
+    ExcpHandler   VADC0_C0_2_IRQHandler
+    ExcpHandler   VADC0_C0_3_IRQHandler
+    ExcpHandler   VADC0_G0_0_IRQHandler
+    ExcpHandler   VADC0_G0_1_IRQHandler
+    ExcpHandler   VADC0_G0_2_IRQHandler
+    ExcpHandler   VADC0_G0_3_IRQHandler
+    ExcpHandler   VADC0_G1_0_IRQHandler
+    ExcpHandler   VADC0_G1_1_IRQHandler
+    ExcpHandler   VADC0_G1_2_IRQHandler
+    ExcpHandler   VADC0_G1_3_IRQHandler
+    ExcpHandler   VADC0_G2_0_IRQHandler
+    ExcpHandler   VADC0_G2_1_IRQHandler
+    ExcpHandler   VADC0_G2_2_IRQHandler
+    ExcpHandler   VADC0_G2_3_IRQHandler
+    ExcpHandler   VADC0_G3_0_IRQHandler
+    ExcpHandler   VADC0_G3_1_IRQHandler
+    ExcpHandler   VADC0_G3_2_IRQHandler
+    ExcpHandler   VADC0_G3_3_IRQHandler
+    ExcpHandler   DSD0_0_IRQHandler
+    ExcpHandler   DSD0_1_IRQHandler
+    ExcpHandler   DSD0_2_IRQHandler
+    ExcpHandler   DSD0_3_IRQHandler
+    ExcpHandler   DSD0_4_IRQHandler
+    ExcpHandler   DSD0_5_IRQHandler
+    ExcpHandler   DSD0_6_IRQHandler
+    ExcpHandler   DSD0_7_IRQHandler
+    ExcpHandler   DAC0_0_IRQHandler
+    ExcpHandler   DAC0_1_IRQHandler
+    ExcpHandler   CCU40_0_IRQHandler
+    ExcpHandler   CCU40_1_IRQHandler
+    ExcpHandler   CCU40_2_IRQHandler
+    ExcpHandler   CCU40_3_IRQHandler
+    ExcpHandler   CCU41_0_IRQHandler
+    ExcpHandler   CCU41_1_IRQHandler
+    ExcpHandler   CCU41_2_IRQHandler
+    ExcpHandler   CCU41_3_IRQHandler
+    ExcpHandler   CCU42_0_IRQHandler
+    ExcpHandler   CCU42_1_IRQHandler
+    ExcpHandler   CCU42_2_IRQHandler
+    ExcpHandler   CCU42_3_IRQHandler
+    ExcpHandler   CCU43_0_IRQHandler
+    ExcpHandler   CCU43_1_IRQHandler
+    ExcpHandler   CCU43_2_IRQHandler
+    ExcpHandler   CCU43_3_IRQHandler
+    ExcpHandler   CCU80_0_IRQHandler
+    ExcpHandler   CCU80_1_IRQHandler
+    ExcpHandler   CCU80_2_IRQHandler
+    ExcpHandler   CCU80_3_IRQHandler
+    ExcpHandler   CCU81_0_IRQHandler
+    ExcpHandler   CCU81_1_IRQHandler
+    ExcpHandler   CCU81_2_IRQHandler
+    ExcpHandler   CCU81_3_IRQHandler
+    ExcpHandler   POSIF0_0_IRQHandler
+    ExcpHandler   POSIF0_1_IRQHandler
+    ExcpHandler   POSIF1_0_IRQHandler
+    ExcpHandler   POSIF1_1_IRQHandler
+    ExcpHandler   HRPWM_0_IRQHandler
+    ExcpHandler   HRPWM_1_IRQHandler
+    ExcpHandler   HRPWM_2_IRQHandler
+    ExcpHandler   HRPWM_3_IRQHandler
+    ExcpHandler   CAN0_0_IRQHandler
+    ExcpHandler   CAN0_1_IRQHandler
+    ExcpHandler   CAN0_2_IRQHandler
+    ExcpHandler   CAN0_3_IRQHandler
+    ExcpHandler   CAN0_4_IRQHandler
+    ExcpHandler   CAN0_5_IRQHandler
+    ExcpHandler   CAN0_6_IRQHandler
+    ExcpHandler   CAN0_7_IRQHandler
+    ExcpHandler   USIC0_0_IRQHandler
+    ExcpHandler   USIC0_1_IRQHandler
+    ExcpHandler   USIC0_2_IRQHandler
+    ExcpHandler   USIC0_3_IRQHandler
+    ExcpHandler   USIC0_4_IRQHandler
+    ExcpHandler   USIC0_5_IRQHandler
+    ExcpHandler   USIC1_0_IRQHandler
+    ExcpHandler   USIC1_1_IRQHandler
+    ExcpHandler   USIC1_2_IRQHandler
+    ExcpHandler   USIC1_3_IRQHandler
+    ExcpHandler   USIC1_4_IRQHandler
+    ExcpHandler   USIC1_5_IRQHandler
+    ExcpHandler   LEDTS0_0_IRQHandler
+    ExcpHandler   FCE0_0_IRQHandler
+    ExcpHandler   GPDMA0_0_IRQHandler
+    ExcpHandler   USB0_0_IRQHandler
+    ExcpHandler   ETH0_0_IRQHandler
+
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
+
+;*  Definition of the default weak SystemInit_DAVE3 function.
+;*  This function will be called by the CMSIS SystemInit function.
+;*  If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
+;*  which will overule this weak definition
+SystemInit_DAVE3  PROC
+                  EXPORT  SystemInit_DAVE3             [WEAK]
+                  NOP
+                  BX     LR
+                  ENDP
+
+;*  Definition of the default weak DAVE3 function for clock App usage.
+;* AllowPLLInitByStartup Handler */
+AllowPLLInitByStartup    PROC
+                  EXPORT  AllowPLLInitByStartup        [WEAK]
+                  MOV    R0,#1
+                  BX     LR
+                  ENDP
+
+                  ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s

@@ -2,11 +2,11 @@
 ; * @file     startup_XMC4500.s
 ; * @brief    CMSIS Cortex-M4 Core Device Startup File for
 ; *           Infineon XMC4500 Device Series
-; * @version  V1.03
+; * @version  V1.20
-; * @date     16. Jan. 2012
+; * @date     05. February 2013
 ; *
 ; * @note
-; * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
 ; *
 ; * @par
 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M
@@ -22,6 +22,13 @@
 ; *
 ; ******************************************************************************/
 
+;/* ********************* Version History *********************************** */
+;/* ***************************************************************************
+; V1.00 , February 2012, First version
+; V1.10 , August 2012, Adding Dave3 init function call
+; V1.20 , February 2013, FIX for CPU prefetch bug implemented
+;**************************************************************************** */
+
 
 ;*  <<< Use Configuration Wizard in Context Menu >>>
 
@@ -53,6 +60,74 @@ __heap_limit
                 THUMB
 
 
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
+;/*
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
+; * A veneer defined below will first
+; * be executed which in turn branches to the final exception handler.
+; *
+; * In addition to defining the veneers, the vector table must for these buggy
+; * devices contain the veneers.
+; */
+
+;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define
+;or use define below
+              GBLL WORKAROUND_PMU_CM001
+
+;/* A macro to setup a vector table entry based on STEP ID */
+              IF    :DEF:WORKAROUND_PMU_CM001
+                MACRO
+                ExcpVector $Handler
+                  DCD   $Handler._Veneer
+                MEND
+              ELSE
+                MACRO
+                ExcpVector $Handler
+                  DCD   $Handler
+                MEND
+              ENDIF
+
+;/* A macro to ease definition of the various handlers based on STEP ID */
+              IF     :DEF:WORKAROUND_PMU_CM001
+
+                ;/* First define the final exception handler */
+                MACRO
+                ExcpHandler $Handler_Func
+$Handler_Func\
+                  PROC
+                  EXPORT  $Handler_Func            [WEAK]
+                  B       .
+                  ENDP
+
+                ;/* And then define a veneer that will branch to the final excp handler */
+$Handler_Func._Veneer\
+                  PROC
+                  EXPORT  $Handler_Func._Veneer    [WEAK]
+                  LDR     R0, =$Handler_Func
+                  PUSH    {LR}
+                  BLX     R0
+                  POP     {PC}
+                  ALIGN
+                  LTORG
+                  ENDP
+                MEND
+
+              ELSE
+
+                ;/* No prefetch bug, hence define only the final exception handler */
+                MACRO
+                ExcpHandler $Handler_Func
+$Handler_Func\
+                  PROC
+                  EXPORT  $Handler_Func            [WEAK]
+                  B       .
+                  ENDP
+                MEND
+
+              ENDIF
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
+
+
 ;* ================== START OF VECTOR TABLE DEFINITION ====================== */
 ;* Vector Table - This gets programed into VTOR register */
                 AREA    RESET, DATA, READONLY
@@ -63,136 +138,137 @@ __heap_limit
 
 
 __Vectors
-    DCD   __initial_sp                ;* Top of Stack                 */
+    DCD          __initial_sp               ; Top of Stack
-    DCD   Reset_Handler               ;* Reset Handler                */
+    DCD          Reset_Handler              ; Reset Handler
-    DCD   NMI_Handler                 ;* NMI Handler                  */
-    DCD   HardFault_Handler           ;* Hard Fault Handler           */
-    DCD   MemManage_Handler           ;* MPU Fault Handler            */
-    DCD   BusFault_Handler            ;* Bus Fault Handler            */
-    DCD   UsageFault_Handler          ;* Usage Fault Handler          */
-    DCD   0                           ;* Reserved                     */
-    DCD   0                           ;* Reserved                     */
-    DCD   0                           ;* Reserved                     */
-    DCD   0                           ;* Reserved                     */
-    DCD   SVC_Handler                 ;* SVCall Handler               */
-    DCD   DebugMon_Handler            ;* Debug Monitor Handler        */
-    DCD   0                           ;* Reserved                     */
-    DCD   PendSV_Handler              ;* PendSV Handler               */
-    DCD   SysTick_Handler             ;* SysTick Handler              */
 
-    ;* Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals */
+    ExcpVector   NMI_Handler                ; NMI Handler
-    DCD   SCU_0_IRQHandler            ;* Handler name for SR SCU_0     */
+    ExcpVector   HardFault_Handler          ; Hard Fault Handler
-    DCD   ERU0_0_IRQHandler           ;* Handler name for SR ERU0_0    */
+    ExcpVector   MemManage_Handler          ; MPU Fault Handler
-    DCD   ERU0_1_IRQHandler           ;* Handler name for SR ERU0_1    */
+    ExcpVector   BusFault_Handler           ; Bus Fault Handler
-    DCD   ERU0_2_IRQHandler           ;* Handler name for SR ERU0_2    */
+    ExcpVector   UsageFault_Handler         ; Usage Fault Handler
-    DCD   ERU0_3_IRQHandler           ;* Handler name for SR ERU0_3    */ 
+    DCD          0                          ; Reserved
-    DCD   ERU1_0_IRQHandler           ;* Handler name for SR ERU1_0    */
+    DCD          0                          ; Reserved
-    DCD   ERU1_1_IRQHandler           ;* Handler name for SR ERU1_1    */
+    DCD          0                          ; Reserved
-    DCD   ERU1_2_IRQHandler           ;* Handler name for SR ERU1_2    */
+    DCD          0                          ; Reserved
-    DCD   ERU1_3_IRQHandler           ;* Handler name for SR ERU1_3    */
+    DCD   		 SVC_Handler                ; SVCall Handler
-    DCD   0                           ;* Not Available                 */
+    ExcpVector   DebugMon_Handler           ; Debug Monitor Handler
-    DCD   0                           ;* Not Available                 */
+    DCD          0                          ; Reserved
-    DCD   0                           ;* Not Available                 */
+    DCD   		 PendSV_Handler             ; PendSV Handler
-    DCD   PMU0_0_IRQHandler           ;* Handler name for SR PMU0_0    */
+    DCD   		 SysTick_Handler            ; SysTick Handler
-    DCD   0                           ;* Not Available                 */
+
-    DCD   VADC0_C0_0_IRQHandler       ;* Handler name for SR VADC0_C0_0  */
+    ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals
-    DCD   VADC0_C0_1_IRQHandler       ;* Handler name for SR VADC0_C0_1  */
+    ExcpVector   SCU_0_IRQHandler           ; Handler name for SR SCU_0
-    DCD   VADC0_C0_2_IRQHandler       ;* Handler name for SR VADC0_C0_1  */
+    ExcpVector   ERU0_0_IRQHandler          ; Handler name for SR ERU0_0
-    DCD   VADC0_C0_3_IRQHandler       ;* Handler name for SR VADC0_C0_3  */
+    ExcpVector   ERU0_1_IRQHandler          ; Handler name for SR ERU0_1
-    DCD   VADC0_G0_0_IRQHandler       ;* Handler name for SR VADC0_G0_0  */
+    ExcpVector   ERU0_2_IRQHandler          ; Handler name for SR ERU0_2
-    DCD   VADC0_G0_1_IRQHandler       ;* Handler name for SR VADC0_G0_1  */
+    ExcpVector   ERU0_3_IRQHandler          ; Handler name for SR ERU0_3
-    DCD   VADC0_G0_2_IRQHandler       ;* Handler name for SR VADC0_G0_2  */
+    ExcpVector   ERU1_0_IRQHandler          ; Handler name for SR ERU1_0
-    DCD   VADC0_G0_3_IRQHandler       ;* Handler name for SR VADC0_G0_3  */
+    ExcpVector   ERU1_1_IRQHandler          ; Handler name for SR ERU1_1
-    DCD   VADC0_G1_0_IRQHandler       ;* Handler name for SR VADC0_G1_0  */
+    ExcpVector   ERU1_2_IRQHandler          ; Handler name for SR ERU1_2
-    DCD   VADC0_G1_1_IRQHandler       ;* Handler name for SR VADC0_G1_1  */
+    ExcpVector   ERU1_3_IRQHandler          ; Handler name for SR ERU1_3
-    DCD   VADC0_G1_2_IRQHandler       ;* Handler name for SR VADC0_G1_2  */
+    DCD          0                          ; Reserved
-    DCD   VADC0_G1_3_IRQHandler       ;* Handler name for SR VADC0_G1_3  */
+    DCD          0                          ; Reserved
-    DCD   VADC0_G2_0_IRQHandler       ;* Handler name for SR VADC0_G2_0  */
+    DCD          0                          ; Reserved
-    DCD   VADC0_G2_1_IRQHandler       ;* Handler name for SR VADC0_G2_1  */
+    ExcpVector   PMU0_0_IRQHandler          ; Handler name for SR PMU0_0
-    DCD   VADC0_G2_2_IRQHandler       ;* Handler name for SR VADC0_G2_2  */
+    DCD          0                          ; Reserved
-    DCD   VADC0_G2_3_IRQHandler       ;* Handler name for SR VADC0_G2_3  */
+    ExcpVector   VADC0_C0_0_IRQHandler      ; Handler name for SR VADC0_C0_0
-    DCD   VADC0_G3_0_IRQHandler       ;* Handler name for SR VADC0_G3_0  */
+    ExcpVector   VADC0_C0_1_IRQHandler      ; Handler name for SR VADC0_C0_1
-    DCD   VADC0_G3_1_IRQHandler       ;* Handler name for SR VADC0_G3_1  */
+    ExcpVector   VADC0_C0_2_IRQHandler      ; Handler name for SR VADC0_C0_1
-    DCD   VADC0_G3_2_IRQHandler       ;* Handler name for SR VADC0_G3_2  */
+    ExcpVector   VADC0_C0_3_IRQHandler      ; Handler name for SR VADC0_C0_3
-    DCD   VADC0_G3_3_IRQHandler       ;* Handler name for SR VADC0_G3_3  */
+    ExcpVector   VADC0_G0_0_IRQHandler      ; Handler name for SR VADC0_G0_0
-    DCD   DSD0_0_IRQHandler           ;* Handler name for SR DSD0_0    */
+    ExcpVector   VADC0_G0_1_IRQHandler      ; Handler name for SR VADC0_G0_1
-    DCD   DSD0_1_IRQHandler           ;* Handler name for SR DSD0_1    */
+    ExcpVector   VADC0_G0_2_IRQHandler      ; Handler name for SR VADC0_G0_2
-    DCD   DSD0_2_IRQHandler           ;* Handler name for SR DSD0_2    */
+    ExcpVector   VADC0_G0_3_IRQHandler      ; Handler name for SR VADC0_G0_3
-    DCD   DSD0_3_IRQHandler           ;* Handler name for SR DSD0_3    */
+    ExcpVector   VADC0_G1_0_IRQHandler      ; Handler name for SR VADC0_G1_0
-    DCD   DSD0_4_IRQHandler           ;* Handler name for SR DSD0_4    */
+    ExcpVector   VADC0_G1_1_IRQHandler      ; Handler name for SR VADC0_G1_1
-    DCD   DSD0_5_IRQHandler           ;* Handler name for SR DSD0_5    */
+    ExcpVector   VADC0_G1_2_IRQHandler      ; Handler name for SR VADC0_G1_2
-    DCD   DSD0_6_IRQHandler           ;* Handler name for SR DSD0_6    */
+    ExcpVector   VADC0_G1_3_IRQHandler      ; Handler name for SR VADC0_G1_3
-    DCD   DSD0_7_IRQHandler           ;* Handler name for SR DSD0_7    */
+    ExcpVector   VADC0_G2_0_IRQHandler      ; Handler name for SR VADC0_G2_0
-    DCD   DAC0_0_IRQHandler           ;* Handler name for SR DAC0_0    */
+    ExcpVector   VADC0_G2_1_IRQHandler      ; Handler name for SR VADC0_G2_1
-    DCD   DAC0_1_IRQHandler           ;* Handler name for SR DAC0_0    */
+    ExcpVector   VADC0_G2_2_IRQHandler      ; Handler name for SR VADC0_G2_2
-    DCD   CCU40_0_IRQHandler          ;* Handler name for SR CCU40_0   */
+    ExcpVector   VADC0_G2_3_IRQHandler      ; Handler name for SR VADC0_G2_3
-    DCD   CCU40_1_IRQHandler          ;* Handler name for SR CCU40_1   */
+    ExcpVector   VADC0_G3_0_IRQHandler      ; Handler name for SR VADC0_G3_0
-    DCD   CCU40_2_IRQHandler          ;* Handler name for SR CCU40_2   */
+    ExcpVector   VADC0_G3_1_IRQHandler      ; Handler name for SR VADC0_G3_1
-    DCD   CCU40_3_IRQHandler          ;* Handler name for SR CCU40_3   */
+    ExcpVector   VADC0_G3_2_IRQHandler      ; Handler name for SR VADC0_G3_2
-    DCD   CCU41_0_IRQHandler          ;* Handler name for SR CCU41_0   */
+    ExcpVector   VADC0_G3_3_IRQHandler      ; Handler name for SR VADC0_G3_3
-    DCD   CCU41_1_IRQHandler          ;* Handler name for SR CCU41_1   */
+    ExcpVector   DSD0_0_IRQHandler          ; Handler name for SR DSD0_0
-    DCD   CCU41_2_IRQHandler          ;* Handler name for SR CCU41_2   */
+    ExcpVector   DSD0_1_IRQHandler          ; Handler name for SR DSD0_1
-    DCD   CCU41_3_IRQHandler          ;* Handler name for SR CCU41_3   */
+    ExcpVector   DSD0_2_IRQHandler          ; Handler name for SR DSD0_2
-    DCD   CCU42_0_IRQHandler          ;* Handler name for SR CCU42_0   */
+    ExcpVector   DSD0_3_IRQHandler          ; Handler name for SR DSD0_3
-    DCD   CCU42_1_IRQHandler          ;* Handler name for SR CCU42_1   */
+    ExcpVector   DSD0_4_IRQHandler          ; Handler name for SR DSD0_4
-    DCD   CCU42_2_IRQHandler          ;* Handler name for SR CCU42_2   */
+    ExcpVector   DSD0_5_IRQHandler          ; Handler name for SR DSD0_5
-    DCD   CCU42_3_IRQHandler          ;* Handler name for SR CCU42_3   */
+    ExcpVector   DSD0_6_IRQHandler          ; Handler name for SR DSD0_6
-    DCD   CCU43_0_IRQHandler          ;* Handler name for SR CCU43_0   */
+    ExcpVector   DSD0_7_IRQHandler          ; Handler name for SR DSD0_7
-    DCD   CCU43_1_IRQHandler          ;* Handler name for SR CCU43_1   */
+    ExcpVector   DAC0_0_IRQHandler          ; Handler name for SR DAC0_0
-    DCD   CCU43_2_IRQHandler          ;* Handler name for SR CCU43_2   */
+    ExcpVector   DAC0_1_IRQHandler          ; Handler name for SR DAC0_1
-    DCD   CCU43_3_IRQHandler          ;* Handler name for SR CCU43_3   */
+    ExcpVector   CCU40_0_IRQHandler         ; Handler name for SR CCU40_0
-    DCD   CCU80_0_IRQHandler          ;* Handler name for SR CCU80_0   */
+    ExcpVector   CCU40_1_IRQHandler         ; Handler name for SR CCU40_1
-    DCD   CCU80_1_IRQHandler          ;* Handler name for SR CCU80_1   */
+    ExcpVector   CCU40_2_IRQHandler         ; Handler name for SR CCU40_2
-    DCD   CCU80_2_IRQHandler          ;* Handler name for SR CCU80_2   */
+    ExcpVector   CCU40_3_IRQHandler         ; Handler name for SR CCU40_3
-    DCD   CCU80_3_IRQHandler          ;* Handler name for SR CCU80_3   */
+    ExcpVector   CCU41_0_IRQHandler         ; Handler name for SR CCU41_0
-    DCD   CCU81_0_IRQHandler          ;* Handler name for SR CCU81_0   */
+    ExcpVector   CCU41_1_IRQHandler         ; Handler name for SR CCU41_1
-    DCD   CCU81_1_IRQHandler          ;* Handler name for SR CCU81_1   */
+    ExcpVector   CCU41_2_IRQHandler         ; Handler name for SR CCU41_2
-    DCD   CCU81_2_IRQHandler          ;* Handler name for SR CCU81_2   */
+    ExcpVector   CCU41_3_IRQHandler         ; Handler name for SR CCU41_3
-    DCD   CCU81_3_IRQHandler          ;* Handler name for SR CCU81_3   */
+    ExcpVector   CCU42_0_IRQHandler         ; Handler name for SR CCU42_0
-    DCD   POSIF0_0_IRQHandler         ;* Handler name for SR POSIF0_0  */
+    ExcpVector   CCU42_1_IRQHandler         ; Handler name for SR CCU42_1
-    DCD   POSIF0_1_IRQHandler         ;* Handler name for SR POSIF0_1  */
+    ExcpVector   CCU42_2_IRQHandler         ; Handler name for SR CCU42_2
-    DCD   POSIF1_0_IRQHandler         ;* Handler name for SR POSIF1_0  */
+    ExcpVector   CCU42_3_IRQHandler         ; Handler name for SR CCU42_3
-    DCD   POSIF1_1_IRQHandler         ;* Handler name for SR POSIF1_1  */
+    ExcpVector   CCU43_0_IRQHandler         ; Handler name for SR CCU43_0
-    DCD   0                           ;* Not Available                 */
+    ExcpVector   CCU43_1_IRQHandler         ; Handler name for SR CCU43_1
-    DCD   0                           ;* Not Available                 */
+    ExcpVector   CCU43_2_IRQHandler         ; Handler name for SR CCU43_2
-    DCD   0                           ;* Not Available                 */
+    ExcpVector   CCU43_3_IRQHandler         ; Handler name for SR CCU43_3
-    DCD   0                           ;* Not Available                 */
+    ExcpVector   CCU80_0_IRQHandler         ; Handler name for SR CCU80_0
-    DCD   CAN0_0_IRQHandler           ;* Handler name for SR CAN0_0    */
+    ExcpVector   CCU80_1_IRQHandler         ; Handler name for SR CCU80_1
-    DCD   CAN0_1_IRQHandler           ;* Handler name for SR CAN0_1    */
+    ExcpVector   CCU80_2_IRQHandler         ; Handler name for SR CCU80_2
-    DCD   CAN0_2_IRQHandler           ;* Handler name for SR CAN0_2    */
+    ExcpVector   CCU80_3_IRQHandler         ; Handler name for SR CCU80_3
-    DCD   CAN0_3_IRQHandler           ;* Handler name for SR CAN0_3    */
+    ExcpVector   CCU81_0_IRQHandler         ; Handler name for SR CCU81_0
-    DCD   CAN0_4_IRQHandler           ;* Handler name for SR CAN0_4    */
+    ExcpVector   CCU81_1_IRQHandler         ; Handler name for SR CCU81_1
-    DCD   CAN0_5_IRQHandler           ;* Handler name for SR CAN0_5    */
+    ExcpVector   CCU81_2_IRQHandler         ; Handler name for SR CCU81_2
-    DCD   CAN0_6_IRQHandler           ;* Handler name for SR CAN0_6    */
+    ExcpVector   CCU81_3_IRQHandler         ; Handler name for SR CCU81_3
-    DCD   CAN0_7_IRQHandler           ;* Handler name for SR CAN0_7    */
+    ExcpVector   POSIF0_0_IRQHandler        ; Handler name for SR POSIF0_0
-    DCD   USIC0_0_IRQHandler          ;* Handler name for SR USIC0_0   */
+    ExcpVector   POSIF0_1_IRQHandler        ; Handler name for SR POSIF0_1
-    DCD   USIC0_1_IRQHandler          ;* Handler name for SR USIC0_1   */
+    ExcpVector   POSIF1_0_IRQHandler        ; Handler name for SR POSIF1_0
-    DCD   USIC0_2_IRQHandler          ;* Handler name for SR USIC0_2   */
+    ExcpVector   POSIF1_1_IRQHandler        ; Handler name for SR POSIF1_1
-    DCD   USIC0_3_IRQHandler          ;* Handler name for SR USIC0_3   */
+    DCD          0                          ; Reserved
-    DCD   USIC0_4_IRQHandler          ;* Handler name for SR USIC0_4   */
+    DCD          0                          ; Reserved
-    DCD   USIC0_5_IRQHandler          ;* Handler name for SR USIC0_5   */
+    DCD          0                          ; Reserved
-    DCD   USIC1_0_IRQHandler          ;* Handler name for SR USIC1_0   */
+    DCD          0                          ; Reserved
-    DCD   USIC1_1_IRQHandler          ;* Handler name for SR USIC1_1   */
+    ExcpVector   CAN0_0_IRQHandler          ; Handler name for SR CAN0_0
-    DCD   USIC1_2_IRQHandler          ;* Handler name for SR USIC1_2   */
+    ExcpVector   CAN0_1_IRQHandler          ; Handler name for SR CAN0_1
-    DCD   USIC1_3_IRQHandler          ;* Handler name for SR USIC1_3   */
+    ExcpVector   CAN0_2_IRQHandler          ; Handler name for SR CAN0_2
-    DCD   USIC1_4_IRQHandler          ;* Handler name for SR USIC1_4   */
+    ExcpVector   CAN0_3_IRQHandler          ; Handler name for SR CAN0_3
-    DCD   USIC1_5_IRQHandler          ;* Handler name for SR USIC1_5   */
+    ExcpVector   CAN0_4_IRQHandler          ; Handler name for SR CAN0_4
-    DCD   USIC2_0_IRQHandler          ;* Handler name for SR USIC2_0   */
+    ExcpVector   CAN0_5_IRQHandler          ; Handler name for SR CAN0_5
-    DCD   USIC2_1_IRQHandler          ;* Handler name for SR USIC2_1   */
+    ExcpVector   CAN0_6_IRQHandler          ; Handler name for SR CAN0_6
-    DCD   USIC2_2_IRQHandler          ;* Handler name for SR USIC2_2   */
+    ExcpVector   CAN0_7_IRQHandler          ; Handler name for SR CAN0_7
-    DCD   USIC2_3_IRQHandler          ;* Handler name for SR USIC2_3   */
+    ExcpVector   USIC0_0_IRQHandler         ; Handler name for SR USIC0_0
-    DCD   USIC2_4_IRQHandler          ;* Handler name for SR USIC2_4   */
+    ExcpVector   USIC0_1_IRQHandler         ; Handler name for SR USIC0_1
-    DCD   USIC2_5_IRQHandler          ;* Handler name for SR USIC2_5   */
+    ExcpVector   USIC0_2_IRQHandler         ; Handler name for SR USIC0_2
-    DCD   LEDTS0_0_IRQHandler         ;* Handler name for SR LEDTS0_0  */
+    ExcpVector   USIC0_3_IRQHandler         ; Handler name for SR USIC0_3
-    DCD   0                           ;* Not Available                 */
+    ExcpVector   USIC0_4_IRQHandler         ; Handler name for SR USIC0_4
-    DCD   FCE0_0_IRQHandler           ;* Handler name for SR FCE0_0    */
+    ExcpVector   USIC0_5_IRQHandler         ; Handler name for SR USIC0_5
-    DCD   GPDMA0_0_IRQHandler         ;* Handler name for SR GPDMA0_0  */
+    ExcpVector   USIC1_0_IRQHandler         ; Handler name for SR USIC1_0
-    DCD   SDMMC0_0_IRQHandler         ;* Handler name for SR SDMMC0_0  */
+    ExcpVector   USIC1_1_IRQHandler         ; Handler name for SR USIC1_1
-    DCD   USB0_0_IRQHandler           ;* Handler name for SR USB0_0    */
+    ExcpVector   USIC1_2_IRQHandler         ; Handler name for SR USIC1_2
-    DCD   ETH0_0_IRQHandler           ;* Handler name for SR ETH0_0    */
+    ExcpVector   USIC1_3_IRQHandler         ; Handler name for SR USIC1_3
-    DCD   0                           ;* Not Available                 */
+    ExcpVector   USIC1_4_IRQHandler         ; Handler name for SR USIC1_4
-    DCD   GPDMA1_0_IRQHandler         ;* Handler name for SR GPDMA1_0  */
+    ExcpVector   USIC1_5_IRQHandler         ; Handler name for SR USIC1_5
-    DCD   0                           ;* Not Available                 */
+    ExcpVector   USIC2_0_IRQHandler         ; Handler name for SR USIC2_0
+    ExcpVector   USIC2_1_IRQHandler         ; Handler name for SR USIC2_1
+    ExcpVector   USIC2_2_IRQHandler         ; Handler name for SR USIC2_2
+    ExcpVector   USIC2_3_IRQHandler         ; Handler name for SR USIC2_3
+    ExcpVector   USIC2_4_IRQHandler         ; Handler name for SR USIC2_4
+    ExcpVector   USIC2_5_IRQHandler         ; Handler name for SR USIC2_5
+    ExcpVector   LEDTS0_0_IRQHandler        ; Handler name for SR LEDTS0_0
+    DCD          0                          ; Reserved
+    ExcpVector   FCE0_0_IRQHandler          ; Handler name for SR FCE0_0
+    ExcpVector   GPDMA0_0_IRQHandler        ; Handler name for SR GPDMA0_0
+    ExcpVector   SDMMC0_0_IRQHandler        ; Handler name for SR SDMMC0_0
+    ExcpVector   USB0_0_IRQHandler          ; Handler name for SR USB0_0
+    ExcpVector   ETH0_0_IRQHandler          ; Handler name for SR ETH0_0
+    DCD          0                          ; Reserved
+    ExcpVector   GPDMA1_0_IRQHandler        ; Handler name for SR GPDMA1_0
+    DCD          0                          ; Reserved
 __Vectors_End
 
 __Vectors_Size  EQU  __Vectors_End - __Vectors
@@ -214,36 +290,17 @@ Reset_Handler    PROC
         LDR     R1, =0xE000ED08 ;*VTOR register
         STR     R0,[R1]
 
-				; switch off branch prediction required in A11 step to use cached memory
-        LDR R0,=0x58004000  ;PREF_PCON         
-				LDR R1,[R0]
-				ORR R1,R1,#0x00010000
-				STR R1,[R0]
-
-        ; Clear existing parity errors if any required in A11 step 
-				LDR R0,=0x50004150  ;SCU_GCU_PEFLAG
-				LDR R1,=0xFFFFFFFF
-				STR R1,[R0]
-
-				; Disable parity  required in A11 step
-				LDR R0,=0x5000413C ; SCU_GCU_PEEN
-				MOV R1,#0
-				STR R1,[R0]
-
-        ;enable un-aligned memory access 
-        LDR     R1, =0xE000ED14 
-        LDR.W   R0,[R1,#0x0]
-        BIC     R0,R0,#0x8
-        STR.W   R0,[R1,#0x0]
-
-
         ;* C routines are likely to be called. Setup the stack now
         LDR     SP,=__initial_sp
 
-
         LDR     R0, = SystemInit
         BLX     R0
 
+        ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
+        ;weakly defined here though for a potential override.
+
+        LDR     R0, = SystemInit_DAVE3
+        BLX     R0
 
         ;* Reset stack pointer before zipping off to user application
         LDR     SP,=__initial_sp
@@ -251,265 +308,135 @@ Reset_Handler    PROC
         LDR     R0, =__main
         BX      R0
 
+        ALIGN
         ENDP
 
 
+
+
 ;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
 
-;* Default exception Handlers - Users may override this default functionality by
 
-NMI_Handler     PROC
+
-                EXPORT  NMI_Handler                [WEAK]
+;/* Default exception Handlers - Users may override this default functionality by
-                B       .
+;   defining handlers of the same name in their C code */
-                ENDP
+
-HardFault_Handler\
+    ExcpHandler   NMI_Handler
-                PROC
+    ExcpHandler   HardFault_Handler
-                EXPORT  HardFault_Handler          [WEAK]
+    ExcpHandler   MemManage_Handler
-                B       .
+    ExcpHandler   BusFault_Handler
-                ENDP
+    ExcpHandler   UsageFault_Handler
-MemManage_Handler\
+    ExcpHandler   SVC_Handler
-                PROC
+    ExcpHandler   DebugMon_Handler
-                EXPORT  MemManage_Handler          [WEAK]
+    ExcpHandler   PendSV_Handler
-                B       .
+    ExcpHandler   SysTick_Handler
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
 
 ;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
 
 ;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
 
 ;* IRQ Handlers */
-               EXPORT   SCU_0_IRQHandler           [WEAK]
+    ExcpHandler   SCU_0_IRQHandler
-               EXPORT   ERU0_0_IRQHandler          [WEAK]
+    ExcpHandler   ERU0_0_IRQHandler
-               EXPORT   ERU0_1_IRQHandler          [WEAK]
+    ExcpHandler   ERU0_1_IRQHandler
-               EXPORT   ERU0_2_IRQHandler          [WEAK]
+    ExcpHandler   ERU0_2_IRQHandler
-               EXPORT   ERU0_3_IRQHandler          [WEAK]
+    ExcpHandler   ERU0_3_IRQHandler
-               EXPORT   ERU1_0_IRQHandler          [WEAK]
+    ExcpHandler   ERU1_0_IRQHandler
-               EXPORT   ERU1_1_IRQHandler          [WEAK]
+    ExcpHandler   ERU1_1_IRQHandler
-               EXPORT   ERU1_2_IRQHandler          [WEAK]
+    ExcpHandler   ERU1_2_IRQHandler
-               EXPORT   ERU1_3_IRQHandler          [WEAK]
+    ExcpHandler   ERU1_3_IRQHandler
-               EXPORT   PMU0_0_IRQHandler          [WEAK]
+    ExcpHandler   PMU0_0_IRQHandler
-               EXPORT   VADC0_C0_0_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_C0_0_IRQHandler
-               EXPORT   VADC0_C0_1_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_C0_1_IRQHandler
-               EXPORT   VADC0_C0_2_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_C0_2_IRQHandler
-               EXPORT   VADC0_C0_3_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_C0_3_IRQHandler
-               EXPORT   VADC0_G0_0_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G0_0_IRQHandler
-               EXPORT   VADC0_G0_1_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G0_1_IRQHandler
-               EXPORT   VADC0_G0_2_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G0_2_IRQHandler
-               EXPORT   VADC0_G0_3_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G0_3_IRQHandler
-               EXPORT   VADC0_G1_0_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G1_0_IRQHandler
-               EXPORT   VADC0_G1_1_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G1_1_IRQHandler
-               EXPORT   VADC0_G1_2_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G1_2_IRQHandler
-               EXPORT   VADC0_G1_3_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G1_3_IRQHandler
-               EXPORT   VADC0_G2_0_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G2_0_IRQHandler
-               EXPORT   VADC0_G2_1_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G2_1_IRQHandler
-               EXPORT   VADC0_G2_2_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G2_2_IRQHandler
-               EXPORT   VADC0_G2_3_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G2_3_IRQHandler
-               EXPORT   VADC0_G3_0_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G3_0_IRQHandler
-               EXPORT   VADC0_G3_1_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G3_1_IRQHandler
-               EXPORT   VADC0_G3_2_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G3_2_IRQHandler
-               EXPORT   VADC0_G3_3_IRQHandler      [WEAK]
+    ExcpHandler   VADC0_G3_3_IRQHandler
-               EXPORT   DSD0_0_IRQHandler          [WEAK]
+    ExcpHandler   DSD0_0_IRQHandler
-               EXPORT   DSD0_1_IRQHandler          [WEAK]
+    ExcpHandler   DSD0_1_IRQHandler
-               EXPORT   DSD0_2_IRQHandler          [WEAK]
+    ExcpHandler   DSD0_2_IRQHandler
-               EXPORT   DSD0_3_IRQHandler          [WEAK]
+    ExcpHandler   DSD0_3_IRQHandler
-               EXPORT   DSD0_4_IRQHandler          [WEAK]
+    ExcpHandler   DSD0_4_IRQHandler
-               EXPORT   DSD0_5_IRQHandler          [WEAK]
+    ExcpHandler   DSD0_5_IRQHandler
-               EXPORT   DSD0_6_IRQHandler          [WEAK]
+    ExcpHandler   DSD0_6_IRQHandler
-               EXPORT   DSD0_7_IRQHandler          [WEAK]
+    ExcpHandler   DSD0_7_IRQHandler
-               EXPORT   DAC0_0_IRQHandler          [WEAK]
+    ExcpHandler   DAC0_0_IRQHandler
-               EXPORT   DAC0_1_IRQHandler          [WEAK]
+    ExcpHandler   DAC0_1_IRQHandler
-               EXPORT   CCU40_0_IRQHandler         [WEAK]
+    ExcpHandler   CCU40_0_IRQHandler
-               EXPORT   CCU40_1_IRQHandler         [WEAK]
+    ExcpHandler   CCU40_1_IRQHandler
-               EXPORT   CCU40_2_IRQHandler         [WEAK]
+    ExcpHandler   CCU40_2_IRQHandler
-               EXPORT   CCU40_3_IRQHandler         [WEAK]
+    ExcpHandler   CCU40_3_IRQHandler
-               EXPORT   CCU41_0_IRQHandler         [WEAK]
+    ExcpHandler   CCU41_0_IRQHandler
-               EXPORT   CCU41_1_IRQHandler         [WEAK]
+    ExcpHandler   CCU41_1_IRQHandler
-               EXPORT   CCU41_2_IRQHandler         [WEAK]
+    ExcpHandler   CCU41_2_IRQHandler
-               EXPORT   CCU41_3_IRQHandler         [WEAK]
+    ExcpHandler   CCU41_3_IRQHandler
-               EXPORT   CCU42_0_IRQHandler         [WEAK]
+    ExcpHandler   CCU42_0_IRQHandler
-               EXPORT   CCU42_1_IRQHandler         [WEAK]
+    ExcpHandler   CCU42_1_IRQHandler
-               EXPORT   CCU42_2_IRQHandler         [WEAK]
+    ExcpHandler   CCU42_2_IRQHandler
-               EXPORT   CCU42_3_IRQHandler         [WEAK]
+    ExcpHandler   CCU42_3_IRQHandler
-               EXPORT   CCU43_0_IRQHandler         [WEAK]
+    ExcpHandler   CCU43_0_IRQHandler
-               EXPORT   CCU43_1_IRQHandler         [WEAK]
+    ExcpHandler   CCU43_1_IRQHandler
-               EXPORT   CCU43_2_IRQHandler         [WEAK]
+    ExcpHandler   CCU43_2_IRQHandler
-               EXPORT   CCU43_3_IRQHandler         [WEAK]
+    ExcpHandler   CCU43_3_IRQHandler
-               EXPORT   CCU80_0_IRQHandler         [WEAK]
+    ExcpHandler   CCU80_0_IRQHandler
-               EXPORT   CCU80_1_IRQHandler         [WEAK]
+    ExcpHandler   CCU80_1_IRQHandler
-               EXPORT   CCU80_2_IRQHandler         [WEAK]
+    ExcpHandler   CCU80_2_IRQHandler
-               EXPORT   CCU80_3_IRQHandler         [WEAK]
+    ExcpHandler   CCU80_3_IRQHandler
-               EXPORT   CCU81_0_IRQHandler         [WEAK]
+    ExcpHandler   CCU81_0_IRQHandler
-               EXPORT   CCU81_1_IRQHandler         [WEAK]
+    ExcpHandler   CCU81_1_IRQHandler
-               EXPORT   CCU81_2_IRQHandler         [WEAK]
+    ExcpHandler   CCU81_2_IRQHandler
-               EXPORT   CCU81_3_IRQHandler         [WEAK]
+    ExcpHandler   CCU81_3_IRQHandler
-               EXPORT   POSIF0_0_IRQHandler        [WEAK]
+    ExcpHandler   POSIF0_0_IRQHandler
-               EXPORT   POSIF0_1_IRQHandler        [WEAK]
+    ExcpHandler   POSIF0_1_IRQHandler
-               EXPORT   POSIF1_0_IRQHandler        [WEAK]
+    ExcpHandler   POSIF1_0_IRQHandler
-               EXPORT   POSIF1_1_IRQHandler        [WEAK]
+    ExcpHandler   POSIF1_1_IRQHandler
-               EXPORT   CAN0_0_IRQHandler          [WEAK]
+    ExcpHandler   CAN0_0_IRQHandler
-               EXPORT   CAN0_1_IRQHandler          [WEAK]
+    ExcpHandler   CAN0_1_IRQHandler
-               EXPORT   CAN0_2_IRQHandler          [WEAK]
+    ExcpHandler   CAN0_2_IRQHandler
-               EXPORT   CAN0_3_IRQHandler          [WEAK]
+    ExcpHandler   CAN0_3_IRQHandler
-               EXPORT   CAN0_4_IRQHandler          [WEAK]
+    ExcpHandler   CAN0_4_IRQHandler
-               EXPORT   CAN0_5_IRQHandler          [WEAK]
+    ExcpHandler   CAN0_5_IRQHandler
-               EXPORT   CAN0_6_IRQHandler          [WEAK]
+    ExcpHandler   CAN0_6_IRQHandler
-               EXPORT   CAN0_7_IRQHandler          [WEAK]
+    ExcpHandler   CAN0_7_IRQHandler
-               EXPORT   USIC0_0_IRQHandler         [WEAK]
+    ExcpHandler   USIC0_0_IRQHandler
-               EXPORT   USIC0_1_IRQHandler         [WEAK]
+    ExcpHandler   USIC0_1_IRQHandler
-               EXPORT   USIC0_2_IRQHandler         [WEAK]
+    ExcpHandler   USIC0_2_IRQHandler
-               EXPORT   USIC0_3_IRQHandler         [WEAK]
+    ExcpHandler   USIC0_3_IRQHandler
-               EXPORT   USIC0_4_IRQHandler         [WEAK]
+    ExcpHandler   USIC0_4_IRQHandler
-               EXPORT   USIC0_5_IRQHandler         [WEAK]
+    ExcpHandler   USIC0_5_IRQHandler
-               EXPORT   USIC1_0_IRQHandler         [WEAK]
+    ExcpHandler   USIC1_0_IRQHandler
-               EXPORT   USIC1_1_IRQHandler         [WEAK]
+    ExcpHandler   USIC1_1_IRQHandler
-               EXPORT   USIC1_2_IRQHandler         [WEAK]
+    ExcpHandler   USIC1_2_IRQHandler
-               EXPORT   USIC1_3_IRQHandler         [WEAK]
+    ExcpHandler   USIC1_3_IRQHandler
-               EXPORT   USIC1_4_IRQHandler         [WEAK]
+    ExcpHandler   USIC1_4_IRQHandler
-               EXPORT   USIC1_5_IRQHandler         [WEAK]
+    ExcpHandler   USIC1_5_IRQHandler
-               EXPORT   USIC2_0_IRQHandler         [WEAK]
+    ExcpHandler   USIC2_0_IRQHandler
-               EXPORT   USIC2_1_IRQHandler         [WEAK]
+    ExcpHandler   USIC2_1_IRQHandler
-               EXPORT   USIC2_2_IRQHandler         [WEAK]
+    ExcpHandler   USIC2_2_IRQHandler
-               EXPORT   USIC2_3_IRQHandler         [WEAK]
+    ExcpHandler   USIC2_3_IRQHandler
-               EXPORT   USIC2_4_IRQHandler         [WEAK]
+    ExcpHandler   USIC2_4_IRQHandler
-               EXPORT   USIC2_5_IRQHandler         [WEAK]
+    ExcpHandler   USIC2_5_IRQHandler
-               EXPORT   LEDTS0_0_IRQHandler        [WEAK]
+    ExcpHandler   LEDTS0_0_IRQHandler
-               EXPORT   FCE0_0_IRQHandler          [WEAK]
+    ExcpHandler   FCE0_0_IRQHandler
-               EXPORT   GPDMA0_0_IRQHandler        [WEAK]
+    ExcpHandler   GPDMA0_0_IRQHandler
-               EXPORT   SDMMC0_0_IRQHandler        [WEAK]
+    ExcpHandler   SDMMC0_0_IRQHandler
-               EXPORT   USB0_0_IRQHandler          [WEAK]
+    ExcpHandler   USB0_0_IRQHandler
-               EXPORT   ETH0_0_IRQHandler          [WEAK]
+    ExcpHandler   ETH0_0_IRQHandler
-               EXPORT   GPDMA1_0_IRQHandler        [WEAK]
+    ExcpHandler   GPDMA1_0_IRQHandler
-
-
-SCU_0_IRQHandler     
-ERU0_0_IRQHandler     
-ERU0_1_IRQHandler     
-ERU0_2_IRQHandler     
-ERU0_3_IRQHandler     
-ERU1_0_IRQHandler     
-ERU1_1_IRQHandler     
-ERU1_2_IRQHandler     
-ERU1_3_IRQHandler     
-PMU0_0_IRQHandler     
-VADC0_C0_0_IRQHandler     
-VADC0_C0_1_IRQHandler     
-VADC0_C0_2_IRQHandler     
-VADC0_C0_3_IRQHandler     
-VADC0_G0_0_IRQHandler     
-VADC0_G0_1_IRQHandler     
-VADC0_G0_2_IRQHandler     
-VADC0_G0_3_IRQHandler     
-VADC0_G1_0_IRQHandler     
-VADC0_G1_1_IRQHandler     
-VADC0_G1_2_IRQHandler     
-VADC0_G1_3_IRQHandler     
-VADC0_G2_0_IRQHandler     
-VADC0_G2_1_IRQHandler     
-VADC0_G2_2_IRQHandler     
-VADC0_G2_3_IRQHandler     
-VADC0_G3_0_IRQHandler     
-VADC0_G3_1_IRQHandler     
-VADC0_G3_2_IRQHandler     
-VADC0_G3_3_IRQHandler     
-DSD0_0_IRQHandler     
-DSD0_1_IRQHandler     
-DSD0_2_IRQHandler     
-DSD0_3_IRQHandler     
-DSD0_4_IRQHandler     
-DSD0_5_IRQHandler     
-DSD0_6_IRQHandler     
-DSD0_7_IRQHandler     
-DAC0_0_IRQHandler     
-DAC0_1_IRQHandler     
-CCU40_0_IRQHandler     
-CCU40_1_IRQHandler     
-CCU40_2_IRQHandler     
-CCU40_3_IRQHandler     
-CCU41_0_IRQHandler     
-CCU41_1_IRQHandler     
-CCU41_2_IRQHandler     
-CCU41_3_IRQHandler     
-CCU42_0_IRQHandler     
-CCU42_1_IRQHandler     
-CCU42_2_IRQHandler     
-CCU42_3_IRQHandler     
-CCU43_0_IRQHandler     
-CCU43_1_IRQHandler     
-CCU43_2_IRQHandler     
-CCU43_3_IRQHandler     
-CCU80_0_IRQHandler     
-CCU80_1_IRQHandler     
-CCU80_2_IRQHandler     
-CCU80_3_IRQHandler     
-CCU81_0_IRQHandler     
-CCU81_1_IRQHandler     
-CCU81_2_IRQHandler     
-CCU81_3_IRQHandler     
-POSIF0_0_IRQHandler     
-POSIF0_1_IRQHandler     
-POSIF1_0_IRQHandler     
-POSIF1_1_IRQHandler     
-CAN0_0_IRQHandler     
-CAN0_1_IRQHandler     
-CAN0_2_IRQHandler     
-CAN0_3_IRQHandler     
-CAN0_4_IRQHandler     
-CAN0_5_IRQHandler     
-CAN0_6_IRQHandler     
-CAN0_7_IRQHandler     
-USIC0_0_IRQHandler     
-USIC0_1_IRQHandler     
-USIC0_2_IRQHandler     
-USIC0_3_IRQHandler     
-USIC0_4_IRQHandler     
-USIC0_5_IRQHandler     
-USIC1_0_IRQHandler     
-USIC1_1_IRQHandler     
-USIC1_2_IRQHandler     
-USIC1_3_IRQHandler     
-USIC1_4_IRQHandler     
-USIC1_5_IRQHandler     
-USIC2_0_IRQHandler     
-USIC2_1_IRQHandler     
-USIC2_2_IRQHandler     
-USIC2_3_IRQHandler     
-USIC2_4_IRQHandler     
-USIC2_5_IRQHandler     
-LEDTS0_0_IRQHandler     
-FCE0_0_IRQHandler     
-GPDMA0_0_IRQHandler     
-SDMMC0_0_IRQHandler     
-USB0_0_IRQHandler     
-ETH0_0_IRQHandler     
-GPDMA1_0_IRQHandler     
-
 
 ;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
 
@@ -517,10 +444,21 @@ GPDMA1_0_IRQHandler
 ;*  This function will be called by the CMSIS SystemInit function.
 ;*  If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
 ;*  which will overule this weak definition
+SystemInit_DAVE3  PROC
+                  EXPORT  SystemInit_DAVE3             [WEAK]
+                  NOP
+                  BX     LR
+                  ENDP
 
-;*SystemInit_DAVE3
+;*  Definition of the default weak DAVE3 function for clock App usage.
-;*  NOP
+;* AllowPLLInitByStartup Handler */
-;*  BX LR
+AllowPLLInitByStartup    PROC
+                  EXPORT  AllowPLLInitByStartup        [WEAK]
+                  MOV    R0,#1
+                  BX     LR
+                  ENDP
+
+                  ALIGN
 
 ;*******************************************************************************
 ; User Stack and Heap initialization
@@ -544,12 +482,10 @@ __user_initial_stackheap
                  LDR     R3, = Stack_Mem
                  BX      LR
 
+                 ALIGN
 
                  ENDIF
 
-				 ALIGN
                  END
 
-;******************* (C) COPYRIGHT 2011 Infineon Techonlogies *****END OF FILE*****
+;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****
-
-

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.c

@@ -0,0 +1,708 @@
+/**************************************************************************//**
+ * @file     system_XMC4200.c
+ * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File
+ *           for the Infineon XMC4000 Device Series
+ * @version  V3.0.1 Alpha
+ * @date     26. September 2012
+ *
+ * @note
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <system_XMC4200.h>
+#include <XMC4200.h>
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock;
+
+/* clock definitions, do not modify! */
+#define SCU_CLOCK_CRYSTAL              	1
+#define SCU_CLOCK_BACK_UP_FACTORY		   	2
+#define SCU_CLOCK_BACK_UP_AUTOMATIC	   	3
+
+
+#define HIB_CLOCK_FOSI					1
+#define HIB_CLOCK_OSCULP				2
+
+
+
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+
+/*--------------------- Watchdog Configuration -------------------------------
+//
+// <e> Watchdog Configuration
+//     <o1.0> Disable Watchdog
+//
+// </e>
+*/
+#define WDT_SETUP               1
+#define WDTENB_nVal             0x00000001
+
+/*--------------------- CLOCK Configuration -------------------------------
+//
+// <e> Main Clock Configuration
+//     <o1.0..1> CPU clock divider
+//                     <0=> fCPU = fSYS
+//                     <1=> fCPU = fSYS / 2
+//     <o2.0..1>  Peripheral Bus clock divider
+//                     <0=> fPB	= fCPU
+//                     <1=> fPB	= fCPU / 2
+//     <o3.0..1>  CCU Bus clock divider
+//                     <0=> fCCU = fCPU
+//                     <1=> fCCU = fCPU / 2
+//
+// </e>
+//
+*/
+
+#define SCU_CLOCK_SETUP               1
+#define	SCU_CPUCLKCR_DIV		0x00000000
+#define	SCU_PBCLKCR_DIV		    0x00000000
+#define	SCU_CCUCLKCR_DIV		0x00000000
+/* not avalible in config wizzard*/
+/*
+* mandatory clock parameters **************************************************
+*
+* source for clock generation
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
+*
+**************************************************************************************/
+// Selection of imput lock for PLL
+/*************************************************************************************/
+#define	SCU_PLL_CLOCK_INPUT	SCU_CLOCK_CRYSTAL
+//#define	SCU_PLL_CLOCK_INPUT	SCU_CLOCK_BACK_UP_FACTORY
+//#define	SCU_PLL_CLOCK_INPUT	SCU_CLOCK_BACK_UP_AUTOMATIC
+
+/*************************************************************************************/
+// Standby clock selection for Backup clock source trimming
+/*************************************************************************************/
+#define	SCU_STANDBY_CLOCK  HIB_CLOCK_OSCULP
+//#define	SCU_STANDBY_CLOCK  HIB_CLOCK_FOSI
+
+/*************************************************************************************/
+// Global clock parameters
+/*************************************************************************************/
+#define CLOCK_FSYS							80000000
+#define	CLOCK_CRYSTAL_FREQUENCY	12000000
+#define	CLOCK_BACK_UP						24000000
+
+/*************************************************************************************/
+/* OSC_HP setup parameters */
+/*************************************************************************************/
+#define	SCU_OSC_HP_MODE	0xF0
+#define	SCU_OSCHPWDGDIV	2
+
+/*************************************************************************************/
+/* MAIN PLL setup parameters */
+/*************************************************************************************/
+//Divider settings for external crystal @ 12 MHz
+/*************************************************************************************/
+#define 	SCU_PLL_K1DIV	1
+#define 	SCU_PLL_K1DIV	1
+#define 	SCU_PLL_K2DIV	5
+#define 	SCU_PLL_PDIV	1
+#define 	SCU_PLL_NDIV	79
+
+/*************************************************************************************/
+//Divider settings for use of backup clock source trimmed
+/*************************************************************************************/
+//#define 	SCU_PLL_K1DIV	1
+//#define 	SCU_PLL_K2DIV	5
+//#define 	SCU_PLL_PDIV	3
+//#define 	SCU_PLL_NDIV	79
+/*************************************************************************************/
+
+
+/*--------------------- USB CLOCK Configuration ---------------------------
+//
+// <e> USB Clock Configuration
+//
+// </e>
+//
+*/
+
+#define SCU_USB_CLOCK_SETUP              0
+/* not avalible in config wizzard*/
+#define 	SCU_USBPLL_PDIV	0
+#define 	SCU_USBPLL_NDIV	31
+#define 	SCU_USBDIV	3
+
+/*--------------------- Flash Wait State Configuration -------------------------------
+//
+// <e> Flash Wait State Configuration
+//     <o1.0..3>   Flash Wait State
+//                     <0=> 3 WS
+//                     <1=> 4 WS
+//                     <2=> 5 WS
+//										 <3=> 6 WS
+// </e>
+//
+*/
+
+#define PMU_FLASH             1
+#define	PMU_FLASH_WS					0x00000000
+
+
+/*--------------------- CLOCKOUT Configuration -------------------------------
+//
+// <e> Clock OUT Configuration
+//     <o1.0..1>   Clockout Source Selection
+//                     <0=> System Clock
+//                     <2=> Divided value of USB PLL output
+//                     <3=> Divided value of PLL Clock
+//     <o2.0..4>   Clockout divider <1-10><#-1>
+//     <o3.0..1>   Clockout Pin Selection
+//                     <0=> P1.15
+//                     <1=> P0.8
+//
+//
+// </e>
+//
+*/
+
+#define SCU_CLOCKOUT_SETUP               0
+#define	SCU_CLOCKOUT_SOURCE		0x00000000
+#define	SCU_CLOCKOUT_DIV		0x00000009
+#define	SCU_CLOCKOUT_PIN		0x00000001
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+#if SCU_CLOCK_SETUP
+uint32_t SystemCoreClock = CLOCK_FSYS;
+#else
+uint32_t SystemCoreClock = CLOCK_BACK_UP;
+#endif
+
+/*----------------------------------------------------------------------------
+  static functions declarations
+ *----------------------------------------------------------------------------*/
+#if (SCU_CLOCK_SETUP == 1)
+static int SystemClockSetup(void);
+#endif
+
+#if (SCU_USB_CLOCK_SETUP == 1)
+static int USBClockSetup(void);
+#endif
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the PLL and update the
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+int temp;
+
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+               (3UL << 11*2)  );               /* set CP11 Full Access */
+#endif
+
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
+
+/* Setup the WDT */
+#if WDT_SETUP
+
+WDT->CTR &= ~WDTENB_nVal;
+
+#endif
+
+
+/* Setup the Flash Wait State */
+#if PMU_FLASH
+temp = FLASH0->FCON;
+temp &= ~FLASH_FCON_WSPFLASH_Msk;
+temp |= PMU_FLASH_WS+3;
+FLASH0->FCON = temp;
+#endif
+
+
+/* Setup the clockout */
+#if SCU_CLOCKOUT_SETUP
+
+SCU_CLK->EXTCLKCR	|= SCU_CLOCKOUT_SOURCE;
+/*set PLL div for clkout */
+SCU_CLK->EXTCLKCR	|= SCU_CLOCKOUT_DIV<<16;
+
+if (SCU_CLOCKOUT_PIN) {
+						PORT0->IOCR8 = 0x00000088;   /*P0.8 --> ALT1 select +  HWSEL */
+					    PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
+					    PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk);  /*set to strong driver */
+						}
+else {
+		PORT1->IOCR12 = 0x88000000;                    /*P1.15--> ALT1 select */
+	    PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk);  /*set to strong driver */
+		}
+
+#endif
+
+
+/* Setup the System clock */
+#if SCU_CLOCK_SETUP
+SystemClockSetup();
+#endif
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
+
+
+/* Setup the USB PL */
+#if SCU_USB_CLOCK_SETUP
+USBClockSetup();
+#endif
+
+
+
+}
+
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  * @note   -
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+unsigned int PDIV;
+unsigned int NDIV;
+unsigned int K2DIV;
+unsigned int long VCO;
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+if (SCU_CLK->SYSCLKCR ==  0x00010000)
+{
+	if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
+		/* check if PLL is locked */
+		/* read back divider settings */
+		 PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
+		 NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
+		 K2DIV  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
+
+		if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
+		/* the selected clock is the Backup clock fofi */
+		VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
+		SystemCoreClock = VCO/K2DIV;
+		/* in case the sysclock div is used */
+		SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+
+		}
+		else
+		{
+		/* the selected clock is the PLL external oscillator */
+		VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
+		SystemCoreClock = VCO/K2DIV;
+		/* in case the sysclock div is used */
+		SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+		}
+
+
+	}
+}
+else
+{
+SystemCoreClock = CLOCK_BACK_UP;
+}
+
+
+}
+
+
+/**
+  * @brief  -
+  * @note   -
+  * @param  None
+  * @retval None
+  */
+#if (SCU_CLOCK_SETUP == 1)
+static int SystemClockSetup(void)
+{
+int temp;
+unsigned int long VCO;
+int stepping_K2DIV;
+
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
+
+/* check if PLL is switched on */
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
+/* enable PLL first */
+  SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
+
+}
+
+/* Enable OSC_HP if not already on*/
+  if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
+  {
+	/********************************************************************************************************************/
+	/*   Use external crystal for PLL clock input                                                                            */
+	/********************************************************************************************************************/
+
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
+	   SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);	 /*enable the OSC_HP*/
+	   /* setup OSC WDG devider */
+	   SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
+	   /* select external OSC as PLL input */
+	   SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
+	   /* restart OSC Watchdog */
+	   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
+
+       /* Timeout for wait loop ~150ms */
+	   /********************************/
+	   SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+	   do
+	   {
+       ;/* wait for ~150ms  */
+	   }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
+
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+	   if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+	   return(0);/* Return Error */
+
+    }
+  }
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
+	{
+	/********************************************************************************************************************/
+	/*   Use factory trimming Back-up clock for PLL clock input                                                                            */
+	/********************************************************************************************************************/
+		/* PLL Back up clock selected */
+		SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+	}
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
+  {
+	/********************************************************************************************************************/
+	/*   Use automatic trimming Back-up clock for PLL clock input                                                                            */
+	/********************************************************************************************************************/
+	/* check for HIB Domain enabled  */
+	if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
+		SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
+
+   /* check for HIB Domain is not in reset state  */
+	if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
+	    SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
+
+			/* PLL Back up clock selected */
+		SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+		if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
+			{
+			/****************************************************************************************************************/
+			/*   Use fOSI as source of the standby clock                                                                             */
+			/****************************************************************************************************************/
+			SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+
+			SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+			for(temp=0;temp<=0xFFFF;temp++);
+
+			SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+			}
+		else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
+			{
+			/****************************************************************************************************************/
+			/*   Use fULP as source of the standby clock                                                                            */
+			/****************************************************************************************************************/
+			/*check OSCUL if running correct*/
+			if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
+				{
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
+
+					SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
+					/*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
+					/* select OSCUL clock for RTC*/
+					SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+					/*enable OSCULP WDG Alarm Enable*/
+					SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+					/*wait now for clock is stable */
+					do
+					{
+					SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+					for(temp=0;temp<=0xFFFF;temp++);
+					}
+					while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
+
+					SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+				}
+			// now OSCULP is running and can be used
+			SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+			while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+
+			SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+			/*TRIAL for delay loop*/
+			for(temp=0;temp<=0xFFFF;temp++);
+
+			SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+			/*TRIAL for delay loop*/
+			for(temp=0;temp<=0xFFFF;temp++);
+
+			}
+  }
+
+	/********************************************************************************************************************/
+	/*   Setup and look the main PLL                                                                                    */
+	/********************************************************************************************************************/
+
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
+	/* Systen is still running from internal clock */
+		   /* select FOFI as system clock */
+		   if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
+
+
+			 /*calulation for stepping*/
+			 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+			 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+					VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+			 stepping_K2DIV = (VCO/24000000)-1;
+			 /* Go to bypass the Main PLL */
+		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
+		   /* disconnect OSC_HP to PLL */
+		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
+		   /* Setup devider settings for main PLL */
+		   SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+		   /* we may have to set OSCDISCDIS */
+		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
+		   /* connect OSC_HP to PLL */
+		   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
+		   /* restart PLL Lock detection */
+		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
+		   /* wait for PLL Lock */
+		   /* setup time out loop */
+	       /* Timeout for wait loo ~150ms */
+		   /********************************/
+		   SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+		   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+		   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+		                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+
+		   while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
+	       SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+
+		   if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
+		   		{
+				/* Go back to the Main PLL */
+				SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
+				}
+				else return(0);
+
+
+	   /*********************************************************
+	   here we need to setup the system clock divider
+	   *********************************************************/
+
+		SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
+		SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
+		SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
+
+
+  		/* Switch system clock to PLL */
+	   SCU_CLK->SYSCLKCR |=  0x00010000;
+
+	   /* we may have to reset OSCDISCDIS */
+	   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
+
+
+		 /*********************************************************/
+		 /* Delay for next K2 step ~50µs */
+		 /*********************************************************/
+		 SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+		 SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+		 SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+										 SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+
+		 while (SysTick->VAL >= 100);								   /* wait for ~50µs  */
+		 SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+		 /*********************************************************/
+
+	   /*********************************************************
+	   here the ramp up of the system clock starts FSys < 60MHz
+	   *********************************************************/
+		if (CLOCK_FSYS > 60000000){
+			 /*calulation for stepping*/
+			 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+			 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+					VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+			 stepping_K2DIV = (VCO/60000000)-1;
+
+			 /* Setup devider settings for main PLL */
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+		 }
+		 else
+		 {
+				/* Setup devider settings for main PLL */
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+		    SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */
+			  return(1);
+		 }
+
+		 /*********************************************************/
+		 /* Delay for next K2 step ~50µs */
+		 /*********************************************************/
+	   SysTick->LOAD  = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+
+	   while (SysTick->VAL >= 100);								   /* wait for ~50µs  */
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+	   /********************************/
+
+   /*********************************************************
+	   here the ramp up of the system clock starts FSys < 90MHz
+	   *********************************************************/
+		if (CLOCK_FSYS > 90000000){
+			 /*calulation for stepping*/
+			 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+			 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+					VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+			 stepping_K2DIV = (VCO/90000000)-1;
+
+			 /* Setup devider settings for main PLL */
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+		 }
+		 else
+		 {
+				/* Setup devider settings for main PLL */
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+	      SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */
+				return(1);
+		 }
+
+		 /*********************************************************/
+		 /* Delay for next K2 step ~50µs */
+		 /*********************************************************/
+	   SysTick->LOAD  = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+
+	   while (SysTick->VAL >= 100);								   /* wait for ~50µs  */
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+	   /********************************/
+
+	   /* Setup devider settings for main PLL */
+	   SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+
+	   SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */
+	}
+ }/* end this weak function enables DAVE3 clock App usage */
+   return(1);
+
+}
+#endif
+
+/**
+  * @brief  -
+  * @note   -
+  * @param  None
+  * @retval None
+  */
+#if (SCU_USB_CLOCK_SETUP == 1)
+static int USBClockSetup(void)
+{
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
+
+/* check if PLL is switched on */
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
+	/* enable PLL first */
+  SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
+}
+
+/* check and if not already running enable OSC_HP */
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
+		 /* check if Main PLL is switched on for OSC WD*/
+		 if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
+			/* enable PLL first */
+  			SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
+		 }
+	   SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);	 /*enable the OSC_HP*/
+	   /* setup OSC WDG devider */
+	   SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
+	   /* restart OSC Watchdog */
+	   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
+
+       /* Timeout for wait loop ~150ms */
+	   /********************************/
+	   SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+	   do
+	   {
+       ;/* wait for ~150ms  */
+	   }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
+
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+	   if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+	   return(0);/* Return Error */
+
+  }
+
+
+/* Setup USB PLL */
+   /* Go to bypass the Main PLL */
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
+   /* disconnect OSC_FI to PLL */
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
+   /* Setup devider settings for main PLL */
+   SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
+   /* Setup USBDIV settings USB clock */
+   SCU_CLK->USBCLKCR = SCU_USBDIV;
+   /* we may have to set OSCDISCDIS */
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
+   /* connect OSC_FI to PLL */
+   SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
+   /* restart PLL Lock detection */
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
+   /* wait for PLL Lock */
+   while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
+
+ }/* end this weak function enables DAVE3 clock App usage */
+   return(1);
+
+}
+#endif
+

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.h

@@ -0,0 +1,72 @@
+/**************************************************************************//**
+ * @file     system_XMC4200.h
+ * @brief    Header file for the XMC4200-Series systeminit
+ *           
+ * @version  V1.0
+ * @date     27. August 2012
+ *
+ * @note
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.  
+ * This file can be freely distributed within development tools that are supporting such microcontrollers. 
+
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_XMC4200_H
+#define __SYSTEM_XMC4200_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+extern void SystemInit (void);
+
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/* this weak function enables DAVE3 clock App usage */		
+extern uint32_t AllowPLLInitByStartup(void);		
+				
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.c

@@ -0,0 +1,707 @@
+/**************************************************************************//**
+ * @file     system_XMC4400.c
+ * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File
+ *           for the Infineon XMC4500 Device Series
+ * @version  V3.0.1 Alpha
+ * @date     17. September 2012
+ *
+ * @note
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <system_XMC4400.h>
+#include <XMC4400.h>
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock;
+
+/* clock definitions, do not modify! */
+#define SCU_CLOCK_CRYSTAL              	1
+#define SCU_CLOCK_BACK_UP_FACTORY		   	2
+#define SCU_CLOCK_BACK_UP_AUTOMATIC	   	3
+
+
+#define HIB_CLOCK_FOSI					1
+#define HIB_CLOCK_OSCULP				2
+
+
+
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+
+/*--------------------- Watchdog Configuration -------------------------------
+//
+// <e> Watchdog Configuration
+//     <o1.0> Disable Watchdog
+//
+// </e>
+*/
+#define WDT_SETUP               1
+#define WDTENB_nVal             0x00000001
+
+/*--------------------- CLOCK Configuration -------------------------------
+//
+// <e> Main Clock Configuration
+//     <o1.0..1> CPU clock divider
+//                     <0=> fCPU = fSYS
+//                     <1=> fCPU = fSYS / 2
+//     <o2.0..1>  Peripheral Bus clock divider
+//                     <0=> fPB	= fCPU
+//                     <1=> fPB	= fCPU / 2
+//     <o3.0..1>  CCU Bus clock divider
+//                     <0=> fCCU = fCPU
+//                     <1=> fCCU = fCPU / 2
+//
+// </e>
+//
+*/
+
+#define SCU_CLOCK_SETUP               1
+#define	SCU_CPUCLKCR_DIV		0x00000000
+#define	SCU_PBCLKCR_DIV		    0x00000000
+#define	SCU_CCUCLKCR_DIV		0x00000000
+/* not avalible in config wizzard*/
+/*
+* mandatory clock parameters **************************************************
+*
+* source for clock generation
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
+*
+**************************************************************************************/
+// Selection of imput lock for PLL
+/*************************************************************************************/
+#define	SCU_PLL_CLOCK_INPUT	SCU_CLOCK_CRYSTAL
+//#define	SCU_PLL_CLOCK_INPUT	SCU_CLOCK_BACK_UP_FACTORY
+//#define	SCU_PLL_CLOCK_INPUT	SCU_CLOCK_BACK_UP_AUTOMATIC
+
+/*************************************************************************************/
+// Standby clock selection for Backup clock source trimming
+/*************************************************************************************/
+#define	SCU_STANDBY_CLOCK  HIB_CLOCK_OSCULP
+//#define	SCU_STANDBY_CLOCK  HIB_CLOCK_FOSI
+
+/*************************************************************************************/
+// Global clock parameters
+/*************************************************************************************/
+#define CLOCK_FSYS							120000000
+#define	CLOCK_CRYSTAL_FREQUENCY	12000000
+#define	CLOCK_BACK_UP						24000000
+
+/*************************************************************************************/
+/* OSC_HP setup parameters */
+/*************************************************************************************/
+#define	SCU_OSC_HP_MODE	0xF0
+#define	SCU_OSCHPWDGDIV	2
+
+/*************************************************************************************/
+/* MAIN PLL setup parameters */
+/*************************************************************************************/
+//Divider settings for external crystal @ 12 MHz
+/*************************************************************************************/
+#define 	SCU_PLL_K1DIV	1
+#define 	SCU_PLL_K2DIV	3
+#define 	SCU_PLL_PDIV	1
+#define 	SCU_PLL_NDIV	79
+
+/*************************************************************************************/
+//Divider settings for use of backup clock source trimmed
+/*************************************************************************************/
+//#define 	SCU_PLL_K1DIV	1
+//#define 	SCU_PLL_K2DIV	3
+//#define 	SCU_PLL_PDIV	3
+//#define 	SCU_PLL_NDIV	79
+/*************************************************************************************/
+
+
+/*--------------------- USB CLOCK Configuration ---------------------------
+//
+// <e> USB Clock Configuration
+//
+// </e>
+//
+*/
+
+#define SCU_USB_CLOCK_SETUP              0
+/* not avalible in config wizzard*/
+#define 	SCU_USBPLL_PDIV	0
+#define 	SCU_USBPLL_NDIV	31
+#define 	SCU_USBDIV	3
+
+/*--------------------- Flash Wait State Configuration -------------------------------
+//
+// <e> Flash Wait State Configuration
+//     <o1.0..3>   Flash Wait State
+//                     <0=> 3 WS
+//                     <1=> 4 WS
+//                     <2=> 5 WS
+//										 <3=> 6 WS
+// </e>
+//
+*/
+
+#define PMU_FLASH             1
+#define	PMU_FLASH_WS					0x00000000
+
+
+/*--------------------- CLOCKOUT Configuration -------------------------------
+//
+// <e> Clock OUT Configuration
+//     <o1.0..1>   Clockout Source Selection
+//                     <0=> System Clock
+//                     <2=> Divided value of USB PLL output
+//                     <3=> Divided value of PLL Clock
+//     <o2.0..4>   Clockout divider <1-10><#-1>
+//     <o3.0..1>   Clockout Pin Selection
+//                     <0=> P1.15
+//                     <1=> P0.8
+//
+//
+// </e>
+//
+*/
+
+#define SCU_CLOCKOUT_SETUP               0
+#define	SCU_CLOCKOUT_SOURCE		0x00000000
+#define	SCU_CLOCKOUT_DIV		0x00000009
+#define	SCU_CLOCKOUT_PIN		0x00000001
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+#if SCU_CLOCK_SETUP
+uint32_t SystemCoreClock = CLOCK_FSYS;
+#else
+uint32_t SystemCoreClock = CLOCK_BACK_UP;
+#endif
+
+/*----------------------------------------------------------------------------
+  static functions declarations
+ *----------------------------------------------------------------------------*/
+#if (SCU_CLOCK_SETUP == 1)
+static int SystemClockSetup(void);
+#endif
+
+#if (SCU_USB_CLOCK_SETUP == 1)
+static int USBClockSetup(void);
+#endif
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the PLL and update the
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+int temp;
+
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+               (3UL << 11*2)  );               /* set CP11 Full Access */
+#endif
+
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
+
+/* Setup the WDT */
+#if WDT_SETUP
+
+WDT->CTR &= ~WDTENB_nVal;
+
+#endif
+
+
+/* Setup the Flash Wait State */
+#if PMU_FLASH
+temp = FLASH0->FCON;
+temp &= ~FLASH_FCON_WSPFLASH_Msk;
+temp |= PMU_FLASH_WS+3;
+FLASH0->FCON = temp;
+#endif
+
+
+/* Setup the clockout */
+#if SCU_CLOCKOUT_SETUP
+
+SCU_CLK->EXTCLKCR	|= SCU_CLOCKOUT_SOURCE;
+/*set PLL div for clkout */
+SCU_CLK->EXTCLKCR	|= SCU_CLOCKOUT_DIV<<16;
+
+if (SCU_CLOCKOUT_PIN) {
+						PORT0->IOCR8 = 0x00000088;   /*P0.8 --> ALT1 select +  HWSEL */
+					    PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
+					    PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk);  /*set to strong driver */
+						}
+else {
+		PORT1->IOCR12 = 0x88000000;                    /*P1.15--> ALT1 select */
+	    PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk);  /*set to strong driver */
+		}
+
+#endif
+
+
+/* Setup the System clock */
+#if SCU_CLOCK_SETUP
+SystemClockSetup();
+#endif
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
+
+
+/* Setup the USB PL */
+#if SCU_USB_CLOCK_SETUP
+USBClockSetup();
+#endif
+
+
+
+}
+
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  * @note   -
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+unsigned int PDIV;
+unsigned int NDIV;
+unsigned int K2DIV;
+unsigned int long VCO;
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+if (SCU_CLK->SYSCLKCR ==  0x00010000)
+{
+	if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
+		/* check if PLL is locked */
+		/* read back divider settings */
+		 PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
+		 NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
+		 K2DIV  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
+
+		if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
+		/* the selected clock is the Backup clock fofi */
+		VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
+		SystemCoreClock = VCO/K2DIV;
+		/* in case the sysclock div is used */
+		SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+
+		}
+		else
+		{
+		/* the selected clock is the PLL external oscillator */
+		VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
+		SystemCoreClock = VCO/K2DIV;
+		/* in case the sysclock div is used */
+		SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+		}
+
+
+	}
+}
+else
+{
+SystemCoreClock = CLOCK_BACK_UP;
+}
+
+
+}
+
+
+/**
+  * @brief  -
+  * @note   -
+  * @param  None
+  * @retval None
+  */
+#if (SCU_CLOCK_SETUP == 1)
+static int SystemClockSetup(void)
+{
+int temp;
+unsigned int long VCO;
+int stepping_K2DIV;
+
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
+
+/* check if PLL is switched on */
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
+/* enable PLL first */
+  SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
+
+}
+
+/* Enable OSC_HP if not already on*/
+  if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
+  {
+	/********************************************************************************************************************/
+	/*   Use external crystal for PLL clock input                                                                            */
+	/********************************************************************************************************************/
+
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
+	   SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);	 /*enable the OSC_HP*/
+	   /* setup OSC WDG devider */
+	   SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
+	   /* select external OSC as PLL input */
+	   SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
+	   /* restart OSC Watchdog */
+	   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
+
+       /* Timeout for wait loop ~150ms */
+	   /********************************/
+	   SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+	   do
+	   {
+       ;/* wait for ~150ms  */
+	   }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
+
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+	   if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+	   return(0);/* Return Error */
+
+    }
+  }
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
+	{
+	/********************************************************************************************************************/
+	/*   Use factory trimming Back-up clock for PLL clock input                                                                            */
+	/********************************************************************************************************************/
+		/* PLL Back up clock selected */
+		SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+	}
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
+  {
+	/********************************************************************************************************************/
+	/*   Use automatic trimming Back-up clock for PLL clock input                                                                            */
+	/********************************************************************************************************************/
+	/* check for HIB Domain enabled  */
+	if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
+		SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
+
+   /* check for HIB Domain is not in reset state  */
+	if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
+	    SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
+
+			/* PLL Back up clock selected */
+		SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+		if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
+			{
+			/****************************************************************************************************************/
+			/*   Use fOSI as source of the standby clock                                                                             */
+			/****************************************************************************************************************/
+			SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+
+			SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+			for(temp=0;temp<=0xFFFF;temp++);
+
+			SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+			}
+		else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
+			{
+			/****************************************************************************************************************/
+			/*   Use fULP as source of the standby clock                                                                            */
+			/****************************************************************************************************************/
+			/*check OSCUL if running correct*/
+			if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
+				{
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
+
+					SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
+					/*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
+					/* select OSCUL clock for RTC*/
+					SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+					/*enable OSCULP WDG Alarm Enable*/
+					SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+					/*wait now for clock is stable */
+					do
+					{
+					SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+					for(temp=0;temp<=0xFFFF;temp++);
+					}
+					while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
+
+					SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+					while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+				}
+			// now OSCULP is running and can be used
+			SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+			while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+
+			SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+			/*TRIAL for delay loop*/
+			for(temp=0;temp<=0xFFFF;temp++);
+
+			SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+			/*TRIAL for delay loop*/
+			for(temp=0;temp<=0xFFFF;temp++);
+
+			}
+  }
+
+	/********************************************************************************************************************/
+	/*   Setup and look the main PLL                                                                                    */
+	/********************************************************************************************************************/
+
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
+	/* Systen is still running from internal clock */
+		   /* select FOFI as system clock */
+		   if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
+
+
+			 /*calulation for stepping*/
+			 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+			 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+					VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+			 stepping_K2DIV = (VCO/24000000)-1;
+			 /* Go to bypass the Main PLL */
+		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
+		   /* disconnect OSC_HP to PLL */
+		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
+		   /* Setup devider settings for main PLL */
+		   SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+		   /* we may have to set OSCDISCDIS */
+		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
+		   /* connect OSC_HP to PLL */
+		   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
+		   /* restart PLL Lock detection */
+		   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
+		   /* wait for PLL Lock */
+		   /* setup time out loop */
+	       /* Timeout for wait loo ~150ms */
+		   /********************************/
+		   SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+		   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+		   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+		                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+
+		   while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
+	       SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+
+		   if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
+		   		{
+				/* Go back to the Main PLL */
+				SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
+				}
+				else return(0);
+
+
+	   /*********************************************************
+	   here we need to setup the system clock divider
+	   *********************************************************/
+
+		SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
+		SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
+		SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
+
+
+  		/* Switch system clock to PLL */
+	   SCU_CLK->SYSCLKCR |=  0x00010000;
+
+	   /* we may have to reset OSCDISCDIS */
+	   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
+
+
+		 /*********************************************************/
+		 /* Delay for next K2 step ~50µs */
+		 /*********************************************************/
+		 SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+		 SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+		 SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+										 SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+
+		 while (SysTick->VAL >= 100);								   /* wait for ~50µs  */
+		 SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+		 /*********************************************************/
+
+	   /*********************************************************
+	   here the ramp up of the system clock starts FSys < 60MHz
+	   *********************************************************/
+		if (CLOCK_FSYS > 60000000){
+			 /*calulation for stepping*/
+			 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+			 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+					VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+			 stepping_K2DIV = (VCO/60000000)-1;
+
+			 /* Setup devider settings for main PLL */
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+		 }
+		 else
+		 {
+				/* Setup devider settings for main PLL */
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+		    SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */
+			  return(1);
+		 }
+
+		 /*********************************************************/
+		 /* Delay for next K2 step ~50µs */
+		 /*********************************************************/
+	   SysTick->LOAD  = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+
+	   while (SysTick->VAL >= 100);								   /* wait for ~50µs  */
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+	   /********************************/
+
+   /*********************************************************
+	   here the ramp up of the system clock starts FSys < 90MHz
+	   *********************************************************/
+		if (CLOCK_FSYS > 90000000){
+			 /*calulation for stepping*/
+			 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+			 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+					VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+			 stepping_K2DIV = (VCO/90000000)-1;
+
+			 /* Setup devider settings for main PLL */
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+		 }
+		 else
+		 {
+				/* Setup devider settings for main PLL */
+				SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+	      SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */
+				return(1);
+		 }
+
+		 /*********************************************************/
+		 /* Delay for next K2 step ~50µs */
+		 /*********************************************************/
+	   SysTick->LOAD  = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+
+	   while (SysTick->VAL >= 100);								   /* wait for ~50µs  */
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+	   /********************************/
+
+	   /* Setup devider settings for main PLL */
+	   SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+
+	   SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */
+	}
+ }/* end this weak function enables DAVE3 clock App usage */
+   return(1);
+
+}
+#endif
+
+/**
+  * @brief  -
+  * @note   -
+  * @param  None
+  * @retval None
+  */
+#if (SCU_USB_CLOCK_SETUP == 1)
+static int USBClockSetup(void)
+{
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
+
+/* check if PLL is switched on */
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
+	/* enable PLL first */
+  SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
+}
+
+/* check and if not already running enable OSC_HP */
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
+		 /* check if Main PLL is switched on for OSC WD*/
+		 if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
+			/* enable PLL first */
+  			SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
+		 }
+	   SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);	 /*enable the OSC_HP*/
+	   /* setup OSC WDG devider */
+	   SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
+	   /* restart OSC Watchdog */
+	   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
+
+       /* Timeout for wait loop ~150ms */
+	   /********************************/
+	   SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+	   SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */
+	   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+	                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+	   do
+	   {
+       ;/* wait for ~150ms  */
+	   }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
+
+	   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */
+	   if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+	   return(0);/* Return Error */
+
+  }
+
+
+/* Setup USB PLL */
+   /* Go to bypass the Main PLL */
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
+   /* disconnect OSC_FI to PLL */
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
+   /* Setup devider settings for main PLL */
+   SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
+   /* Setup USBDIV settings USB clock */
+   SCU_CLK->USBCLKCR = SCU_USBDIV;
+   /* we may have to set OSCDISCDIS */
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
+   /* connect OSC_FI to PLL */
+   SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
+   /* restart PLL Lock detection */
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
+   /* wait for PLL Lock */
+   while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
+
+ }/* end this weak function enables DAVE3 clock App usage */
+   return(1);
+
+}
+#endif
+

FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.h

@@ -0,0 +1,72 @@
+/**************************************************************************//**
+ * @file     system_XMC4400.h
+ * @brief    Header file for the XMC4400-Series systeminit
+ *           
+ * @version  V1.0
+ * @date     17. August 2012
+ *
+ * @note
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.  
+ * This file can be freely distributed within development tools that are supporting such microcontrollers. 
+
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_XMC4400_H
+#define __SYSTEM_XMC4400_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+extern void SystemInit (void);
+
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/* this weak function enables DAVE3 clock App usage */		
+extern uint32_t AllowPLLInitByStartup(void);		
+				
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif