mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
Code review suggestions
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
parent
ea60cd130a
commit
b7c0fc1c8f
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@ -65,9 +65,9 @@
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#define tskMPU_REGION_EXECUTE_NEVER ( 1U << 2U )
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#define tskMPU_REGION_NORMAL_MEMORY ( 1U << 3U )
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#define tskMPU_REGION_DEVICE_MEMORY ( 1U << 4U )
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#if ( portHAS_ARMV8_1_M_EXTENSION == 1 )
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#if ( portARMV8M_MINOR_VERSION >= 1 )
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#define tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ( 1U << 5U )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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#endif /* portARMV8M_MINOR_VERSION >= 1 */
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/* MPU region permissions stored in MPU settings to
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* authorize access requests. */
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@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#if ( portARMV8M_MINOR_VERSION >= 1 )
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/* Enable Privileged eXecute Never MPU attribute for the selected memory
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* region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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#endif /* portARMV8M_MINOR_VERSION >= 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
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/* Enable MPU. */
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#define portMPU_ENABLE_BIT ( 1UL << 0UL )
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/* Expected value of the portMPU_TYPE register. */
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/* Expected value of the portMPU_TYPE register. */
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#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
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/* Extract first address of the MPU region as encoded in the
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@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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#if ( portARMV8M_MINOR_VERSION >= 1 )
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{
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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}
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#endif /* portARMV8M_MINOR_VERSION >= 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M35P"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -55,7 +55,7 @@
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*/
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#define portARCH_NAME "Cortex-M55"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 1
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -55,7 +55,7 @@
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*/
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#define portARCH_NAME "Cortex-M85"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 1
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M35P"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -55,7 +55,7 @@
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*/
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#define portARCH_NAME "Cortex-M55"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 1
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -55,7 +55,7 @@
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*/
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#define portARCH_NAME "Cortex-M85"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 1
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#if ( portARMV8M_MINOR_VERSION >= 1 )
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/* Enable Privileged eXecute Never MPU attribute for the selected memory
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* region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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#endif /* portARMV8M_MINOR_VERSION >= 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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/* Enable MPU. */
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#define portMPU_ENABLE_BIT ( 1UL << 0UL )
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/* Expected value of the portMPU_TYPE register. */
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/* Expected value of the portMPU_TYPE register. */
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#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
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/* Extract first address of the MPU region as encoded in the
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@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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#if ( portARMV8M_MINOR_VERSION >= 1 )
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{
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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}
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#endif /* portARMV8M_MINOR_VERSION >= 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#if ( portARMV8M_MINOR_VERSION >= 1 )
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/* Enable Privileged eXecute Never MPU attribute for the selected memory
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* region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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#endif /* portARMV8M_MINOR_VERSION >= 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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/* Enable MPU. */
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#define portMPU_ENABLE_BIT ( 1UL << 0UL )
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/* Expected value of the portMPU_TYPE register. */
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/* Expected value of the portMPU_TYPE register. */
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#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
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/* Extract first address of the MPU region as encoded in the
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@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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#if ( portARMV8M_MINOR_VERSION >= 1 )
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{
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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}
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#endif /* portARMV8M_MINOR_VERSION >= 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#if ( portARMV8M_MINOR_VERSION >= 1 )
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/* Enable Privileged eXecute Never MPU attribute for the selected memory
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* region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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#endif /* portARMV8M_MINOR_VERSION >= 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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/* Enable MPU. */
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#define portMPU_ENABLE_BIT ( 1UL << 0UL )
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/* Expected value of the portMPU_TYPE register. */
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/* Expected value of the portMPU_TYPE register. */
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#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
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/* Extract first address of the MPU region as encoded in the
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@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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#if ( portARMV8M_MINOR_VERSION >= 1 )
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{
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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}
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#endif /* portARMV8M_MINOR_VERSION >= 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#if ( portARMV8M_MINOR_VERSION >= 1 )
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/* Enable Privileged eXecute Never MPU attribute for the selected memory
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* region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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#endif /* portARMV8M_MINOR_VERSION >= 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
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/* Enable MPU. */
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#define portMPU_ENABLE_BIT ( 1UL << 0UL )
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/* Expected value of the portMPU_TYPE register. */
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/* Expected value of the portMPU_TYPE register. */
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#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
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/* Extract first address of the MPU region as encoded in the
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@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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#if ( portARMV8M_MINOR_VERSION >= 1 )
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{
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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}
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#endif /* portARMV8M_MINOR_VERSION >= 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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@ -50,7 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -50,7 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -50,7 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -55,7 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -55,7 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -55,7 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -55,7 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -50,7 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -50,7 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -50,7 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -50,7 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -50,7 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -50,7 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -55,7 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -55,7 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -55,7 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,10 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
@ -236,7 +237,7 @@ typedef void ( * portISR_t )( void );
|
|||
/* Enable MPU. */
|
||||
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
|
||||
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
/* Expected value of the portMPU_TYPE register. */
|
||||
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
|
@ -1886,12 +1887,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
|
|
|
@ -55,7 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
Loading…
Reference in a new issue