mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 09:38:32 -04:00
Add AVR32 port and demo files.
This commit is contained in:
Richard Barry
parent
4c3a1e29e0
commit
b727359f1b
52 changed files with 10299 additions and 0 deletions
216
Demo/AVR32_UC3/DRIVERS/GPIO/gpio.c
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216
Demo/AVR32_UC3/DRIVERS/GPIO/gpio.c
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@ -0,0 +1,216 @@
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/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief GPIO driver for AVR32 UC3.
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*
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* This file defines a useful set of functions for the GPIO.
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*
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* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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* - Supported devices: All AVR32 devices with a PWM module can be used.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support email: avr32@atmel.com
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*
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*****************************************************************************/
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/* Copyright (c) 2007, Atmel Corporation All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
|
||||
*
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||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
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||||
*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of ATMEL may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "gpio.h"
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//! GPIO module instance.
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#define GPIO AVR32_GPIO
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int gpio_enable_module(avr32_gpiomap_t gpiomap, int size)
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{
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int i,status=GPIO_SUCCESS;
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for(i=0; i<size; i++) {
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status |= gpio_enable_module_pin(**gpiomap, *(*gpiomap+1) );
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gpiomap++;
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}
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return status;
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}
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int gpio_enable_module_pin(int pin, int function)
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{
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volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];
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// Enable the correct function
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switch(function)
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{
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case 0: // A function
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gpio_port->pmr0c = (1<<(pin%32));
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gpio_port->pmr1c = (1<<(pin%32));
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break;
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case 1: // B function
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gpio_port->pmr0s = (1<<(pin%32));
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gpio_port->pmr1c = (1<<(pin%32));
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break;
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case 2: // C function
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gpio_port->pmr0c = (1<<(pin%32));
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gpio_port->pmr1s = (1<<(pin%32));
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break;
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default:
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return GPIO_INVALID_ARGUMENT;
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}
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// Disable gpio control
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gpio_port->gperc = (1<<(pin%32));
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return GPIO_SUCCESS;
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}
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void gpio_enable_gpio(avr32_gpiomap_t gpiomap, int size)
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{
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int i;
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for(i=0; i<size; i++){
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gpio_enable_gpio_pin(**gpiomap);
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gpiomap++;
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}
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}
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void gpio_enable_gpio_pin(int pin)
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{
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volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];
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gpio_port->gpers = 1<<(pin%32);
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}
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void gpio_enable_gpio_glitch_filter(int pin)
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{
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volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];
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gpio_port->gfers = 1<<(pin%32);
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}
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void gpio_disable_gpio_glitch_filter(int pin)
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{
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volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];
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gpio_port->gferc = 1<<(pin%32);
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}
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void gpio_disable_module(avr32_gpiomap_t gpiomap, int size)
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{
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int i;
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for(i=0; i<size; i++){
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gpio_disable_gpio_pin(**gpiomap);
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gpiomap++;
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}
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}
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void gpio_disable_gpio_pin(int pin)
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{
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volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];
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gpio_port->gperc = 1<<(pin%32);
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}
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int gpio_pin_value(int pin)
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{
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volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];
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return (gpio_port->pvr >>(pin%32))&1;
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}
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void gpio_set_gpio_pin(int pin)
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{
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// The port holding that pin.
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volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];
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gpio_port->ovrs = (1<<(pin%32)); // Value to be driven on the I/O line: 1
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gpio_port->oders = (1<<(pin%32)); // The GPIO output driver is enabled for that pin.
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gpio_port->gpers = (1<<(pin%32)); // The GPIO module controls that pin.
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}
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void gpio_clr_gpio_pin(int pin)
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{
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volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; // The port holding that pin.
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gpio_port->ovrc = (1<<(pin%32)); // Value to be driven on the I/O line: 0
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gpio_port->oders = (1<<(pin%32)); // The GPIO output driver is enabled for that pin.
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gpio_port->gpers = (1<<(pin%32)); // The GPIO module controls that pin.
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}
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void gpio_tgl_gpio_pin(int pin)
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{
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volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; // The port holding that pin.
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gpio_port->ovrt = (1<<(pin%32)); // Toggle the I/O line.
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gpio_port->oders = (1<<(pin%32)); // The GPIO output driver is enabled for that pin.
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gpio_port->gpers = (1<<(pin%32)); // The GPIO module controls that pin.
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}
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void gpio_cfg_int_gpio_pin(int pin, int level)
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{
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volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; // The port holding that pin.
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gpio_port->gpers = 1<<(pin%32); // GPIO controller enable
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gpio_port->gfers = 1<<(pin%32); // GPIO glitch filter enable
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switch (level)
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{
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case GPIO_RISING_EDGE:
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{
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// mode rising edge
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gpio_port->imr0s = 1<<(pin%32);
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gpio_port->imr1c = 1<<(pin%32);
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break;
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}
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case GPIO_FALLING_EDGE:
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{
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// mode falling edge
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gpio_port->imr0c = 1<<(pin%32);
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gpio_port->imr1s = 1<<(pin%32);
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break;
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}
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default :
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{
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// mode pin change
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gpio_port->imr0c = 1<<(pin%32);
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gpio_port->imr1c = 1<<(pin%32);
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break;
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}
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}
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gpio_port->iers = 1<<(pin%32); // GPIO interrupt enable
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}
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195
Demo/AVR32_UC3/DRIVERS/GPIO/gpio.h
Normal file
195
Demo/AVR32_UC3/DRIVERS/GPIO/gpio.h
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@ -0,0 +1,195 @@
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/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief GPIO header for AVR32 UC3.
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*
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* This file contains basic GPIO driver functions.
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*
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* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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* - Supported devices: All AVR32 devices with a GPIO module can be used.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support email: avr32@atmel.com
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*
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*****************************************************************************/
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/* Copyright (c) 2007, Atmel Corporation All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
||||
*
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||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
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||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _GPIO_H_
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#define _GPIO_H_
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#if __GNUC__
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# include <avr32/io.h>
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#elif __ICCAVR32__
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# include <avr32/iouc3a0512.h>
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#else
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# error Unknown compiler
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#endif
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/*! \name General GPIO API defines
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* These values are returned by the GPIO API:
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*/
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//! @{
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#define GPIO_SUCCESS 0 //!< Function successfully completed
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#define GPIO_FAILURE -1 //!< Function did not successfully complete for some unspecified reason
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#define GPIO_INVALID_ARGUMENT 1 //!< Input paramters are out of range
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//! @}
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/*! \name Interrupt configuration defines
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* Configure the method used to trigger the interrupt:
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*/
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//! @{
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#define GPIO_RISING_EDGE 1 //!< configure IT upon Rising Edge
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#define GPIO_FALLING_EDGE 2 //!< configure IT upon Falling Edge
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#define GPIO_INPUT_CHANGE 3 //!< configure IT upon Pin Change
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//! @}
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/*!
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* A type definitions of pins and module connectivity.
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* First column is the pin number, the second is gpio connectivity.
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*/
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typedef char avr32_gpiomap_t[][2];
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/*!
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* \brief Enable a module pin for a given set of pins and respective modules.
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*
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* \param gpiomap A list of pins and pio connectivity
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* \param size The number of pins in \a gpiomap
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* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT
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*/
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extern int gpio_enable_module(avr32_gpiomap_t gpiomap, int size);
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/*!
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* \brief Enable a special module (function) for a pin (pin number).
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*
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* \param pin The pin number
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* \param function The pin function
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* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT
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*/
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extern int gpio_enable_module_pin(int pin, int function);
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/*!
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* \brief Enable pins of a module according gpiomap.
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*
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* \param gpiomap The pin map
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* \param size The number of pins in \a gpiomap
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*/
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extern void gpio_enable_gpio(avr32_gpiomap_t gpiomap, int size);
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/*!
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* \brief Enable the GPIO module to control the pin.
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*
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* \param pin The pin number
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*/
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extern void gpio_enable_gpio_pin(int pin);
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/*!
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* \brief Enable the GPIO glitch filter.
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*
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* When the glitch filter is enabled, a
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* glitch with duration of less than 1 clock cycle is automatically rejected, while a pulse with duration
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* of 2 clock cycles or more is accepted. For pulse durations between 1 clock cycle and 2 clock
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* cycles, the pulse may or may not be taken into account, depending on the precise timing of its
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* occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 clock cycles, whereas for
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* a glitch to be reliably filtered out, its duration must not exceed 1 clock cycle. The filter introduces
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* 2 clock cycles latency.
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*
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* \param pin The pin number
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* \return \ref GPIO_SUCCESS
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*/
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extern void gpio_enable_gpio_glitch_filter(int pin);
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/*!
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* \brief Disable the GPIO glitch filter.
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*
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* \param pin The pin number
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*/
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extern void gpio_disable_gpio_glitch_filter(int pin);
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/*!
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* \brief Return the pin value
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*
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* \param pin The pin number
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* \return pin value
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*/
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extern int gpio_pin_value(int pin);
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/*!
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* \brief Disable the GPIO module to control a set of pins according to gpiomap.
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*
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* \param gpiomap The pin map
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* \param size The number of pins in \a gpiomap
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*/
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extern void gpio_disable_module(avr32_gpiomap_t gpiomap, int size);
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/*!
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* \brief Disable the GPIO module to control the pin.
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*
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* \param pin The pin number
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*/
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extern void gpio_disable_gpio_pin(int pin);
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/*!
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* \brief Configure a pin to generate IT
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*
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* \param pin GPIO pin number to configure.
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* \param level level to configure (\ref GPIO_RISING_EDGE, \ref GPIO_FALLING_EDGE, \ref GPIO_INPUT_CHANGE).
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*/
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extern void gpio_cfg_int_gpio_pin(int pin, int level);
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/*!
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* \brief Drive a gpio pin value to 1.
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*
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* \param pin The pin number
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*/
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extern void gpio_set_gpio_pin(int pin);
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/*!
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* \brief Drive a gpio pin value to 0.
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*
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* \param pin The pin number
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*/
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extern void gpio_clr_gpio_pin(int pin);
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/*!
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* \brief This function toggle a gpio pin value.
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*
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* \param pin The pin number
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*/
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extern void gpio_tgl_gpio_pin(int pin);
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#endif // _GPIO_H_
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201
Demo/AVR32_UC3/DRIVERS/INTC/intc.c
Normal file
201
Demo/AVR32_UC3/DRIVERS/INTC/intc.c
Normal file
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@ -0,0 +1,201 @@
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/*This file is prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
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*
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* \brief INTC driver for AVR32 UC3.
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*
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* AVR32 Interrupt Controller driver module.
|
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*
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||||
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
|
||||
* - Supported devices: All AVR32 devices with an INTC module can be used.
|
||||
* - AppNote:
|
||||
*
|
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* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#if __GNUC__
|
||||
# include <avr32/io.h>
|
||||
#elif __ICCAVR32__
|
||||
# include <avr32/iouc3a0512.h>
|
||||
#else
|
||||
# error Unknown compiler
|
||||
#endif
|
||||
|
||||
#include "compiler.h"
|
||||
#include "preprocessor.h"
|
||||
#include "intc.h"
|
||||
|
||||
|
||||
//! Values to store in the interrupt priority registers for the various interrupt priority levels.
|
||||
extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];
|
||||
|
||||
//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.
|
||||
//! Each line handler table contains a set of pointers to interrupt handlers.
|
||||
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
|
||||
static volatile __int_handler _int_line_handler_table_##GRP[AVR32_INTC_NUM_IRQS_PER_GRP##GRP];
|
||||
MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
|
||||
#undef DECL_INT_LINE_HANDLER_TABLE
|
||||
|
||||
//! Table containing for each interrupt group the number of interrupt request
|
||||
//! lines and a pointer to the table of interrupt line handlers.
|
||||
static const struct
|
||||
{
|
||||
unsigned int num_irqs;
|
||||
volatile __int_handler *_int_line_handler_table;
|
||||
} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
|
||||
{
|
||||
#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
|
||||
{AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
|
||||
MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
|
||||
#undef INSERT_INT_LINE_HANDLER_TABLE
|
||||
};
|
||||
|
||||
|
||||
/*! \brief Default interrupt handler.
|
||||
*
|
||||
* \note Taken and adapted from Newlib.
|
||||
*/
|
||||
#if __GNUC__
|
||||
__attribute__((__interrupt__))
|
||||
#elif __ICCAVR32__
|
||||
__interrupt
|
||||
#endif
|
||||
static void _unhandled_interrupt(void)
|
||||
{
|
||||
// Catch unregistered interrupts.
|
||||
while (TRUE);
|
||||
}
|
||||
|
||||
|
||||
/*! \brief Gets the interrupt handler of the current event at the \a int_lev
|
||||
* interrupt priority level (called from exception.S).
|
||||
*
|
||||
* \param int_lev Interrupt priority level to handle.
|
||||
*
|
||||
* \return Interrupt handler to execute.
|
||||
*
|
||||
* \note Taken and adapted from Newlib.
|
||||
*/
|
||||
__int_handler _get_interrupt_handler(unsigned int int_lev)
|
||||
{
|
||||
// ICR3 is mapped first, ICR0 last.
|
||||
// Code in exception.S puts int_lev in R12 which is used by AVR32-GCC to pass
|
||||
// a single argument to a function.
|
||||
unsigned int int_grp = (&AVR32_INTC.icr3)[INT3 - int_lev];
|
||||
unsigned int int_req = AVR32_INTC.irr[int_grp];
|
||||
|
||||
// As an interrupt may disappear while it is being fetched by the CPU
|
||||
// (spurious interrupt caused by a delayed response from an MCU peripheral to
|
||||
// an interrupt flag clear or interrupt disable instruction), check if there
|
||||
// are remaining interrupt lines to process.
|
||||
// If a spurious interrupt occurs, the status register (SR) contains an
|
||||
// execution mode and interrupt level masks corresponding to a level 0
|
||||
// interrupt, whatever the interrupt priority level causing the spurious
|
||||
// event. This behavior has been chosen because a spurious interrupt has not
|
||||
// to be a priority one and because it may not cause any trouble to other
|
||||
// interrupts.
|
||||
// However, these spurious interrupts place the hardware in an unstable state
|
||||
// and could give problems in other/future versions of the CPU, so the
|
||||
// software has to be written so that they never occur. The only safe way of
|
||||
// achieving this is to always clear or disable peripheral interrupts with the
|
||||
// following sequence:
|
||||
// 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
|
||||
// 2: Perform the bus access to the peripheral register that clears or
|
||||
// disables the interrupt.
|
||||
// 3: Wait until the interrupt has actually been cleared or disabled by the
|
||||
// peripheral. This is usually performed by reading from a register in the
|
||||
// same peripheral (it DOES NOT have to be the same register that was
|
||||
// accessed in step 2, but it MUST be in the same peripheral), what takes
|
||||
// bus system latencies into account, but peripheral internal latencies
|
||||
// (generally 0 cycle) also have to be considered.
|
||||
// 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
|
||||
// Note that steps 1 and 4 are useless inside interrupt handlers as the
|
||||
// corresponding interrupt level is automatically masked by IxM (unless IxM is
|
||||
// explicitly cleared by the software).
|
||||
//
|
||||
// Get the right IRQ handler.
|
||||
//
|
||||
// If several interrupt lines are active in the group, the interrupt line with
|
||||
// the highest number is selected. This is to be coherent with the
|
||||
// prioritization of interrupt groups performed by the hardware interrupt
|
||||
// controller.
|
||||
//
|
||||
// If no handler has been registered for the pending interrupt,
|
||||
// _unhandled_interrupt will be selected thanks to the initialization of
|
||||
// _int_line_handler_table_x by INTC_init_interrupts.
|
||||
//
|
||||
// exception.S will provide the interrupt handler with a clean interrupt stack
|
||||
// frame, with nothing more pushed onto the stack. The interrupt handler must
|
||||
// manage the `rete' instruction, what can be done thanks to pure assembly,
|
||||
// inline assembly or the `__attribute__((__interrupt__))' C function
|
||||
// attribute.
|
||||
return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;
|
||||
}
|
||||
|
||||
|
||||
void INTC_init_interrupts(void)
|
||||
{
|
||||
unsigned int int_grp, int_req;
|
||||
|
||||
// For all interrupt groups,
|
||||
for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
|
||||
{
|
||||
// For all interrupt request lines of each group,
|
||||
for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)
|
||||
{
|
||||
// Assign _unhandled_interrupt as default interrupt handler.
|
||||
_int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;
|
||||
}
|
||||
|
||||
// Set the interrupt group priority register to its default value.
|
||||
// By default, all interrupt groups are linked to the interrupt priority
|
||||
// level 0 and to the interrupt vector _int0.
|
||||
AVR32_INTC.ipr[int_grp] = ipr_val[INT0];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev)
|
||||
{
|
||||
unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
|
||||
|
||||
// Store in _int_line_handler_table_x the pointer to the interrupt handler, so
|
||||
// that _get_interrupt_handler can retrieve it when the interrupt is vectored.
|
||||
_int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;
|
||||
|
||||
// Program the corresponding IPRX register to set the interrupt priority level
|
||||
// and the interrupt vector offset that will be fetched by the core interrupt
|
||||
// system.
|
||||
// NOTE: The _intx functions are intermediate assembly functions between the
|
||||
// core interrupt system and the user interrupt handler.
|
||||
AVR32_INTC.ipr[int_grp] = ipr_val[int_lev & (AVR32_INTC_IPR0_INTLEV_MASK >> AVR32_INTC_IPR0_INTLEV_OFFSET)];
|
||||
}
|
||||
104
Demo/AVR32_UC3/DRIVERS/INTC/intc.h
Normal file
104
Demo/AVR32_UC3/DRIVERS/INTC/intc.h
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
/*This file is prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief INTC driver for AVR32 UC3.
|
||||
*
|
||||
* AVR32 Interrupt Controller driver module.
|
||||
*
|
||||
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
|
||||
* - Supported devices: All AVR32 devices with an INTC module can be used.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _INTC_H_
|
||||
#define _INTC_H_
|
||||
|
||||
#include "compiler.h"
|
||||
|
||||
|
||||
//! Maximal number of interrupt request lines per group.
|
||||
#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32
|
||||
|
||||
//! Number of interrupt priority levels.
|
||||
#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR0_INTLEV_SIZE)
|
||||
|
||||
/*! \name Interrupt Priority Levels
|
||||
*/
|
||||
//! @{
|
||||
#define INT0 0 //!< Lowest interrupt priority level.
|
||||
#define INT1 1
|
||||
#define INT2 2
|
||||
#define INT3 3 //!< Highest interrupt priority level.
|
||||
//! @}
|
||||
|
||||
|
||||
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
|
||||
|
||||
//! Pointer to interrupt handler.
|
||||
#if __GNUC__
|
||||
typedef void (*__int_handler)(void);
|
||||
#elif __ICCAVR32__
|
||||
typedef void (__interrupt *__int_handler)(void);
|
||||
#endif
|
||||
|
||||
|
||||
/*! \brief Initializes the hardware interrupt controller driver.
|
||||
*
|
||||
* \note Taken and adapted from Newlib.
|
||||
*/
|
||||
extern void INTC_init_interrupts(void);
|
||||
|
||||
/*! \brief Registers an interrupt handler.
|
||||
*
|
||||
* \param handler Interrupt handler to register.
|
||||
* \param irq IRQ of the interrupt handler to register.
|
||||
* \param int_lev Interrupt priority level to assign to the group of this IRQ.
|
||||
*
|
||||
* \warning The interrupt handler must manage the `rete' instruction, what can
|
||||
* be done thanks to pure assembly, inline assembly or the
|
||||
* `__attribute__((__interrupt__))' C function attribute.
|
||||
*
|
||||
* \warning If several interrupt handlers of a same group are registered with
|
||||
* different priority levels, only the latest priority level set will
|
||||
* be effective.
|
||||
*
|
||||
* \note Taken and adapted from Newlib.
|
||||
*/
|
||||
extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev);
|
||||
|
||||
#endif // __AVR32_ABI_COMPILER__
|
||||
|
||||
|
||||
#endif // _INTC_H_
|
||||
608
Demo/AVR32_UC3/DRIVERS/PM/pm.c
Normal file
608
Demo/AVR32_UC3/DRIVERS/PM/pm.c
Normal file
|
|
@ -0,0 +1,608 @@
|
|||
/*This file has been prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief Power Manager driver.
|
||||
*
|
||||
*
|
||||
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
|
||||
* - Supported devices: All AVR32 devices.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#include "pm.h"
|
||||
|
||||
|
||||
void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)
|
||||
{
|
||||
union {
|
||||
unsigned long oscctrl0;
|
||||
avr32_pm_oscctrl0_t OSCCTRL0;
|
||||
} oscctrl0 ;
|
||||
// Read
|
||||
oscctrl0.oscctrl0 = pm->oscctrl0;
|
||||
// Modify
|
||||
oscctrl0.OSCCTRL0.mode = AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK;
|
||||
// Write
|
||||
pm->oscctrl0 = oscctrl0.oscctrl0;
|
||||
}
|
||||
|
||||
|
||||
void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)
|
||||
{
|
||||
union {
|
||||
unsigned long oscctrl0;
|
||||
avr32_pm_oscctrl0_t OSCCTRL0;
|
||||
} oscctrl0 ;
|
||||
// Read
|
||||
oscctrl0.oscctrl0 = pm->oscctrl0;
|
||||
// Modify
|
||||
oscctrl0.OSCCTRL0.mode = (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :
|
||||
AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3;
|
||||
// Write
|
||||
pm->oscctrl0 = oscctrl0.oscctrl0;
|
||||
}
|
||||
|
||||
|
||||
void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)
|
||||
{
|
||||
union {
|
||||
avr32_pm_mcctrl_t MCCTRL;
|
||||
unsigned long mcctrl;
|
||||
} mcctrl;
|
||||
union {
|
||||
unsigned long oscctrl0;
|
||||
avr32_pm_oscctrl0_t OSCCTRL0;
|
||||
} oscctrl0 ;
|
||||
|
||||
// Read register
|
||||
mcctrl.mcctrl = pm->mcctrl;
|
||||
oscctrl0.oscctrl0 = pm->oscctrl0;
|
||||
// Modify
|
||||
mcctrl.MCCTRL.osc0en = 1;
|
||||
oscctrl0.OSCCTRL0.startup = startup;
|
||||
// Write back
|
||||
pm->oscctrl0 = oscctrl0.oscctrl0;
|
||||
pm->mcctrl = mcctrl.mcctrl;
|
||||
|
||||
while(!pm->ISR.osc0rdy); //For osc output valid
|
||||
}
|
||||
|
||||
|
||||
void pm_disable_clk0(volatile avr32_pm_t *pm)
|
||||
{
|
||||
union {
|
||||
avr32_pm_mcctrl_t MCCTRL;
|
||||
unsigned long mcctrl;
|
||||
} mcctrl;
|
||||
|
||||
// Read register
|
||||
mcctrl.mcctrl = pm->mcctrl;
|
||||
|
||||
// Modify
|
||||
mcctrl.MCCTRL.osc0en = 0;
|
||||
|
||||
// Write back
|
||||
pm->mcctrl = mcctrl.mcctrl;
|
||||
}
|
||||
|
||||
|
||||
void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
|
||||
{
|
||||
union {
|
||||
avr32_pm_mcctrl_t MCCTRL;
|
||||
unsigned long mcctrl;
|
||||
} mcctrl;
|
||||
union {
|
||||
unsigned long oscctrl0;
|
||||
avr32_pm_oscctrl0_t OSCCTRL0;
|
||||
} oscctrl0 ;
|
||||
|
||||
// Read register
|
||||
mcctrl.mcctrl = pm->mcctrl;
|
||||
oscctrl0.oscctrl0 = pm->oscctrl0;
|
||||
// Modify
|
||||
mcctrl.MCCTRL.osc0en = 1;
|
||||
oscctrl0.OSCCTRL0.startup=startup;
|
||||
// Write back
|
||||
pm->mcctrl = mcctrl.mcctrl;
|
||||
pm->oscctrl0 = oscctrl0.oscctrl0;
|
||||
}
|
||||
|
||||
|
||||
void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm)
|
||||
{
|
||||
while(!pm->ISR.osc0rdy);
|
||||
}
|
||||
|
||||
|
||||
void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)
|
||||
{
|
||||
union {
|
||||
unsigned long oscctrl1;
|
||||
avr32_pm_oscctrl1_t OSCCTRL1;
|
||||
} oscctrl1 ;
|
||||
// Read
|
||||
oscctrl1.oscctrl1= pm->oscctrl1;
|
||||
// Modify
|
||||
oscctrl1.OSCCTRL1.mode = AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK;
|
||||
// Write
|
||||
pm->oscctrl1 = oscctrl1.oscctrl1;
|
||||
}
|
||||
|
||||
|
||||
void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)
|
||||
{
|
||||
union {
|
||||
unsigned long oscctrl1;
|
||||
avr32_pm_oscctrl1_t OSCCTRL1;
|
||||
} oscctrl1 ;
|
||||
// Read
|
||||
oscctrl1.oscctrl1= pm->oscctrl1;
|
||||
// Modify
|
||||
oscctrl1.OSCCTRL1.mode = (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :
|
||||
AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3;
|
||||
// Write
|
||||
pm->oscctrl1 = oscctrl1.oscctrl1;
|
||||
}
|
||||
|
||||
|
||||
void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)
|
||||
{
|
||||
union {
|
||||
avr32_pm_mcctrl_t MCCTRL;
|
||||
unsigned long mcctrl;
|
||||
} mcctrl;
|
||||
union {
|
||||
unsigned long oscctrl1;
|
||||
avr32_pm_oscctrl1_t OSCCTRL1;
|
||||
} oscctrl1 ;
|
||||
|
||||
// Read register
|
||||
mcctrl.mcctrl = pm->mcctrl;
|
||||
oscctrl1.oscctrl1 = pm->oscctrl1;
|
||||
|
||||
mcctrl.MCCTRL.osc1en = 1;
|
||||
oscctrl1.OSCCTRL1.startup=startup;
|
||||
// Write back
|
||||
pm->oscctrl1 = oscctrl1.oscctrl1;
|
||||
pm->mcctrl = mcctrl.mcctrl;
|
||||
|
||||
while(!pm->ISR.osc1rdy);
|
||||
}
|
||||
|
||||
|
||||
void pm_disable_clk1(volatile avr32_pm_t *pm)
|
||||
{
|
||||
union {
|
||||
avr32_pm_mcctrl_t MCCTRL;
|
||||
unsigned long mcctrl;
|
||||
} mcctrl;
|
||||
|
||||
|
||||
// Read register
|
||||
mcctrl.mcctrl = pm->mcctrl;
|
||||
|
||||
// Modify
|
||||
mcctrl.MCCTRL.osc1en = 0;
|
||||
|
||||
// Write back
|
||||
pm->mcctrl = mcctrl.mcctrl;
|
||||
}
|
||||
|
||||
|
||||
void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
|
||||
{
|
||||
union {
|
||||
avr32_pm_mcctrl_t MCCTRL;
|
||||
unsigned long mcctrl;
|
||||
} mcctrl;
|
||||
union {
|
||||
unsigned long oscctrl1;
|
||||
avr32_pm_oscctrl1_t OSCCTRL1;
|
||||
} oscctrl1 ;
|
||||
|
||||
// Read register
|
||||
mcctrl.mcctrl = pm->mcctrl;
|
||||
oscctrl1.oscctrl1 = pm->oscctrl1;
|
||||
|
||||
mcctrl.MCCTRL.osc1en = 1;
|
||||
oscctrl1.OSCCTRL1.startup=startup;
|
||||
// Write back
|
||||
pm->oscctrl1 = oscctrl1.oscctrl1;
|
||||
pm->mcctrl = mcctrl.mcctrl;
|
||||
}
|
||||
|
||||
|
||||
void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)
|
||||
{
|
||||
while(!pm->ISR.osc1rdy);
|
||||
}
|
||||
|
||||
|
||||
void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm)
|
||||
{
|
||||
union {
|
||||
unsigned long oscctrl32;
|
||||
avr32_pm_oscctrl32_t OSCCTRL32;
|
||||
} u_ctrl;
|
||||
u_ctrl.oscctrl32 = pm->oscctrl32;
|
||||
u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK;
|
||||
pm->oscctrl32 = u_ctrl.oscctrl32;
|
||||
}
|
||||
|
||||
|
||||
void pm_enable_osc32_crystal(volatile avr32_pm_t *pm)
|
||||
{
|
||||
union {
|
||||
unsigned long oscctrl32;
|
||||
avr32_pm_oscctrl32_t OSCCTRL32;
|
||||
} u_ctrl;
|
||||
u_ctrl.oscctrl32 = pm->oscctrl32;
|
||||
u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_CRYSTAL;
|
||||
pm->oscctrl32 = u_ctrl.oscctrl32;
|
||||
}
|
||||
|
||||
|
||||
void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup)
|
||||
{
|
||||
union {
|
||||
unsigned long oscctrl32;
|
||||
avr32_pm_oscctrl32_t OSCCTRL32;
|
||||
} oscctrl32 ;
|
||||
|
||||
// Read register
|
||||
oscctrl32.oscctrl32 = pm->oscctrl32;
|
||||
// Modify
|
||||
oscctrl32.OSCCTRL32.osc32en = 1;
|
||||
oscctrl32.OSCCTRL32.startup=startup;
|
||||
// Write back
|
||||
pm->oscctrl32 = oscctrl32.oscctrl32;
|
||||
|
||||
while(!pm->ISR.osc32rdy);
|
||||
}
|
||||
|
||||
|
||||
void pm_disable_clk32(volatile avr32_pm_t *pm)
|
||||
{
|
||||
// To get rid of a GCC bug
|
||||
// This makes C code longer, but not ASM
|
||||
union {
|
||||
unsigned long oscctrl32;
|
||||
avr32_pm_oscctrl32_t OSCCTRL32;
|
||||
} oscctrl32 ;
|
||||
|
||||
// Read register
|
||||
oscctrl32.oscctrl32 = pm->oscctrl32;
|
||||
// Modify
|
||||
oscctrl32.OSCCTRL32.osc32en = 0;
|
||||
// Write back
|
||||
pm->oscctrl32 = oscctrl32.oscctrl32;
|
||||
}
|
||||
|
||||
|
||||
void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
|
||||
{
|
||||
union {
|
||||
unsigned long oscctrl32;
|
||||
avr32_pm_oscctrl32_t OSCCTRL32;
|
||||
} oscctrl32 ;
|
||||
|
||||
// Read register
|
||||
oscctrl32.oscctrl32 = pm->oscctrl32;
|
||||
// Modify
|
||||
oscctrl32.OSCCTRL32.osc32en = 1;
|
||||
oscctrl32.OSCCTRL32.startup=startup;
|
||||
// Write back
|
||||
pm->oscctrl32 = oscctrl32.oscctrl32;
|
||||
}
|
||||
|
||||
|
||||
void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)
|
||||
{
|
||||
// To get rid of a GCC bug
|
||||
// This makes C code longer, but not ASM
|
||||
|
||||
while(!pm->ISR.osc32rdy);
|
||||
}
|
||||
|
||||
|
||||
void pm_cksel(volatile avr32_pm_t *pm,
|
||||
unsigned int pbadiv,
|
||||
unsigned int pbasel,
|
||||
unsigned int pbbdiv,
|
||||
unsigned int pbbsel,
|
||||
unsigned int hsbdiv,
|
||||
unsigned int hsbsel)
|
||||
{
|
||||
// Force the compiler to generate only one 32 bits access
|
||||
union {
|
||||
avr32_pm_cksel_t selval ;
|
||||
unsigned long uword32;
|
||||
} cksel;
|
||||
|
||||
cksel.uword32 = 0;
|
||||
|
||||
cksel.selval.cpudiv = hsbdiv;
|
||||
cksel.selval.cpusel = hsbsel;
|
||||
cksel.selval.hsbdiv = hsbdiv;
|
||||
cksel.selval.hsbsel = hsbsel;
|
||||
cksel.selval.pbbdiv = pbbdiv;
|
||||
cksel.selval.pbbsel = pbbsel;
|
||||
cksel.selval.pbadiv = pbadiv;
|
||||
cksel.selval.pbasel = pbasel;
|
||||
|
||||
pm->cksel = cksel.uword32;
|
||||
|
||||
// Wait for ckrdy bit and then clear it
|
||||
while(!(pm->ISR.ckrdy));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
void pm_gc_setup(volatile avr32_pm_t *pm,
|
||||
unsigned int gc,
|
||||
unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)
|
||||
unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1
|
||||
unsigned int diven,
|
||||
unsigned int div) {
|
||||
union {
|
||||
unsigned long gcctrl;
|
||||
avr32_pm_gcctrl_t GCCTRL;
|
||||
} u_gc;
|
||||
|
||||
u_gc.GCCTRL.oscsel = pll_osc;
|
||||
u_gc.GCCTRL.pllsel = osc_or_pll;
|
||||
u_gc.GCCTRL.diven = diven;
|
||||
u_gc.GCCTRL.div = div;
|
||||
u_gc.GCCTRL.cen = 0; // Disable GC first
|
||||
pm->gcctrl[gc] = u_gc.gcctrl;
|
||||
}
|
||||
|
||||
|
||||
void pm_gc_enable(volatile avr32_pm_t *pm,
|
||||
unsigned int gc) {
|
||||
union {
|
||||
unsigned long gcctrl;
|
||||
avr32_pm_gcctrl_t GCCTRL;
|
||||
} u_gc;
|
||||
u_gc.gcctrl = pm->gcctrl[gc];
|
||||
u_gc.GCCTRL.cen = 1;
|
||||
pm->gcctrl[gc] = u_gc.gcctrl;
|
||||
}
|
||||
|
||||
|
||||
void pm_gc_disable(volatile avr32_pm_t *pm,
|
||||
unsigned int gc) {
|
||||
union {
|
||||
unsigned long gcctrl;
|
||||
avr32_pm_gcctrl_t GCCTRL;
|
||||
} u_gc;
|
||||
u_gc.gcctrl = pm->gcctrl[gc];
|
||||
u_gc.GCCTRL.cen = 0;
|
||||
pm->gcctrl[gc] = u_gc.gcctrl;
|
||||
}
|
||||
|
||||
|
||||
void pm_pll_setup(volatile avr32_pm_t *pm,
|
||||
unsigned int pll,
|
||||
unsigned int mul,
|
||||
unsigned int div,
|
||||
unsigned int osc,
|
||||
unsigned int lockcount) {
|
||||
|
||||
union {
|
||||
unsigned long pll ;
|
||||
avr32_pm_pll_t PLL ;
|
||||
} u_pll;
|
||||
|
||||
u_pll.pll=0;
|
||||
|
||||
u_pll.PLL.pllmul = mul;
|
||||
u_pll.PLL.plldiv = div;
|
||||
u_pll.PLL.pllosc = osc;
|
||||
u_pll.PLL.pllcount = lockcount;
|
||||
|
||||
u_pll.PLL.pllopt = 0;
|
||||
|
||||
u_pll.PLL.plltest = 0;
|
||||
|
||||
(pm->pll)[pll] = u_pll.pll;
|
||||
}
|
||||
|
||||
|
||||
void pm_pll_set_option(volatile avr32_pm_t *pm,
|
||||
unsigned int pll,
|
||||
unsigned int pll_freq,
|
||||
unsigned int pll_div2,
|
||||
unsigned int pll_wbwdisable) {
|
||||
union {
|
||||
unsigned long pll ;
|
||||
avr32_pm_pll_t PLL ;
|
||||
} u_pll;
|
||||
|
||||
u_pll.pll = (pm->pll)[pll];
|
||||
u_pll.PLL.pllopt = pll_freq | (pll_div2<<1) | (pll_wbwdisable<<2);
|
||||
(pm->pll)[pll] = u_pll.pll;
|
||||
}
|
||||
|
||||
|
||||
unsigned int pm_pll_get_option(volatile avr32_pm_t *pm,
|
||||
unsigned int pll) {
|
||||
return (pm->PLL)[pll].pllopt;
|
||||
}
|
||||
|
||||
|
||||
void pm_pll_enable(volatile avr32_pm_t *pm,
|
||||
unsigned int pll) {
|
||||
union {
|
||||
unsigned long pll ;
|
||||
avr32_pm_pll_t PLL ;
|
||||
} u_pll;
|
||||
|
||||
u_pll.pll = (pm->pll)[pll];
|
||||
u_pll.PLL.pllen = 1;
|
||||
(pm->pll)[pll] = u_pll.pll;
|
||||
}
|
||||
|
||||
|
||||
void pm_pll_disable(volatile avr32_pm_t *pm,
|
||||
unsigned int pll) {
|
||||
union {
|
||||
unsigned long pll ;
|
||||
avr32_pm_pll_t PLL ;
|
||||
} u_pll;
|
||||
|
||||
u_pll.pll = (pm->pll)[pll];
|
||||
u_pll.PLL.pllen = 0;
|
||||
(pm->pll)[pll] = u_pll.pll;
|
||||
}
|
||||
|
||||
|
||||
void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)
|
||||
{
|
||||
while(!pm->ISR.lock0);
|
||||
|
||||
// Bypass the lock signal of the PLL
|
||||
pm->pll[0] |= AVR32_PM_PLL0_PLLBPL_MASK;
|
||||
}
|
||||
|
||||
|
||||
void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)
|
||||
{
|
||||
while(!pm->ISR.lock1);
|
||||
|
||||
// Bypass the lock signal of the PLL
|
||||
pm->pll[1] |= AVR32_PM_PLL1_PLLBPL_MASK;
|
||||
}
|
||||
|
||||
|
||||
void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)
|
||||
{
|
||||
union {
|
||||
avr32_pm_mcctrl_t MCCTRL;
|
||||
unsigned long mcctrl;
|
||||
} mcctrl;
|
||||
// Read
|
||||
mcctrl.mcctrl = pm->mcctrl;
|
||||
// Modify
|
||||
mcctrl.MCCTRL.mcsel = clock;
|
||||
// Write Back
|
||||
pm->MCCTRL.mcsel = mcctrl.mcctrl;
|
||||
}
|
||||
|
||||
|
||||
void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup)
|
||||
{
|
||||
pm_enable_osc0_crystal(pm, fosc0); // Enable the Osc0 in crystal mode
|
||||
pm_enable_clk0(pm, startup); // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal
|
||||
pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0
|
||||
}
|
||||
|
||||
|
||||
void pm_bod_enable_irq(volatile struct avr32_pm_t *pm) {
|
||||
|
||||
union {
|
||||
unsigned long ier ;
|
||||
avr32_pm_ier_t IER ;
|
||||
} u_ier;
|
||||
u_ier.ier = 0;
|
||||
u_ier.IER.boddet = 1;
|
||||
|
||||
pm->ier = u_ier.ier;
|
||||
}
|
||||
|
||||
|
||||
void pm_bod_disable_irq(volatile struct avr32_pm_t *pm) {
|
||||
|
||||
union {
|
||||
unsigned long idr ;
|
||||
avr32_pm_idr_t IDR ;
|
||||
} u_idr;
|
||||
u_idr.idr = 0;
|
||||
u_idr.IDR.boddet = 1;
|
||||
|
||||
pm->idr = u_idr.idr;
|
||||
}
|
||||
|
||||
|
||||
void pm_bod_clear_irq(volatile struct avr32_pm_t *pm) {
|
||||
|
||||
union {
|
||||
unsigned long icr ;
|
||||
avr32_pm_idr_t ICR ;
|
||||
} u_icr;
|
||||
u_icr.icr = 0;
|
||||
u_icr.ICR.boddet = 1;
|
||||
|
||||
pm->icr = u_icr.icr;
|
||||
}
|
||||
|
||||
|
||||
unsigned long pm_bod_get_irq_status(volatile struct avr32_pm_t *pm) {
|
||||
|
||||
return pm->ISR.boddet;
|
||||
}
|
||||
|
||||
|
||||
unsigned long pm_bod_get_irq_enable_bit(volatile struct avr32_pm_t *pm) {
|
||||
|
||||
return pm->IMR.boddet;
|
||||
}
|
||||
|
||||
|
||||
unsigned long pm_bod_get_level(volatile avr32_pm_t *pm) {
|
||||
union {
|
||||
unsigned long bod ;
|
||||
avr32_pm_bod_t BOD ;
|
||||
} u_bod;
|
||||
|
||||
u_bod.bod = pm->bod;
|
||||
|
||||
return (unsigned long) u_bod.BOD.level;
|
||||
|
||||
}
|
||||
|
||||
|
||||
void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value) {
|
||||
(pm->gplp)[gplp] = value;
|
||||
|
||||
}
|
||||
|
||||
|
||||
unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp) {
|
||||
|
||||
return (pm->gplp)[gplp];
|
||||
}
|
||||
331
Demo/AVR32_UC3/DRIVERS/PM/pm.h
Normal file
331
Demo/AVR32_UC3/DRIVERS/PM/pm.h
Normal file
|
|
@ -0,0 +1,331 @@
|
|||
/*This file has been prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief Power Manager driver.
|
||||
*
|
||||
*
|
||||
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
|
||||
* - Supported devices: All AVR32 devices.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PM_H_
|
||||
#define _PM_H_
|
||||
|
||||
#if __GNUC__
|
||||
# include <avr32/io.h>
|
||||
#elif __ICCAVR32__
|
||||
# include <avr32/iouc3a0512.h>
|
||||
# include <avr32/uc3a0512.h>
|
||||
#else
|
||||
# error Unknown compiler
|
||||
#endif
|
||||
|
||||
#include "compiler.h"
|
||||
#include "preprocessor.h"
|
||||
|
||||
|
||||
/*! \brief Sets the MCU in the specified sleep mode.
|
||||
*
|
||||
* \param mode Sleep mode:
|
||||
* \arg \c AVR32_PM_SMODE_IDLE: Idle;
|
||||
* \arg \c AVR32_PM_SMODE_FROZEN: Frozen;
|
||||
* \arg \c AVR32_PM_SMODE_STANDBY: Standby;
|
||||
* \arg \c AVR32_PM_SMODE_STOP: Stop;
|
||||
* \arg \c AVR32_PM_SMODE_SHUTDOWN: Shutdown (DeepStop);
|
||||
* \arg \c AVR32_PM_SMODE_STATIC: Static.
|
||||
*/
|
||||
#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));}
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the external clock mode of the oscillator 0.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the crystal mode of the oscillator 0.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param fosc0 Oscillator 0 crystal frequency (Hz)
|
||||
*/
|
||||
extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the oscillator 0 to be used with a startup time.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param startup Clock 0 startup time. Time is expressed in term of RCOsc periods (3-bit value)
|
||||
*/
|
||||
extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will disable the oscillator 0.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_disable_clk0(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the oscillator 0 to be used with no startup time.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param startup Clock 0 startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked.
|
||||
*/
|
||||
extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will wait until the Osc0 clock is ready.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the external clock mode of the oscillator 1.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the crystal mode of the oscillator 1.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param fosc1 Oscillator 1 crystal frequency (Hz)
|
||||
*/
|
||||
extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the oscillator 1 to be used with a startup time.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param startup Clock 1 startup time. Time is expressed in term of RCOsc periods (3-bit value)
|
||||
*/
|
||||
extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will disable the oscillator 1.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_disable_clk1(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the oscillator 1 to be used with no startup time.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param startup Clock 1 startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked.
|
||||
*/
|
||||
extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will wait until the Osc1 clock is ready.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the external clock mode of the 32-kHz oscillator.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the crystal mode of the 32-kHz oscillator.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the oscillator 32 to be used with a startup time.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param startup Clock 32 kHz startup time. Time is expressed in term of RCOsc periods (3-bit value)
|
||||
*/
|
||||
extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will disable the oscillator 32.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_disable_clk32(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable the oscillator 32 to be used with no startup time.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param startup Clock 32 kHz startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked.
|
||||
*/
|
||||
extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will wait until the osc32 clock is ready.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
//FIXME update this header -SM
|
||||
/*!
|
||||
* \brief This function will select all the power manager clocks.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param pbadiv Peripheral Bus A clock divisor enable
|
||||
* \param pbasel Peripheral Bus A select
|
||||
* \param pbbdiv Peripheral Bus B clock divisor enable
|
||||
* \param pbbsel Peripheral Bus B select
|
||||
* \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)
|
||||
* \param hsbsel High Speed Bus select (CPU clock = HSB clock )
|
||||
*/
|
||||
extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will setup a generic clock.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param gc generic clock number (0 for gc0...)
|
||||
* \param osc_or_pll Use OSC (=0) or PLL (=1)
|
||||
* \param pll_osc Select Osc0/PLL0 or Osc1/PLL1
|
||||
* \param diven Generic clock divisor enable
|
||||
* \param div Generic clock divisor
|
||||
*/
|
||||
extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable a generic clock.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param gc generic clock number (0 for gc0...)
|
||||
*/
|
||||
extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will disable a generic clock.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param gc generic clock number (0 for gc0...)
|
||||
*/
|
||||
extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc);
|
||||
|
||||
|
||||
//FIXME update this header -SM
|
||||
/*!
|
||||
* \brief This function will setup a PLL.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param pll PLL number(0 for PLL0, 1 for PLL1)
|
||||
* \param mul
|
||||
* \param div
|
||||
* \param osc
|
||||
* \param lockcount
|
||||
*/
|
||||
extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount);
|
||||
|
||||
|
||||
//FIXME update this header -SM
|
||||
/*!
|
||||
* \brief This function will set a PLL option.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param pll PLL number(0 for PLL0, 1 for PLL1)
|
||||
* \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
|
||||
* \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
|
||||
* \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
|
||||
*/
|
||||
extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable);
|
||||
|
||||
|
||||
//FIXME update this header -SM
|
||||
/*!
|
||||
* \brief This function will get a PLL option.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param pll PLL number(0 for PLL0, 1 for PLL1)
|
||||
* \return Option
|
||||
*/
|
||||
extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will enable a PLL.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param pll PLL number(0 for PLL0, 1 for PLL1)
|
||||
*/
|
||||
extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will disable a PLL.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param pll PLL number(0 for PLL0, 1 for PLL1)
|
||||
*/
|
||||
extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will wait for PLL0 locked
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will wait for PLL1 locked
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
*/
|
||||
extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief This function will switch the power manager main clock.
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0.
|
||||
*/
|
||||
extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock);
|
||||
|
||||
|
||||
/*!
|
||||
* \brief Switch main clock to clock Osc0 (crystal mode)
|
||||
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
|
||||
* \param fosc0 Oscillator 0 crystal frequency (Hz)
|
||||
* \param startup Crystal 0 startup time. Time is expressed in term of RCOsc periods (3-bit value)
|
||||
*/
|
||||
extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup);
|
||||
|
||||
|
||||
#endif // _PM_H_
|
||||
299
Demo/AVR32_UC3/DRIVERS/TC/tc.c
Normal file
299
Demo/AVR32_UC3/DRIVERS/TC/tc.c
Normal file
|
|
@ -0,0 +1,299 @@
|
|||
/*This file is prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief TC driver for AVR32 UC3.
|
||||
*
|
||||
* AVR32 Timer/Counter driver module.
|
||||
*
|
||||
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
|
||||
* - Supported devices: All AVR32 devices with a TC module can be used.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#if __GNUC__
|
||||
# include <avr32/io.h>
|
||||
#elif __ICCAVR32__
|
||||
# include <avr32/iouc3a0512.h>
|
||||
#else
|
||||
# error Unknown compiler
|
||||
#endif
|
||||
|
||||
#include "compiler.h"
|
||||
#include "tc.h"
|
||||
|
||||
|
||||
int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
return tc->channel[channel].imr;
|
||||
}
|
||||
|
||||
|
||||
int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
// Enable the appropriate interrupts.
|
||||
tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET |
|
||||
bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET |
|
||||
bitfield->ldras << AVR32_TC_LDRAS_OFFSET |
|
||||
bitfield->cpcs << AVR32_TC_CPCS_OFFSET |
|
||||
bitfield->cpbs << AVR32_TC_CPBS_OFFSET |
|
||||
bitfield->cpas << AVR32_TC_CPAS_OFFSET |
|
||||
bitfield->lovrs << AVR32_TC_LOVRS_OFFSET |
|
||||
bitfield->covfs << AVR32_TC_COVFS_OFFSET;
|
||||
|
||||
// Disable the appropriate interrupts.
|
||||
tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET |
|
||||
(~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET |
|
||||
(~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET |
|
||||
(~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET |
|
||||
(~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET |
|
||||
(~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET |
|
||||
(~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET |
|
||||
(~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS || ext_clk_sig_src >= 1 << AVR32_TC_BMR_TC0XC0S_SIZE)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
// Clear bit-field and set the correct behavior.
|
||||
tc->bmr = (tc->bmr & ~(AVR32_TC_BMR_TC0XC0S_MASK << (channel * AVR32_TC_BMR_TC0XC0S_SIZE))) |
|
||||
(ext_clk_sig_src << (channel * AVR32_TC_BMR_TC0XC0S_SIZE));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (opt->channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
// MEASURE SIGNALS: Capture operating mode.
|
||||
tc->channel[opt->channel].cmr = opt->ldrb << AVR32_TC_LDRB_OFFSET |
|
||||
opt->ldra << AVR32_TC_LDRA_OFFSET |
|
||||
0 << AVR32_TC_WAVE_OFFSET |
|
||||
opt->cpctrg << AVR32_TC_CPCTRG_OFFSET |
|
||||
opt->abetrg << AVR32_TC_ABETRG_OFFSET |
|
||||
opt->etrgedg << AVR32_TC_ETRGEDG_OFFSET|
|
||||
opt->ldbdis << AVR32_TC_LDBDIS_OFFSET |
|
||||
opt->ldbstop << AVR32_TC_LDBSTOP_OFFSET |
|
||||
opt->burst << AVR32_TC_BURST_OFFSET |
|
||||
opt->clki << AVR32_TC_CLKI_OFFSET |
|
||||
opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (opt->channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
// GENERATE SIGNALS: Waveform operating mode.
|
||||
tc->channel[opt->channel].cmr = opt->bswtrg << AVR32_TC_BSWTRG_OFFSET |
|
||||
opt->beevt << AVR32_TC_BEEVT_OFFSET |
|
||||
opt->bcpc << AVR32_TC_BCPC_OFFSET |
|
||||
opt->bcpb << AVR32_TC_BCPB_OFFSET |
|
||||
opt->aswtrg << AVR32_TC_ASWTRG_OFFSET |
|
||||
opt->aeevt << AVR32_TC_AEEVT_OFFSET |
|
||||
opt->acpc << AVR32_TC_ACPC_OFFSET |
|
||||
opt->acpa << AVR32_TC_ACPA_OFFSET |
|
||||
1 << AVR32_TC_WAVE_OFFSET |
|
||||
opt->wavsel << AVR32_TC_WAVSEL_OFFSET |
|
||||
opt->enetrg << AVR32_TC_ENETRG_OFFSET |
|
||||
opt->eevt << AVR32_TC_EEVT_OFFSET |
|
||||
opt->eevtedg << AVR32_TC_EEVTEDG_OFFSET |
|
||||
opt->cpcdis << AVR32_TC_CPCDIS_OFFSET |
|
||||
opt->cpcstop << AVR32_TC_CPCSTOP_OFFSET |
|
||||
opt->burst << AVR32_TC_BURST_OFFSET |
|
||||
opt->clki << AVR32_TC_CLKI_OFFSET |
|
||||
opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int tc_start(volatile avr32_tc_t *tc, unsigned int channel)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
// Enable, reset and start the selected timer/counter channel.
|
||||
tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK | AVR32_TC_CLKEN_MASK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int tc_stop(volatile avr32_tc_t *tc, unsigned int channel)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
// Disable the selected timer/counter channel.
|
||||
tc->channel[channel].ccr = AVR32_TC_CLKDIS_MASK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
// Reset the selected timer/counter channel.
|
||||
tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void tc_sync_trigger(volatile avr32_tc_t *tc)
|
||||
{
|
||||
// Reset all channels of the selected timer/counter.
|
||||
tc->bcr = AVR32_TC_BCR_SYNC_MASK;
|
||||
}
|
||||
|
||||
|
||||
int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
return tc->channel[channel].sr;
|
||||
}
|
||||
|
||||
|
||||
int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
return Rd_bitfield(tc->channel[channel].cv, AVR32_TC_CV_MASK);
|
||||
}
|
||||
|
||||
|
||||
int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
return Rd_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK);
|
||||
}
|
||||
|
||||
|
||||
int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
return Rd_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK);
|
||||
}
|
||||
|
||||
|
||||
int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
return Rd_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK);
|
||||
}
|
||||
|
||||
|
||||
int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
// This function is only available in WAVEFORM mode.
|
||||
if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
|
||||
Wr_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK, value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
// This function is only available in WAVEFORM mode.
|
||||
if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
|
||||
Wr_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK, value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
|
||||
{
|
||||
// Check for valid input.
|
||||
if (channel >= TC_NUMBER_OF_CHANNELS)
|
||||
return TC_INVALID_ARGUMENT;
|
||||
|
||||
// This function is only available in WAVEFORM mode.
|
||||
if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
|
||||
Wr_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK, value);
|
||||
|
||||
return value;
|
||||
}
|
||||
586
Demo/AVR32_UC3/DRIVERS/TC/tc.h
Normal file
586
Demo/AVR32_UC3/DRIVERS/TC/tc.h
Normal file
|
|
@ -0,0 +1,586 @@
|
|||
/*This file is prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief Timer/Counter driver for AVR32 UC3.
|
||||
*
|
||||
* AVR32 Timer/Counter driver module.
|
||||
*
|
||||
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
|
||||
* - Supported devices: All AVR32 devices with a TC module can be used.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _TC_H_
|
||||
#define _TC_H_
|
||||
|
||||
#if __GNUC__
|
||||
# include <avr32/io.h>
|
||||
#elif __ICCAVR32__
|
||||
# include <avr32/iouc3a0512.h>
|
||||
#else
|
||||
# error Unknown compiler
|
||||
#endif
|
||||
|
||||
|
||||
//! TC driver functions return value in case of invalid argument(s).
|
||||
#define TC_INVALID_ARGUMENT -1
|
||||
|
||||
//! Number of timer/counter channels.
|
||||
#define TC_NUMBER_OF_CHANNELS (sizeof(((avr32_tc_t *)0)->channel) / sizeof(avr32_tc_channel_t))
|
||||
|
||||
/*! \name External Clock Signal 0 Selection
|
||||
*/
|
||||
//! @{
|
||||
#define TC_CH0_EXT_CLK0_SRC_TCLK0 AVR32_TC_TC0XC0S_TCLK0
|
||||
#define TC_CH0_EXT_CLK0_SRC_NO_CLK AVR32_TC_TC0XC0S_NO_CLK
|
||||
#define TC_CH0_EXT_CLK0_SRC_TIOA1 AVR32_TC_TC0XC0S_TIOA1
|
||||
#define TC_CH0_EXT_CLK0_SRC_TIOA2 AVR32_TC_TC0XC0S_TIOA2
|
||||
//! @}
|
||||
|
||||
/*! \name External Clock Signal 1 Selection
|
||||
*/
|
||||
//! @{
|
||||
#define TC_CH1_EXT_CLK1_SRC_TCLK1 AVR32_TC_TC1XC1S_TCLK1
|
||||
#define TC_CH1_EXT_CLK1_SRC_NO_CLK AVR32_TC_TC1XC1S_NO_CLK
|
||||
#define TC_CH1_EXT_CLK1_SRC_TIOA0 AVR32_TC_TC1XC1S_TIOA0
|
||||
#define TC_CH1_EXT_CLK1_SRC_TIOA2 AVR32_TC_TC1XC1S_TIOA2
|
||||
//! @}
|
||||
|
||||
/*! \name External Clock Signal 2 Selection
|
||||
*/
|
||||
//! @{
|
||||
#define TC_CH2_EXT_CLK2_SRC_TCLK2 AVR32_TC_TC2XC2S_TCLK2
|
||||
#define TC_CH2_EXT_CLK2_SRC_NO_CLK AVR32_TC_TC2XC2S_NO_CLK
|
||||
#define TC_CH2_EXT_CLK2_SRC_TIOA0 AVR32_TC_TC2XC2S_TIOA0
|
||||
#define TC_CH2_EXT_CLK2_SRC_TIOA1 AVR32_TC_TC2XC2S_TIOA1
|
||||
//! @}
|
||||
|
||||
/*! \name Event/Trigger Actions on Output
|
||||
*/
|
||||
//! @{
|
||||
#define TC_EVT_EFFECT_NOOP AVR32_TC_NONE
|
||||
#define TC_EVT_EFFECT_SET AVR32_TC_SET
|
||||
#define TC_EVT_EFFECT_CLEAR AVR32_TC_CLEAR
|
||||
#define TC_EVT_EFFECT_TOGGLE AVR32_TC_TOGGLE
|
||||
//! @}
|
||||
|
||||
/*! \name RC Compare Trigger Enable
|
||||
*/
|
||||
//! @{
|
||||
#define TC_NO_TRIGGER_COMPARE_RC 0
|
||||
#define TC_TRIGGER_COMPARE_RC 1
|
||||
//! @}
|
||||
|
||||
/*! \name Waveform Selection
|
||||
*/
|
||||
//! @{
|
||||
#define TC_WAVEFORM_SEL_UP_MODE AVR32_TC_WAVSEL_UP_NO_AUTO
|
||||
#define TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UP_AUTO
|
||||
#define TC_WAVEFORM_SEL_UPDOWN_MODE AVR32_TC_WAVSEL_UPDOWN_NO_AUTO
|
||||
#define TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UPDOWN_AUTO
|
||||
//! @}
|
||||
|
||||
/*! \name TIOA or TIOB External Trigger Selection
|
||||
*/
|
||||
//! @{
|
||||
#define TC_EXT_TRIG_SEL_TIOA 1
|
||||
#define TC_EXT_TRIG_SEL_TIOB 0
|
||||
//! @}
|
||||
|
||||
/*! \name External Event Selection
|
||||
*/
|
||||
//! @{
|
||||
#define TC_EXT_EVENT_SEL_TIOB_INPUT AVR32_TC_EEVT_TIOB_INPUT
|
||||
#define TC_EXT_EVENT_SEL_XC0_OUTPUT AVR32_TC_EEVT_XC0_OUTPUT
|
||||
#define TC_EXT_EVENT_SEL_XC1_OUTPUT AVR32_TC_EEVT_XC1_OUTPUT
|
||||
#define TC_EXT_EVENT_SEL_XC2_OUTPUT AVR32_TC_EEVT_XC2_OUTPUT
|
||||
//! @}
|
||||
|
||||
/*! \name Edge Selection
|
||||
*/
|
||||
//! @{
|
||||
#define TC_SEL_NO_EDGE AVR32_TC_EEVTEDG_NO_EDGE
|
||||
#define TC_SEL_RISING_EDGE AVR32_TC_EEVTEDG_POS_EDGE
|
||||
#define TC_SEL_FALLING_EDGE AVR32_TC_EEVTEDG_NEG_EDGE
|
||||
#define TC_SEL_EACH_EDGE AVR32_TC_EEVTEDG_BOTH_EDGES
|
||||
//! @}
|
||||
|
||||
/*! \name Burst Signal Selection
|
||||
*/
|
||||
//! @{
|
||||
#define TC_BURST_NOT_GATED AVR32_TC_BURST_NOT_GATED
|
||||
#define TC_BURST_CLK_AND_XC0 AVR32_TC_BURST_CLK_AND_XC0
|
||||
#define TC_BURST_CLK_AND_XC1 AVR32_TC_BURST_CLK_AND_XC1
|
||||
#define TC_BURST_CLK_AND_XC2 AVR32_TC_BURST_CLK_AND_XC2
|
||||
//! @}
|
||||
|
||||
/*! \name Clock Invert
|
||||
*/
|
||||
//! @{
|
||||
#define TC_CLOCK_RISING_EDGE 0
|
||||
#define TC_CLOCK_FALLING_EDGE 1
|
||||
//! @}
|
||||
|
||||
/*! \name Clock Selection
|
||||
*/
|
||||
//! @{
|
||||
#define TC_CLOCK_SOURCE_TC1 AVR32_TC_TCCLKS_TIMER_DIV1_CLOCK
|
||||
#define TC_CLOCK_SOURCE_TC2 AVR32_TC_TCCLKS_TIMER_DIV2_CLOCK
|
||||
#define TC_CLOCK_SOURCE_TC3 AVR32_TC_TCCLKS_TIMER_DIV3_CLOCK
|
||||
#define TC_CLOCK_SOURCE_TC4 AVR32_TC_TCCLKS_TIMER_DIV4_CLOCK
|
||||
#define TC_CLOCK_SOURCE_TC5 AVR32_TC_TCCLKS_TIMER_DIV5_CLOCK
|
||||
#define TC_CLOCK_SOURCE_XC0 AVR32_TC_TCCLKS_XC0
|
||||
#define TC_CLOCK_SOURCE_XC1 AVR32_TC_TCCLKS_XC1
|
||||
#define TC_CLOCK_SOURCE_XC2 AVR32_TC_TCCLKS_XC2
|
||||
//! @}
|
||||
|
||||
|
||||
//! Timer/counter interrupts.
|
||||
typedef struct
|
||||
{
|
||||
unsigned int :24;
|
||||
|
||||
//! External trigger interrupt.
|
||||
unsigned int etrgs : 1;
|
||||
|
||||
//! RB load interrupt.
|
||||
unsigned int ldrbs : 1;
|
||||
|
||||
//! RA load interrupt.
|
||||
unsigned int ldras : 1;
|
||||
|
||||
//! RC compare interrupt.
|
||||
unsigned int cpcs : 1;
|
||||
|
||||
//! RB compare interrupt.
|
||||
unsigned int cpbs : 1;
|
||||
|
||||
//! RA compare interrupt.
|
||||
unsigned int cpas : 1;
|
||||
|
||||
//! Load overrun interrupt.
|
||||
unsigned int lovrs : 1;
|
||||
|
||||
//! Counter overflow interrupt.
|
||||
unsigned int covfs : 1;
|
||||
} tc_interrupt_t;
|
||||
|
||||
//! Parameters when initializing a timer/counter in capture mode.
|
||||
typedef struct
|
||||
{
|
||||
//! Channel to initialize.
|
||||
unsigned int channel ;
|
||||
|
||||
unsigned int :12;
|
||||
|
||||
//! RB loading selection:\n
|
||||
//! - \ref TC_SEL_NO_EDGE;\n
|
||||
//! - \ref TC_SEL_RISING_EDGE;\n
|
||||
//! - \ref TC_SEL_FALLING_EDGE;\n
|
||||
//! - \ref TC_SEL_EACH_EDGE.
|
||||
unsigned int ldrb : 2;
|
||||
|
||||
//! RA loading selection:\n
|
||||
//! - \ref TC_SEL_NO_EDGE;\n
|
||||
//! - \ref TC_SEL_RISING_EDGE;\n
|
||||
//! - \ref TC_SEL_FALLING_EDGE;\n
|
||||
//! - \ref TC_SEL_EACH_EDGE.
|
||||
unsigned int ldra : 2;
|
||||
|
||||
unsigned int : 1;
|
||||
|
||||
//! RC compare trigger enable:\n
|
||||
//! - \ref TC_NO_TRIGGER_COMPARE_RC;\n
|
||||
//! - \ref TC_TRIGGER_COMPARE_RC.
|
||||
unsigned int cpctrg : 1;
|
||||
|
||||
unsigned int : 3;
|
||||
|
||||
//! TIOA or TIOB external trigger selection:\n
|
||||
//! - \ref TC_EXT_TRIG_SEL_TIOA;\n
|
||||
//! - \ref TC_EXT_TRIG_SEL_TIOB.
|
||||
unsigned int abetrg : 1;
|
||||
|
||||
//! External trigger edge selection:\n
|
||||
//! - \ref TC_SEL_NO_EDGE;\n
|
||||
//! - \ref TC_SEL_RISING_EDGE;\n
|
||||
//! - \ref TC_SEL_FALLING_EDGE;\n
|
||||
//! - \ref TC_SEL_EACH_EDGE.
|
||||
unsigned int etrgedg : 2;
|
||||
|
||||
//! Counter clock disable with RB loading:\n
|
||||
//! - \c FALSE;\n
|
||||
//! - \c TRUE.
|
||||
unsigned int ldbdis : 1;
|
||||
|
||||
//! Counter clock stopped with RB loading:\n
|
||||
//! - \c FALSE;\n
|
||||
//! - \c TRUE.
|
||||
unsigned int ldbstop : 1;
|
||||
|
||||
//! Burst signal selection:\n
|
||||
//! - \ref TC_BURST_NOT_GATED;\n
|
||||
//! - \ref TC_BURST_CLK_AND_XC0;\n
|
||||
//! - \ref TC_BURST_CLK_AND_XC1;\n
|
||||
//! - \ref TC_BURST_CLK_AND_XC2.
|
||||
unsigned int burst : 2;
|
||||
|
||||
//! Clock invert:\n
|
||||
//! - \ref TC_CLOCK_RISING_EDGE;\n
|
||||
//! - \ref TC_CLOCK_FALLING_EDGE.
|
||||
unsigned int clki : 1;
|
||||
|
||||
//! Clock selection:\n
|
||||
//! - \ref TC_CLOCK_SOURCE_TC1;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_TC2;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_TC3;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_TC4;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_TC5;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_XC0;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_XC1;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_XC2.
|
||||
unsigned int tcclks : 3;
|
||||
} tc_capture_opt_t;
|
||||
|
||||
//! Parameters when initializing a timer/counter in waveform mode.
|
||||
typedef struct
|
||||
{
|
||||
//! Channel to initialize.
|
||||
unsigned int channel ;
|
||||
|
||||
//! Software trigger effect on TIOB:\n
|
||||
//! - \ref TC_EVT_EFFECT_NOOP;\n
|
||||
//! - \ref TC_EVT_EFFECT_SET;\n
|
||||
//! - \ref TC_EVT_EFFECT_CLEAR;\n
|
||||
//! - \ref TC_EVT_EFFECT_TOGGLE.
|
||||
unsigned int bswtrg : 2;
|
||||
|
||||
//! External event effect on TIOB:\n
|
||||
//! - \ref TC_EVT_EFFECT_NOOP;\n
|
||||
//! - \ref TC_EVT_EFFECT_SET;\n
|
||||
//! - \ref TC_EVT_EFFECT_CLEAR;\n
|
||||
//! - \ref TC_EVT_EFFECT_TOGGLE.
|
||||
unsigned int beevt : 2;
|
||||
|
||||
//! RC compare effect on TIOB:\n
|
||||
//! - \ref TC_EVT_EFFECT_NOOP;\n
|
||||
//! - \ref TC_EVT_EFFECT_SET;\n
|
||||
//! - \ref TC_EVT_EFFECT_CLEAR;\n
|
||||
//! - \ref TC_EVT_EFFECT_TOGGLE.
|
||||
unsigned int bcpc : 2;
|
||||
|
||||
//! RB compare effect on TIOB:\n
|
||||
//! - \ref TC_EVT_EFFECT_NOOP;\n
|
||||
//! - \ref TC_EVT_EFFECT_SET;\n
|
||||
//! - \ref TC_EVT_EFFECT_CLEAR;\n
|
||||
//! - \ref TC_EVT_EFFECT_TOGGLE.
|
||||
unsigned int bcpb : 2;
|
||||
|
||||
//! Software trigger effect on TIOA:\n
|
||||
//! - \ref TC_EVT_EFFECT_NOOP;\n
|
||||
//! - \ref TC_EVT_EFFECT_SET;\n
|
||||
//! - \ref TC_EVT_EFFECT_CLEAR;\n
|
||||
//! - \ref TC_EVT_EFFECT_TOGGLE.
|
||||
unsigned int aswtrg : 2;
|
||||
|
||||
//! External event effect on TIOA:\n
|
||||
//! - \ref TC_EVT_EFFECT_NOOP;\n
|
||||
//! - \ref TC_EVT_EFFECT_SET;\n
|
||||
//! - \ref TC_EVT_EFFECT_CLEAR;\n
|
||||
//! - \ref TC_EVT_EFFECT_TOGGLE.
|
||||
unsigned int aeevt : 2;
|
||||
|
||||
//! RC compare effect on TIOA:\n
|
||||
//! - \ref TC_EVT_EFFECT_NOOP;\n
|
||||
//! - \ref TC_EVT_EFFECT_SET;\n
|
||||
//! - \ref TC_EVT_EFFECT_CLEAR;\n
|
||||
//! - \ref TC_EVT_EFFECT_TOGGLE.
|
||||
unsigned int acpc : 2;
|
||||
|
||||
//! RA compare effect on TIOA:\n
|
||||
//! - \ref TC_EVT_EFFECT_NOOP;\n
|
||||
//! - \ref TC_EVT_EFFECT_SET;\n
|
||||
//! - \ref TC_EVT_EFFECT_CLEAR;\n
|
||||
//! - \ref TC_EVT_EFFECT_TOGGLE.
|
||||
unsigned int acpa : 2;
|
||||
|
||||
unsigned int : 1;
|
||||
|
||||
//! Waveform selection:\n
|
||||
//! - \ref TC_WAVEFORM_SEL_UP_MODE;\n
|
||||
//! - \ref TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER;\n
|
||||
//! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE;\n
|
||||
//! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER.
|
||||
unsigned int wavsel : 2;
|
||||
|
||||
//! External event trigger enable:\n
|
||||
//! - \c FALSE;\n
|
||||
//! - \c TRUE.
|
||||
unsigned int enetrg : 1;
|
||||
|
||||
//! External event selection:\n
|
||||
//! - \ref TC_EXT_EVENT_SEL_TIOB_INPUT;\n
|
||||
//! - \ref TC_EXT_EVENT_SEL_XC0_OUTPUT;\n
|
||||
//! - \ref TC_EXT_EVENT_SEL_XC1_OUTPUT;\n
|
||||
//! - \ref TC_EXT_EVENT_SEL_XC2_OUTPUT.
|
||||
unsigned int eevt : 2;
|
||||
|
||||
//! External event edge selection:\n
|
||||
//! - \ref TC_SEL_NO_EDGE;\n
|
||||
//! - \ref TC_SEL_RISING_EDGE;\n
|
||||
//! - \ref TC_SEL_FALLING_EDGE;\n
|
||||
//! - \ref TC_SEL_EACH_EDGE.
|
||||
unsigned int eevtedg : 2;
|
||||
|
||||
//! Counter clock disable with RC compare:\n
|
||||
//! - \c FALSE;\n
|
||||
//! - \c TRUE.
|
||||
unsigned int cpcdis : 1;
|
||||
|
||||
//! Counter clock stopped with RC compare:\n
|
||||
//! - \c FALSE;\n
|
||||
//! - \c TRUE.
|
||||
unsigned int cpcstop : 1;
|
||||
|
||||
//! Burst signal selection:\n
|
||||
//! - \ref TC_BURST_NOT_GATED;\n
|
||||
//! - \ref TC_BURST_CLK_AND_XC0;\n
|
||||
//! - \ref TC_BURST_CLK_AND_XC1;\n
|
||||
//! - \ref TC_BURST_CLK_AND_XC2.
|
||||
unsigned int burst : 2;
|
||||
|
||||
//! Clock invert:\n
|
||||
//! - \ref TC_CLOCK_RISING_EDGE;\n
|
||||
//! - \ref TC_CLOCK_FALLING_EDGE.
|
||||
unsigned int clki : 1;
|
||||
|
||||
//! Clock selection:\n
|
||||
//! - \ref TC_CLOCK_SOURCE_TC1;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_TC2;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_TC3;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_TC4;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_TC5;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_XC0;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_XC1;\n
|
||||
//! - \ref TC_CLOCK_SOURCE_XC2.
|
||||
unsigned int tcclks : 3;
|
||||
} tc_waveform_opt_t;
|
||||
|
||||
|
||||
/*! \brief Reads timer/counter interrupt settings.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
*
|
||||
* \retval >=0 The interrupt enable configuration organized according to \ref tc_interrupt_t.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel);
|
||||
|
||||
/*! \brief Enables various timer/counter interrupts.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
* \param bitfield The interrupt enable configuration.
|
||||
*
|
||||
* \retval 0 Success.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield);
|
||||
|
||||
/*! \brief Selects which external clock to use and how to configure it.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
* \param ext_clk_sig_src External clock signal selection:
|
||||
* \arg \c TC_CH0_EXT_CLK0_SRC_TCLK0;
|
||||
* \arg \c TC_CH0_EXT_CLK0_SRC_NO_CLK;
|
||||
* \arg \c TC_CH0_EXT_CLK0_SRC_TIOA1;
|
||||
* \arg \c TC_CH0_EXT_CLK0_SRC_TIOA2;
|
||||
* \arg \c TC_CH1_EXT_CLK1_SRC_TCLK1;
|
||||
* \arg \c TC_CH1_EXT_CLK1_SRC_NO_CLK;
|
||||
* \arg \c TC_CH1_EXT_CLK1_SRC_TIOA0;
|
||||
* \arg \c TC_CH1_EXT_CLK1_SRC_TIOA2;
|
||||
* \arg \c TC_CH2_EXT_CLK2_SRC_TCLK2;
|
||||
* \arg \c TC_CH2_EXT_CLK2_SRC_NO_CLK;
|
||||
* \arg \c TC_CH2_EXT_CLK2_SRC_TIOA0;
|
||||
* \arg \c TC_CH2_EXT_CLK2_SRC_TIOA1.
|
||||
*
|
||||
* \retval 0 Success.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src);
|
||||
|
||||
/*! \brief Sets options for timer/counter capture initialization.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param opt Options for capture mode.
|
||||
*
|
||||
* \retval 0 Success.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt);
|
||||
|
||||
/*! \brief Sets options for timer/counter waveform initialization.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param opt Options for waveform generation.
|
||||
*
|
||||
* \retval 0 Success.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt);
|
||||
|
||||
/*! \brief Starts a timer/counter.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
*
|
||||
* \retval 0 Success.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_start(volatile avr32_tc_t *tc, unsigned int channel);
|
||||
|
||||
/*! \brief Stops a timer/counter.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
*
|
||||
* \retval 0 Success.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_stop(volatile avr32_tc_t *tc, unsigned int channel);
|
||||
|
||||
/*! \brief Performs a software trigger: the counter is reset and the clock is started.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
*
|
||||
* \retval 0 Success.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel);
|
||||
|
||||
/*! \brief Asserts a SYNC signal to generate a software trigger and reset all channels.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
*/
|
||||
extern void tc_sync_trigger(volatile avr32_tc_t *tc);
|
||||
|
||||
/*! \brief Reads the status register.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
*
|
||||
* \retval >=0 Status register value.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel);
|
||||
|
||||
/*! \brief Reads the channel's TC counter and returns the value.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
*
|
||||
* \retval >=0 TC counter value.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel);
|
||||
|
||||
/*! \brief Reads the channel's RA register and returns the value.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
*
|
||||
* \retval >=0 RA register value.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel);
|
||||
|
||||
/*! \brief Reads the channel's RB register and returns the value.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
*
|
||||
* \retval >=0 RB register value.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel);
|
||||
|
||||
/*! \brief Reads the channel's RC register and returns the value.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
*
|
||||
* \retval >=0 RC register value.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel);
|
||||
|
||||
/*! \brief Writes a value to the channel's RA register.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
* \param value Value to write to the RA register.
|
||||
*
|
||||
* \retval >=0 Written value.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value);
|
||||
|
||||
/*! \brief Writes a value to the channel's RB register.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
* \param value Value to write to the RB register.
|
||||
*
|
||||
* \retval >=0 Written value.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value);
|
||||
|
||||
/*! \brief Writes a value to the channel's RC register.
|
||||
*
|
||||
* \param tc Pointer to the TC instance to access.
|
||||
* \param channel The TC instance channel to access.
|
||||
* \param value Value to write to the RC register.
|
||||
*
|
||||
* \retval >=0 Written value.
|
||||
* \retval TC_INVALID_ARGUMENT Invalid argument(s).
|
||||
*/
|
||||
extern int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value);
|
||||
|
||||
|
||||
#endif // _TC_H_
|
||||
437
Demo/AVR32_UC3/DRIVERS/USART/usart.c
Normal file
437
Demo/AVR32_UC3/DRIVERS/USART/usart.c
Normal file
|
|
@ -0,0 +1,437 @@
|
|||
/*This file is prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief USART driver for AVR32 UC3.
|
||||
*
|
||||
* This file contains basic functions for the AVR32 USART, with support for all
|
||||
* modes, settings and clock speeds.
|
||||
*
|
||||
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
|
||||
* - Supported devices: All AVR32 devices with a USART module can be used.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#include "usart.h"
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/*! \name Private Functions
|
||||
*/
|
||||
//! @{
|
||||
|
||||
|
||||
/*! \brief Checks if the USART is in multidrop mode.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
*
|
||||
* \return \c 1 if the USART is in multidrop mode, otherwise \c 0.
|
||||
*/
|
||||
#if __GNUC__
|
||||
__attribute__((__always_inline__))
|
||||
#endif
|
||||
static __inline__ int usart_mode_is_multidrop(volatile avr32_usart_t *usart)
|
||||
{
|
||||
return ((usart->mr >> AVR32_USART_MR_PAR_OFFSET) & AVR32_USART_MR_PAR_MULTI) == AVR32_USART_MR_PAR_MULTI;
|
||||
}
|
||||
|
||||
|
||||
/*! \brief Calculates a clock divider (\e CD) that gets the USART as close to a
|
||||
* wanted baudrate as possible.
|
||||
*
|
||||
* Baudrate calculation:
|
||||
* \f$ baudrate = \frac{Selected Clock}{16 \times CD} \f$ with 16x oversampling or
|
||||
* \f$ baudrate = \frac{Selected Clock}{8 \times CD} \f$ with 8x oversampling.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param baudrate Wanted baudrate.
|
||||
* \param pba_hz USART module input clock frequency (PBA clock, Hz).
|
||||
*
|
||||
* \retval USART_SUCCESS Baudrate successfully initialized.
|
||||
* \retval USART_INVALID_INPUT Wanted baudrate is impossible with given clock speed.
|
||||
*/
|
||||
|
||||
static int usart_set_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, long pba_hz)
|
||||
{
|
||||
// Clock divider.
|
||||
int cd;
|
||||
|
||||
// Baudrate calculation.
|
||||
if (baudrate < pba_hz / 16)
|
||||
{
|
||||
// Use 16x oversampling.
|
||||
usart->mr &=~ AVR32_USART_MR_OVER_MASK;
|
||||
cd = pba_hz / (16 * baudrate);
|
||||
|
||||
if ((cd >65535)) return USART_INVALID_INPUT;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Use 8x oversampling.
|
||||
usart->mr |= AVR32_USART_MR_OVER_MASK;
|
||||
cd = pba_hz / (8 * baudrate);
|
||||
|
||||
if ((cd < 1)||(cd >65535)) return USART_INVALID_INPUT;
|
||||
}
|
||||
usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;
|
||||
|
||||
return USART_SUCCESS;
|
||||
}
|
||||
|
||||
//! @}
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/*! \name Initialization Functions
|
||||
*/
|
||||
//! @{
|
||||
|
||||
|
||||
void usart_reset(volatile avr32_usart_t *usart)
|
||||
{
|
||||
// Disable all USART interrupts.
|
||||
// Interrupts needed should be set explicitly on every reset.
|
||||
usart->idr = 0xFFFFFFFF;
|
||||
|
||||
// Reset mode and other registers that could cause unpredictable behavior after reset.
|
||||
usart->mr = 0;
|
||||
usart->rtor = 0;
|
||||
usart->ttgr = 0;
|
||||
|
||||
// Shutdown TX and RX (will be re-enabled when setup has successfully completed),
|
||||
// reset status bits and turn off DTR and RTS.
|
||||
usart->cr = AVR32_USART_CR_RSTRX_MASK |
|
||||
AVR32_USART_CR_RSTTX_MASK |
|
||||
AVR32_USART_CR_RSTSTA_MASK |
|
||||
AVR32_USART_CR_RSTIT_MASK |
|
||||
AVR32_USART_CR_RSTNACK_MASK |
|
||||
AVR32_USART_CR_DTRDIS_MASK |
|
||||
AVR32_USART_CR_RTSDIS_MASK;
|
||||
}
|
||||
|
||||
|
||||
int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
|
||||
{
|
||||
// Reset the USART and shutdown TX and RX.
|
||||
usart_reset(usart);
|
||||
|
||||
// Check input values.
|
||||
if (!opt) // Null pointer.
|
||||
return USART_INVALID_INPUT;
|
||||
if (opt->charlength < 5 || opt->charlength > 9 ||
|
||||
opt->paritytype > 7 ||
|
||||
opt->stopbits > 2 + 255 ||
|
||||
opt->channelmode > 3)
|
||||
return USART_INVALID_INPUT;
|
||||
|
||||
if (usart_set_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)
|
||||
return USART_INVALID_INPUT;
|
||||
|
||||
if (opt->charlength == 9)
|
||||
{
|
||||
// Character length set to 9 bits. MODE9 dominates CHRL.
|
||||
usart->mr |= AVR32_USART_MR_MODE9_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
// CHRL gives the character length (- 5) when MODE9 = 0.
|
||||
usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
|
||||
}
|
||||
|
||||
usart->mr |= (opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET) |
|
||||
(opt->paritytype << AVR32_USART_MR_PAR_OFFSET);
|
||||
|
||||
if (opt->stopbits > USART_2_STOPBITS)
|
||||
{
|
||||
// Set two stop bits
|
||||
usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;
|
||||
// and a timeguard period gives the rest.
|
||||
usart->ttgr = opt->stopbits - USART_2_STOPBITS;
|
||||
}
|
||||
else
|
||||
// Insert 1, 1.5 or 2 stop bits.
|
||||
usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;
|
||||
|
||||
// Setup complete; enable communication.
|
||||
// Enable input and output.
|
||||
usart->cr |= AVR32_USART_CR_TXEN_MASK |
|
||||
AVR32_USART_CR_RXEN_MASK;
|
||||
|
||||
return USART_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
|
||||
{
|
||||
// First: Setup standard RS232.
|
||||
if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
|
||||
return USART_INVALID_INPUT;
|
||||
|
||||
// Clear previous mode.
|
||||
usart->mr &= ~AVR32_USART_MR_MODE_MASK;
|
||||
// Hardware handshaking.
|
||||
usart->mr |= USART_MODE_HW_HSH << AVR32_USART_MR_MODE_OFFSET;
|
||||
|
||||
return USART_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt,
|
||||
long pba_hz, unsigned char irda_filter)
|
||||
{
|
||||
// First: Setup standard RS232.
|
||||
if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
|
||||
return USART_INVALID_INPUT;
|
||||
|
||||
// Set IrDA counter.
|
||||
usart->ifr = irda_filter;
|
||||
|
||||
// Activate "low-pass filtering" of input.
|
||||
usart->mr |= AVR32_USART_MR_FILTER_MASK;
|
||||
|
||||
return USART_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
|
||||
{
|
||||
// First: Setup standard RS232.
|
||||
if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
|
||||
return USART_INVALID_INPUT;
|
||||
|
||||
// Clear previous mode.
|
||||
usart->mr &= ~AVR32_USART_MR_MODE_MASK;
|
||||
// Set modem mode.
|
||||
usart->mr |= USART_MODE_MODEM << AVR32_USART_MR_MODE_OFFSET;
|
||||
|
||||
return USART_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
|
||||
{
|
||||
// First: Setup standard RS232.
|
||||
if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
|
||||
return USART_INVALID_INPUT;
|
||||
|
||||
// Clear previous mode.
|
||||
usart->mr &= ~AVR32_USART_MR_MODE_MASK;
|
||||
// Set RS485 mode.
|
||||
usart->mr |= USART_MODE_RS485 << AVR32_USART_MR_MODE_OFFSET;
|
||||
|
||||
return USART_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
int usart_init_iso7816(volatile avr32_usart_t *usart, const iso7816_options_t *opt, int t, long pba_hz)
|
||||
{
|
||||
// Reset the USART and shutdown TX and RX.
|
||||
usart_reset(usart);
|
||||
|
||||
// Check input values.
|
||||
if (!opt) // Null pointer.
|
||||
return USART_INVALID_INPUT;
|
||||
|
||||
if (t == 0)
|
||||
{
|
||||
// Set USART mode to ISO7816, T=0.
|
||||
// The T=0 protocol always uses 2 stop bits.
|
||||
usart->mr = (USART_MODE_ISO7816_T0 << AVR32_USART_MR_MODE_OFFSET) |
|
||||
(AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET) |
|
||||
(opt->bit_order << AVR32_USART_MR_MSBF_OFFSET); // Allow MSBF in T=0.
|
||||
}
|
||||
else if (t == 1)
|
||||
{
|
||||
// Only LSB first in the T=1 protocol.
|
||||
// max_iterations field is only used in T=0 mode.
|
||||
if (opt->bit_order != 0 ||
|
||||
opt->max_iterations != 0)
|
||||
return USART_INVALID_INPUT;
|
||||
// Set USART mode to ISO7816, T=1.
|
||||
// The T=1 protocol always uses 1 stop bit.
|
||||
usart->mr = (USART_MODE_ISO7816_T1 << AVR32_USART_MR_MODE_OFFSET) |
|
||||
(AVR32_USART_MR_NBSTOP_1 << AVR32_USART_MR_NBSTOP_OFFSET);
|
||||
}
|
||||
else
|
||||
return USART_INVALID_INPUT;
|
||||
|
||||
if (usart_set_baudrate(usart, opt->iso7816_hz, pba_hz) == USART_INVALID_INPUT)
|
||||
return USART_INVALID_INPUT;
|
||||
|
||||
// Set FIDI register: bit rate = selected clock/FI_DI_ratio/16.
|
||||
usart->fidi = opt->fidi_ratio;
|
||||
// Set ISO7816 spesific options in the MODE register.
|
||||
usart->mr |= (opt->inhibit_nack << AVR32_USART_MR_INACK_OFFSET) |
|
||||
(opt->dis_suc_nack << AVR32_USART_MR_DSNACK_OFFSET) |
|
||||
(opt->max_iterations << AVR32_USART_MR_MAX_ITERATION_OFFSET) |
|
||||
AVR32_USART_MR_CLKO_MASK; // Enable clock output.
|
||||
|
||||
// Setup complete; enable input.
|
||||
// Leave TX disabled for now.
|
||||
usart->cr |= AVR32_USART_CR_RXEN_MASK;
|
||||
|
||||
return USART_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
//! @}
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/*! \name Transmit/Receive Functions
|
||||
*/
|
||||
//! @{
|
||||
|
||||
|
||||
int usart_send_address(volatile avr32_usart_t *usart, int address)
|
||||
{
|
||||
// Check if USART is in multidrop / RS485 mode.
|
||||
if (!usart_mode_is_multidrop(usart)) return USART_MODE_FAULT;
|
||||
|
||||
// Prepare to send an address.
|
||||
usart->cr |= AVR32_USART_CR_SENDA_MASK;
|
||||
|
||||
// Write the address to TX.
|
||||
usart_bw_write_char(usart, address);
|
||||
|
||||
return USART_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
int usart_write_char(volatile avr32_usart_t *usart, int c)
|
||||
{
|
||||
if (usart->csr & AVR32_USART_CSR_TXRDY_MASK)
|
||||
{
|
||||
usart->thr = c;
|
||||
return USART_SUCCESS;
|
||||
}
|
||||
else
|
||||
return USART_TX_BUSY;
|
||||
}
|
||||
|
||||
|
||||
int usart_putchar(volatile avr32_usart_t *usart, int c)
|
||||
{
|
||||
int timeout = USART_DEFAULT_TIMEOUT;
|
||||
|
||||
if (c == '\n')
|
||||
{
|
||||
do
|
||||
{
|
||||
if (!timeout--) return USART_FAILURE;
|
||||
} while (usart_write_char(usart, '\r') != USART_SUCCESS);
|
||||
|
||||
timeout = USART_DEFAULT_TIMEOUT;
|
||||
}
|
||||
|
||||
do
|
||||
{
|
||||
if (!timeout--) return USART_FAILURE;
|
||||
} while (usart_write_char(usart, c) != USART_SUCCESS);
|
||||
|
||||
return USART_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
int usart_read_char(volatile avr32_usart_t *usart, int *c)
|
||||
{
|
||||
// Check for errors: frame, parity and overrun. In RS485 mode, a parity error
|
||||
// would mean that an address char has been received.
|
||||
if (usart->csr & (AVR32_USART_CSR_OVRE_MASK |
|
||||
AVR32_USART_CSR_FRAME_MASK |
|
||||
AVR32_USART_CSR_PARE_MASK))
|
||||
return USART_RX_ERROR;
|
||||
|
||||
// No error; if we really did receive a char, read it and return SUCCESS.
|
||||
if (usart->csr & AVR32_USART_CSR_RXRDY_MASK)
|
||||
{
|
||||
*c = (unsigned short)usart->rhr;
|
||||
return USART_SUCCESS;
|
||||
}
|
||||
else
|
||||
return USART_RX_EMPTY;
|
||||
}
|
||||
|
||||
|
||||
int usart_getchar(volatile avr32_usart_t *usart)
|
||||
{
|
||||
int c, ret;
|
||||
|
||||
while ((ret = usart_read_char(usart, &c)) == USART_RX_EMPTY);
|
||||
|
||||
if (ret == USART_RX_ERROR)
|
||||
return USART_FAILURE;
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
|
||||
void usart_write_line(volatile avr32_usart_t *usart, const char *string)
|
||||
{
|
||||
while (*string != '\0')
|
||||
usart_putchar(usart, *string++);
|
||||
}
|
||||
|
||||
|
||||
int usart_get_echo_line(volatile avr32_usart_t *usart)
|
||||
{
|
||||
int rx_char;
|
||||
int retval = USART_SUCCESS;
|
||||
|
||||
while (1)
|
||||
{
|
||||
rx_char = usart_getchar(usart);
|
||||
if (rx_char == USART_FAILURE)
|
||||
{
|
||||
usart_write_line(usart, "Error!!!\n");
|
||||
break;
|
||||
}
|
||||
if (rx_char == '\x03')
|
||||
{
|
||||
retval = USART_FAILURE;
|
||||
break;
|
||||
}
|
||||
usart_putchar(usart, rx_char);
|
||||
if (rx_char == '\r')
|
||||
{
|
||||
usart_putchar(usart, '\n');
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
//! @}
|
||||
419
Demo/AVR32_UC3/DRIVERS/USART/usart.h
Normal file
419
Demo/AVR32_UC3/DRIVERS/USART/usart.h
Normal file
|
|
@ -0,0 +1,419 @@
|
|||
/*This file is prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief USART driver for AVR32 UC3.
|
||||
*
|
||||
* This file contains basic functions for the AVR32 USART, with support for all
|
||||
* modes, settings and clock speeds.
|
||||
*
|
||||
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
|
||||
* - Supported devices: All AVR32 devices with a USART module can be used.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _USART_H_
|
||||
#define _USART_H_
|
||||
|
||||
#if __GNUC__
|
||||
# include <avr32/io.h>
|
||||
#elif __ICCAVR32__
|
||||
# include <avr32/iouc3a0512.h>
|
||||
#else
|
||||
# error Unknown compiler
|
||||
#endif
|
||||
|
||||
#include "compiler.h"
|
||||
|
||||
|
||||
/*! \name Return Values
|
||||
*/
|
||||
//! @{
|
||||
#define USART_SUCCESS 0 //!< Successful completion.
|
||||
#define USART_FAILURE -1 //!< Failure because of some unspecified reason.
|
||||
#define USART_INVALID_INPUT 1 //!< Input value out of range.
|
||||
#define USART_INVALID_ARGUMENT -1 //!< Argument value out of range.
|
||||
#define USART_TX_BUSY 2 //!< Transmitter was busy.
|
||||
#define USART_RX_EMPTY 3 //!< Nothing was received.
|
||||
#define USART_RX_ERROR 4 //!< Transmission error occurred.
|
||||
#define USART_MODE_FAULT 5 //!< USART not in the appropriate mode.
|
||||
//! @}
|
||||
|
||||
//! Default time-out value (number of attempts).
|
||||
#define USART_DEFAULT_TIMEOUT 10000
|
||||
|
||||
/*! \name Parity Settings
|
||||
*/
|
||||
//! @{
|
||||
#define USART_EVEN_PARITY AVR32_USART_MR_PAR_EVEN //!< Use even parity on character transmission.
|
||||
#define USART_ODD_PARITY AVR32_USART_MR_PAR_ODD //!< Use odd parity on character transmission.
|
||||
#define USART_SPACE_PARITY AVR32_USART_MR_PAR_SPACE //!< Use a space as parity bit.
|
||||
#define USART_MARK_PARITY AVR32_USART_MR_PAR_MARK //!< Use a mark as parity bit.
|
||||
#define USART_NO_PARITY AVR32_USART_MR_PAR_NONE //!< Don't use a parity bit.
|
||||
#define USART_MULTIDROP_PARITY AVR32_USART_MR_PAR_MULTI //!< Parity bit is used to flag address characters.
|
||||
//! @}
|
||||
|
||||
/*! \name Operating Modes
|
||||
*/
|
||||
//! @{
|
||||
#define USART_MODE_NORMAL AVR32_USART_MR_MODE_NORMAL //!< Normal RS232 mode.
|
||||
#define USART_MODE_RS485 AVR32_USART_MR_MODE_RS485 //!< RS485 mode.
|
||||
#define USART_MODE_HW_HSH AVR32_USART_MR_MODE_HARDWARE //!< RS232 mode with hardware handshaking.
|
||||
#define USART_MODE_MODEM AVR32_USART_MR_MODE_MODEM //!< Modem mode.
|
||||
#define USART_MODE_ISO7816_T0 AVR32_USART_MR_MODE_ISO7816_T0 //!< ISO7816, T = 0 mode.
|
||||
#define USART_MODE_ISO7816_T1 AVR32_USART_MR_MODE_ISO7816_T1 //!< ISO7816, T = 1 mode.
|
||||
#define USART_MODE_IRDA AVR32_USART_MR_MODE_IRDA //!< IrDA mode.
|
||||
#define USART_MODE_SW_HSH AVR32_USART_MR_MODE_SOFTWARE //!< RS232 mode with software handshaking.
|
||||
//! @}
|
||||
|
||||
/*! \name Channel Modes
|
||||
*/
|
||||
//! @{
|
||||
#define USART_NORMAL_CHMODE AVR32_USART_MR_CHMODE_NORMAL //!< Normal communication.
|
||||
#define USART_AUTO_ECHO AVR32_USART_MR_CHMODE_ECHO //!< Echo data.
|
||||
#define USART_LOCAL_LOOPBACK AVR32_USART_MR_CHMODE_LOCAL_LOOP //!< Local loopback.
|
||||
#define USART_REMOTE_LOOPBACK AVR32_USART_MR_CHMODE_REMOTE_LOOP //!< Remote loopback.
|
||||
//! @}
|
||||
|
||||
/*! \name Stop Bits Settings
|
||||
*/
|
||||
//! @{
|
||||
#define USART_1_STOPBIT AVR32_USART_MR_NBSTOP_1 //!< Use 1 stop bit.
|
||||
#define USART_1_5_STOPBITS AVR32_USART_MR_NBSTOP_1_5 //!< Use 1.5 stop bits.
|
||||
#define USART_2_STOPBITS AVR32_USART_MR_NBSTOP_2 //!< Use 2 stop bits (for more, just give the number of bits).
|
||||
//! @}
|
||||
|
||||
|
||||
//! Input parameters when initializing RS232 and similar modes.
|
||||
typedef struct
|
||||
{
|
||||
//! Set baudrate of the USART.
|
||||
unsigned long baudrate;
|
||||
|
||||
//! Number of bits to transmit as a character (5 to 9).
|
||||
unsigned char charlength;
|
||||
|
||||
//! How to calculate the parity bit: \ref USART_EVEN_PARITY, \ref USART_ODD_PARITY,
|
||||
//! \ref USART_SPACE_PARITY, \ref USART_MARK_PARITY, \ref USART_NO_PARITY or
|
||||
//! \ref USART_MULTIDROP_PARITY.
|
||||
unsigned char paritytype;
|
||||
|
||||
//! Number of stop bits between two characters: \ref USART_1_STOPBIT,
|
||||
//! \ref USART_1_5_STOPBITS, \ref USART_2_STOPBITS or any number from 3 to 257
|
||||
//! which will result in a time guard period of that length between characters.
|
||||
unsigned short stopbits;
|
||||
|
||||
//! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO,
|
||||
//! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK.
|
||||
unsigned char channelmode;
|
||||
} usart_options_t;
|
||||
|
||||
//! Input parameters when initializing ISO7816 modes.
|
||||
typedef struct
|
||||
{
|
||||
//! Set the frequency of the ISO7816 clock.
|
||||
unsigned long iso7816_hz;
|
||||
|
||||
//! The number of ISO7816 clock ticks in every bit period (1 to 2047, 0 = disable clock).
|
||||
//! Bit rate = \ref iso7816_hz / \ref fidi_ratio.
|
||||
unsigned short fidi_ratio;
|
||||
|
||||
//! Inhibit Non Acknowledge:\n
|
||||
//! - 0: the NACK is generated;\n
|
||||
//! - 1: the NACK is not generated.
|
||||
//!
|
||||
//! \note This bit will be used only in ISO7816 mode, protocol T = 0 receiver.
|
||||
int inhibit_nack;
|
||||
|
||||
//! Disable successive NACKs.
|
||||
//! Successive parity errors are counted up to the value in the \ref max_iterations field.
|
||||
//! These parity errors generate a NACK on the ISO line. As soon as this value is reached,
|
||||
//! no addititional NACK is sent on the ISO line. The ITERATION flag is asserted.
|
||||
int dis_suc_nack;
|
||||
|
||||
//! Max number of repetitions (0 to 7).
|
||||
unsigned char max_iterations;
|
||||
|
||||
//! Bit order in transmitted characters:\n
|
||||
//! - 0: LSB first;\n
|
||||
//! - 1: MSB first.
|
||||
int bit_order;
|
||||
} iso7816_options_t;
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/*! \name Initialization Functions
|
||||
*/
|
||||
//! @{
|
||||
|
||||
/*! \brief Resets the USART and disables TX and RX.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
*/
|
||||
extern void usart_reset(volatile avr32_usart_t *usart);
|
||||
|
||||
/*! \brief Sets up the USART to use the standard RS232 protocol.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param opt Options needed to set up RS232 communication (see \ref usart_options_t).
|
||||
* \param pba_hz USART module input clock frequency (PBA clock, Hz).
|
||||
*
|
||||
* \retval USART_SUCCESS Mode successfully initialized.
|
||||
* \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.
|
||||
*/
|
||||
extern int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);
|
||||
|
||||
/*! \brief Sets up the USART to use hardware handshaking.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param opt Options needed to set up RS232 communication (see \ref usart_options_t).
|
||||
* \param pba_hz USART module input clock frequency (PBA clock, Hz).
|
||||
*
|
||||
* \retval USART_SUCCESS Mode successfully initialized.
|
||||
* \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.
|
||||
*
|
||||
* \note \ref usart_init_rs232 does not need to be invoked before this function.
|
||||
*/
|
||||
extern int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);
|
||||
|
||||
/*! \brief Sets up the USART to use the IrDA protocol.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param opt Options needed to set up RS232 communication (see \ref usart_options_t).
|
||||
* \param pba_hz USART module input clock frequency (PBA clock, Hz).
|
||||
* \param irda_filter Counter used to distinguish received ones from zeros.
|
||||
*
|
||||
* \retval USART_SUCCESS Mode successfully initialized.
|
||||
* \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.
|
||||
*/
|
||||
extern int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt,
|
||||
long pba_hz, unsigned char irda_filter);
|
||||
|
||||
/*! \brief Sets up the USART to use the modem protocol, activating dedicated inputs/outputs.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param opt Options needed to set up RS232 communication (see \ref usart_options_t).
|
||||
* \param pba_hz USART module input clock frequency (PBA clock, Hz).
|
||||
*
|
||||
* \retval USART_SUCCESS Mode successfully initialized.
|
||||
* \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.
|
||||
*/
|
||||
extern int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);
|
||||
|
||||
/*! \brief Sets up the USART to use the RS485 protocol.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param opt Options needed to set up RS232 communication (see \ref usart_options_t).
|
||||
* \param pba_hz USART module input clock frequency (PBA clock, Hz).
|
||||
*
|
||||
* \retval USART_SUCCESS Mode successfully initialized.
|
||||
* \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.
|
||||
*/
|
||||
extern int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);
|
||||
|
||||
/*! \brief Sets up the USART to use the ISO7816 T=0 or T=1 smartcard protocols.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param opt Options needed to set up ISO7816 communication (see \ref iso7816_options_t).
|
||||
* \param t ISO7816 mode to use (T=0 or T=1).
|
||||
* \param pba_hz USART module input clock frequency (PBA clock, Hz).
|
||||
*
|
||||
* \retval USART_SUCCESS Mode successfully initialized.
|
||||
* \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.
|
||||
*/
|
||||
extern int usart_init_iso7816(volatile avr32_usart_t *usart, const iso7816_options_t *opt, int t, long pba_hz);
|
||||
|
||||
//! @}
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/*! \name Read and Reset Error Status Bits
|
||||
*/
|
||||
//! @{
|
||||
|
||||
/*! \brief Resets the error status.
|
||||
*
|
||||
* This function resets the status bits indicating that a parity error,
|
||||
* framing error or overrun has occurred. The RXBRK bit, indicating
|
||||
* a start/end of break condition on the RX line, is also reset.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
*/
|
||||
#if __GNUC__
|
||||
__attribute__((__always_inline__))
|
||||
#endif
|
||||
extern __inline__ void usart_reset_status(volatile avr32_usart_t *usart)
|
||||
{
|
||||
usart->cr |= AVR32_USART_CR_RSTSTA_MASK;
|
||||
}
|
||||
|
||||
/*! \brief Checks if a parity error has occurred since last status reset.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
*
|
||||
* \return \c 1 if a parity error has been detected, otherwise \c 0.
|
||||
*/
|
||||
#if __GNUC__
|
||||
__attribute__((__always_inline__))
|
||||
#endif
|
||||
extern __inline__ int usart_parity_error(volatile avr32_usart_t *usart)
|
||||
{
|
||||
return (usart->csr & AVR32_USART_CSR_PARE_MASK) != 0;
|
||||
}
|
||||
|
||||
/*! \brief Checks if a framing error has occurred since last status reset.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
*
|
||||
* \return \c 1 if a framing error has been detected, otherwise \c 0.
|
||||
*/
|
||||
#if __GNUC__
|
||||
__attribute__((__always_inline__))
|
||||
#endif
|
||||
extern __inline__ int usart_framing_error(volatile avr32_usart_t *usart)
|
||||
{
|
||||
return (usart->csr & AVR32_USART_CSR_FRAME_MASK) != 0;
|
||||
}
|
||||
|
||||
/*! \brief Checks if an overrun error has occurred since last status reset.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
*
|
||||
* \return \c 1 if a overrun error has been detected, otherwise \c 0.
|
||||
*/
|
||||
#if __GNUC__
|
||||
__attribute__((__always_inline__))
|
||||
#endif
|
||||
extern __inline__ int usart_overrun_error(volatile avr32_usart_t *usart)
|
||||
{
|
||||
return (usart->csr & AVR32_USART_CSR_OVRE_MASK) != 0;
|
||||
}
|
||||
|
||||
//! @}
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/*! \name Transmit/Receive Functions
|
||||
*/
|
||||
//! @{
|
||||
|
||||
/*! \brief Addresses a receiver.
|
||||
*
|
||||
* While in RS485 mode, receivers only accept data addressed to them.
|
||||
* A packet/char with the address tag set has to precede any data.
|
||||
* This function is used to address a receiver. This receiver should read
|
||||
* all the following data, until an address packet addresses another receiver.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param address Address of the target device.
|
||||
*
|
||||
* \retval USART_SUCCESS Address successfully sent (if current mode is RS485).
|
||||
* \retval USART_MODE_FAULT Wrong operating mode.
|
||||
*/
|
||||
extern int usart_send_address(volatile avr32_usart_t *usart, int address);
|
||||
|
||||
/*! \brief Writes the given character to the TX buffer if the transmitter is ready.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param c The character (up to 9 bits) to transmit.
|
||||
*
|
||||
* \retval USART_SUCCESS The transmitter was ready.
|
||||
* \retval USART_TX_BUSY The transmitter was busy.
|
||||
*/
|
||||
extern int usart_write_char(volatile avr32_usart_t *usart, int c);
|
||||
|
||||
/*! \brief An active wait writing a character to the USART.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param c The character (up to 9 bits) to transmit.
|
||||
*/
|
||||
#if __GNUC__
|
||||
__attribute__((__always_inline__))
|
||||
#endif
|
||||
extern __inline__ void usart_bw_write_char(volatile avr32_usart_t *usart, int c)
|
||||
{
|
||||
while (usart_write_char(usart, c) != USART_SUCCESS);
|
||||
}
|
||||
|
||||
/*! \brief Sends a character with the USART.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param c Character to write.
|
||||
*
|
||||
* \retval USART_SUCCESS The character was written.
|
||||
* \retval USART_FAILURE The function timed out before the USART transmitter became ready to send.
|
||||
*/
|
||||
extern int usart_putchar(volatile avr32_usart_t *usart, int c);
|
||||
|
||||
/*! \brief Checks the RX buffer for a received character, and stores it at the
|
||||
* given memory location.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param c Pointer to the where the read character should be stored
|
||||
* (must be at least short in order to accept 9-bit characters).
|
||||
*
|
||||
* \retval USART_SUCCESS The character was read successfully.
|
||||
* \retval USART_RX_EMPTY The RX buffer was empty.
|
||||
* \retval USART_RX_ERROR An error was deteceted.
|
||||
*/
|
||||
extern int usart_read_char(volatile avr32_usart_t *usart, int *c);
|
||||
|
||||
/*! \brief Waits until a character is received, and returns it.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
*
|
||||
* \return The received character, or \ref USART_FAILURE upon error.
|
||||
*/
|
||||
extern int usart_getchar(volatile avr32_usart_t *usart);
|
||||
|
||||
/*! \brief Writes one character string to the USART.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
* \param string String to be written.
|
||||
*/
|
||||
extern void usart_write_line(volatile avr32_usart_t *usart, const char *string);
|
||||
|
||||
/*! \brief Gets and echoes characters until end of line.
|
||||
*
|
||||
* \param usart Base address of the USART instance.
|
||||
*
|
||||
* \retval USART_SUCCESS Success.
|
||||
* \retval USART_FAILURE ETX character received.
|
||||
*/
|
||||
extern int usart_get_echo_line(volatile avr32_usart_t *usart);
|
||||
|
||||
//! @}
|
||||
|
||||
|
||||
#endif // _USART_H_
|
||||
Loading…
Add table
Add a link
Reference in a new issue