mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-02 12:24:07 -04:00
Remove some large files from the repository that don't need to be there.
This commit is contained in:
Richard Barry
parent
678396f61b
commit
731a01f8f4
6 changed files with 0 additions and 13231 deletions
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@ -1,563 +0,0 @@
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=========================================================================
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Time: Sat Aug 27 15:05:27 GMT Daylight Time 2011
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Running: run_batch_mode 96334104
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{COLLECTING: INSTANCE MCB_DDR3 }
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{COLLECTING: C_INTERCONNECT_S0_AXI_MASTERS microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM OPTIONAL string none microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM}
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{COLLECTING: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S0_AXI_ACLK_RATIO 100000000 UPDATE integer 1 }
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||||
{COLLECTING: C_INTERCONNECT_S0_AXI_SECURE 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S0_AXI_AW_REGISTER 1 OPTIONAL integer 0 1}
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{COLLECTING: C_INTERCONNECT_S0_AXI_AR_REGISTER 1 OPTIONAL integer 0 1}
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{COLLECTING: C_INTERCONNECT_S0_AXI_W_REGISTER 1 OPTIONAL integer 0 1}
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{COLLECTING: C_INTERCONNECT_S0_AXI_R_REGISTER 1 OPTIONAL integer 0 1}
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{COLLECTING: C_INTERCONNECT_S0_AXI_B_REGISTER 1 OPTIONAL integer 0 1}
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||||
{COLLECTING: C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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||||
{COLLECTING: C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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||||
{COLLECTING: C_S0_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S0_AXI_AXI_VER 1.02.a CONSTANT }
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{COLLECTING: C_INTERCONNECT_S1_AXI_MASTERS none OPTIONAL string none }
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{COLLECTING: C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_ACLK_RATIO 1 UPDATE integer 1 }
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||||
{COLLECTING: C_INTERCONNECT_S1_AXI_SECURE 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S1_AXI_AW_REGISTER 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S1_AXI_AR_REGISTER 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S1_AXI_W_REGISTER 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S1_AXI_R_REGISTER 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S1_AXI_B_REGISTER 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_S1_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S1_AXI_AXI_VER 1.01.a CONSTANT }
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{COLLECTING: C_INTERCONNECT_S2_AXI_MASTERS none OPTIONAL string none }
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{COLLECTING: C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_ACLK_RATIO 1 UPDATE integer 1 }
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||||
{COLLECTING: C_INTERCONNECT_S2_AXI_SECURE 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S2_AXI_AW_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_AR_REGISTER 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S2_AXI_W_REGISTER 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S2_AXI_R_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_B_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_S2_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S2_AXI_AXI_VER 1.01.a CONSTANT }
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{COLLECTING: C_INTERCONNECT_S3_AXI_MASTERS none OPTIONAL string none }
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{COLLECTING: C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_ACLK_RATIO 1 UPDATE integer 1 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_SECURE 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_AW_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_AR_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_W_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_R_REGISTER 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S3_AXI_B_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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||||
{COLLECTING: C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_S3_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S3_AXI_AXI_VER 1.01.a CONSTANT }
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{COLLECTING: C_INTERCONNECT_S4_AXI_MASTERS none OPTIONAL string none }
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{COLLECTING: C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_ACLK_RATIO 1 UPDATE integer 1 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_SECURE 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_AW_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_AR_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_W_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_R_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_B_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_S4_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S4_AXI_AXI_VER 1.01.a CONSTANT }
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{COLLECTING: C_INTERCONNECT_S5_AXI_MASTERS none OPTIONAL string none }
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{COLLECTING: C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_ACLK_RATIO 1 UPDATE integer 1 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_SECURE 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_AW_REGISTER 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S5_AXI_AR_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_W_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_R_REGISTER 0 OPTIONAL integer 0 }
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||||
{COLLECTING: C_INTERCONNECT_S5_AXI_B_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_S5_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S5_AXI_AXI_VER 1.01.a CONSTANT }
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{COLLECTING: C_MCB_LOC MEMC3 OPTIONAL MEMC3 }
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{COLLECTING: C_MCB_RZQ_LOC K7 OPTIONAL STRING NOT_SET K7}
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{COLLECTING: C_MCB_ZIO_LOC R7 OPTIONAL STRING NOT_SET R7}
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{COLLECTING: C_MCB_PERFORMANCE STANDARD OPTIONAL STRING STANDARD }
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{COLLECTING: C_BYPASS_CORE_UCF 0 OPTIONAL 0 }
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{COLLECTING: C_S0_AXI_BASEADDR 0x80000000 OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF 0x80000000}
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{COLLECTING: C_S0_AXI_HIGHADDR 0x807FFFFF OPTIONAL STD_LOGIC_VECTOR 0x00000000 0x807FFFFF}
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{COLLECTING: C_S1_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF }
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{COLLECTING: C_S1_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 }
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{COLLECTING: C_S2_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF }
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{COLLECTING: C_S2_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 }
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{COLLECTING: C_S3_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF }
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{COLLECTING: C_S3_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 }
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{COLLECTING: C_S4_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF }
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{COLLECTING: C_S4_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 }
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{COLLECTING: C_S5_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF }
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{COLLECTING: C_S5_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 }
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{COLLECTING: C_MEM_TYPE DDR3 OPTIONAL STRING DDR3 }
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{COLLECTING: C_MEM_PARTNO MT41J64M16XX-187E REQUIRE STRING NOT_SET MT41J64M16XX-187E}
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{COLLECTING: C_MEM_BASEPARTNO NOT_SET OPTIONAL STRING NOT_SET }
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{COLLECTING: C_NUM_DQ_PINS 16 OPTIONAL_UPDATE INTEGER 16 }
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{COLLECTING: C_MEM_ADDR_WIDTH 13 OPTIONAL_UPDATE INTEGER 13 }
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{COLLECTING: C_MEM_BANKADDR_WIDTH 3 OPTIONAL_UPDATE INTEGER 3 }
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{COLLECTING: C_MEM_NUM_COL_BITS 10 OPTIONAL_UPDATE INTEGER 10 }
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{COLLECTING: C_MEM_TRAS -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TRCD -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TREFI -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TRFC -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TRP -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TWR -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TRTP -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TWTR -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_PORT_CONFIG B32_B32_B32_B32 OPTIONAL STRING B32_B32_B32_B32 }
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{COLLECTING: C_SKIP_IN_TERM_CAL 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_SKIP_IN_TERM_CAL_VALUE NONE OPTIONAL STRING NONE }
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{COLLECTING: C_MEMCLK_PERIOD 0 OPTIONAL_UPDATE INTEGER 0 }
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{COLLECTING: C_MEM_ADDR_ORDER ROW_BANK_COLUMN OPTIONAL STRING ROW_BANK_COLUMN }
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{COLLECTING: C_MEM_TZQINIT_MAXCNT 512 UPDATE INTEGER 512 }
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{COLLECTING: C_MEM_CAS_LATENCY 6 UPDATE INTEGER 6 }
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{COLLECTING: C_SIMULATION FALSE OPTIONAL STRING FALSE }
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{COLLECTING: C_MEM_DDR1_2_ODS FULL OPTIONAL STRING FULL }
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{COLLECTING: C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS CLASS_II OPTIONAL STRING CLASS_II }
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{COLLECTING: C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS CLASS_II OPTIONAL STRING CLASS_II }
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{COLLECTING: C_MEM_DDR2_RTT 150OHMS OPTIONAL STRING 150OHMS }
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{COLLECTING: C_MEM_DDR2_DIFF_DQS_EN YES OPTIONAL STRING YES }
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{COLLECTING: C_MEM_DDR2_3_PA_SR FULL OPTIONAL STRING FULL }
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{COLLECTING: C_MEM_DDR2_3_HIGH_TEMP_SR NORMAL OPTIONAL STRING NORMAL }
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{COLLECTING: C_MEM_DDR3_CAS_WR_LATENCY 5 UPDATE INTEGER 5 }
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{COLLECTING: C_MEM_DDR3_CAS_LATENCY 6 UPDATE INTEGER 6 }
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{COLLECTING: C_MEM_DDR3_ODS DIV6 OPTIONAL STRING DIV6 }
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{COLLECTING: C_MEM_DDR3_RTT DIV4 OPTIONAL STRING DIV4 }
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{COLLECTING: C_MEM_DDR3_AUTO_SR ENABLED OPTIONAL STRING ENABLED }
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{COLLECTING: C_MEM_MOBILE_PA_SR FULL OPTIONAL STRING FULL }
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{COLLECTING: C_MEM_MDDR_ODS FULL OPTIONAL STRING FULL }
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{COLLECTING: C_ARB_ALGORITHM 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_ARB_NUM_TIME_SLOTS 12 OPTIONAL INTEGER 12 }
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{COLLECTING: C_ARB_TIME_SLOT_0 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 }
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{COLLECTING: C_ARB_TIME_SLOT_1 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 }
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{COLLECTING: C_ARB_TIME_SLOT_2 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 }
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{COLLECTING: C_ARB_TIME_SLOT_3 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 }
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{COLLECTING: C_ARB_TIME_SLOT_4 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 }
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{COLLECTING: C_ARB_TIME_SLOT_5 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 }
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{COLLECTING: C_ARB_TIME_SLOT_6 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 }
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{COLLECTING: C_ARB_TIME_SLOT_7 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 }
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{COLLECTING: C_ARB_TIME_SLOT_8 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 }
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{COLLECTING: C_ARB_TIME_SLOT_9 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 }
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{COLLECTING: C_ARB_TIME_SLOT_10 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 }
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{COLLECTING: C_ARB_TIME_SLOT_11 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 }
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{COLLECTING: C_S0_AXI_ENABLE 1 OPTIONAL INTEGER 1 }
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{COLLECTING: C_S0_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
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{COLLECTING: C_S0_AXI_ID_WIDTH 3 UPDATE INTEGER 4 }
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{COLLECTING: C_S0_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
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{COLLECTING: C_S0_AXI_DATA_WIDTH 32 OPTIONAL INTEGER 32 }
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{COLLECTING: C_S0_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S0_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S0_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S0_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
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{COLLECTING: C_S0_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
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{COLLECTING: C_S0_AXI_STRICT_COHERENCY 0 OPTIONAL_UPDATE INTEGER 1 0}
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{COLLECTING: C_S0_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S1_AXI_ENABLE 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S1_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
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{COLLECTING: C_S1_AXI_ID_WIDTH 4 UPDATE INTEGER 4 }
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{COLLECTING: C_S1_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
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{COLLECTING: C_S1_AXI_DATA_WIDTH 32 OPTIONAL INTEGER 32 }
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{COLLECTING: C_S1_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S1_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S1_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S1_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
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{COLLECTING: C_S1_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
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{COLLECTING: C_S1_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S1_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S2_AXI_ENABLE 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S2_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
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{COLLECTING: C_S2_AXI_ID_WIDTH 4 UPDATE INTEGER 4 }
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{COLLECTING: C_S2_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
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{COLLECTING: C_S2_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 }
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{COLLECTING: C_S2_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S2_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S2_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S2_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
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{COLLECTING: C_S2_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
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{COLLECTING: C_S2_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S2_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S3_AXI_ENABLE 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S3_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
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{COLLECTING: C_S3_AXI_ID_WIDTH 4 UPDATE INTEGER 4 }
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{COLLECTING: C_S3_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
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{COLLECTING: C_S3_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 }
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{COLLECTING: C_S3_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S3_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S3_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S3_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
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{COLLECTING: C_S3_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
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{COLLECTING: C_S3_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 }
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||||
{COLLECTING: C_S3_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
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||||
{COLLECTING: C_S4_AXI_ENABLE 0 OPTIONAL INTEGER 0 }
|
||||
{COLLECTING: C_S4_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
|
||||
{COLLECTING: C_S4_AXI_ID_WIDTH 4 UPDATE INTEGER 4 }
|
||||
{COLLECTING: C_S4_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
|
||||
{COLLECTING: C_S4_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 }
|
||||
{COLLECTING: C_S4_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S4_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S4_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S4_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
|
||||
{COLLECTING: C_S4_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
|
||||
{COLLECTING: C_S4_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S4_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
|
||||
{COLLECTING: C_S5_AXI_ENABLE 0 OPTIONAL INTEGER 0 }
|
||||
{COLLECTING: C_S5_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
|
||||
{COLLECTING: C_S5_AXI_ID_WIDTH 4 UPDATE INTEGER 4 }
|
||||
{COLLECTING: C_S5_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
|
||||
{COLLECTING: C_S5_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 }
|
||||
{COLLECTING: C_S5_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S5_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S5_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S5_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
|
||||
{COLLECTING: C_S5_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
|
||||
{COLLECTING: C_S5_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S5_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
|
||||
{COLLECTING: C_MCB_USE_EXTERNAL_BUFPLL 0 OPTIONAL INTEGER 0 }
|
||||
{COLLECTING: C_SYS_RST_PRESENT 1 UPDATE INTEGER 0 }
|
||||
{COLLECTING: HW_VER 1.02.a }
|
||||
{SENDING PARAMETER: C_ARB_ALGORITHM : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_NUM_TIME_SLOTS : 12 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_0 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_1 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_2 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_3 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_4 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_5 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_6 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_7 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_8 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_9 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_10 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_11 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_BYPASS_CORE_UCF : 0 {} OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_ACLK_RATIO : 100000000 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_AR_REGISTER : 1 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_AW_REGISTER : 1 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_B_REGISTER : 1 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_MASTERS : {microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_R_REGISTER : 1 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_W_REGISTER : 1 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_ACLK_RATIO : 1 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_AR_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_AW_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_B_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_MASTERS : none string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_R_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_W_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_ACLK_RATIO : 1 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_AR_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_AW_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_B_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_MASTERS : none string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_R_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_W_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_ACLK_RATIO : 1 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_AR_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_AW_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_B_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_MASTERS : none string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_R_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_W_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_ACLK_RATIO : 1 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_AR_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_AW_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_B_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_MASTERS : none string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_R_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_W_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_ACLK_RATIO : 1 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_AR_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_AW_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_B_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_MASTERS : none string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_R_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_W_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_MCB_LOC : MEMC3 {} OPTIONAL}
|
||||
{SENDING PARAMETER: C_MCB_PERFORMANCE : STANDARD STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MCB_RZQ_LOC : K7 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MCB_USE_EXTERNAL_BUFPLL : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_MCB_ZIO_LOC : R7 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_ADDR_ORDER : ROW_BANK_COLUMN STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_ADDR_WIDTH : 13 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_BANKADDR_WIDTH : 3 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_BASEPARTNO : NOT_SET STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_CAS_LATENCY : 6 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS : CLASS_II STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS : CLASS_II STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR1_2_ODS : FULL STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR2_3_HIGH_TEMP_SR : NORMAL STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR2_3_PA_SR : FULL STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR2_DIFF_DQS_EN : YES STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR2_RTT : 150OHMS STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR3_AUTO_SR : ENABLED STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR3_CAS_LATENCY : 6 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_DDR3_CAS_WR_LATENCY : 5 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_DDR3_ODS : DIV6 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR3_RTT : DIV4 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_MDDR_ODS : FULL STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_MOBILE_PA_SR : FULL STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_NUM_COL_BITS : 10 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_PARTNO : MT41J64M16XX-187E STRING REQUIRE}
|
||||
{SENDING PARAMETER: C_MEM_TRAS : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TRCD : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TREFI : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TRFC : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TRP : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TRTP : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TWR : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TWTR : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TYPE : DDR3 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_TZQINIT_MAXCNT : 512 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_MEMCLK_PERIOD : 0 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_NUM_DQ_PINS : 16 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_PORT_CONFIG : B32_B32_B32_B32 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S0_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S0_AXI_AXI_VER : 1.02.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S0_AXI_BASEADDR : 0x80000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_DATA_WIDTH : 32 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_ENABLE : 1 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_HIGHADDR : 0x807FFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_ID_WIDTH : 3 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S0_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S0_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S0_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_STRICT_COHERENCY : 0 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S0_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S0_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S0_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S1_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S1_AXI_AXI_VER : 1.01.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S1_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_DATA_WIDTH : 32 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_ENABLE : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_ID_WIDTH : 4 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S1_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S2_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S2_AXI_AXI_VER : 1.01.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S2_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S2_AXI_DATA_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S2_AXI_ENABLE : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S2_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S2_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S2_AXI_ID_WIDTH : 4 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S2_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S2_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S3_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S3_AXI_AXI_VER : 1.01.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S3_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S3_AXI_DATA_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S3_AXI_ENABLE : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S3_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S3_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S3_AXI_ID_WIDTH : 4 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S3_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S3_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S4_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S4_AXI_AXI_VER : 1.01.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S4_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S4_AXI_DATA_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S4_AXI_ENABLE : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S4_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S4_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S4_AXI_ID_WIDTH : 4 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S4_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S4_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S5_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S5_AXI_AXI_VER : 1.01.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S5_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S5_AXI_DATA_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S5_AXI_ENABLE : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S5_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S5_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S5_AXI_ID_WIDTH : 4 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S5_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S5_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_SIMULATION : FALSE STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_SKIP_IN_TERM_CAL : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_SKIP_IN_TERM_CAL_VALUE : NONE STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_SYS_RST_PRESENT : 1 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: HW_VER : 1.02.a {} {}}
|
||||
{SENDING PARAMETER: INSTANCE : MCB_DDR3 {} {}}
|
||||
{Executing C:/devtools/Xilinx/13.1/ISE_DS/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_v3_7/bin/nt/mig.exe -cg_exc_inp mig_input.txt -cg_exc_out mig_output.txt}
|
||||
{SET: IGNORE C_MCB_LOC = MEMC3 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_DDR3_ODS = DIV6 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MCB_ZIO_LOC = R7 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: UPDATE C_S4_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S0_AXI_BASEADDR = 0x80000000 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_MDDR_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_DDR2_DIFF_DQS_EN = YES (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S2_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S0_AXI_DATA_WIDTH = 32 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: CHECK C_MEM_NUM_COL_BITS = 10 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_DDR3_RTT = DIV4 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDREM C_MEM_CAS_LATENCY = 6 (BATCH:UPDATE::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_MEM_TRFC = 160000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_AR_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: UPDATE C_S3_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S0_AXI_SUPPORTS_NARROW_BURST = Auto (BATCH:OPTIONAL_UPDATE::MPD:DEFVAL)}
|
||||
{SET: IGNORE C_S0_AXI_STRICT_COHERENCY = 0 (BATCH:OPTIONAL_UPDATE::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_10 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_SECURE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_11 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_NUM_TIME_SLOTS = 12 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S5_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S2_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_MEM_TRTP = 7500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_MEM_TREFI = 7800000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S0_AXI_ENABLE = 1 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_MOBILE_PA_SR = FULL (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_SKIP_IN_TERM_CAL = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_DDR2_3_HIGH_TEMP_SR = NORMAL (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDREM C_S0_AXI_SUPPORTS_READ = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S0_AXI_HIGHADDR = 0x807FFFFF (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR1_2_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_TYPE = DDR3 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: CHECK C_MEM_ADDR_WIDTH = 13 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S5_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_S4_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S0_AXI_ENABLE_AP = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_MEM_TWR = 15000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S3_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDREM C_S0_AXI_SUPPORTS_WRITE = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S0_AXI_ADDR_WIDTH = 32 (BATCH:CONSTANT::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS = CLASS_II (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDREM C_MEM_DDR3_CAS_WR_LATENCY = 5 (BATCH:UPDATE::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_W_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR2_RTT = 150OHMS (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MCB_PERFORMANCE = STANDARD (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: CHECK C_MEM_BANKADDR_WIDTH = 3 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_B_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_SIMULATION = FALSE (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S1_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_MEM_TWTR = 7500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_S3_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_MEM_TRAS = 37500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDREM C_MEM_DDR3_CAS_LATENCY = 6 (BATCH:UPDATE::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S5_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S1_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_MEM_TRCD = 13130 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_0 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_ALGORITHM = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_MEM_TRP = 13130 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_1 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS = CLASS_II (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_2 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_3 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR3_AUTO_SR = ENABLED (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_4 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_5 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_6 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_AW_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_7 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_MEMCLK_PERIOD = 0 (BATCH:OPTIONAL_UPDATE:SKIP_BATCH:MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MCB_RZQ_LOC = K7 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_8 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_ADDR_ORDER = ROW_BANK_COLUMN (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MCB_USE_EXTERNAL_BUFPLL = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_R_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_9 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S4_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S1_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_SKIP_IN_TERM_CAL_VALUE = NONE (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S2_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR2_3_PA_SR = FULL (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_PORT_CONFIG = B32_B32_B32_B32 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_PARTNO = MT41J64M16XX-187E (BATCH:REQUIRE::MHS:COMPVAL)}
|
||||
{SET: CHECK C_NUM_DQ_PINS = 16 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)}
|
||||
RETURN: 0
|
||||
Loading…
Add table
Add a link
Reference in a new issue