XPS Project Report

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.html deleted file mode 100644 index 1dda8a75f..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.html +++ /dev/null @@ -1,12 +0,0 @@ - - - - -XPS Project Report - -XPS Project Report - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html deleted file mode 100644 index 8d96d046d..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html +++ /dev/null @@ -1,6004 +0,0 @@ - - - - -XPS Project Report - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Printable Version

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Overview

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Resources Used
1	MicroBlaze
2	AXI Interconnect
2	Local Memory Bus (LMB) 1.0
1	Block RAM (BRAM) Block
2	LMB BRAM Controller
1	AXI S6 Memory Controller(DDR/DDR2/DDR3)
1	Processor System Reset Module
1	Clock Generator
1	MicroBlaze Debug Module (MDM)
1	AXI UART (Lite)
2	AXI General Purpose IO
1	AXI Ethernet
1	AXI DMA Engine
1	AXI Interrupt Controller
1	AXI Timer/Counter

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Specifics
Generated	Sat Aug 27 15:05:44 2011
EDK Version	13.1
Device Family	spartan6
Device	xc6slx45tfgg484-3

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Block Diagram	TOP

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BlockDiagram

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External Ports	TOP

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-Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK)
INTR  indicates Interrupt ports,(SIGIS = INTR)
RESET  indicates Reset ports, (SIGIS = RST)
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) -

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#	NAME		DIR	[LSB:MSB]	SIG		ATTRIBUTES
-SHARED -	RESET		I	1	RESET		RESET
-ETHERNET -	ETHERNET_MII_TX_CLK		I	1	ETHERNET_MII_TX_CLK
-ETHERNET -	ETHERNET_RXD		I	0:7	ETHERNET_RXD
-ETHERNET -	ETHERNET_RX_CLK		I	1	ETHERNET_RX_CLK
-ETHERNET -	ETHERNET_RX_DV		I	1	ETHERNET_RX_DV
-ETHERNET -	ETHERNET_RX_ER		I	1	ETHERNET_RX_ER
-ETHERNET -	ETHERNET_MDIO		IO	1	ETHERNET_MDIO
-ETHERNET -	ETHERNET_MDC		O	1	ETHERNET_MDC
-ETHERNET -	ETHERNET_PHY_RST_N		O	1	ETHERNET_PHY_RST_N
-ETHERNET -	ETHERNET_TXD		O	0:7	ETHERNET_TXD
-ETHERNET -	ETHERNET_TX_CLK		O	1	ETHERNET_TX_CLK
-ETHERNET -	ETHERNET_TX_EN		O	1	ETHERNET_TX_EN
-ETHERNET -	ETHERNET_TX_ER		O	1	ETHERNET_TX_ER
-LEDs_4Bits -	LEDs_4Bits_TRI_O		O	0:3	LEDs_4Bits_TRI_O
-MCB_DDR3 -	mcbx_dram_dq		IO	0:15	mcbx_dram_dq
-MCB_DDR3 -	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
-MCB_DDR3 -	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
-MCB_DDR3 -	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
-MCB_DDR3 -	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
-MCB_DDR3 -	rzq		IO	1	rzq
-MCB_DDR3 -	zio		IO	1	zio
-MCB_DDR3 -	mcbx_dram_addr		O	0:12	mcbx_dram_addr
-MCB_DDR3 -	mcbx_dram_ba		O	0:2	mcbx_dram_ba
-MCB_DDR3 -	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
-MCB_DDR3 -	mcbx_dram_cke		O	1	mcbx_dram_cke
-MCB_DDR3 -	mcbx_dram_clk		O	1	mcbx_dram_clk
-MCB_DDR3 -	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
-MCB_DDR3 -	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
-MCB_DDR3 -	mcbx_dram_ldm		O	1	mcbx_dram_ldm
-MCB_DDR3 -	mcbx_dram_odt		O	1	mcbx_dram_odt
-MCB_DDR3 -	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
-MCB_DDR3 -	mcbx_dram_udm		O	1	mcbx_dram_udm
-MCB_DDR3 -	mcbx_dram_we_n		O	1	mcbx_dram_we_n
-Push_Buttons_4Bits -	Push_Buttons_4Bits_TRI_I		I	0:3	Push_Buttons_4Bits_TRI_I
-RS232_Uart_1 -	RS232_Uart_1_sin		I	1	RS232_Uart_1_sin
-RS232_Uart_1 -	RS232_Uart_1_sout		O	1	RS232_Uart_1_sout
-clock_generator_0 -	CLK_N		I	1	CLK		CLK
-clock_generator_0 -	CLK_P		I	1	CLK		CLK

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Processors	TOP

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-microblaze_0 - MicroBlaze
The MicroBlaze 32 bit soft processor

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IP Specs
Core	Version	Documentation
microblaze	8.10.a	IP

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microblaze_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	MB_RESET		I	1	proc_sys_reset_0_MB_Reset
1	CLK		I	1	clk_100_0000MHzPLL0
2	INTERRUPT		I	1	microblaze_0_interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
M_AXI_DP	MASTER	AXI	axi4lite_0			8 Peripherals.
DLMB	MASTER	LMB	microblaze_0_dlmb			microblaze_0_d_bram_ctrl
ILMB	MASTER	LMB	microblaze_0_ilmb			microblaze_0_i_bram_ctrl
M_AXI_DC	MASTER	AXI	axi4_0			2 Peripherals.
M_AXI_IC	MASTER	AXI	axi4_0			2 Peripherals.
DEBUG	TARGET	XIL_MBDEBUG3	microblaze_0_debug			debug_module

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Parameters

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Name	Value
C_SCO	0
C_FREQ	0
C_DATA_SIZE	32
C_DYNAMIC_BUS_SIZING	1
C_FAMILY	virtex5
C_INSTANCE	microblaze
C_FAULT_TOLERANT	0
C_ECC_USE_CE_EXCEPTION	0
C_ENDIANNESS	0
C_AREA_OPTIMIZED	0
C_OPTIMIZATION	0
C_INTERCONNECT	2
C_STREAM_INTERCONNECT	0
C_DPLB_DWIDTH	32
C_DPLB_NATIVE_DWIDTH	32
C_DPLB_BURST_EN	0
C_DPLB_P2P	0
C_IPLB_DWIDTH	32
C_IPLB_NATIVE_DWIDTH	32
C_IPLB_BURST_EN	0
C_IPLB_P2P	0
C_M_AXI_DP_SUPPORTS_THREADS	0
C_M_AXI_DP_THREAD_ID_WIDTH	1
C_M_AXI_DP_SUPPORTS_READ	1
C_M_AXI_DP_SUPPORTS_WRITE	1
C_M_AXI_DP_SUPPORTS_NARROW_BURST	0
C_M_AXI_DP_DATA_WIDTH	32
C_M_AXI_DP_ADDR_WIDTH	32
C_M_AXI_DP_PROTOCOL	AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS	0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING	1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING	1
C_M_AXI_IP_SUPPORTS_THREADS	0
C_M_AXI_IP_THREAD_ID_WIDTH	1
C_M_AXI_IP_SUPPORTS_READ	1
C_M_AXI_IP_SUPPORTS_WRITE	0
C_M_AXI_IP_SUPPORTS_NARROW_BURST	0
C_M_AXI_IP_DATA_WIDTH	32
C_M_AXI_IP_ADDR_WIDTH	32
C_M_AXI_IP_PROTOCOL	AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING	1
C_D_AXI	0
C_D_PLB	0
C_D_LMB	1
C_I_AXI	0
C_I_PLB	0
C_I_LMB	1
C_USE_MSR_INSTR	1
C_USE_PCMP_INSTR	1
C_USE_BARREL	1
C_USE_DIV	0
C_USE_HW_MUL	1
C_USE_FPU	0
C_UNALIGNED_EXCEPTIONS	0
C_ILL_OPCODE_EXCEPTION	0
C_M_AXI_I_BUS_EXCEPTION	0
C_M_AXI_D_BUS_EXCEPTION	0
C_IPLB_BUS_EXCEPTION	0
C_DPLB_BUS_EXCEPTION	0
C_DIV_ZERO_EXCEPTION	0
C_FPU_EXCEPTION	0
C_FSL_EXCEPTION	0
C_USE_STACK_PROTECTION	0
C_PVR	0
C_PVR_USER1	0x00
C_PVR_USER2	0x00000000
C_DEBUG_ENABLED	1
C_NUMBER_OF_PC_BRK	7
C_NUMBER_OF_RD_ADDR_BRK	2
C_NUMBER_OF_WR_ADDR_BRK	2
C_INTERRUPT_IS_EDGE	0
C_EDGE_IS_POSITIVE	1
C_RESET_MSR	0x00000000
C_OPCODE_0x0_ILLEGAL	0
C_FSL_LINKS	0
C_FSL_DATA_SIZE	32
C_USE_EXTENDED_FSL_INSTR	0
C_M0_AXIS_PROTOCOL	GENERIC
C_S0_AXIS_PROTOCOL	GENERIC
C_M1_AXIS_PROTOCOL	GENERIC
C_S1_AXIS_PROTOCOL	GENERIC
C_M2_AXIS_PROTOCOL	GENERIC
C_S2_AXIS_PROTOCOL	GENERIC
C_M3_AXIS_PROTOCOL	GENERIC
C_S3_AXIS_PROTOCOL	GENERIC
C_M4_AXIS_PROTOCOL	GENERIC
C_S4_AXIS_PROTOCOL	GENERIC
C_M5_AXIS_PROTOCOL	GENERIC
C_S5_AXIS_PROTOCOL	GENERIC
C_M6_AXIS_PROTOCOL	GENERIC
C_S6_AXIS_PROTOCOL	GENERIC
C_M7_AXIS_PROTOCOL	GENERIC
C_S7_AXIS_PROTOCOL	GENERIC
C_M8_AXIS_PROTOCOL	GENERIC
C_S8_AXIS_PROTOCOL	GENERIC
C_M9_AXIS_PROTOCOL	GENERIC
C_S9_AXIS_PROTOCOL	GENERIC
C_M10_AXIS_PROTOCOL	GENERIC
C_S10_AXIS_PROTOCOL	GENERIC
C_M11_AXIS_PROTOCOL	GENERIC
C_S11_AXIS_PROTOCOL	GENERIC
C_M12_AXIS_PROTOCOL	GENERIC
C_S12_AXIS_PROTOCOL	GENERIC
C_M13_AXIS_PROTOCOL	GENERIC
C_S13_AXIS_PROTOCOL	GENERIC
C_M14_AXIS_PROTOCOL	GENERIC
C_S14_AXIS_PROTOCOL	GENERIC
C_M15_AXIS_PROTOCOL	GENERIC
C_S15_AXIS_PROTOCOL	GENERIC
C_M0_AXIS_DATA_WIDTH	32
C_S0_AXIS_DATA_WIDTH	32
C_M1_AXIS_DATA_WIDTH	32
C_S1_AXIS_DATA_WIDTH	32
C_M2_AXIS_DATA_WIDTH	32
C_S2_AXIS_DATA_WIDTH	32

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Name	Value
C_M3_AXIS_DATA_WIDTH	32
C_S3_AXIS_DATA_WIDTH	32
C_M4_AXIS_DATA_WIDTH	32
C_S4_AXIS_DATA_WIDTH	32
C_M5_AXIS_DATA_WIDTH	32
C_S5_AXIS_DATA_WIDTH	32
C_M6_AXIS_DATA_WIDTH	32
C_S6_AXIS_DATA_WIDTH	32
C_M7_AXIS_DATA_WIDTH	32
C_S7_AXIS_DATA_WIDTH	32
C_M8_AXIS_DATA_WIDTH	32
C_S8_AXIS_DATA_WIDTH	32
C_M9_AXIS_DATA_WIDTH	32
C_S9_AXIS_DATA_WIDTH	32
C_M10_AXIS_DATA_WIDTH	32
C_S10_AXIS_DATA_WIDTH	32
C_M11_AXIS_DATA_WIDTH	32
C_S11_AXIS_DATA_WIDTH	32
C_M12_AXIS_DATA_WIDTH	32
C_S12_AXIS_DATA_WIDTH	32
C_M13_AXIS_DATA_WIDTH	32
C_S13_AXIS_DATA_WIDTH	32
C_M14_AXIS_DATA_WIDTH	32
C_S14_AXIS_DATA_WIDTH	32
C_M15_AXIS_DATA_WIDTH	32
C_S15_AXIS_DATA_WIDTH	32
C_ICACHE_BASEADDR	0xC0000000
C_ICACHE_HIGHADDR	0xC7FFFFFF
C_USE_ICACHE	1
C_ALLOW_ICACHE_WR	1
C_ADDR_TAG_BITS	17
C_CACHE_BYTE_SIZE	16384
C_ICACHE_USE_FSL	1
C_ICACHE_LINE_LEN	4
C_ICACHE_ALWAYS_USED	1
C_ICACHE_INTERFACE	0
C_ICACHE_VICTIMS	0
C_ICACHE_STREAMS	0
C_ICACHE_FORCE_TAG_LUTRAM	0
C_ICACHE_DATA_WIDTH	0
C_M_AXI_IC_SUPPORTS_THREADS	0
C_M_AXI_IC_THREAD_ID_WIDTH	1
C_M_AXI_IC_SUPPORTS_READ	1
C_M_AXI_IC_SUPPORTS_WRITE	0
C_M_AXI_IC_SUPPORTS_NARROW_BURST	0
C_M_AXI_IC_DATA_WIDTH	32
C_M_AXI_IC_ADDR_WIDTH	32
C_M_AXI_IC_PROTOCOL	AXI4
C_M_AXI_IC_USER_VALUE	0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_IC_AWUSER_WIDTH	5
C_M_AXI_IC_ARUSER_WIDTH	5
C_M_AXI_IC_WUSER_WIDTH	1
C_M_AXI_IC_RUSER_WIDTH	1
C_M_AXI_IC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING	2
C_DCACHE_BASEADDR	0xC0000000
C_DCACHE_HIGHADDR	0xC7FFFFFF
C_USE_DCACHE	1
C_ALLOW_DCACHE_WR	1
C_DCACHE_ADDR_TAG	17
C_DCACHE_BYTE_SIZE	16384
C_DCACHE_USE_FSL	1
C_DCACHE_LINE_LEN	4
C_DCACHE_ALWAYS_USED	1
C_DCACHE_INTERFACE	0
C_DCACHE_USE_WRITEBACK	0
C_DCACHE_VICTIMS	0
C_DCACHE_FORCE_TAG_LUTRAM	0
C_DCACHE_DATA_WIDTH	0
C_M_AXI_DC_SUPPORTS_THREADS	0
C_M_AXI_DC_THREAD_ID_WIDTH	1
C_M_AXI_DC_SUPPORTS_READ	1
C_M_AXI_DC_SUPPORTS_WRITE	1
C_M_AXI_DC_SUPPORTS_NARROW_BURST	0
C_M_AXI_DC_DATA_WIDTH	32
C_M_AXI_DC_ADDR_WIDTH	32
C_M_AXI_DC_PROTOCOL	AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS	0
C_M_AXI_DC_USER_VALUE	0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_DC_AWUSER_WIDTH	5
C_M_AXI_DC_ARUSER_WIDTH	5
C_M_AXI_DC_WUSER_WIDTH	1
C_M_AXI_DC_RUSER_WIDTH	1
C_M_AXI_DC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING	2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING	32
C_USE_MMU	0
C_MMU_DTLB_SIZE	4
C_MMU_ITLB_SIZE	2
C_MMU_TLB_ACCESS	3
C_MMU_ZONES	16
C_MMU_PRIVILEGED_INSTR	0
C_USE_INTERRUPT	0
C_USE_EXT_BRK	0
C_USE_EXT_NM_BRK	0
C_USE_BRANCH_TARGET_CACHE	0
C_BRANCH_TARGET_CACHE_SIZE	0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DC_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DP_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_R_REGISTER	1
C_INTERCONNECT_M_AXI_DP_B_REGISTER	1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DC_R_REGISTER	1
C_INTERCONNECT_M_AXI_DC_B_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_IC_W_REGISTER	1
C_INTERCONNECT_M_AXI_IC_R_REGISTER	1
C_INTERCONNECT_M_AXI_IC_B_REGISTER	1

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Post Synthesis Device Utilization
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Debuggers	TOP

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-debug_module - MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

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IP Specs
Core	Version	Documentation
mdm	2.00.b	IP

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debug_module IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Debug_SYS_Rst		O	1	proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
MBDEBUG_0	INITIATOR	XIL_MBDEBUG3	microblaze_0_debug			microblaze_0
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.

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Parameters

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Name	Value
C_FAMILY	virtex6
C_JTAG_CHAIN	2
C_INTERCONNECT	2
C_BASEADDR	0x74800000
C_HIGHADDR	0x7480FFFF
C_SPLB_AWIDTH	32
C_SPLB_DWIDTH	32
C_SPLB_P2P	0
C_SPLB_MID_WIDTH	3
C_SPLB_NUM_MASTERS	8
C_SPLB_NATIVE_DWIDTH	32

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Name	Value
C_SPLB_SUPPORT_BURSTS	0
C_MB_DBG_PORTS	1
C_USE_UART	1
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

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Post Synthesis Device Utilization
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Interrupt Controllers	TOP

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-microblaze_0_intc - AXI Interrupt Controller
intc core attached to the AXI

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IP Specs
Core	Version	Documentation
axi_intc	1.01.a	IP

-

-

microblaze_0_intc IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	IRQ		O	1	microblaze_0_interrupt
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	INTR		I	1	ETHERNET_INTERRUPT & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut & Push_Buttons_4Bits_IP2INTC_Irpt & RS232_Uart_1_Interrupt & axi_timer_0_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.
-Interrupt Priorities
Priority	SIG			MODULE
0	ETHERNET_INTERRUPT			ETHERNET
1	ETHERNET_dma_mm2s_introut			ETHERNET_dma
2	ETHERNET_dma_s2mm_introut			ETHERNET_dma
3	Push_Buttons_4Bits_IP2INTC_Irpt			Push_Buttons_4Bits
4	RS232_Uart_1_Interrupt			RS232_Uart_1
5	axi_timer_0_Interrupt			axi_timer_0

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x41200000
C_HIGHADDR	0x4120FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_NUM_INTR_INPUTS	2
C_KIND_OF_INTR	0xFFFFFFFF
C_KIND_OF_EDGE	0xFFFFFFFF
C_KIND_OF_LVL	0xFFFFFFFF
C_HAS_IPR	1
C_HAS_SIE	1

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_HAS_CIE	1
C_HAS_IVR	1
C_IRQ_IS_LEVEL	1
C_IRQ_ACTIVE	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Busses	TOP

-
- - - - - - - - -

- - - - - - - - - -

-axi4_0 - AXI Interconnect
AXI4 Memory-Mapped Interconnect

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

-

-

axi4_0 IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	interconnect_aclk		I	1	clk_100_0000MHzPLL0
1	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DC
microblaze_0					MASTER	M_AXI_IC
ETHERNET_dma					MASTER	M_AXI_SG
ETHERNET_dma					MASTER	M_AXI_MM2S
ETHERNET_dma					MASTER	M_AXI_S2MM
MCB_DDR3					SLAVE	S0_AXI

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	1
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-axi4lite_0 - AXI Interconnect
AXI4 Memory-Mapped Interconnect

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

-

-

axi4lite_0 IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
1	INTERCONNECT_ACLK		I	1	clk_50_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DP
debug_module					SLAVE	S_AXI
RS232_Uart_1					SLAVE	S_AXI
LEDs_4Bits					SLAVE	S_AXI
Push_Buttons_4Bits					SLAVE	S_AXI
ETHERNET					SLAVE	S_AXI
ETHERNET_dma					SLAVE	S_AXI_LITE
microblaze_0_intc					SLAVE	S_AXI
axi_timer_0					SLAVE	S_AXI

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	0
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-microblaze_0_dlmb - Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

-

-

microblaze_0_dlmb IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	DLMB
microblaze_0_d_bram_ctrl					SLAVE	SLMB

-

-

- - - - - - - - - - - - - - - - - - - - -

Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-microblaze_0_ilmb - Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

-

-

microblaze_0_ilmb IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	ILMB
microblaze_0_i_bram_ctrl					SLAVE	SLMB

-

-

- - - - - - - - - - - - - - - - - - - - -

Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Memorys	TOP

-
- - -

- - - - - - - - - -

-microblaze_0_bram_block - Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
bram_block	1.00.a	IP

-

-

microblaze_0_bram_block IP Image

- - - - - - - - - - - - - - - - - - - - - -

Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
PORTA	TARGET	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_i_bram_ctrl
PORTB	TARGET	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_d_bram_ctrl

-

-

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Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_MEMSIZE		2048
C_PORT_DWIDTH		32
C_PORT_AWIDTH		32
C_NUM_WE		4
C_FAMILY		virtex2

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Memory Controllers	TOP

-
- - - - - - -

- - - - - - - - - -

-MCB_DDR3 - AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_s6_ddrx	1.02.a	IP

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-

MCB_DDR3 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	mcbx_dram_clk		O	1	mcbx_dram_clk
1	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
2	mcbx_dram_cke		O	1	mcbx_dram_cke
3	mcbx_dram_odt		O	1	mcbx_dram_odt
4	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
5	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
6	mcbx_dram_we_n		O	1	mcbx_dram_we_n
7	mcbx_dram_udm		O	1	mcbx_dram_udm
8	mcbx_dram_ldm		O	1	mcbx_dram_ldm
9	mcbx_dram_ba		O	1	mcbx_dram_ba
10	mcbx_dram_addr		O	1	mcbx_dram_addr
11	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
12	mcbx_dram_dq		IO	1	mcbx_dram_dq
13	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
14	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
15	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
16	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
17	rzq		IO	1	rzq
18	zio		IO	1	zio
19	s0_axi_aclk		I	1	clk_100_0000MHzPLL0
20	ui_clk		I	1	clk_100_0000MHzPLL0
21	sysclk_2x		I	1	clk_600_0000MHzPLL0_nobuf
22	sysclk_2x_180		I	1	clk_600_0000MHz180PLL0_nobuf
23	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
24	PLL_LOCK		I	1	proc_sys_reset_0_Dcm_locked
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S0_AXI	SLAVE	AXI	axi4_0			2 Peripherals.

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_MCB_LOC	MEMC3
C_MCB_RZQ_LOC	K7
C_MCB_ZIO_LOC	R7
C_MCB_PERFORMANCE	STANDARD
C_BYPASS_CORE_UCF	0
C_S0_AXI_BASEADDR	0x80000000
C_S0_AXI_HIGHADDR	0x807FFFFF
C_S1_AXI_BASEADDR	0xFFFFFFFF
C_S1_AXI_HIGHADDR	0x00000000
C_S2_AXI_BASEADDR	0xFFFFFFFF
C_S2_AXI_HIGHADDR	0x00000000
C_S3_AXI_BASEADDR	0xFFFFFFFF
C_S3_AXI_HIGHADDR	0x00000000
C_S4_AXI_BASEADDR	0xFFFFFFFF
C_S4_AXI_HIGHADDR	0x00000000
C_S5_AXI_BASEADDR	0xFFFFFFFF
C_S5_AXI_HIGHADDR	0x00000000
C_MEM_TYPE	DDR3
C_MEM_PARTNO	MT41J64M16XX-187E
C_MEM_BASEPARTNO	NOT_SET
C_NUM_DQ_PINS	16
C_MEM_ADDR_WIDTH	13
C_MEM_BANKADDR_WIDTH	3
C_MEM_NUM_COL_BITS	10
C_MEM_TRAS	-1
C_MEM_TRCD	-1
C_MEM_TREFI	-1
C_MEM_TRFC	-1
C_MEM_TRP	-1
C_MEM_TWR	-1
C_MEM_TRTP	-1
C_MEM_TWTR	-1
C_PORT_CONFIG	B32_B32_B32_B32
C_SKIP_IN_TERM_CAL	0
C_SKIP_IN_TERM_CAL_VALUE	NONE
C_MEMCLK_PERIOD	0
C_MEM_ADDR_ORDER	ROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT	512
C_MEM_CAS_LATENCY	6
C_SIMULATION	FALSE
C_MEM_DDR1_2_ODS	FULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR2_RTT	150OHMS
C_MEM_DDR2_DIFF_DQS_EN	YES
C_MEM_DDR2_3_PA_SR	FULL
C_MEM_DDR2_3_HIGH_TEMP_SR	NORMAL
C_MEM_DDR3_CAS_WR_LATENCY	5
C_MEM_DDR3_CAS_LATENCY	6
C_MEM_DDR3_ODS	DIV6
C_MEM_DDR3_RTT	DIV4
C_MEM_DDR3_AUTO_SR	ENABLED
C_MEM_MOBILE_PA_SR	FULL
C_MEM_MDDR_ODS	FULL
C_ARB_ALGORITHM	0
C_ARB_NUM_TIME_SLOTS	12
C_ARB_TIME_SLOT_0	0b000000000001010011
C_ARB_TIME_SLOT_1	0b000000001010011000
C_ARB_TIME_SLOT_2	0b000000010011000001
C_ARB_TIME_SLOT_3	0b000000011000001010
C_ARB_TIME_SLOT_4	0b000000000001010011
C_ARB_TIME_SLOT_5	0b000000001010011000
C_ARB_TIME_SLOT_6	0b000000010011000001
C_ARB_TIME_SLOT_7	0b000000011000001010
C_ARB_TIME_SLOT_8	0b000000000001010011
C_ARB_TIME_SLOT_9	0b000000001010011000
C_ARB_TIME_SLOT_10	0b000000010011000001
C_ARB_TIME_SLOT_11	0b000000011000001010
C_S0_AXI_ENABLE	1
C_S0_AXI_PROTOCOL	AXI4
C_S0_AXI_ID_WIDTH	4
C_S0_AXI_ADDR_WIDTH	32
C_S0_AXI_DATA_WIDTH	32
C_S0_AXI_SUPPORTS_READ	1
C_S0_AXI_SUPPORTS_WRITE	1
C_S0_AXI_SUPPORTS_NARROW_BURST	1
C_S0_AXI_REG_EN0	0x00000
C_S0_AXI_REG_EN1	0x01000
C_S0_AXI_STRICT_COHERENCY	0
C_S0_AXI_ENABLE_AP	0

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE	4
C_S1_AXI_ENABLE	0
C_S1_AXI_PROTOCOL	AXI4
C_S1_AXI_ID_WIDTH	4
C_S1_AXI_ADDR_WIDTH	32
C_S1_AXI_DATA_WIDTH	32
C_S1_AXI_SUPPORTS_READ	1
C_S1_AXI_SUPPORTS_WRITE	1
C_S1_AXI_SUPPORTS_NARROW_BURST	1
C_S1_AXI_REG_EN0	0x00000
C_S1_AXI_REG_EN1	0x01000
C_S1_AXI_STRICT_COHERENCY	1
C_S1_AXI_ENABLE_AP	0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE	4
C_S2_AXI_ENABLE	0
C_S2_AXI_PROTOCOL	AXI4
C_S2_AXI_ID_WIDTH	4
C_S2_AXI_ADDR_WIDTH	32
C_S2_AXI_DATA_WIDTH	32
C_S2_AXI_SUPPORTS_READ	1
C_S2_AXI_SUPPORTS_WRITE	1
C_S2_AXI_SUPPORTS_NARROW_BURST	1
C_S2_AXI_REG_EN0	0x00000
C_S2_AXI_REG_EN1	0x01000
C_S2_AXI_STRICT_COHERENCY	1
C_S2_AXI_ENABLE_AP	0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE	4
C_S3_AXI_ENABLE	0
C_S3_AXI_PROTOCOL	AXI4
C_S3_AXI_ID_WIDTH	4
C_S3_AXI_ADDR_WIDTH	32
C_S3_AXI_DATA_WIDTH	32
C_S3_AXI_SUPPORTS_READ	1
C_S3_AXI_SUPPORTS_WRITE	1
C_S3_AXI_SUPPORTS_NARROW_BURST	1
C_S3_AXI_REG_EN0	0x00000
C_S3_AXI_REG_EN1	0x01000
C_S3_AXI_STRICT_COHERENCY	1
C_S3_AXI_ENABLE_AP	0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE	4
C_S4_AXI_ENABLE	0
C_S4_AXI_PROTOCOL	AXI4
C_S4_AXI_ID_WIDTH	4
C_S4_AXI_ADDR_WIDTH	32
C_S4_AXI_DATA_WIDTH	32
C_S4_AXI_SUPPORTS_READ	1
C_S4_AXI_SUPPORTS_WRITE	1
C_S4_AXI_SUPPORTS_NARROW_BURST	1
C_S4_AXI_REG_EN0	0x00000
C_S4_AXI_REG_EN1	0x01000
C_S4_AXI_STRICT_COHERENCY	1
C_S4_AXI_ENABLE_AP	0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE	4
C_S5_AXI_ENABLE	0
C_S5_AXI_PROTOCOL	AXI4
C_S5_AXI_ID_WIDTH	4
C_S5_AXI_ADDR_WIDTH	32
C_S5_AXI_DATA_WIDTH	32
C_S5_AXI_SUPPORTS_READ	1
C_S5_AXI_SUPPORTS_WRITE	1
C_S5_AXI_SUPPORTS_NARROW_BURST	1
C_S5_AXI_REG_EN0	0x00000
C_S5_AXI_REG_EN1	0x01000
C_S5_AXI_STRICT_COHERENCY	1
C_S5_AXI_ENABLE_AP	0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE	4
C_MCB_USE_EXTERNAL_BUFPLL	0
C_SYS_RST_PRESENT	0
C_INTERCONNECT_S0_AXI_MASTERS	microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
C_INTERCONNECT_S0_AXI_AW_REGISTER	1
C_INTERCONNECT_S0_AXI_AR_REGISTER	1
C_INTERCONNECT_S0_AXI_W_REGISTER	1
C_INTERCONNECT_S0_AXI_R_REGISTER	1
C_INTERCONNECT_S0_AXI_B_REGISTER	1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

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- - - - - - - - - -

-microblaze_0_d_bram_ctrl - LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

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-

microblaze_0_d_bram_ctrl IP Image

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Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_dlmb			microblaze_0

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

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Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

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Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-microblaze_0_i_bram_ctrl - LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

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microblaze_0_i_bram_ctrl IP Image

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Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_ilmb			microblaze_0

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

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Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Peripherals	TOP

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-ETHERNET - AXI Ethernet
AXI Ethernet MAC

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_ethernet	2.01.a	IP

-

-

ETHERNET IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	MDIO		IO	1	ETHERNET_MDIO
1	MDC		O	1	ETHERNET_MDC
2	GMII_TX_ER		O	1	ETHERNET_TX_ER
3	GMII_TXD		O	1	ETHERNET_TXD
4	GMII_TX_EN		O	1	ETHERNET_TX_EN
5	MII_TX_CLK		I	1	ETHERNET_MII_TX_CLK
6	GMII_TX_CLK		O	1	ETHERNET_TX_CLK
7	GMII_RXD		I	1	ETHERNET_RXD
8	GMII_RX_ER		I	1	ETHERNET_RX_ER
9	GMII_RX_CLK		I	1	ETHERNET_RX_CLK
10	GMII_RX_DV		I	1	ETHERNET_RX_DV
11	PHY_RST_N		O	1	ETHERNET_PHY_RST_N
12	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
13	GTX_CLK		I	1	clk_125_0000MHz
14	REF_CLK		I	1	clk_200_0000MHzPLL0
15	AXI_STR_TXD_ACLK		I	1	clk_100_0000MHzPLL0
16	AXI_STR_TXC_ACLK		I	1	clk_100_0000MHzPLL0
17	AXI_STR_RXD_ACLK		I	1	clk_100_0000MHzPLL0
18	AXI_STR_RXS_ACLK		I	1	clk_100_0000MHzPLL0
19	AXI_STR_TXD_ARESETN		I	1	AXI_STR_TXD_ARESETN
20	AXI_STR_TXC_ARESETN		I	1	AXI_STR_TXC_ARESETN
21	AXI_STR_RXD_ARESETN		I	1	AXI_STR_RXD_ARESETN
22	AXI_STR_RXS_ARESETN		I	1	AXI_STR_RXS_ARESETN
23	INTERRUPT		O	1	ETHERNET_INTERRUPT
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
AXI_STR_RXS	INITIATOR	AXIS	ETHERNET_dma_rxs			ETHERNET_dma
AXI_STR_RXD	INITIATOR	AXIS	ETHERNET_dma_rxd			ETHERNET_dma
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.
AXI_STR_TXD	TARGET	AXIS	ETHERNET_dma_txd			ETHERNET_dma
AXI_STR_TXC	TARGET	AXIS	ETHERNET_dma_txc			ETHERNET_dma

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_AXI_STR_TXC_TDATA_WIDTH	32
C_AXI_STR_TXD_TDATA_WIDTH	32
C_AXI_STR_RXS_TDATA_WIDTH	32
C_AXI_STR_RXD_TDATA_WIDTH	32
C_AXI_STR_TXC_PROTOCOL	XIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_TXD_PROTOCOL	XIL_AXI_STREAM_ETH_DATA
C_AXI_STR_RXS_PROTOCOL	XIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_RXD_PROTOCOL	XIL_AXI_STREAM_ETH_DATA
C_AXI_STR_AVBTX_PROTOCOL	XIL_AXI_STREAM_ETH_AVB_TX
C_AXI_STR_AVBRX_PROTOCOL	XIL_AXI_STREAM_ETH_AVB_RX
C_FAMILY	virtex6
C_S_AXI_ACLK_FREQ_HZ	100000000
C_BASEADDR	0x41240000
C_HIGHADDR	0x4127FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_ID_WIDTH	4
C_TRANS	A
C_PHYADDR	0B00001
C_INCLUDE_IO	1
C_TYPE	1

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Name	Value
C_PHY_TYPE	1
C_HALFDUP	0
C_TXMEM	4096
C_RXMEM	4096
C_TXCSUM	0
C_RXCSUM	0
C_TXVLAN_TRAN	0
C_RXVLAN_TRAN	0
C_TXVLAN_TAG	0
C_RXVLAN_TAG	0
C_TXVLAN_STRP	0
C_RXVLAN_STRP	0
C_MCAST_EXTEND	0
C_STATS	0
C_AVB	0
C_SIMULATION	0
C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC	0
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-ETHERNET_dma - AXI DMA Engine
AXI MemoryMap to/from AXI Stream Direct Memory Access Engine

-

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IP Specs
Core	Version	Documentation
axi_dma	3.00.a	IP

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-

ETHERNET_dma IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	s_axi_lite_aclk		I	1	clk_100_0000MHzPLL0
1	m_axi_sg_aclk		I	1	clk_100_0000MHzPLL0
2	m_axi_mm2s_aclk		I	1	clk_100_0000MHzPLL0
3	m_axi_s2mm_aclk		I	1	clk_100_0000MHzPLL0
4	mm2s_prmry_reset_out_n		O	1	AXI_STR_TXD_ARESETN
5	mm2s_cntrl_reset_out_n		O	1	AXI_STR_TXC_ARESETN
6	s2mm_prmry_reset_out_n		O	1	AXI_STR_RXD_ARESETN
7	s2mm_sts_reset_out_n		O	1	AXI_STR_RXS_ARESETN
8	mm2s_introut		O	1	ETHERNET_dma_mm2s_introut
9	s2mm_introut		O	1	ETHERNET_dma_s2mm_introut
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
M_AXIS_MM2S	INITIATOR	AXIS	ETHERNET_dma_txd			ETHERNET
M_AXIS_CNTRL	INITIATOR	AXIS	ETHERNET_dma_txc			ETHERNET
M_AXI_SG	MASTER	AXI	axi4_0			2 Peripherals.
M_AXI_MM2S	MASTER	AXI	axi4_0			2 Peripherals.
M_AXI_S2MM	MASTER	AXI	axi4_0			2 Peripherals.
S_AXI_LITE	SLAVE	AXI	axi4lite_0			8 Peripherals.
S_AXIS_STS	TARGET	AXIS	ETHERNET_dma_rxs			ETHERNET
S_AXIS_S2MM	TARGET	AXIS	ETHERNET_dma_rxd			ETHERNET

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

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Name	Value
C_S_AXI_LITE_ADDR_WIDTH	32
C_S_AXI_LITE_DATA_WIDTH	32
C_DLYTMR_RESOLUTION	1250
C_PRMRY_IS_ACLK_ASYNC	0
C_SG_INCLUDE_DESC_QUEUE	1
C_SG_INCLUDE_STSCNTRL_STRM	1
C_SG_USE_STSAPP_LENGTH	1
C_SG_LENGTH_WIDTH	16
C_M_AXI_SG_ADDR_WIDTH	32
C_M_AXI_SG_DATA_WIDTH	32
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH	32
C_S_AXIS_S2MM_STS_TDATA_WIDTH	32
C_INCLUDE_MM2S	1
C_INCLUDE_MM2S_DRE	1
C_MM2S_BURST_SIZE	16
C_M_AXI_MM2S_ADDR_WIDTH	32
C_M_AXI_MM2S_DATA_WIDTH	32
C_M_AXIS_MM2S_TDATA_WIDTH	32
C_INCLUDE_S2MM	1
C_INCLUDE_S2MM_DRE	1
C_S2MM_BURST_SIZE	16
C_M_AXI_S2MM_ADDR_WIDTH	32
C_M_AXI_S2MM_DATA_WIDTH	32
C_S_AXIS_S2MM_TDATA_WIDTH	32
C_FAMILY	virtex6
C_BASEADDR	0x41E00000
C_HIGHADDR	0x41E0FFFF
C_S_AXI_LITE_ACLK_FREQ_HZ	100000000
C_M_AXI_SG_ACLK_FREQ_HZ	100000000
C_M_AXI_MM2S_ACLK_FREQ_HZ	100000000
C_M_AXI_S2MM_ACLK_FREQ_HZ	100000000
C_S_AXI_LITE_PROTOCOL	AXI4LITE
C_S_AXI_LITE_SUPPORTS_READ	1
C_S_AXI_LITE_SUPPORTS_WRITE	1
C_M_AXI_SG_PROTOCOL	AXI4
C_M_AXI_SG_SUPPORTS_THREADS	0
C_M_AXI_SG_THREAD_ID_WIDTH	1
C_M_AXI_SG_SUPPORTS_NARROW_BURST	0
C_M_AXI_SG_SUPPORTS_READ	1
C_M_AXI_SG_SUPPORTS_WRITE	1

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_M_AXI_MM2S_PROTOCOL	AXI4
C_M_AXI_MM2S_SUPPORTS_THREADS	0
C_M_AXI_MM2S_THREAD_ID_WIDTH	1
C_M_AXI_MM2S_SUPPORTS_NARROW_BURST	0
C_M_AXI_MM2S_SUPPORTS_READ	1
C_M_AXI_MM2S_SUPPORTS_WRITE	0
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING	4
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH	512
C_M_AXI_S2MM_PROTOCOL	AXI4
C_M_AXI_S2MM_SUPPORTS_THREADS	0
C_M_AXI_S2MM_THREAD_ID_WIDTH	1
C_M_AXI_S2MM_SUPPORTS_NARROW_BURST	0
C_M_AXI_S2MM_SUPPORTS_WRITE	1
C_M_AXI_S2MM_SUPPORTS_READ	0
C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING	4
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH	512
C_M_AXIS_MM2S_PROTOCOL	XIL_AXI_STREAM_ETH_DATA
C_S_AXIS_S2MM_PROTOCOL	XIL_AXI_STREAM_ETH_DATA
C_M_AXIS_CNTRL_PROTOCOL	XIL_AXI_STREAM_ETH_CTRL
C_S_AXIS_STS_PROTOCOL	XIL_AXI_STREAM_ETH_CTRL
C_INTERCONNECT_S_AXI_LITE_AW_REGISTER	1
C_INTERCONNECT_S_AXI_LITE_AR_REGISTER	1
C_INTERCONNECT_S_AXI_LITE_W_REGISTER	1
C_INTERCONNECT_S_AXI_LITE_R_REGISTER	1
C_INTERCONNECT_S_AXI_LITE_B_REGISTER	1
C_INTERCONNECT_M_AXI_SG_AW_REGISTER	1
C_INTERCONNECT_M_AXI_SG_AR_REGISTER	1
C_INTERCONNECT_M_AXI_SG_W_REGISTER	1
C_INTERCONNECT_M_AXI_SG_R_REGISTER	1
C_INTERCONNECT_M_AXI_SG_B_REGISTER	1
C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER	1
C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER	1
C_INTERCONNECT_M_AXI_MM2S_W_REGISTER	1
C_INTERCONNECT_M_AXI_MM2S_R_REGISTER	1
C_INTERCONNECT_M_AXI_MM2S_B_REGISTER	1
C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER	1
C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER	1
C_INTERCONNECT_M_AXI_S2MM_W_REGISTER	1
C_INTERCONNECT_M_AXI_S2MM_R_REGISTER	1
C_INTERCONNECT_M_AXI_S2MM_B_REGISTER	1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

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-

- - - - - - - - - -

-LEDs_4Bits - AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

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IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

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LEDs_4Bits IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_O		O	1	LEDs_4Bits_TRI_O
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

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Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40020000
C_HIGHADDR	0x4002FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	0
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	0
C_DOUT_DEFAULT	0x00000000

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Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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- - - - - - - - - -

-Push_Buttons_4Bits - AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

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IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

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Push_Buttons_4Bits IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_I		I	1	Push_Buttons_4Bits_TRI_I
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	IP2INTC_Irpt		O	1	Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.

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-

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40000000
C_HIGHADDR	0x4000FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	1
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	1
C_DOUT_DEFAULT	0x00000000

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Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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- - - - - - - - - -

-RS232_Uart_1 - AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

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IP Specs
Core	Version	Documentation
axi_uartlite	1.01.a	IP

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RS232_Uart_1 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	TX		O	1	RS232_Uart_1_sout
1	RX		I	1	RS232_Uart_1_sin
2	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
3	Interrupt		O	1	RS232_Uart_1_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.

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-

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_S_AXI_ACLK_FREQ_HZ	100000000
C_BASEADDR	0x40600000
C_HIGHADDR	0x4060FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_BAUDRATE	115200
C_DATA_BITS	8

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Name	Value
C_USE_PARITY	0
C_ODD_PARITY	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-axi_timer_0 - AXI Timer/Counter
Timer counter with AXI interface

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IP Specs
Core	Version	Documentation
axi_timer	1.01.a	IP

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axi_timer_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Interrupt		O	1	axi_timer_0_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.

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-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_FAMILY	virtex6
C_COUNT_WIDTH	32
C_ONE_TIMER_ONLY	0
C_TRIG0_ASSERT	1
C_TRIG1_ASSERT	1

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Name	Value
C_GEN0_ASSERT	1
C_GEN1_ASSERT	1
C_BASEADDR	0x41C00000
C_HIGHADDR	0x41C0FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-

- - -

IP	TOP

-
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-clock_generator_0 - Clock Generator
Clock generator for processor system.

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IP Specs
Core	Version	Documentation
clock_generator	4.01.a	IP

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-

clock_generator_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	RST		I	1	RESET
1	CLKIN		I	1	CLK
2	CLKOUT2		O	1	clk_100_0000MHzPLL0
3	CLKOUT5		O	1	clk_50_0000MHzPLL0
4	CLKOUT3		O	1	clk_125_0000MHz
5	CLKOUT4		O	1	clk_200_0000MHzPLL0
6	CLKOUT0		O	1	clk_600_0000MHzPLL0_nobuf
7	CLKOUT1		O	1	clk_600_0000MHz180PLL0_nobuf
8	LOCKED		O	1	proc_sys_reset_0_Dcm_locked

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_DEVICE	NOT_SET
C_PACKAGE	NOT_SET
C_SPEEDGRADE	NOT_SET
C_CLKIN_FREQ	200000000
C_CLKOUT0_FREQ	600000000
C_CLKOUT0_PHASE	0
C_CLKOUT0_GROUP	PLL0
C_CLKOUT0_BUF	FALSE
C_CLKOUT0_VARIABLE_PHASE	FALSE
C_CLKOUT1_FREQ	600000000
C_CLKOUT1_PHASE	180
C_CLKOUT1_GROUP	PLL0
C_CLKOUT1_BUF	FALSE
C_CLKOUT1_VARIABLE_PHASE	FALSE
C_CLKOUT2_FREQ	100000000
C_CLKOUT2_PHASE	0
C_CLKOUT2_GROUP	PLL0
C_CLKOUT2_BUF	TRUE
C_CLKOUT2_VARIABLE_PHASE	FALSE
C_CLKOUT3_FREQ	125000000
C_CLKOUT3_PHASE	0
C_CLKOUT3_GROUP	NONE
C_CLKOUT3_BUF	TRUE
C_CLKOUT3_VARIABLE_PHASE	FALSE
C_CLKOUT4_FREQ	200000000
C_CLKOUT4_PHASE	0
C_CLKOUT4_GROUP	PLL0
C_CLKOUT4_BUF	TRUE
C_CLKOUT4_VARIABLE_PHASE	FALSE
C_CLKOUT5_FREQ	50000000
C_CLKOUT5_PHASE	0
C_CLKOUT5_GROUP	PLL0
C_CLKOUT5_BUF	TRUE
C_CLKOUT5_VARIABLE_PHASE	FALSE
C_CLKOUT6_FREQ	0
C_CLKOUT6_PHASE	0
C_CLKOUT6_GROUP	NONE
C_CLKOUT6_BUF	TRUE
C_CLKOUT6_VARIABLE_PHASE	FALSE
C_CLKOUT7_FREQ	0
C_CLKOUT7_PHASE	0
C_CLKOUT7_GROUP	NONE
C_CLKOUT7_BUF	TRUE
C_CLKOUT7_VARIABLE_PHASE	FALSE
C_CLKOUT8_FREQ	0
C_CLKOUT8_PHASE	0
C_CLKOUT8_GROUP	NONE

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_CLKOUT8_BUF	TRUE
C_CLKOUT8_VARIABLE_PHASE	FALSE
C_CLKOUT9_FREQ	0
C_CLKOUT9_PHASE	0
C_CLKOUT9_GROUP	NONE
C_CLKOUT9_BUF	TRUE
C_CLKOUT9_VARIABLE_PHASE	FALSE
C_CLKOUT10_FREQ	0
C_CLKOUT10_PHASE	0
C_CLKOUT10_GROUP	NONE
C_CLKOUT10_BUF	TRUE
C_CLKOUT10_VARIABLE_PHASE	FALSE
C_CLKOUT11_FREQ	0
C_CLKOUT11_PHASE	0
C_CLKOUT11_GROUP	NONE
C_CLKOUT11_BUF	TRUE
C_CLKOUT11_VARIABLE_PHASE	FALSE
C_CLKOUT12_FREQ	0
C_CLKOUT12_PHASE	0
C_CLKOUT12_GROUP	NONE
C_CLKOUT12_BUF	TRUE
C_CLKOUT12_VARIABLE_PHASE	FALSE
C_CLKOUT13_FREQ	0
C_CLKOUT13_PHASE	0
C_CLKOUT13_GROUP	NONE
C_CLKOUT13_BUF	TRUE
C_CLKOUT13_VARIABLE_PHASE	FALSE
C_CLKOUT14_FREQ	0
C_CLKOUT14_PHASE	0
C_CLKOUT14_GROUP	NONE
C_CLKOUT14_BUF	TRUE
C_CLKOUT14_VARIABLE_PHASE	FALSE
C_CLKOUT15_FREQ	0
C_CLKOUT15_PHASE	0
C_CLKOUT15_GROUP	NONE
C_CLKOUT15_BUF	TRUE
C_CLKOUT15_VARIABLE_PHASE	FALSE
C_CLKFBIN_FREQ	0
C_CLKFBIN_DESKEW	NONE
C_CLKFBOUT_FREQ	0
C_CLKFBOUT_PHASE	0
C_CLKFBOUT_GROUP	NONE
C_CLKFBOUT_BUF	TRUE
C_PSDONE_GROUP	NONE
C_EXT_RESET_HIGH	1
C_CLK_PRIMITIVE_FEEDBACK_BUF	FALSE
C_CLK_GEN	UPDATE

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-proc_sys_reset_0 - Processor System Reset Module
Reset management module

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IP Specs
Core	Version	Documentation
proc_sys_reset	3.00.a	IP

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proc_sys_reset_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	Ext_Reset_In		I	1	RESET
1	MB_Reset		O	1	proc_sys_reset_0_MB_Reset
2	Slowest_sync_clk		I	1	clk_50_0000MHzPLL0
3	Interconnect_aresetn		O	1	proc_sys_reset_0_Interconnect_aresetn
4	Dcm_locked		I	1	proc_sys_reset_0_Dcm_locked
5	MB_Debug_Sys_Rst		I	1	proc_sys_reset_0_MB_Debug_Sys_Rst
6	BUS_STRUCT_RESET		O	1	proc_sys_reset_0_BUS_STRUCT_RESET

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Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_SUBFAMILY		lx
C_EXT_RST_WIDTH		4
C_AUX_RST_WIDTH		4
C_EXT_RESET_HIGH		1
C_AUX_RESET_HIGH		1
C_NUM_BUS_RST		1
C_NUM_PERP_RST		1
C_NUM_INTERCONNECT_ARESETN		1
C_NUM_PERP_ARESETN		1
C_FAMILY		virtex5

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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Timing Information	TOP

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Post Synthesis Clock Limits
- No clocks could be identified in the design. Run platgen to generate synthesis information. -

-

- diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html deleted file mode 100644 index a178f79c0..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html +++ /dev/null @@ -1,6014 +0,0 @@ - - - - -XPS Project Report - - - - - - - -

TABLE OF CONTENTS

-
Overview
Block Diagram
External Ports
Processor
   microblaze_0
Debuggers
   debug_module
Interrupt Controllers
   microblaze_0_intc
Busses
   axi4_0
   axi4lite_0
   microblaze_0_dlmb
   microblaze_0_ilmb
Memory
   microblaze_0_bram_block
Memory Controllers
   MCB_DDR3
   microblaze_0_d_bram_ctrl
   microblaze_0_i_bram_ctrl
Peripherals
   ETHERNET
   ETHERNET_dma
   LEDs_4Bits
   Push_Buttons_4Bits
   RS232_Uart_1
   axi_timer_0
IP
   clock_generator_0
   proc_sys_reset_0
Timing Information -

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Overview	TOC

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Resources Used
1	MicroBlaze
2	AXI Interconnect
2	Local Memory Bus (LMB) 1.0
1	Block RAM (BRAM) Block
2	LMB BRAM Controller
1	AXI S6 Memory Controller(DDR/DDR2/DDR3)
1	Processor System Reset Module
1	Clock Generator
1	MicroBlaze Debug Module (MDM)
1	AXI UART (Lite)
2	AXI General Purpose IO
1	AXI Ethernet
1	AXI DMA Engine
1	AXI Interrupt Controller
1	AXI Timer/Counter

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Specifics
Generated	Sat Aug 27 15:05:44 2011
EDK Version	13.1
Device Family	spartan6
Device	xc6slx45tfgg484-3

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Block Diagram	TOC

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BlockDiagram

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External Ports	TOC

-
- - - - - - -

- These are the external ports defined in the MHS file. -

-Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK)
INTR  indicates Interrupt ports,(SIGIS = INTR)
RESET  indicates Reset ports, (SIGIS = RST)
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

#	NAME		DIR	[LSB:MSB]	SIG		ATTRIBUTES
-SHARED -	RESET		I	1	RESET		RESET
-ETHERNET -	ETHERNET_MII_TX_CLK		I	1	ETHERNET_MII_TX_CLK
-ETHERNET -	ETHERNET_RXD		I	0:7	ETHERNET_RXD
-ETHERNET -	ETHERNET_RX_CLK		I	1	ETHERNET_RX_CLK
-ETHERNET -	ETHERNET_RX_DV		I	1	ETHERNET_RX_DV
-ETHERNET -	ETHERNET_RX_ER		I	1	ETHERNET_RX_ER
-ETHERNET -	ETHERNET_MDIO		IO	1	ETHERNET_MDIO
-ETHERNET -	ETHERNET_MDC		O	1	ETHERNET_MDC
-ETHERNET -	ETHERNET_PHY_RST_N		O	1	ETHERNET_PHY_RST_N
-ETHERNET -	ETHERNET_TXD		O	0:7	ETHERNET_TXD
-ETHERNET -	ETHERNET_TX_CLK		O	1	ETHERNET_TX_CLK
-ETHERNET -	ETHERNET_TX_EN		O	1	ETHERNET_TX_EN
-ETHERNET -	ETHERNET_TX_ER		O	1	ETHERNET_TX_ER
-LEDs_4Bits -	LEDs_4Bits_TRI_O		O	0:3	LEDs_4Bits_TRI_O
-MCB_DDR3 -	mcbx_dram_dq		IO	0:15	mcbx_dram_dq
-MCB_DDR3 -	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
-MCB_DDR3 -	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
-MCB_DDR3 -	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
-MCB_DDR3 -	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
-MCB_DDR3 -	rzq		IO	1	rzq
-MCB_DDR3 -	zio		IO	1	zio
-MCB_DDR3 -	mcbx_dram_addr		O	0:12	mcbx_dram_addr
-MCB_DDR3 -	mcbx_dram_ba		O	0:2	mcbx_dram_ba
-MCB_DDR3 -	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
-MCB_DDR3 -	mcbx_dram_cke		O	1	mcbx_dram_cke
-MCB_DDR3 -	mcbx_dram_clk		O	1	mcbx_dram_clk
-MCB_DDR3 -	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
-MCB_DDR3 -	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
-MCB_DDR3 -	mcbx_dram_ldm		O	1	mcbx_dram_ldm
-MCB_DDR3 -	mcbx_dram_odt		O	1	mcbx_dram_odt
-MCB_DDR3 -	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
-MCB_DDR3 -	mcbx_dram_udm		O	1	mcbx_dram_udm
-MCB_DDR3 -	mcbx_dram_we_n		O	1	mcbx_dram_we_n
-Push_Buttons_4Bits -	Push_Buttons_4Bits_TRI_I		I	0:3	Push_Buttons_4Bits_TRI_I
-RS232_Uart_1 -	RS232_Uart_1_sin		I	1	RS232_Uart_1_sin
-RS232_Uart_1 -	RS232_Uart_1_sout		O	1	RS232_Uart_1_sout
-clock_generator_0 -	CLK_N		I	1	CLK		CLK
-clock_generator_0 -	CLK_P		I	1	CLK		CLK

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Processors	TOC

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-microblaze_0 - MicroBlaze
The MicroBlaze 32 bit soft processor

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IP Specs
Core	Version	Documentation
microblaze	8.10.a	IP

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microblaze_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	MB_RESET		I	1	proc_sys_reset_0_MB_Reset
1	CLK		I	1	clk_100_0000MHzPLL0
2	INTERRUPT		I	1	microblaze_0_interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
M_AXI_DP	MASTER	AXI	axi4lite_0			8 Peripherals.
DLMB	MASTER	LMB	microblaze_0_dlmb			microblaze_0_d_bram_ctrl
ILMB	MASTER	LMB	microblaze_0_ilmb			microblaze_0_i_bram_ctrl
M_AXI_DC	MASTER	AXI	axi4_0			2 Peripherals.
M_AXI_IC	MASTER	AXI	axi4_0			2 Peripherals.
DEBUG	TARGET	XIL_MBDEBUG3	microblaze_0_debug			debug_module

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_SCO	0
C_FREQ	0
C_DATA_SIZE	32
C_DYNAMIC_BUS_SIZING	1
C_FAMILY	virtex5
C_INSTANCE	microblaze
C_FAULT_TOLERANT	0
C_ECC_USE_CE_EXCEPTION	0
C_ENDIANNESS	0
C_AREA_OPTIMIZED	0
C_OPTIMIZATION	0
C_INTERCONNECT	2
C_STREAM_INTERCONNECT	0
C_DPLB_DWIDTH	32
C_DPLB_NATIVE_DWIDTH	32
C_DPLB_BURST_EN	0
C_DPLB_P2P	0
C_IPLB_DWIDTH	32
C_IPLB_NATIVE_DWIDTH	32
C_IPLB_BURST_EN	0
C_IPLB_P2P	0
C_M_AXI_DP_SUPPORTS_THREADS	0
C_M_AXI_DP_THREAD_ID_WIDTH	1
C_M_AXI_DP_SUPPORTS_READ	1
C_M_AXI_DP_SUPPORTS_WRITE	1
C_M_AXI_DP_SUPPORTS_NARROW_BURST	0
C_M_AXI_DP_DATA_WIDTH	32
C_M_AXI_DP_ADDR_WIDTH	32
C_M_AXI_DP_PROTOCOL	AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS	0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING	1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING	1
C_M_AXI_IP_SUPPORTS_THREADS	0
C_M_AXI_IP_THREAD_ID_WIDTH	1
C_M_AXI_IP_SUPPORTS_READ	1
C_M_AXI_IP_SUPPORTS_WRITE	0
C_M_AXI_IP_SUPPORTS_NARROW_BURST	0
C_M_AXI_IP_DATA_WIDTH	32
C_M_AXI_IP_ADDR_WIDTH	32
C_M_AXI_IP_PROTOCOL	AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING	1
C_D_AXI	0
C_D_PLB	0
C_D_LMB	1
C_I_AXI	0
C_I_PLB	0
C_I_LMB	1
C_USE_MSR_INSTR	1
C_USE_PCMP_INSTR	1
C_USE_BARREL	1
C_USE_DIV	0
C_USE_HW_MUL	1
C_USE_FPU	0
C_UNALIGNED_EXCEPTIONS	0
C_ILL_OPCODE_EXCEPTION	0
C_M_AXI_I_BUS_EXCEPTION	0
C_M_AXI_D_BUS_EXCEPTION	0
C_IPLB_BUS_EXCEPTION	0
C_DPLB_BUS_EXCEPTION	0
C_DIV_ZERO_EXCEPTION	0
C_FPU_EXCEPTION	0
C_FSL_EXCEPTION	0
C_USE_STACK_PROTECTION	0
C_PVR	0
C_PVR_USER1	0x00
C_PVR_USER2	0x00000000
C_DEBUG_ENABLED	1
C_NUMBER_OF_PC_BRK	7
C_NUMBER_OF_RD_ADDR_BRK	2
C_NUMBER_OF_WR_ADDR_BRK	2
C_INTERRUPT_IS_EDGE	0
C_EDGE_IS_POSITIVE	1
C_RESET_MSR	0x00000000
C_OPCODE_0x0_ILLEGAL	0
C_FSL_LINKS	0
C_FSL_DATA_SIZE	32
C_USE_EXTENDED_FSL_INSTR	0
C_M0_AXIS_PROTOCOL	GENERIC
C_S0_AXIS_PROTOCOL	GENERIC
C_M1_AXIS_PROTOCOL	GENERIC
C_S1_AXIS_PROTOCOL	GENERIC
C_M2_AXIS_PROTOCOL	GENERIC
C_S2_AXIS_PROTOCOL	GENERIC
C_M3_AXIS_PROTOCOL	GENERIC
C_S3_AXIS_PROTOCOL	GENERIC
C_M4_AXIS_PROTOCOL	GENERIC
C_S4_AXIS_PROTOCOL	GENERIC
C_M5_AXIS_PROTOCOL	GENERIC
C_S5_AXIS_PROTOCOL	GENERIC
C_M6_AXIS_PROTOCOL	GENERIC
C_S6_AXIS_PROTOCOL	GENERIC
C_M7_AXIS_PROTOCOL	GENERIC
C_S7_AXIS_PROTOCOL	GENERIC
C_M8_AXIS_PROTOCOL	GENERIC
C_S8_AXIS_PROTOCOL	GENERIC
C_M9_AXIS_PROTOCOL	GENERIC
C_S9_AXIS_PROTOCOL	GENERIC
C_M10_AXIS_PROTOCOL	GENERIC
C_S10_AXIS_PROTOCOL	GENERIC
C_M11_AXIS_PROTOCOL	GENERIC
C_S11_AXIS_PROTOCOL	GENERIC
C_M12_AXIS_PROTOCOL	GENERIC
C_S12_AXIS_PROTOCOL	GENERIC
C_M13_AXIS_PROTOCOL	GENERIC
C_S13_AXIS_PROTOCOL	GENERIC
C_M14_AXIS_PROTOCOL	GENERIC
C_S14_AXIS_PROTOCOL	GENERIC
C_M15_AXIS_PROTOCOL	GENERIC
C_S15_AXIS_PROTOCOL	GENERIC
C_M0_AXIS_DATA_WIDTH	32
C_S0_AXIS_DATA_WIDTH	32
C_M1_AXIS_DATA_WIDTH	32
C_S1_AXIS_DATA_WIDTH	32
C_M2_AXIS_DATA_WIDTH	32
C_S2_AXIS_DATA_WIDTH	32

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_M3_AXIS_DATA_WIDTH	32
C_S3_AXIS_DATA_WIDTH	32
C_M4_AXIS_DATA_WIDTH	32
C_S4_AXIS_DATA_WIDTH	32
C_M5_AXIS_DATA_WIDTH	32
C_S5_AXIS_DATA_WIDTH	32
C_M6_AXIS_DATA_WIDTH	32
C_S6_AXIS_DATA_WIDTH	32
C_M7_AXIS_DATA_WIDTH	32
C_S7_AXIS_DATA_WIDTH	32
C_M8_AXIS_DATA_WIDTH	32
C_S8_AXIS_DATA_WIDTH	32
C_M9_AXIS_DATA_WIDTH	32
C_S9_AXIS_DATA_WIDTH	32
C_M10_AXIS_DATA_WIDTH	32
C_S10_AXIS_DATA_WIDTH	32
C_M11_AXIS_DATA_WIDTH	32
C_S11_AXIS_DATA_WIDTH	32
C_M12_AXIS_DATA_WIDTH	32
C_S12_AXIS_DATA_WIDTH	32
C_M13_AXIS_DATA_WIDTH	32
C_S13_AXIS_DATA_WIDTH	32
C_M14_AXIS_DATA_WIDTH	32
C_S14_AXIS_DATA_WIDTH	32
C_M15_AXIS_DATA_WIDTH	32
C_S15_AXIS_DATA_WIDTH	32
C_ICACHE_BASEADDR	0xC0000000
C_ICACHE_HIGHADDR	0xC7FFFFFF
C_USE_ICACHE	1
C_ALLOW_ICACHE_WR	1
C_ADDR_TAG_BITS	17
C_CACHE_BYTE_SIZE	16384
C_ICACHE_USE_FSL	1
C_ICACHE_LINE_LEN	4
C_ICACHE_ALWAYS_USED	1
C_ICACHE_INTERFACE	0
C_ICACHE_VICTIMS	0
C_ICACHE_STREAMS	0
C_ICACHE_FORCE_TAG_LUTRAM	0
C_ICACHE_DATA_WIDTH	0
C_M_AXI_IC_SUPPORTS_THREADS	0
C_M_AXI_IC_THREAD_ID_WIDTH	1
C_M_AXI_IC_SUPPORTS_READ	1
C_M_AXI_IC_SUPPORTS_WRITE	0
C_M_AXI_IC_SUPPORTS_NARROW_BURST	0
C_M_AXI_IC_DATA_WIDTH	32
C_M_AXI_IC_ADDR_WIDTH	32
C_M_AXI_IC_PROTOCOL	AXI4
C_M_AXI_IC_USER_VALUE	0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_IC_AWUSER_WIDTH	5
C_M_AXI_IC_ARUSER_WIDTH	5
C_M_AXI_IC_WUSER_WIDTH	1
C_M_AXI_IC_RUSER_WIDTH	1
C_M_AXI_IC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING	2
C_DCACHE_BASEADDR	0xC0000000
C_DCACHE_HIGHADDR	0xC7FFFFFF
C_USE_DCACHE	1
C_ALLOW_DCACHE_WR	1
C_DCACHE_ADDR_TAG	17
C_DCACHE_BYTE_SIZE	16384
C_DCACHE_USE_FSL	1
C_DCACHE_LINE_LEN	4
C_DCACHE_ALWAYS_USED	1
C_DCACHE_INTERFACE	0
C_DCACHE_USE_WRITEBACK	0
C_DCACHE_VICTIMS	0
C_DCACHE_FORCE_TAG_LUTRAM	0
C_DCACHE_DATA_WIDTH	0
C_M_AXI_DC_SUPPORTS_THREADS	0
C_M_AXI_DC_THREAD_ID_WIDTH	1
C_M_AXI_DC_SUPPORTS_READ	1
C_M_AXI_DC_SUPPORTS_WRITE	1
C_M_AXI_DC_SUPPORTS_NARROW_BURST	0
C_M_AXI_DC_DATA_WIDTH	32
C_M_AXI_DC_ADDR_WIDTH	32
C_M_AXI_DC_PROTOCOL	AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS	0
C_M_AXI_DC_USER_VALUE	0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS	1
C_M_AXI_DC_AWUSER_WIDTH	5
C_M_AXI_DC_ARUSER_WIDTH	5
C_M_AXI_DC_WUSER_WIDTH	1
C_M_AXI_DC_RUSER_WIDTH	1
C_M_AXI_DC_BUSER_WIDTH	1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING	2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING	32
C_USE_MMU	0
C_MMU_DTLB_SIZE	4
C_MMU_ITLB_SIZE	2
C_MMU_TLB_ACCESS	3
C_MMU_ZONES	16
C_MMU_PRIVILEGED_INSTR	0
C_USE_INTERRUPT	0
C_USE_EXT_BRK	0
C_USE_EXT_NM_BRK	0
C_USE_BRANCH_TARGET_CACHE	0
C_BRANCH_TARGET_CACHE_SIZE	0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DC_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AW_REGISTER	1
C_INTERCONNECT_M_AXI_DP_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DP_W_REGISTER	1
C_INTERCONNECT_M_AXI_DP_R_REGISTER	1
C_INTERCONNECT_M_AXI_DP_B_REGISTER	1
C_INTERCONNECT_M_AXI_DC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_DC_R_REGISTER	1
C_INTERCONNECT_M_AXI_DC_B_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AW_REGISTER	1
C_INTERCONNECT_M_AXI_IC_AR_REGISTER	1
C_INTERCONNECT_M_AXI_IC_W_REGISTER	1
C_INTERCONNECT_M_AXI_IC_R_REGISTER	1
C_INTERCONNECT_M_AXI_IC_B_REGISTER	1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Debuggers	TOC

-
- - -

- - - - - - - - - -

-debug_module - MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
mdm	2.00.b	IP

-

-

debug_module IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Debug_SYS_Rst		O	1	proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
MBDEBUG_0	INITIATOR	XIL_MBDEBUG3	microblaze_0_debug			microblaze_0
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_JTAG_CHAIN	2
C_INTERCONNECT	2
C_BASEADDR	0x74800000
C_HIGHADDR	0x7480FFFF
C_SPLB_AWIDTH	32
C_SPLB_DWIDTH	32
C_SPLB_P2P	0
C_SPLB_MID_WIDTH	3
C_SPLB_NUM_MASTERS	8
C_SPLB_NATIVE_DWIDTH	32

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_SPLB_SUPPORT_BURSTS	0
C_MB_DBG_PORTS	1
C_USE_UART	1
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Interrupt Controllers	TOC

-
- - -

- - - - - - - - - -

-microblaze_0_intc - AXI Interrupt Controller
intc core attached to the AXI

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_intc	1.01.a	IP

-

-

microblaze_0_intc IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	IRQ		O	1	microblaze_0_interrupt
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	INTR		I	1	ETHERNET_INTERRUPT & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut & Push_Buttons_4Bits_IP2INTC_Irpt & RS232_Uart_1_Interrupt & axi_timer_0_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.
-Interrupt Priorities
Priority	SIG			MODULE
0	ETHERNET_INTERRUPT			ETHERNET
1	ETHERNET_dma_mm2s_introut			ETHERNET_dma
2	ETHERNET_dma_s2mm_introut			ETHERNET_dma
3	Push_Buttons_4Bits_IP2INTC_Irpt			Push_Buttons_4Bits
4	RS232_Uart_1_Interrupt			RS232_Uart_1
5	axi_timer_0_Interrupt			axi_timer_0

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-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x41200000
C_HIGHADDR	0x4120FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_NUM_INTR_INPUTS	2
C_KIND_OF_INTR	0xFFFFFFFF
C_KIND_OF_EDGE	0xFFFFFFFF
C_KIND_OF_LVL	0xFFFFFFFF
C_HAS_IPR	1
C_HAS_SIE	1

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_HAS_CIE	1
C_HAS_IVR	1
C_IRQ_IS_LEVEL	1
C_IRQ_ACTIVE	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Busses	TOC

-
- - - - - - - - -

- - - - - - - - - -

-axi4_0 - AXI Interconnect
AXI4 Memory-Mapped Interconnect

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

-

-

axi4_0 IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	interconnect_aclk		I	1	clk_100_0000MHzPLL0
1	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DC
microblaze_0					MASTER	M_AXI_IC
ETHERNET_dma					MASTER	M_AXI_SG
ETHERNET_dma					MASTER	M_AXI_MM2S
ETHERNET_dma					MASTER	M_AXI_S2MM
MCB_DDR3					SLAVE	S0_AXI

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	1
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-axi4lite_0 - AXI Interconnect
AXI4 Memory-Mapped Interconnect

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_interconnect	1.02.a	IP

-

-

axi4lite_0 IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	INTERCONNECT_ARESETN		I	1	proc_sys_reset_0_Interconnect_aresetn
1	INTERCONNECT_ACLK		I	1	clk_50_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	M_AXI_DP
debug_module					SLAVE	S_AXI
RS232_Uart_1					SLAVE	S_AXI
LEDs_4Bits					SLAVE	S_AXI
Push_Buttons_4Bits					SLAVE	S_AXI
ETHERNET					SLAVE	S_AXI
ETHERNET_dma					SLAVE	S_AXI_LITE
microblaze_0_intc					SLAVE	S_AXI
axi_timer_0					SLAVE	S_AXI

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	rtl
C_BASEFAMILY	rtl
C_NUM_SLAVE_SLOTS	1
C_NUM_MASTER_SLOTS	1
C_AXI_ID_WIDTH	1
C_AXI_ADDR_WIDTH	32
C_AXI_DATA_MAX_WIDTH	32
C_S_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH	0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH	32
C_S_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR	0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT	0b0000000000000000
C_S_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_M_AXI_ACLK_RATIO	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC	0b0000000000000000
C_INTERCONNECT_ACLK_RATIO	1
C_S_AXI_SUPPORTS_WRITE	0b1111111111111111
C_S_AXI_SUPPORTS_READ	0b1111111111111111
C_M_AXI_SUPPORTS_WRITE	0b1111111111111111
C_M_AXI_SUPPORTS_READ	0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS	0
C_AXI_AWUSER_WIDTH	1
C_AXI_ARUSER_WIDTH	1
C_AXI_WUSER_WIDTH	1
C_AXI_RUSER_WIDTH	1
C_AXI_BUSER_WIDTH	1
C_AXI_CONNECTIVITY	0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD	0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING	0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST	0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_READ_ACCEPTANCE	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_READ_ISSUING	0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE	0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE	0b1111111111111111
C_S_AXI_READ_FIFO_DELAY	0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE	0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY	0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE	0b1111111111111111
C_M_AXI_READ_FIFO_DELAY	0b0000000000000000
C_S_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER	0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER	0
C_INTERCONNECT_CONNECTIVITY_MODE	0
C_USE_CTRL_PORT	0
C_USE_INTERRUPT	1
C_RANGE_CHECK	2
C_S_AXI_CTRL_PROTOCOL	AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_BASEADDR	0xFFFFFFFF
C_HIGHADDR	0x00000000
C_DEBUG	0

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

- - - - - - - - - -

-microblaze_0_dlmb - Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

-

-

microblaze_0_dlmb IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	DLMB
microblaze_0_d_bram_ctrl					SLAVE	SLMB

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Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-microblaze_0_ilmb - Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

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IP Specs
Core	Version	Documentation
lmb_v10	2.00.a	IP

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-

microblaze_0_ilmb IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
1	LMB_CLK		I	1	clk_100_0000MHzPLL0
Bus Connections
INSTANCE					INTERFACE TYPE	INTERFACE NAME
microblaze_0					MASTER	ILMB
microblaze_0_i_bram_ctrl					SLAVE	SLMB

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-

- - - - - - - - - - - - - - - - - - - - -

Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_LMB_NUM_SLAVES		4
C_LMB_AWIDTH		32
C_LMB_DWIDTH		32
C_EXT_RESET_HIGH		1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

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-

- - -

Memorys	TOC

-
- - -

- - - - - - - - - -

-microblaze_0_bram_block - Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
bram_block	1.00.a	IP

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-

microblaze_0_bram_block IP Image

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Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
PORTA	TARGET	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_i_bram_ctrl
PORTB	TARGET	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_d_bram_ctrl

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Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_MEMSIZE		2048
C_PORT_DWIDTH		32
C_PORT_AWIDTH		32
C_NUM_WE		4
C_FAMILY		virtex2

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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- - -

Memory Controllers	TOC

-
- - - - - - -

- - - - - - - - - -

-MCB_DDR3 - AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

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- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_s6_ddrx	1.02.a	IP

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-

MCB_DDR3 IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	mcbx_dram_clk		O	1	mcbx_dram_clk
1	mcbx_dram_clk_n		O	1	mcbx_dram_clk_n
2	mcbx_dram_cke		O	1	mcbx_dram_cke
3	mcbx_dram_odt		O	1	mcbx_dram_odt
4	mcbx_dram_ras_n		O	1	mcbx_dram_ras_n
5	mcbx_dram_cas_n		O	1	mcbx_dram_cas_n
6	mcbx_dram_we_n		O	1	mcbx_dram_we_n
7	mcbx_dram_udm		O	1	mcbx_dram_udm
8	mcbx_dram_ldm		O	1	mcbx_dram_ldm
9	mcbx_dram_ba		O	1	mcbx_dram_ba
10	mcbx_dram_addr		O	1	mcbx_dram_addr
11	mcbx_dram_ddr3_rst		O	1	mcbx_dram_ddr3_rst
12	mcbx_dram_dq		IO	1	mcbx_dram_dq
13	mcbx_dram_dqs		IO	1	mcbx_dram_dqs
14	mcbx_dram_dqs_n		IO	1	mcbx_dram_dqs_n
15	mcbx_dram_udqs		IO	1	mcbx_dram_udqs
16	mcbx_dram_udqs_n		IO	1	mcbx_dram_udqs_n
17	rzq		IO	1	rzq
18	zio		IO	1	zio
19	s0_axi_aclk		I	1	clk_100_0000MHzPLL0
20	ui_clk		I	1	clk_100_0000MHzPLL0
21	sysclk_2x		I	1	clk_600_0000MHzPLL0_nobuf
22	sysclk_2x_180		I	1	clk_600_0000MHz180PLL0_nobuf
23	SYS_RST		I	1	proc_sys_reset_0_BUS_STRUCT_RESET
24	PLL_LOCK		I	1	proc_sys_reset_0_Dcm_locked
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S0_AXI	SLAVE	AXI	axi4_0			2 Peripherals.

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-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_MCB_LOC	MEMC3
C_MCB_RZQ_LOC	K7
C_MCB_ZIO_LOC	R7
C_MCB_PERFORMANCE	STANDARD
C_BYPASS_CORE_UCF	0
C_S0_AXI_BASEADDR	0x80000000
C_S0_AXI_HIGHADDR	0x807FFFFF
C_S1_AXI_BASEADDR	0xFFFFFFFF
C_S1_AXI_HIGHADDR	0x00000000
C_S2_AXI_BASEADDR	0xFFFFFFFF
C_S2_AXI_HIGHADDR	0x00000000
C_S3_AXI_BASEADDR	0xFFFFFFFF
C_S3_AXI_HIGHADDR	0x00000000
C_S4_AXI_BASEADDR	0xFFFFFFFF
C_S4_AXI_HIGHADDR	0x00000000
C_S5_AXI_BASEADDR	0xFFFFFFFF
C_S5_AXI_HIGHADDR	0x00000000
C_MEM_TYPE	DDR3
C_MEM_PARTNO	MT41J64M16XX-187E
C_MEM_BASEPARTNO	NOT_SET
C_NUM_DQ_PINS	16
C_MEM_ADDR_WIDTH	13
C_MEM_BANKADDR_WIDTH	3
C_MEM_NUM_COL_BITS	10
C_MEM_TRAS	-1
C_MEM_TRCD	-1
C_MEM_TREFI	-1
C_MEM_TRFC	-1
C_MEM_TRP	-1
C_MEM_TWR	-1
C_MEM_TRTP	-1
C_MEM_TWTR	-1
C_PORT_CONFIG	B32_B32_B32_B32
C_SKIP_IN_TERM_CAL	0
C_SKIP_IN_TERM_CAL_VALUE	NONE
C_MEMCLK_PERIOD	0
C_MEM_ADDR_ORDER	ROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT	512
C_MEM_CAS_LATENCY	6
C_SIMULATION	FALSE
C_MEM_DDR1_2_ODS	FULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS	CLASS_II
C_MEM_DDR2_RTT	150OHMS
C_MEM_DDR2_DIFF_DQS_EN	YES
C_MEM_DDR2_3_PA_SR	FULL
C_MEM_DDR2_3_HIGH_TEMP_SR	NORMAL
C_MEM_DDR3_CAS_WR_LATENCY	5
C_MEM_DDR3_CAS_LATENCY	6
C_MEM_DDR3_ODS	DIV6
C_MEM_DDR3_RTT	DIV4
C_MEM_DDR3_AUTO_SR	ENABLED
C_MEM_MOBILE_PA_SR	FULL
C_MEM_MDDR_ODS	FULL
C_ARB_ALGORITHM	0
C_ARB_NUM_TIME_SLOTS	12
C_ARB_TIME_SLOT_0	0b000000000001010011
C_ARB_TIME_SLOT_1	0b000000001010011000
C_ARB_TIME_SLOT_2	0b000000010011000001
C_ARB_TIME_SLOT_3	0b000000011000001010
C_ARB_TIME_SLOT_4	0b000000000001010011
C_ARB_TIME_SLOT_5	0b000000001010011000
C_ARB_TIME_SLOT_6	0b000000010011000001
C_ARB_TIME_SLOT_7	0b000000011000001010
C_ARB_TIME_SLOT_8	0b000000000001010011
C_ARB_TIME_SLOT_9	0b000000001010011000
C_ARB_TIME_SLOT_10	0b000000010011000001
C_ARB_TIME_SLOT_11	0b000000011000001010
C_S0_AXI_ENABLE	1
C_S0_AXI_PROTOCOL	AXI4
C_S0_AXI_ID_WIDTH	4
C_S0_AXI_ADDR_WIDTH	32
C_S0_AXI_DATA_WIDTH	32
C_S0_AXI_SUPPORTS_READ	1
C_S0_AXI_SUPPORTS_WRITE	1
C_S0_AXI_SUPPORTS_NARROW_BURST	1
C_S0_AXI_REG_EN0	0x00000
C_S0_AXI_REG_EN1	0x01000
C_S0_AXI_STRICT_COHERENCY	0
C_S0_AXI_ENABLE_AP	0

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE	4
C_S1_AXI_ENABLE	0
C_S1_AXI_PROTOCOL	AXI4
C_S1_AXI_ID_WIDTH	4
C_S1_AXI_ADDR_WIDTH	32
C_S1_AXI_DATA_WIDTH	32
C_S1_AXI_SUPPORTS_READ	1
C_S1_AXI_SUPPORTS_WRITE	1
C_S1_AXI_SUPPORTS_NARROW_BURST	1
C_S1_AXI_REG_EN0	0x00000
C_S1_AXI_REG_EN1	0x01000
C_S1_AXI_STRICT_COHERENCY	1
C_S1_AXI_ENABLE_AP	0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE	4
C_S2_AXI_ENABLE	0
C_S2_AXI_PROTOCOL	AXI4
C_S2_AXI_ID_WIDTH	4
C_S2_AXI_ADDR_WIDTH	32
C_S2_AXI_DATA_WIDTH	32
C_S2_AXI_SUPPORTS_READ	1
C_S2_AXI_SUPPORTS_WRITE	1
C_S2_AXI_SUPPORTS_NARROW_BURST	1
C_S2_AXI_REG_EN0	0x00000
C_S2_AXI_REG_EN1	0x01000
C_S2_AXI_STRICT_COHERENCY	1
C_S2_AXI_ENABLE_AP	0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE	4
C_S3_AXI_ENABLE	0
C_S3_AXI_PROTOCOL	AXI4
C_S3_AXI_ID_WIDTH	4
C_S3_AXI_ADDR_WIDTH	32
C_S3_AXI_DATA_WIDTH	32
C_S3_AXI_SUPPORTS_READ	1
C_S3_AXI_SUPPORTS_WRITE	1
C_S3_AXI_SUPPORTS_NARROW_BURST	1
C_S3_AXI_REG_EN0	0x00000
C_S3_AXI_REG_EN1	0x01000
C_S3_AXI_STRICT_COHERENCY	1
C_S3_AXI_ENABLE_AP	0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE	4
C_S4_AXI_ENABLE	0
C_S4_AXI_PROTOCOL	AXI4
C_S4_AXI_ID_WIDTH	4
C_S4_AXI_ADDR_WIDTH	32
C_S4_AXI_DATA_WIDTH	32
C_S4_AXI_SUPPORTS_READ	1
C_S4_AXI_SUPPORTS_WRITE	1
C_S4_AXI_SUPPORTS_NARROW_BURST	1
C_S4_AXI_REG_EN0	0x00000
C_S4_AXI_REG_EN1	0x01000
C_S4_AXI_STRICT_COHERENCY	1
C_S4_AXI_ENABLE_AP	0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE	4
C_S5_AXI_ENABLE	0
C_S5_AXI_PROTOCOL	AXI4
C_S5_AXI_ID_WIDTH	4
C_S5_AXI_ADDR_WIDTH	32
C_S5_AXI_DATA_WIDTH	32
C_S5_AXI_SUPPORTS_READ	1
C_S5_AXI_SUPPORTS_WRITE	1
C_S5_AXI_SUPPORTS_NARROW_BURST	1
C_S5_AXI_REG_EN0	0x00000
C_S5_AXI_REG_EN1	0x01000
C_S5_AXI_STRICT_COHERENCY	1
C_S5_AXI_ENABLE_AP	0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE	4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE	4
C_MCB_USE_EXTERNAL_BUFPLL	0
C_SYS_RST_PRESENT	0
C_INTERCONNECT_S0_AXI_MASTERS	microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
C_INTERCONNECT_S0_AXI_AW_REGISTER	1
C_INTERCONNECT_S0_AXI_AR_REGISTER	1
C_INTERCONNECT_S0_AXI_W_REGISTER	1
C_INTERCONNECT_S0_AXI_R_REGISTER	1
C_INTERCONNECT_S0_AXI_B_REGISTER	1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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- - - - - - - - - -

-microblaze_0_d_bram_ctrl - LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

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-

microblaze_0_d_bram_ctrl IP Image

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Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_dlmb			microblaze_0

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-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

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Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

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Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

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-

- - - - - - - - - -

-microblaze_0_i_bram_ctrl - LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

-

- - - - - - - - - - -

IP Specs
Core	Version	Documentation
lmb_bram_if_cntlr	3.00.a	IP

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microblaze_0_i_bram_ctrl IP Image

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Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
BRAM_PORT	INITIATOR	XIL_BRAM	microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block			microblaze_0_bram_block
SLMB	SLAVE	LMB	microblaze_0_ilmb			microblaze_0

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_BASEADDR	0x00000000
C_HIGHADDR	0x00001FFF
C_FAMILY	virtex5
C_MASK	0x00800000
C_LMB_AWIDTH	32
C_LMB_DWIDTH	32
C_ECC	0
C_INTERCONNECT	0
C_FAULT_INJECT	0
C_CE_FAILING_REGISTERS	0
C_UE_FAILING_REGISTERS	0
C_ECC_STATUS_REGISTERS	0
C_ECC_ONOFF_REGISTER	0
C_ECC_ONOFF_RESET_VALUE	1
C_CE_COUNTER_WIDTH	0
C_WRITE_ACCESS	2

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Name	Value
C_SPLB_CTRL_BASEADDR	0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR	0x00000000
C_SPLB_CTRL_AWIDTH	32
C_SPLB_CTRL_DWIDTH	32
C_SPLB_CTRL_P2P	0
C_SPLB_CTRL_MID_WIDTH	1
C_SPLB_CTRL_NUM_MASTERS	1
C_SPLB_CTRL_SUPPORT_BURSTS	0
C_SPLB_CTRL_NATIVE_DWIDTH	32
C_SPLB_CTRL_CLK_FREQ_HZ	100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ	100000000
C_S_AXI_CTRL_BASEADDR	0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR	0x00000000
C_S_AXI_CTRL_ADDR_WIDTH	32
C_S_AXI_CTRL_DATA_WIDTH	32
C_S_AXI_CTRL_PROTOCOL	AXI4LITE

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

-

-

-

-

- - -

Peripherals	TOC

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- - - - - - - - - -

-ETHERNET - AXI Ethernet
AXI Ethernet MAC

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- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_ethernet	2.01.a	IP

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-

ETHERNET IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	MDIO		IO	1	ETHERNET_MDIO
1	MDC		O	1	ETHERNET_MDC
2	GMII_TX_ER		O	1	ETHERNET_TX_ER
3	GMII_TXD		O	1	ETHERNET_TXD
4	GMII_TX_EN		O	1	ETHERNET_TX_EN
5	MII_TX_CLK		I	1	ETHERNET_MII_TX_CLK
6	GMII_TX_CLK		O	1	ETHERNET_TX_CLK
7	GMII_RXD		I	1	ETHERNET_RXD
8	GMII_RX_ER		I	1	ETHERNET_RX_ER
9	GMII_RX_CLK		I	1	ETHERNET_RX_CLK
10	GMII_RX_DV		I	1	ETHERNET_RX_DV
11	PHY_RST_N		O	1	ETHERNET_PHY_RST_N
12	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
13	GTX_CLK		I	1	clk_125_0000MHz
14	REF_CLK		I	1	clk_200_0000MHzPLL0
15	AXI_STR_TXD_ACLK		I	1	clk_100_0000MHzPLL0
16	AXI_STR_TXC_ACLK		I	1	clk_100_0000MHzPLL0
17	AXI_STR_RXD_ACLK		I	1	clk_100_0000MHzPLL0
18	AXI_STR_RXS_ACLK		I	1	clk_100_0000MHzPLL0
19	AXI_STR_TXD_ARESETN		I	1	AXI_STR_TXD_ARESETN
20	AXI_STR_TXC_ARESETN		I	1	AXI_STR_TXC_ARESETN
21	AXI_STR_RXD_ARESETN		I	1	AXI_STR_RXD_ARESETN
22	AXI_STR_RXS_ARESETN		I	1	AXI_STR_RXS_ARESETN
23	INTERRUPT		O	1	ETHERNET_INTERRUPT
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
AXI_STR_RXS	INITIATOR	AXIS	ETHERNET_dma_rxs			ETHERNET_dma
AXI_STR_RXD	INITIATOR	AXIS	ETHERNET_dma_rxd			ETHERNET_dma
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.
AXI_STR_TXD	TARGET	AXIS	ETHERNET_dma_txd			ETHERNET_dma
AXI_STR_TXC	TARGET	AXIS	ETHERNET_dma_txc			ETHERNET_dma

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_AXI_STR_TXC_TDATA_WIDTH	32
C_AXI_STR_TXD_TDATA_WIDTH	32
C_AXI_STR_RXS_TDATA_WIDTH	32
C_AXI_STR_RXD_TDATA_WIDTH	32
C_AXI_STR_TXC_PROTOCOL	XIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_TXD_PROTOCOL	XIL_AXI_STREAM_ETH_DATA
C_AXI_STR_RXS_PROTOCOL	XIL_AXI_STREAM_ETH_CTRL
C_AXI_STR_RXD_PROTOCOL	XIL_AXI_STREAM_ETH_DATA
C_AXI_STR_AVBTX_PROTOCOL	XIL_AXI_STREAM_ETH_AVB_TX
C_AXI_STR_AVBRX_PROTOCOL	XIL_AXI_STREAM_ETH_AVB_RX
C_FAMILY	virtex6
C_S_AXI_ACLK_FREQ_HZ	100000000
C_BASEADDR	0x41240000
C_HIGHADDR	0x4127FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_S_AXI_ID_WIDTH	4
C_TRANS	A
C_PHYADDR	0B00001
C_INCLUDE_IO	1
C_TYPE	1

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Name	Value
C_PHY_TYPE	1
C_HALFDUP	0
C_TXMEM	4096
C_RXMEM	4096
C_TXCSUM	0
C_RXCSUM	0
C_TXVLAN_TRAN	0
C_RXVLAN_TRAN	0
C_TXVLAN_TAG	0
C_RXVLAN_TAG	0
C_TXVLAN_STRP	0
C_RXVLAN_STRP	0
C_MCAST_EXTEND	0
C_STATS	0
C_AVB	0
C_SIMULATION	0
C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC	0
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

-

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- - - - - - - - - -

-ETHERNET_dma - AXI DMA Engine
AXI MemoryMap to/from AXI Stream Direct Memory Access Engine

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- - - - - - - - - - -

IP Specs
Core	Version	Documentation
axi_dma	3.00.a	IP

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-

ETHERNET_dma IP Image

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	s_axi_lite_aclk		I	1	clk_100_0000MHzPLL0
1	m_axi_sg_aclk		I	1	clk_100_0000MHzPLL0
2	m_axi_mm2s_aclk		I	1	clk_100_0000MHzPLL0
3	m_axi_s2mm_aclk		I	1	clk_100_0000MHzPLL0
4	mm2s_prmry_reset_out_n		O	1	AXI_STR_TXD_ARESETN
5	mm2s_cntrl_reset_out_n		O	1	AXI_STR_TXC_ARESETN
6	s2mm_prmry_reset_out_n		O	1	AXI_STR_RXD_ARESETN
7	s2mm_sts_reset_out_n		O	1	AXI_STR_RXS_ARESETN
8	mm2s_introut		O	1	ETHERNET_dma_mm2s_introut
9	s2mm_introut		O	1	ETHERNET_dma_s2mm_introut
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
M_AXIS_MM2S	INITIATOR	AXIS	ETHERNET_dma_txd			ETHERNET
M_AXIS_CNTRL	INITIATOR	AXIS	ETHERNET_dma_txc			ETHERNET
M_AXI_SG	MASTER	AXI	axi4_0			2 Peripherals.
M_AXI_MM2S	MASTER	AXI	axi4_0			2 Peripherals.
M_AXI_S2MM	MASTER	AXI	axi4_0			2 Peripherals.
S_AXI_LITE	SLAVE	AXI	axi4lite_0			8 Peripherals.
S_AXIS_STS	TARGET	AXIS	ETHERNET_dma_rxs			ETHERNET
S_AXIS_S2MM	TARGET	AXIS	ETHERNET_dma_rxd			ETHERNET

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-

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

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Name	Value
C_S_AXI_LITE_ADDR_WIDTH	32
C_S_AXI_LITE_DATA_WIDTH	32
C_DLYTMR_RESOLUTION	1250
C_PRMRY_IS_ACLK_ASYNC	0
C_SG_INCLUDE_DESC_QUEUE	1
C_SG_INCLUDE_STSCNTRL_STRM	1
C_SG_USE_STSAPP_LENGTH	1
C_SG_LENGTH_WIDTH	16
C_M_AXI_SG_ADDR_WIDTH	32
C_M_AXI_SG_DATA_WIDTH	32
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH	32
C_S_AXIS_S2MM_STS_TDATA_WIDTH	32
C_INCLUDE_MM2S	1
C_INCLUDE_MM2S_DRE	1
C_MM2S_BURST_SIZE	16
C_M_AXI_MM2S_ADDR_WIDTH	32
C_M_AXI_MM2S_DATA_WIDTH	32
C_M_AXIS_MM2S_TDATA_WIDTH	32
C_INCLUDE_S2MM	1
C_INCLUDE_S2MM_DRE	1
C_S2MM_BURST_SIZE	16
C_M_AXI_S2MM_ADDR_WIDTH	32
C_M_AXI_S2MM_DATA_WIDTH	32
C_S_AXIS_S2MM_TDATA_WIDTH	32
C_FAMILY	virtex6
C_BASEADDR	0x41E00000
C_HIGHADDR	0x41E0FFFF
C_S_AXI_LITE_ACLK_FREQ_HZ	100000000
C_M_AXI_SG_ACLK_FREQ_HZ	100000000
C_M_AXI_MM2S_ACLK_FREQ_HZ	100000000
C_M_AXI_S2MM_ACLK_FREQ_HZ	100000000
C_S_AXI_LITE_PROTOCOL	AXI4LITE
C_S_AXI_LITE_SUPPORTS_READ	1
C_S_AXI_LITE_SUPPORTS_WRITE	1
C_M_AXI_SG_PROTOCOL	AXI4
C_M_AXI_SG_SUPPORTS_THREADS	0
C_M_AXI_SG_THREAD_ID_WIDTH	1
C_M_AXI_SG_SUPPORTS_NARROW_BURST	0
C_M_AXI_SG_SUPPORTS_READ	1
C_M_AXI_SG_SUPPORTS_WRITE	1

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Name	Value
C_M_AXI_MM2S_PROTOCOL	AXI4
C_M_AXI_MM2S_SUPPORTS_THREADS	0
C_M_AXI_MM2S_THREAD_ID_WIDTH	1
C_M_AXI_MM2S_SUPPORTS_NARROW_BURST	0
C_M_AXI_MM2S_SUPPORTS_READ	1
C_M_AXI_MM2S_SUPPORTS_WRITE	0
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING	4
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH	512
C_M_AXI_S2MM_PROTOCOL	AXI4
C_M_AXI_S2MM_SUPPORTS_THREADS	0
C_M_AXI_S2MM_THREAD_ID_WIDTH	1
C_M_AXI_S2MM_SUPPORTS_NARROW_BURST	0
C_M_AXI_S2MM_SUPPORTS_WRITE	1
C_M_AXI_S2MM_SUPPORTS_READ	0
C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING	4
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH	512
C_M_AXIS_MM2S_PROTOCOL	XIL_AXI_STREAM_ETH_DATA
C_S_AXIS_S2MM_PROTOCOL	XIL_AXI_STREAM_ETH_DATA
C_M_AXIS_CNTRL_PROTOCOL	XIL_AXI_STREAM_ETH_CTRL
C_S_AXIS_STS_PROTOCOL	XIL_AXI_STREAM_ETH_CTRL
C_INTERCONNECT_S_AXI_LITE_AW_REGISTER	1
C_INTERCONNECT_S_AXI_LITE_AR_REGISTER	1
C_INTERCONNECT_S_AXI_LITE_W_REGISTER	1
C_INTERCONNECT_S_AXI_LITE_R_REGISTER	1
C_INTERCONNECT_S_AXI_LITE_B_REGISTER	1
C_INTERCONNECT_M_AXI_SG_AW_REGISTER	1
C_INTERCONNECT_M_AXI_SG_AR_REGISTER	1
C_INTERCONNECT_M_AXI_SG_W_REGISTER	1
C_INTERCONNECT_M_AXI_SG_R_REGISTER	1
C_INTERCONNECT_M_AXI_SG_B_REGISTER	1
C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER	1
C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER	1
C_INTERCONNECT_M_AXI_MM2S_W_REGISTER	1
C_INTERCONNECT_M_AXI_MM2S_R_REGISTER	1
C_INTERCONNECT_M_AXI_MM2S_B_REGISTER	1
C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER	1
C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER	1
C_INTERCONNECT_M_AXI_S2MM_W_REGISTER	1
C_INTERCONNECT_M_AXI_S2MM_R_REGISTER	1
C_INTERCONNECT_M_AXI_S2MM_B_REGISTER	1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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- - - - - - - - - -

-LEDs_4Bits - AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

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IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

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LEDs_4Bits IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_O		O	1	LEDs_4Bits_TRI_O
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

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Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40020000
C_HIGHADDR	0x4002FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	0
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	0
C_DOUT_DEFAULT	0x00000000

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Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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- - - - - - - - - -

-Push_Buttons_4Bits - AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

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IP Specs
Core	Version	Documentation
axi_gpio	1.01.a	IP

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Push_Buttons_4Bits IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	GPIO_IO_I		I	1	Push_Buttons_4Bits_TRI_I
1	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
2	IP2INTC_Irpt		O	1	Push_Buttons_4Bits_IP2INTC_Irpt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.

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-

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

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Name	Value
C_FAMILY	virtex6
C_BASEADDR	0x40000000
C_HIGHADDR	0x4000FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_GPIO_WIDTH	4
C_GPIO2_WIDTH	32
C_ALL_INPUTS	1
C_ALL_INPUTS_2	0
C_INTERRUPT_PRESENT	1
C_DOUT_DEFAULT	0x00000000

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Name	Value
C_TRI_DEFAULT	0xFFFFFFFF
C_IS_DUAL	0
C_DOUT_DEFAULT_2	0x00000000
C_TRI_DEFAULT_2	0xFFFFFFFF
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-RS232_Uart_1 - AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

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IP Specs
Core	Version	Documentation
axi_uartlite	1.01.a	IP

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RS232_Uart_1 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	TX		O	1	RS232_Uart_1_sout
1	RX		I	1	RS232_Uart_1_sin
2	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
3	Interrupt		O	1	RS232_Uart_1_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.

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-

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Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_S_AXI_ACLK_FREQ_HZ	100000000
C_BASEADDR	0x40600000
C_HIGHADDR	0x4060FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32
C_BAUDRATE	115200
C_DATA_BITS	8

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Name	Value
C_USE_PARITY	0
C_ODD_PARITY	1
C_S_AXI_PROTOCOL	AXI4LITE
C_INTERCONNECT_S_AXI_AW_REGISTER	1
C_INTERCONNECT_S_AXI_AR_REGISTER	1
C_INTERCONNECT_S_AXI_W_REGISTER	1
C_INTERCONNECT_S_AXI_R_REGISTER	1
C_INTERCONNECT_S_AXI_B_REGISTER	1

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-axi_timer_0 - AXI Timer/Counter
Timer counter with AXI interface

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IP Specs
Core	Version	Documentation
axi_timer	1.01.a	IP

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axi_timer_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	S_AXI_ACLK		I	1	clk_50_0000MHzPLL0
1	Interrupt		O	1	axi_timer_0_Interrupt
Bus Interfaces
NAME	TYPE	BUSSTD	BUS			Connected To
S_AXI	SLAVE	AXI	axi4lite_0			8 Peripherals.

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-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - -

Name	Value
C_S_AXI_PROTOCOL	AXI4LITE
C_FAMILY	virtex6
C_COUNT_WIDTH	32
C_ONE_TIMER_ONLY	0
C_TRIG0_ASSERT	1
C_TRIG1_ASSERT	1

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Name	Value
C_GEN0_ASSERT	1
C_GEN1_ASSERT	1
C_BASEADDR	0x41C00000
C_HIGHADDR	0x41C0FFFF
C_S_AXI_ADDR_WIDTH	32
C_S_AXI_DATA_WIDTH	32

- - - - -

Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-

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IP	TOC

-
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- - - - - - - - - -

-clock_generator_0 - Clock Generator
Clock generator for processor system.

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IP Specs
Core	Version	Documentation
clock_generator	4.01.a	IP

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-

clock_generator_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	RST		I	1	RESET
1	CLKIN		I	1	CLK
2	CLKOUT2		O	1	clk_100_0000MHzPLL0
3	CLKOUT5		O	1	clk_50_0000MHzPLL0
4	CLKOUT3		O	1	clk_125_0000MHz
5	CLKOUT4		O	1	clk_200_0000MHzPLL0
6	CLKOUT0		O	1	clk_600_0000MHzPLL0_nobuf
7	CLKOUT1		O	1	clk_600_0000MHz180PLL0_nobuf
8	LOCKED		O	1	proc_sys_reset_0_Dcm_locked

-

-

- - - - - - - -

Parameters

- - These are the current parameter settings for this module. -

- Parameters marked with - yellow - indicate parameters set by the user. -
- Parameters marked with - blue - indicate parameters set by the system. - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Name	Value
C_FAMILY	virtex6
C_DEVICE	NOT_SET
C_PACKAGE	NOT_SET
C_SPEEDGRADE	NOT_SET
C_CLKIN_FREQ	200000000
C_CLKOUT0_FREQ	600000000
C_CLKOUT0_PHASE	0
C_CLKOUT0_GROUP	PLL0
C_CLKOUT0_BUF	FALSE
C_CLKOUT0_VARIABLE_PHASE	FALSE
C_CLKOUT1_FREQ	600000000
C_CLKOUT1_PHASE	180
C_CLKOUT1_GROUP	PLL0
C_CLKOUT1_BUF	FALSE
C_CLKOUT1_VARIABLE_PHASE	FALSE
C_CLKOUT2_FREQ	100000000
C_CLKOUT2_PHASE	0
C_CLKOUT2_GROUP	PLL0
C_CLKOUT2_BUF	TRUE
C_CLKOUT2_VARIABLE_PHASE	FALSE
C_CLKOUT3_FREQ	125000000
C_CLKOUT3_PHASE	0
C_CLKOUT3_GROUP	NONE
C_CLKOUT3_BUF	TRUE
C_CLKOUT3_VARIABLE_PHASE	FALSE
C_CLKOUT4_FREQ	200000000
C_CLKOUT4_PHASE	0
C_CLKOUT4_GROUP	PLL0
C_CLKOUT4_BUF	TRUE
C_CLKOUT4_VARIABLE_PHASE	FALSE
C_CLKOUT5_FREQ	50000000
C_CLKOUT5_PHASE	0
C_CLKOUT5_GROUP	PLL0
C_CLKOUT5_BUF	TRUE
C_CLKOUT5_VARIABLE_PHASE	FALSE
C_CLKOUT6_FREQ	0
C_CLKOUT6_PHASE	0
C_CLKOUT6_GROUP	NONE
C_CLKOUT6_BUF	TRUE
C_CLKOUT6_VARIABLE_PHASE	FALSE
C_CLKOUT7_FREQ	0
C_CLKOUT7_PHASE	0
C_CLKOUT7_GROUP	NONE
C_CLKOUT7_BUF	TRUE
C_CLKOUT7_VARIABLE_PHASE	FALSE
C_CLKOUT8_FREQ	0
C_CLKOUT8_PHASE	0
C_CLKOUT8_GROUP	NONE

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Name	Value
C_CLKOUT8_BUF	TRUE
C_CLKOUT8_VARIABLE_PHASE	FALSE
C_CLKOUT9_FREQ	0
C_CLKOUT9_PHASE	0
C_CLKOUT9_GROUP	NONE
C_CLKOUT9_BUF	TRUE
C_CLKOUT9_VARIABLE_PHASE	FALSE
C_CLKOUT10_FREQ	0
C_CLKOUT10_PHASE	0
C_CLKOUT10_GROUP	NONE
C_CLKOUT10_BUF	TRUE
C_CLKOUT10_VARIABLE_PHASE	FALSE
C_CLKOUT11_FREQ	0
C_CLKOUT11_PHASE	0
C_CLKOUT11_GROUP	NONE
C_CLKOUT11_BUF	TRUE
C_CLKOUT11_VARIABLE_PHASE	FALSE
C_CLKOUT12_FREQ	0
C_CLKOUT12_PHASE	0
C_CLKOUT12_GROUP	NONE
C_CLKOUT12_BUF	TRUE
C_CLKOUT12_VARIABLE_PHASE	FALSE
C_CLKOUT13_FREQ	0
C_CLKOUT13_PHASE	0
C_CLKOUT13_GROUP	NONE
C_CLKOUT13_BUF	TRUE
C_CLKOUT13_VARIABLE_PHASE	FALSE
C_CLKOUT14_FREQ	0
C_CLKOUT14_PHASE	0
C_CLKOUT14_GROUP	NONE
C_CLKOUT14_BUF	TRUE
C_CLKOUT14_VARIABLE_PHASE	FALSE
C_CLKOUT15_FREQ	0
C_CLKOUT15_PHASE	0
C_CLKOUT15_GROUP	NONE
C_CLKOUT15_BUF	TRUE
C_CLKOUT15_VARIABLE_PHASE	FALSE
C_CLKFBIN_FREQ	0
C_CLKFBIN_DESKEW	NONE
C_CLKFBOUT_FREQ	0
C_CLKFBOUT_PHASE	0
C_CLKFBOUT_GROUP	NONE
C_CLKFBOUT_BUF	TRUE
C_PSDONE_GROUP	NONE
C_EXT_RESET_HIGH	1
C_CLK_PRIMITIVE_FEEDBACK_BUF	FALSE
C_CLK_GEN	UPDATE

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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-proc_sys_reset_0 - Processor System Reset Module
Reset management module

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IP Specs
Core	Version	Documentation
proc_sys_reset	3.00.a	IP

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proc_sys_reset_0 IP Image

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PORT LIST
These are the ports listed in the MHS file. - - Please refer to the IP documentation for complete information about module ports. -
#	NAME		DIR	[LSB:MSB]	SIGNAL
0	Ext_Reset_In		I	1	RESET
1	MB_Reset		O	1	proc_sys_reset_0_MB_Reset
2	Slowest_sync_clk		I	1	clk_50_0000MHzPLL0
3	Interconnect_aresetn		O	1	proc_sys_reset_0_Interconnect_aresetn
4	Dcm_locked		I	1	proc_sys_reset_0_Dcm_locked
5	MB_Debug_Sys_Rst		I	1	proc_sys_reset_0_MB_Debug_Sys_Rst
6	BUS_STRUCT_RESET		O	1	proc_sys_reset_0_BUS_STRUCT_RESET

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Parameters
- - These are the current parameter settings for this module. - - Parameters marked with - yellow - indicate parameters set by the user. - - Parameters marked with - blue - indicate parameters set by the system. - -
Name		Value
C_SUBFAMILY		lx
C_EXT_RST_WIDTH		4
C_AUX_RST_WIDTH		4
C_EXT_RESET_HIGH		1
C_AUX_RESET_HIGH		1
C_NUM_BUS_RST		1
C_NUM_PERP_RST		1
C_NUM_INTERCONNECT_ARESETN		1
C_NUM_PERP_ARESETN		1
C_FAMILY		virtex5

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Post Synthesis Device Utilization
- Device utilization information is not available for this IP. Run platgen to generate synthesis information. -

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Timing Information	TOC

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Post Synthesis Clock Limits
- No clocks could be identified in the design. Run platgen to generate synthesis information. -

-

- - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html deleted file mode 100644 index 88f408ceb..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_toc.html +++ /dev/null @@ -1,73 +0,0 @@ - - - - -Table of Contents - - - - -

-Overview
Block Diagram
External Ports

-

Processor -

-

Debuggers -

-

Interrupt Controllers -

- microblaze_0_intc

-

Busses -

-   axi4_0
   axi4lite_0
   microblaze_0_dlmb
   microblaze_0_ilmb

-

Memory -

- microblaze_0_bram_block

-

Memory Controllers -

-   MCB_DDR3
   microblaze_0_d_bram_ctrl
   microblaze_0_i_bram_ctrl

-

Peripherals -

-   ETHERNET
   ETHERNET_dma
   LEDs_4Bits
   Push_Buttons_4Bits
   RS232_Uart_1
   axi_timer_0

-

IP -

- clock_generator_0
proc_sys_reset_0
Timing Information
-

- diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log deleted file mode 100644 index 5855e82bc..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log +++ /dev/null @@ -1,563 +0,0 @@ -========================================================================= -Time: Sat Aug 27 15:05:27 GMT Daylight Time 2011 -Running: run_batch_mode 96334104 -{COLLECTING: INSTANCE MCB_DDR3 } -{COLLECTING: C_INTERCONNECT_S0_AXI_MASTERS microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM OPTIONAL string none microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} -{COLLECTING: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S0_AXI_ACLK_RATIO 100000000 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S0_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S0_AXI_AW_REGISTER 1 OPTIONAL integer 0 1} -{COLLECTING: C_INTERCONNECT_S0_AXI_AR_REGISTER 1 OPTIONAL integer 0 1} -{COLLECTING: C_INTERCONNECT_S0_AXI_W_REGISTER 1 OPTIONAL integer 0 1} -{COLLECTING: C_INTERCONNECT_S0_AXI_R_REGISTER 1 OPTIONAL integer 0 1} -{COLLECTING: C_INTERCONNECT_S0_AXI_B_REGISTER 1 OPTIONAL integer 0 1} -{COLLECTING: C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S0_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S0_AXI_AXI_VER 1.02.a CONSTANT } -{COLLECTING: C_INTERCONNECT_S1_AXI_MASTERS none OPTIONAL string none } -{COLLECTING: C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_ACLK_RATIO 1 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S1_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_AW_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_AR_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_W_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_R_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_B_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S1_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S1_AXI_AXI_VER 1.01.a CONSTANT } -{COLLECTING: C_INTERCONNECT_S2_AXI_MASTERS none OPTIONAL string none } -{COLLECTING: C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_ACLK_RATIO 1 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S2_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_AW_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_AR_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_W_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_R_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_B_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S2_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S2_AXI_AXI_VER 1.01.a CONSTANT } -{COLLECTING: C_INTERCONNECT_S3_AXI_MASTERS none OPTIONAL string none } -{COLLECTING: C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_ACLK_RATIO 1 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S3_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_AW_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_AR_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_W_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_R_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_B_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S3_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S3_AXI_AXI_VER 1.01.a CONSTANT } -{COLLECTING: C_INTERCONNECT_S4_AXI_MASTERS none OPTIONAL string none } -{COLLECTING: C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_ACLK_RATIO 1 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S4_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_AW_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_AR_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_W_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_R_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_B_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S4_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S4_AXI_AXI_VER 1.01.a CONSTANT } -{COLLECTING: C_INTERCONNECT_S5_AXI_MASTERS none OPTIONAL string none } -{COLLECTING: C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_ACLK_RATIO 1 UPDATE integer 1 } -{COLLECTING: C_INTERCONNECT_S5_AXI_SECURE 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_AW_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_AR_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_W_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_R_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_B_REGISTER 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } -{COLLECTING: C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } -{COLLECTING: C_S5_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } -{COLLECTING: C_S5_AXI_AXI_VER 1.01.a CONSTANT } -{COLLECTING: C_MCB_LOC MEMC3 OPTIONAL MEMC3 } -{COLLECTING: C_MCB_RZQ_LOC K7 OPTIONAL STRING NOT_SET K7} -{COLLECTING: C_MCB_ZIO_LOC R7 OPTIONAL STRING NOT_SET R7} -{COLLECTING: C_MCB_PERFORMANCE STANDARD OPTIONAL STRING STANDARD } -{COLLECTING: C_BYPASS_CORE_UCF 0 OPTIONAL 0 } -{COLLECTING: C_S0_AXI_BASEADDR 0x80000000 OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF 0x80000000} -{COLLECTING: C_S0_AXI_HIGHADDR 0x807FFFFF OPTIONAL STD_LOGIC_VECTOR 0x00000000 0x807FFFFF} -{COLLECTING: C_S1_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } -{COLLECTING: C_S1_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } -{COLLECTING: C_S2_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } -{COLLECTING: C_S2_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } -{COLLECTING: C_S3_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } -{COLLECTING: C_S3_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } -{COLLECTING: C_S4_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } -{COLLECTING: C_S4_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } -{COLLECTING: C_S5_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } -{COLLECTING: C_S5_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } -{COLLECTING: C_MEM_TYPE DDR3 OPTIONAL STRING DDR3 } -{COLLECTING: C_MEM_PARTNO MT41J64M16XX-187E REQUIRE STRING NOT_SET MT41J64M16XX-187E} -{COLLECTING: C_MEM_BASEPARTNO NOT_SET OPTIONAL STRING NOT_SET } -{COLLECTING: C_NUM_DQ_PINS 16 OPTIONAL_UPDATE INTEGER 16 } -{COLLECTING: C_MEM_ADDR_WIDTH 13 OPTIONAL_UPDATE INTEGER 13 } -{COLLECTING: C_MEM_BANKADDR_WIDTH 3 OPTIONAL_UPDATE INTEGER 3 } -{COLLECTING: C_MEM_NUM_COL_BITS 10 OPTIONAL_UPDATE INTEGER 10 } -{COLLECTING: C_MEM_TRAS -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TRCD -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TREFI -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TRFC -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TRP -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TWR -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TRTP -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_MEM_TWTR -1 OPTIONAL_UPDATE INTEGER -1 } -{COLLECTING: C_PORT_CONFIG B32_B32_B32_B32 OPTIONAL STRING B32_B32_B32_B32 } -{COLLECTING: C_SKIP_IN_TERM_CAL 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_SKIP_IN_TERM_CAL_VALUE NONE OPTIONAL STRING NONE } -{COLLECTING: C_MEMCLK_PERIOD 0 OPTIONAL_UPDATE INTEGER 0 } -{COLLECTING: C_MEM_ADDR_ORDER ROW_BANK_COLUMN OPTIONAL STRING ROW_BANK_COLUMN } -{COLLECTING: C_MEM_TZQINIT_MAXCNT 512 UPDATE INTEGER 512 } -{COLLECTING: C_MEM_CAS_LATENCY 6 UPDATE INTEGER 6 } -{COLLECTING: C_SIMULATION FALSE OPTIONAL STRING FALSE } -{COLLECTING: C_MEM_DDR1_2_ODS FULL OPTIONAL STRING FULL } -{COLLECTING: C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS CLASS_II OPTIONAL STRING CLASS_II } -{COLLECTING: C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS CLASS_II OPTIONAL STRING CLASS_II } -{COLLECTING: C_MEM_DDR2_RTT 150OHMS OPTIONAL STRING 150OHMS } -{COLLECTING: C_MEM_DDR2_DIFF_DQS_EN YES OPTIONAL STRING YES } -{COLLECTING: C_MEM_DDR2_3_PA_SR FULL OPTIONAL STRING FULL } -{COLLECTING: C_MEM_DDR2_3_HIGH_TEMP_SR NORMAL OPTIONAL STRING NORMAL } -{COLLECTING: C_MEM_DDR3_CAS_WR_LATENCY 5 UPDATE INTEGER 5 } -{COLLECTING: C_MEM_DDR3_CAS_LATENCY 6 UPDATE INTEGER 6 } -{COLLECTING: C_MEM_DDR3_ODS DIV6 OPTIONAL STRING DIV6 } -{COLLECTING: C_MEM_DDR3_RTT DIV4 OPTIONAL STRING DIV4 } -{COLLECTING: C_MEM_DDR3_AUTO_SR ENABLED OPTIONAL STRING ENABLED } -{COLLECTING: C_MEM_MOBILE_PA_SR FULL OPTIONAL STRING FULL } -{COLLECTING: C_MEM_MDDR_ODS FULL OPTIONAL STRING FULL } -{COLLECTING: C_ARB_ALGORITHM 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_ARB_NUM_TIME_SLOTS 12 OPTIONAL INTEGER 12 } -{COLLECTING: C_ARB_TIME_SLOT_0 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 } -{COLLECTING: C_ARB_TIME_SLOT_1 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 } -{COLLECTING: C_ARB_TIME_SLOT_2 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 } -{COLLECTING: C_ARB_TIME_SLOT_3 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 } -{COLLECTING: C_ARB_TIME_SLOT_4 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 } -{COLLECTING: C_ARB_TIME_SLOT_5 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 } -{COLLECTING: C_ARB_TIME_SLOT_6 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 } -{COLLECTING: C_ARB_TIME_SLOT_7 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 } -{COLLECTING: C_ARB_TIME_SLOT_8 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 } -{COLLECTING: C_ARB_TIME_SLOT_9 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 } -{COLLECTING: C_ARB_TIME_SLOT_10 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 } -{COLLECTING: C_ARB_TIME_SLOT_11 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 } -{COLLECTING: C_S0_AXI_ENABLE 1 OPTIONAL INTEGER 1 } -{COLLECTING: C_S0_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S0_AXI_ID_WIDTH 3 UPDATE INTEGER 4 } -{COLLECTING: C_S0_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S0_AXI_DATA_WIDTH 32 OPTIONAL INTEGER 32 } -{COLLECTING: C_S0_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S0_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S0_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S0_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S0_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S0_AXI_STRICT_COHERENCY 0 OPTIONAL_UPDATE INTEGER 1 0} -{COLLECTING: C_S0_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S1_AXI_ENABLE 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S1_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S1_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } -{COLLECTING: C_S1_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S1_AXI_DATA_WIDTH 32 OPTIONAL INTEGER 32 } -{COLLECTING: C_S1_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S1_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S1_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S1_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S1_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S1_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S1_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S2_AXI_ENABLE 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S2_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S2_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } -{COLLECTING: C_S2_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S2_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S2_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S2_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S2_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S2_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S2_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S2_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S2_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S3_AXI_ENABLE 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S3_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S3_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } -{COLLECTING: C_S3_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S3_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S3_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S3_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S3_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S3_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S3_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S3_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S3_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S4_AXI_ENABLE 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S4_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S4_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } -{COLLECTING: C_S4_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S4_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S4_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S4_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S4_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S4_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S4_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S4_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S4_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S5_AXI_ENABLE 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_S5_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S5_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } -{COLLECTING: C_S5_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S5_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } -{COLLECTING: C_S5_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S5_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S5_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S5_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } -{COLLECTING: C_S5_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } -{COLLECTING: C_S5_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } -{COLLECTING: C_S5_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_MCB_USE_EXTERNAL_BUFPLL 0 OPTIONAL INTEGER 0 } -{COLLECTING: C_SYS_RST_PRESENT 1 UPDATE INTEGER 0 } -{COLLECTING: HW_VER 1.02.a } -{SENDING PARAMETER: C_ARB_ALGORITHM : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_ARB_NUM_TIME_SLOTS : 12 INTEGER OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_0 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_1 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_2 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_3 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_4 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_5 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_6 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_7 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_8 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_9 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_10 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_ARB_TIME_SLOT_11 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_BYPASS_CORE_UCF : 0 {} OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_ACLK_RATIO : 100000000 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_AR_REGISTER : 1 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_AW_REGISTER : 1 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_B_REGISTER : 1 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_MASTERS : {microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_R_REGISTER : 1 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_W_REGISTER : 1 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_ACLK_RATIO : 1 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_AR_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_AW_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_B_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_MASTERS : none string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_R_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_W_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_ACLK_RATIO : 1 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_AR_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_AW_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_B_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_MASTERS : none string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_R_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_W_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_ACLK_RATIO : 1 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_AR_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_AW_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_B_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_MASTERS : none string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_R_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_W_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_ACLK_RATIO : 1 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_AR_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_AW_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_B_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_MASTERS : none string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_R_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_W_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_ACLK_RATIO : 1 integer UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_AR_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_AW_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_B_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_MASTERS : none string OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_R_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_SECURE : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_W_REGISTER : 0 integer OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} -{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} -{SENDING PARAMETER: C_MCB_LOC : MEMC3 {} OPTIONAL} -{SENDING PARAMETER: C_MCB_PERFORMANCE : STANDARD STRING OPTIONAL} -{SENDING PARAMETER: C_MCB_RZQ_LOC : K7 STRING OPTIONAL} -{SENDING PARAMETER: C_MCB_USE_EXTERNAL_BUFPLL : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_MCB_ZIO_LOC : R7 STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_ADDR_ORDER : ROW_BANK_COLUMN STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_ADDR_WIDTH : 13 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_BANKADDR_WIDTH : 3 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_BASEPARTNO : NOT_SET STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_CAS_LATENCY : 6 INTEGER UPDATE} -{SENDING PARAMETER: C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS : CLASS_II STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS : CLASS_II STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR1_2_ODS : FULL STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR2_3_HIGH_TEMP_SR : NORMAL STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR2_3_PA_SR : FULL STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR2_DIFF_DQS_EN : YES STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR2_RTT : 150OHMS STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR3_AUTO_SR : ENABLED STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR3_CAS_LATENCY : 6 INTEGER UPDATE} -{SENDING PARAMETER: C_MEM_DDR3_CAS_WR_LATENCY : 5 INTEGER UPDATE} -{SENDING PARAMETER: C_MEM_DDR3_ODS : DIV6 STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_DDR3_RTT : DIV4 STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_MDDR_ODS : FULL STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_MOBILE_PA_SR : FULL STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_NUM_COL_BITS : 10 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_PARTNO : MT41J64M16XX-187E STRING REQUIRE} -{SENDING PARAMETER: C_MEM_TRAS : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TRCD : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TREFI : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TRFC : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TRP : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TRTP : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TWR : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TWTR : -1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_MEM_TYPE : DDR3 STRING OPTIONAL} -{SENDING PARAMETER: C_MEM_TZQINIT_MAXCNT : 512 INTEGER UPDATE} -{SENDING PARAMETER: C_MEMCLK_PERIOD : 0 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_NUM_DQ_PINS : 16 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_PORT_CONFIG : B32_B32_B32_B32 STRING OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S0_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S0_AXI_AXI_VER : 1.02.a {} CONSTANT} -{SENDING PARAMETER: C_S0_AXI_BASEADDR : 0x80000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_DATA_WIDTH : 32 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_ENABLE : 1 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_HIGHADDR : 0x807FFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_ID_WIDTH : 3 INTEGER UPDATE} -{SENDING PARAMETER: C_S0_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S0_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S0_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_STRICT_COHERENCY : 0 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S0_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S0_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S0_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S1_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S1_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S1_AXI_AXI_VER : 1.01.a {} CONSTANT} -{SENDING PARAMETER: C_S1_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_DATA_WIDTH : 32 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_ENABLE : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_ID_WIDTH : 4 INTEGER UPDATE} -{SENDING PARAMETER: C_S1_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S1_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S1_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S1_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S1_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S1_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S1_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S2_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S2_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S2_AXI_AXI_VER : 1.01.a {} CONSTANT} -{SENDING PARAMETER: C_S2_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S2_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S2_AXI_ENABLE : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S2_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S2_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S2_AXI_ID_WIDTH : 4 INTEGER UPDATE} -{SENDING PARAMETER: C_S2_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S2_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S2_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S2_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S2_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S2_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S2_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S3_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S3_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S3_AXI_AXI_VER : 1.01.a {} CONSTANT} -{SENDING PARAMETER: C_S3_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S3_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S3_AXI_ENABLE : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S3_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S3_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S3_AXI_ID_WIDTH : 4 INTEGER UPDATE} -{SENDING PARAMETER: C_S3_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S3_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S3_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S3_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S3_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S3_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S3_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S4_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S4_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S4_AXI_AXI_VER : 1.01.a {} CONSTANT} -{SENDING PARAMETER: C_S4_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S4_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S4_AXI_ENABLE : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S4_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S4_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S4_AXI_ID_WIDTH : 4 INTEGER UPDATE} -{SENDING PARAMETER: C_S4_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S4_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S4_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S4_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S4_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S4_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S4_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S5_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} -{SENDING PARAMETER: C_S5_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S5_AXI_AXI_VER : 1.01.a {} CONSTANT} -{SENDING PARAMETER: C_S5_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S5_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} -{SENDING PARAMETER: C_S5_AXI_ENABLE : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S5_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S5_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S5_AXI_ID_WIDTH : 4 INTEGER UPDATE} -{SENDING PARAMETER: C_S5_AXI_PROTOCOL : AXI4 STRING CONSTANT} -{SENDING PARAMETER: C_S5_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S5_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S5_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S5_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S5_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_S5_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} -{SENDING PARAMETER: C_SIMULATION : FALSE STRING OPTIONAL} -{SENDING PARAMETER: C_SKIP_IN_TERM_CAL : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_SKIP_IN_TERM_CAL_VALUE : NONE STRING OPTIONAL} -{SENDING PARAMETER: C_SYS_RST_PRESENT : 1 INTEGER UPDATE} -{SENDING PARAMETER: HW_VER : 1.02.a {} {}} -{SENDING PARAMETER: INSTANCE : MCB_DDR3 {} {}} -{Executing C:/devtools/Xilinx/13.1/ISE_DS/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_v3_7/bin/nt/mig.exe -cg_exc_inp mig_input.txt -cg_exc_out mig_output.txt} -{SET: IGNORE C_MCB_LOC = MEMC3 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_DDR3_ODS = DIV6 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MCB_ZIO_LOC = R7 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: UPDATE C_S4_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_S0_AXI_BASEADDR = 0x80000000 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_MEM_MDDR_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_DDR2_DIFF_DQS_EN = YES (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_S2_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_S0_AXI_DATA_WIDTH = 32 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: CHECK C_MEM_NUM_COL_BITS = 10 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} -{SET: IGNORE C_MEM_DDR3_RTT = DIV4 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDREM C_MEM_CAS_LATENCY = 6 (BATCH:UPDATE::MPD:MPDVAL)} -{SET: UPDATE C_MEM_TRFC = 160000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_AR_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: UPDATE C_S3_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_S0_AXI_SUPPORTS_NARROW_BURST = Auto (BATCH:OPTIONAL_UPDATE::MPD:DEFVAL)} -{SET: IGNORE C_S0_AXI_STRICT_COHERENCY = 0 (BATCH:OPTIONAL_UPDATE::MHS:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_10 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_SECURE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_11 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_ARB_NUM_TIME_SLOTS = 12 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_S5_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_S2_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_MEM_TRTP = 7500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_MEM_TREFI = 7800000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_S0_AXI_ENABLE = 1 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_MOBILE_PA_SR = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_SKIP_IN_TERM_CAL = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_DDR2_3_HIGH_TEMP_SR = NORMAL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDREM C_S0_AXI_SUPPORTS_READ = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)} -{SET: IGNORE C_S0_AXI_HIGHADDR = 0x807FFFFF (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_MEM_DDR1_2_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_TYPE = DDR3 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: CHECK C_MEM_ADDR_WIDTH = 13 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} -{SET: UPDATE C_S5_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_S4_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_S0_AXI_ENABLE_AP = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_MEM_TWR = 15000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_S3_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDREM C_S0_AXI_SUPPORTS_WRITE = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)} -{SET: IGNORE C_S0_AXI_ADDR_WIDTH = 32 (BATCH:CONSTANT::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS = CLASS_II (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDREM C_MEM_DDR3_CAS_WR_LATENCY = 5 (BATCH:UPDATE::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_W_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_MEM_DDR2_RTT = 150OHMS (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MCB_PERFORMANCE = STANDARD (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: CHECK C_MEM_BANKADDR_WIDTH = 3 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_B_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_SIMULATION = FALSE (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_S1_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_MEM_TWTR = 7500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_S3_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDATE C_MEM_TRAS = 37500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: UPDREM C_MEM_DDR3_CAS_LATENCY = 6 (BATCH:UPDATE::MPD:MPDVAL)} -{SET: UPDATE C_S5_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_S1_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_MEM_TRCD = 13130 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_0 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_ARB_ALGORITHM = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_MEM_TRP = 13130 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_1 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS = CLASS_II (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_2 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_3 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_MEM_DDR3_AUTO_SR = ENABLED (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_4 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_5 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_6 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_AW_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_7 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_MEMCLK_PERIOD = 0 (BATCH:OPTIONAL_UPDATE:SKIP_BATCH:MPD:MPDVAL)} -{SET: IGNORE C_MCB_RZQ_LOC = K7 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_8 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_MEM_ADDR_ORDER = ROW_BANK_COLUMN (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MCB_USE_EXTERNAL_BUFPLL = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_R_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} -{SET: IGNORE C_ARB_TIME_SLOT_9 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} -{SET: IGNORE C_S4_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_S1_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_SKIP_IN_TERM_CAL_VALUE = NONE (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: UPDATE C_S2_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} -{SET: IGNORE C_MEM_DDR2_3_PA_SR = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_PORT_CONFIG = B32_B32_B32_B32 (BATCH:OPTIONAL::MPD:MPDVAL)} -{SET: IGNORE C_MEM_PARTNO = MT41J64M16XX-187E (BATCH:REQUIRE::MHS:COMPVAL)} -{SET: CHECK C_NUM_DQ_PINS = 16 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} -RETURN: 0 diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html deleted file mode 100644 index 7ac689bd4..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html +++ /dev/null @@ -1,565 +0,0 @@ -Xilinx Design Summary - - - - - - - - - - - - - - - - - - - - - -

Project Status (08/27/2011 - 12:37:45)
Project File:	system.xmp	Implementation State:	Programming File Generated
Module Name:	system	Errors:	-No Errors
Product Version:	EDK 13.1	Warnings:	238 Warnings (0 new)

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XPS Reports					[-]
Report Name	Generated	Errors	Warnings	Infos
Platgen Log File	Sat 27. Aug 12:17:02 2011	0	19 Warnings (18 new)	34 Infos (32 new)
Libgen Log File
Simgen Log File
BitInit Log File
System Log File	Sat 27. Aug 12:34:09 2011

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XPS Synthesis Summary (estimated values)						[-]
Report	Generated	Flip Flops Used	LUTs Used	BRAMS Used	Errors
system	Sat 27. Aug 12:17:50 2011	14696	14247	14	0
mcb_ddr3_wrapper	Sat 27. Aug 12:16:50 2011	373	690		0
debug_module_wrapper	Sat 27. Aug 12:16:27 2011	131	142		0
clock_generator_0_wrapper	Sat 27. Aug 12:16:17 2011		1		0
microblaze_0_bram_block_wrapper	Sat 27. Aug 12:16:12 2011			4	0
microblaze_0_d_bram_ctrl_wrapper	Sat 27. Aug 12:16:06 2011	2	6		0
microblaze_0_i_bram_ctrl_wrapper	Sat 27. Aug 12:16:01 2011	2	6		0
axi4lite_0_wrapper	Sat 27. Aug 12:15:55 2011	2905	1827		0
axi_timer_0_wrapper	Fri 26. Aug 21:17:55 2011	260	272		0
microblaze_0_intc_wrapper	Fri 26. Aug 21:17:45 2011	86	115		0
ethernet_dma_wrapper	Fri 26. Aug 21:17:37 2011	3728	3798		0
ethernet_dma_wrapper_fifo_generator_v8_1_6_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:16:56 2011	107	109		0
ethernet_dma_wrapper_fifo_generator_v8_1_7_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:15:53 2011	98	100		0
ethernet_dma_wrapper_fifo_generator_v8_1_2_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:14:50 2011	68	49	1	0
ethernet_dma_wrapper_fifo_generator_v8_1_1_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:13:47 2011	74	59	1	0
ethernet_dma_wrapper_fifo_generator_v8_1_5_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:12:44 2011	69	49	1	0
ethernet_dma_wrapper_fifo_generator_v8_1_4_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:11:41 2011	99	103		0
ethernet_dma_wrapper_fifo_generator_v8_1_3_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:10:39 2011	97	98		0
ethernet_wrapper	Fri 26. Aug 21:09:24 2011	3166	3264		0
ethernet_wrapper_fifo_generator_v8_1_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:08:27 2011	104	148		0
ethernet_wrapper_blk_mem_gen_v5_2_2_blk_mem_gen_v5_2_xst_1	Fri 26. Aug 21:07:29 2011			1	0
ethernet_wrapper_blk_mem_gen_v5_2_1_blk_mem_gen_v5_2_xst_1	Fri 26. Aug 21:07:03 2011			2	0
ethernet_wrapper_blk_mem_gen_v5_2_4_blk_mem_gen_v5_2_xst_1	Fri 26. Aug 21:06:36 2011			1	0
ethernet_wrapper_blk_mem_gen_v5_2_3_blk_mem_gen_v5_2_xst_1	Fri 26. Aug 21:06:10 2011	2	49	2	0
push_buttons_4bits_wrapper	Fri 26. Aug 21:04:24 2011	72	85		0
leds_4bits_wrapper	Fri 26. Aug 21:04:14 2011	33	41		0
rs232_uart_1_wrapper	Fri 26. Aug 21:04:05 2011	84	102		0
proc_sys_reset_0_wrapper	Fri 26. Aug 21:03:43 2011	69	55		0
microblaze_0_dlmb_wrapper	Fri 26. Aug 21:03:19 2011	1	1		0
microblaze_0_ilmb_wrapper	Fri 26. Aug 21:03:15 2011	1	1		0
microblaze_0_wrapper	Fri 26. Aug 21:03:10 2011	1301	1703		0
axi4_0_wrapper	Fri 26. Aug 21:02:14 2011	1488	1083		0
axi4_0_wrapper_FIFO_GENERATOR_V8_1_2_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:01:57 2011	90	97	2	0
axi4_0_wrapper_FIFO_GENERATOR_V8_1_1_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:00:49 2011	89	96	1	0

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Device Utilization Summary (actual values)					[-]
Slice Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Registers	12,060	54,576	22%
Number used as Flip Flops	12,052
Number used as Latches	0
Number used as Latch-thrus	0
Number used as AND/OR logics	8
Number of Slice LUTs	10,940	27,288	40%
Number used as logic	9,639	27,288	35%
Number using O6 output only	6,889
Number using O5 output only	260
Number using O5 and O6	2,490
Number used as ROM	0
Number used as Memory	693	6,408	10%
Number used as Dual Port RAM	250
Number using O6 output only	10
Number using O5 output only	4
Number using O5 and O6	236
Number used as Single Port RAM	1
Number using O6 output only	1
Number using O5 output only	0
Number using O5 and O6	0
Number used as Shift Register	442
Number using O6 output only	205
Number using O5 output only	7
Number using O5 and O6	230
Number used exclusively as route-thrus	608
Number with same-slice register load	566
Number with same-slice carry load	37
Number with other load	5
Number of occupied Slices	4,589	6,822	67%
Number of LUT Flip Flop pairs used	13,843
Number with an unused Flip Flop	3,765	13,843	27%
Number with an unused LUT	2,903	13,843	20%
Number of fully used LUT-FF pairs	7,175	13,843	51%
Number of unique control sets	697
Number of slice register sites lost to control set restrictions	2,541	54,576	4%
Number of bonded IOBs	87	296	29%
Number of LOCed IOBs	87	87	100%
IOB Flip Flops	27
Number of RAMB16BWERs	12	116	10%
Number of RAMB8BWERs	4	232	1%
Number of BUFIO2/BUFIO2_2CLKs	3	32	9%
Number used as BUFIO2s	3
Number used as BUFIO2_2CLKs	0
Number of BUFIO2FB/BUFIO2FB_2CLKs	0	32	0%
Number of BUFG/BUFGMUXs	6	16	37%
Number used as BUFGs	5
Number used as BUFGMUX	1
Number of DCM/DCM_CLKGENs	0	8	0%
Number of ILOGIC2/ISERDES2s	12	376	3%
Number used as ILOGIC2s	12
Number used as ISERDES2s	0
Number of IODELAY2/IODRP2/IODRP2_MCBs	34	376	9%
Number used as IODELAY2s	10
Number used as IODRP2s	2
Number used as IODRP2_MCBs	22
Number of OLOGIC2/OSERDES2s	60	376	15%
Number used as OLOGIC2s	14
Number used as OSERDES2s	46
Number of BSCANs	1	4	25%
Number of BUFHs	0	256	0%
Number of BUFPLLs	0	8	0%
Number of BUFPLL_MCBs	1	4	25%
Number of DSP48A1s	3	58	5%
Number of GTPA1_DUALs	0	2	0%
Number of ICAPs	0	1	0%
Number of MCBs	1	2	50%
Number of PCIE_A1s	0	1	0%
Number of PCILOGICSEs	0	2	0%
Number of PLL_ADVs	2	4	50%
Number of PMVs	0	1	0%
Number of STARTUPs	0	1	0%
Number of SUSPEND_SYNCs	0	1	0%
Average Fanout of Non-Clock Nets	3.89

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Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0, Component Switching Limit: 0)	Pinout Data:	Pinout Report
Routing Results:	-All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	-All Constraints Met

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Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Translation Report	Current	Sat 27. Aug 12:19:05 2011	0	87 Warnings (0 new)	13 Infos (8 new)
Map Report	Current	Sat 27. Aug 12:28:13 2011	0	50 Warnings (0 new)	1134 Infos (0 new)
Place and Route Report	Current	Sat 27. Aug 12:31:43 2011	0	51 Warnings (0 new)	3 Infos (0 new)
Post-PAR Static Timing Report	Current	Sat 27. Aug 12:32:50 2011	0	3 Warnings (0 new)	3 Infos (0 new)
Bitgen Report	Current	Sat 27. Aug 12:34:09 2011	0	47 Warnings (0 new)	0

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Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Log File	Current	Sat 27. Aug 12:34:09 2011

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Date Generated: 08/27/2011 - 12:37:46 - \ No newline at end of file