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Update the memory alignment within the Cortex-R5 port asm code (#1023)
Update alignment in ARM_CR5 port.
This is the same patch as 553caa18ce
provided by Richard Barry for issue #426 (ARM_CA9).
Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
This commit is contained in:
parent
5da55ba8ad
commit
6270e2aebf
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@ -76,8 +76,8 @@
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/* Save the floating point context, if any. */
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FMRXNE R1, FPSCR
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VPUSHNE {D0-D15}
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PUSHNE {R1}
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VPUSHNE {D0-D15}
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/* Save ulPortTaskHasFPUContext itself. */
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PUSH {R3}
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@ -110,8 +110,8 @@
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CMP R1, #0
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/* Restore the floating point context, if any. */
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POPNE {R0}
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VPOPNE {D0-D15}
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POPNE {R0}
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VMSRNE FPSCR, R0
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#endif /* __ARM_FP */
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@ -147,8 +147,15 @@
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FreeRTOS_SWI_Handler:
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/* Save the context of the current task and select a new task to run. */
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portSAVE_CONTEXT
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/* Ensure bit 2 of the stack pointer is clear. */
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MOV r2, sp
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AND r2, r2, #4
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SUB sp, sp, r2
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LDR R0, vTaskSwitchContextConst
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BLX R0
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portRESTORE_CONTEXT
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@ -256,6 +263,11 @@ switch_before_exit:
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POP {LR}
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portSAVE_CONTEXT
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/* Ensure bit 2 of the stack pointer is clear. */
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MOV r2, sp
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AND r2, r2, #4
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SUB sp, sp, r2
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/* Call the function that selects the new task to execute.
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vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
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instructions, or 8 byte aligned stack allocated data. LR does not need
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