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Update the memory alignment within the Cortex-R5 port asm code (#1023)

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Update alignment in ARM_CR5 port.

This is the same patch as 553caa18ce
provided by Richard Barry for issue #426 (ARM_CA9).

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
This commit is contained in:
Florian La Roche 2024-04-09 07:21:12 +02:00 committed by GitHub
parent 5da55ba8ad
commit 6270e2aebf
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GPG key ID: B5690EEEBB952194
1 changed files with 14 additions and 2 deletions
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16
portable/GCC/ARM_CR5/portASM.S
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@ -76,8 +76,8 @@
/* Save the floating point context, if any. */ /* Save the floating point context, if any. */
FMRXNE R1, FPSCR FMRXNE R1, FPSCR
VPUSHNE {D0-D15}
PUSHNE {R1} PUSHNE {R1}
VPUSHNE {D0-D15}
/* Save ulPortTaskHasFPUContext itself. */ /* Save ulPortTaskHasFPUContext itself. */
PUSH {R3} PUSH {R3}
@ -110,8 +110,8 @@
CMP R1, #0 CMP R1, #0
/* Restore the floating point context, if any. */ /* Restore the floating point context, if any. */
POPNE {R0}
VPOPNE {D0-D15} VPOPNE {D0-D15}
POPNE {R0}
VMSRNE FPSCR, R0 VMSRNE FPSCR, R0
#endif /* __ARM_FP */ #endif /* __ARM_FP */
@ -147,8 +147,15 @@
FreeRTOS_SWI_Handler: FreeRTOS_SWI_Handler:
/* Save the context of the current task and select a new task to run. */ /* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT portSAVE_CONTEXT
/* Ensure bit 2 of the stack pointer is clear. */
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
LDR R0, vTaskSwitchContextConst LDR R0, vTaskSwitchContextConst
BLX R0 BLX R0
portRESTORE_CONTEXT portRESTORE_CONTEXT
@ -256,6 +263,11 @@ switch_before_exit:
POP {LR} POP {LR}
portSAVE_CONTEXT portSAVE_CONTEXT
/* Ensure bit 2 of the stack pointer is clear. */
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
/* Call the function that selects the new task to execute. /* Call the function that selects the new task to execute.
vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
instructions, or 8 byte aligned stack allocated data. LR does not need instructions, or 8 byte aligned stack allocated data. LR does not need