mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-02 04:13:54 -04:00
Style: uncrustify kernel files
This commit is contained in:
Alfred Gedeon
alfred gedeon
parent
66a815653b
commit
587a83d647
385 changed files with 4714 additions and 4338 deletions
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@ -22,6 +22,7 @@
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*-----------------------------------------------------------
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@ -104,7 +105,7 @@
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/* Each task maintains its own interrupt status in the critical nesting
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* variable. Note this is not saved as part of the task context as context
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* switches can only occur when uxCriticalNesting is zero. */
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static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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/*
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* Setup the timer to generate the tick interrupts.
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@ -162,8 +163,8 @@ static uint32_t prvPortGetIPSR( void );
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* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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*/
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#if ( configASSERT_DEFINED == 1 )
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static uint8_t ucMaxSysCallPriority = 0;
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static uint32_t ulMaxPRIGROUPValue = 0;
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static uint8_t ucMaxSysCallPriority = 0;
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static uint32_t ulMaxPRIGROUPValue = 0;
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static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
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#endif /* configASSERT_DEFINED */
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@ -239,8 +240,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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void prvSVCHandler( uint32_t * pulParam )
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{
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uint8_t ucSVCNumber;
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uint32_t ulReg, ulPC;
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uint8_t ucSVCNumber;
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uint32_t ulReg, ulPC;
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#if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
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extern uint32_t __syscalls_flash_start__;
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@ -249,7 +250,7 @@ void prvSVCHandler( uint32_t * pulParam )
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/* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
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* argument (r0) is pulParam[ 0 ]. */
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ulPC = pulParam[ portOFFSET_TO_PC ];
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ulPC = pulParam[ portOFFSET_TO_PC ];
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ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
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switch( ucSVCNumber )
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@ -328,22 +329,22 @@ __asm void prvRestoreContextOfFirstTask( void )
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{
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PRESERVE8
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ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, [ r0 ]
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ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, [ r0 ]
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ldr r0, [ r0 ]
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msr msp, r0 /* Set the msp back to the start of the stack. */
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ldr r3, = pxCurrentTCB /* Restore the context. */
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ldr r1, [ r3 ]
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ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
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add r1, r1, # 4 /* Move onto the second item in the TCB... */
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msr msp, r0 /* Set the msp back to the start of the stack. */
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ldr r3, = pxCurrentTCB /* Restore the context. */
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ldr r1, [ r3 ]
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ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
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add r1, r1, # 4 /* Move onto the second item in the TCB... */
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
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str r3, [ r2 ] /* Disable MPU. */
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
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str r3, [ r2 ] /* Disable MPU. */
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ldr r2, = 0xe000ed9c /* Region Base Address register. */
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ldr r2, = 0xe000ed9c /* Region Base Address register. */
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ldmia r1 !, {
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r4 - r11
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} /* Read 4 sets of MPU registers. */
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@ -351,11 +352,11 @@ __asm void prvRestoreContextOfFirstTask( void )
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r4 - r11
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} /* Write 4 sets of MPU registers. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
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str r3, [ r2 ] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
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str r3, [ r2 ] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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ldmia r0 !, {
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r3 - r11, r14
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@ -380,9 +381,9 @@ BaseType_t xPortStartScheduler( void )
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#if ( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t ulOriginalPriority;
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volatile uint32_t ulOriginalPriority;
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volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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volatile uint8_t ucMaxPriorityValue;
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volatile uint8_t ucMaxPriorityValue;
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/* Determine the maximum priority from which ISR safe FreeRTOS API
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* functions can be called. ISR safe functions are those that end in
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@ -390,21 +391,21 @@ BaseType_t xPortStartScheduler( void )
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* ensure interrupt entry is as fast and simple as possible.
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*
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* Save the interrupt priority value that is about to be clobbered. */
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ulOriginalPriority = *pucFirstUserPriorityRegister;
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ulOriginalPriority = *pucFirstUserPriorityRegister;
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/* Determine the number of priority bits available. First write to all
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* possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Read the value back to see how many bits stuck. */
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ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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{
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@ -432,8 +433,8 @@ BaseType_t xPortStartScheduler( void )
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/* Shift the priority group value back to its position within the AIRCR
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* register. */
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ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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/* Restore the clobbered interrupt priority register to its original
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* value. */
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@ -455,13 +456,13 @@ BaseType_t xPortStartScheduler( void )
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vSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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uxCriticalNesting = 0;
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uxCriticalNesting = 0;
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/* Ensure the VFP is enabled - it should be anyway. */
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vPortEnableVFP();
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/* Lazy save always. */
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*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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/* Start the first task. */
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prvStartFirstTask();
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@ -541,10 +542,10 @@ __asm void xPortPendSVHandler( void )
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PRESERVE8
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mrs r0, psp
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mrs r0, psp
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ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */
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ldr r2, [ r3 ]
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ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */
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ldr r2, [ r3 ]
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tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
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it eq
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@ -573,16 +574,16 @@ __asm void xPortPendSVHandler( void )
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}
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/* Restore the context. */
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ldr r1, [ r3 ]
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ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
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add r1, r1, # 4 /* Move onto the second item in the TCB... */
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ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
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add r1, r1, # 4 /* Move onto the second item in the TCB... */
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
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str r3, [ r2 ] /* Disable MPU. */
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
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str r3, [ r2 ] /* Disable MPU. */
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ldr r2, = 0xe000ed9c /* Region Base Address register. */
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ldr r2, = 0xe000ed9c /* Region Base Address register. */
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ldmia r1 !, {
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r4 - r11
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} /* Read 4 sets of MPU registers. */
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@ -590,11 +591,11 @@ __asm void xPortPendSVHandler( void )
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r4 - r11
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} /* Write 4 sets of MPU registers. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
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str r3, [ r2 ] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
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str r3, [ r2 ] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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ldmia r0 !, {
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r3 - r11, r14
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@ -609,7 +610,7 @@ __asm void xPortPendSVHandler( void )
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msr psp, r0
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bx r14
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nop
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nop
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}
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/*-----------------------------------------------------------*/
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@ -637,12 +638,12 @@ void xPortSysTickHandler( void )
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__weak void vSetupTimerInterrupt( void )
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{
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/* Reset the SysTick. */
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portNVIC_SYSTICK_CTRL_REG = 0UL;
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portNVIC_SYSTICK_CTRL_REG = 0UL;
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Configure SysTick to interrupt at the requested rate. */
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portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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}
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/*-----------------------------------------------------------*/
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@ -689,10 +690,10 @@ static void prvSetupMPU( void )
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( portMPU_REGION_VALID ) |
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( portUNPRIVILEGED_FLASH_REGION );
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portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
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( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
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( portMPU_REGION_ENABLE );
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portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
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( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
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( portMPU_REGION_ENABLE );
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/* Setup the privileged flash for privileged only access. This is where
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* the kernel code is placed. */
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@ -700,10 +701,10 @@ static void prvSetupMPU( void )
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( portMPU_REGION_VALID ) |
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( portPRIVILEGED_FLASH_REGION );
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portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
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( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
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( portMPU_REGION_ENABLE );
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portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
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( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
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( portMPU_REGION_ENABLE );
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/* Setup the privileged data RAM region. This is where the kernel data
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* is placed. */
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@ -711,10 +712,10 @@ static void prvSetupMPU( void )
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( portMPU_REGION_VALID ) |
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( portPRIVILEGED_RAM_REGION );
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portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
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( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
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( portMPU_REGION_ENABLE );
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portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
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( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
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( portMPU_REGION_ENABLE );
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/* By default allow everything to access the general peripherals. The
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* system peripherals and registers are protected. */
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@ -722,15 +723,15 @@ static void prvSetupMPU( void )
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( portMPU_REGION_VALID ) |
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( portGENERAL_PERIPHERALS_REGION );
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portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
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( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
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( portMPU_REGION_ENABLE );
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portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
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( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
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( portMPU_REGION_ENABLE );
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/* Enable the memory fault exception. */
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portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
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portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
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/* Enable the MPU with the background region configured. */
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portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
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portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
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}
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}
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/*-----------------------------------------------------------*/
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@ -794,8 +795,8 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
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extern uint32_t __privileged_data_end__;
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int32_t lIndex;
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uint32_t ul;
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int32_t lIndex;
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uint32_t ul;
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if( xRegions == NULL )
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{
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@ -805,7 +806,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
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( portMPU_REGION_VALID ) |
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( portSTACK_REGION );
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xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
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xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
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( portMPU_REGION_READ_WRITE ) |
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( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
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@ -818,7 +819,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
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( portMPU_REGION_VALID ) |
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( portSTACK_REGION + 1 );
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xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
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xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
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( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
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( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
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@ -828,7 +829,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
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for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
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{
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xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
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xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
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xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
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}
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}
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else
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@ -845,7 +846,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
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( portMPU_REGION_VALID ) |
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( portSTACK_REGION ); /* Region number. */
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xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
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xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
|
||||
( portMPU_REGION_READ_WRITE ) | /* Read and write. */
|
||||
( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
|
||||
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
|
||||
|
|
@ -866,7 +867,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
|
|||
( portMPU_REGION_VALID ) |
|
||||
( portSTACK_REGION + ul ); /* Region number. */
|
||||
|
||||
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
|
||||
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
|
||||
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
|
||||
( xRegions[ lIndex ].ulParameters ) |
|
||||
( portMPU_REGION_ENABLE );
|
||||
|
|
@ -875,7 +876,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
|
|||
{
|
||||
/* Invalidate the region. */
|
||||
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
|
||||
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
|
||||
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
|
||||
}
|
||||
|
||||
lIndex++;
|
||||
|
|
@ -898,7 +899,7 @@ __asm uint32_t prvPortGetIPSR( void )
|
|||
void vPortValidateInterruptPriority( void )
|
||||
{
|
||||
uint32_t ulCurrentInterrupt;
|
||||
uint8_t ucCurrentPriority;
|
||||
uint8_t ucCurrentPriority;
|
||||
|
||||
/* Obtain the number of the currently executing interrupt. */
|
||||
ulCurrentInterrupt = prvPortGetIPSR();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue