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Style: uncrustify kernel files
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385 changed files with 4714 additions and 4338 deletions
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@ -22,24 +22,25 @@
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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EXTERN pxCurrentTCB
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EXTERN ulCriticalNesting
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EXTERN ulCriticalNesting
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;
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Context save and restore macro definitions
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Context save and restore macro definitions
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;
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portSAVE_CONTEXT MACRO
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;
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Push R0 as we are going to use the register.
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STMDB SP !, { R0 }
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STMDB SP !, { R0 }
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;
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Set R0 to point to the task stack pointer.
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STMDB SP, { SP } ^
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STMDB SP, { SP } ^
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NOP
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SUB SP, SP, # 4
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LDMIA SP !, { R0 }
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@ -51,7 +52,7 @@ Push the return address onto the stack.
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;
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Now we have saved LR we can use it instead of R0.
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MOV LR, R0
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MOV LR, R0
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;
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Pop R0 so we can save it onto the system mode stack.
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@ -108,7 +109,7 @@ Restore all system mode registers for the task.
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NOP
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;
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Restore the return address.
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Restore the return address.
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LDR LR, [ LR, # + 60 ]
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;
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@ -22,6 +22,7 @@
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*-----------------------------------------------------------
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@ -216,8 +217,8 @@ void vPortEndScheduler( void )
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/* This function is copied from the ST STR7 library and is
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* copyright STMicroelectronics. Reproduced with permission. */
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u32 b0;
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u16 a0;
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u32 b0;
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u16 a0;
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int32_t err, err_min = n;
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*a = a0 = ( ( n - 1 ) / 65536ul ) + 1;
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@ -225,7 +226,7 @@ void vPortEndScheduler( void )
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for( ; *a <= 256; ( *a )++ )
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{
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*b = n / *a;
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*b = n / *a;
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err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n;
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if( abs( err ) > ( *a / 2 ) )
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@ -237,8 +238,8 @@ void vPortEndScheduler( void )
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if( abs( err ) < abs( err_min ) )
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{
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err_min = err;
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a0 = *a;
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b0 = *b;
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a0 = *a;
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b0 = *b;
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if( err == 0 )
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{
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@ -255,8 +256,8 @@ void vPortEndScheduler( void )
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static void prvSetupTimerInterrupt( void )
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{
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WDG_InitTypeDef xWdg;
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uint16_t a;
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uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
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uint16_t a;
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uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
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/* Configure the watchdog as a free running timer that generates a
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* periodic interrupt. */
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@ -266,7 +267,7 @@ void vPortEndScheduler( void )
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WDG_StructInit( &xWdg );
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prvFindFactors( n, &a, &b );
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xWdg.WDG_Prescaler = a - 1;
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xWdg.WDG_Preload = b - 1;
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xWdg.WDG_Preload = b - 1;
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WDG_Init( &xWdg );
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WDG_ITConfig( ENABLE );
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@ -275,8 +276,8 @@ void vPortEndScheduler( void )
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VIC_ITCmd( WDG_ITLine, ENABLE );
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/* Install the default handlers for both VIC's. */
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VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
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VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
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VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
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VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
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WDG_Cmd( ENABLE );
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}
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@ -306,8 +307,8 @@ void vPortEndScheduler( void )
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/* This function is copied from the ST STR7 library and is
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* copyright STMicroelectronics. Reproduced with permission. */
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u16 b0;
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u8 a0;
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u16 b0;
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u8 a0;
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int32_t err, err_min = n;
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@ -316,7 +317,7 @@ void vPortEndScheduler( void )
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for( ; *a <= 256; ( *a )++ )
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{
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*b = n / *a;
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*b = n / *a;
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err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n;
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if( abs( err ) > ( *a / 2 ) )
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if( abs( err ) < abs( err_min ) )
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{
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err_min = err;
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a0 = *a;
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b0 = *b;
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a0 = *a;
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b0 = *b;
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if( err == 0 )
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{
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@ -345,9 +346,9 @@ void vPortEndScheduler( void )
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static void prvSetupTimerInterrupt( void )
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{
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uint8_t a;
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uint16_t b;
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uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
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uint8_t a;
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uint16_t b;
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uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
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TIM_InitTypeDef timer;
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TIM_StructInit( &timer );
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prvFindFactors( n, &a, &b );
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timer.TIM_Mode = TIM_OCM_CHANNEL_1;
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timer.TIM_OC1_Modes = TIM_TIMING;
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timer.TIM_Clock_Source = TIM_CLK_APB;
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timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING;
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timer.TIM_Prescaler = a - 1;
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timer.TIM_Pulse_Level_1 = TIM_HIGH;
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timer.TIM_Mode = TIM_OCM_CHANNEL_1;
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timer.TIM_OC1_Modes = TIM_TIMING;
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timer.TIM_Clock_Source = TIM_CLK_APB;
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timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING;
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timer.TIM_Prescaler = a - 1;
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timer.TIM_Pulse_Level_1 = TIM_HIGH;
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timer.TIM_Pulse_Length_1 = s_nPulseLength = b - 1;
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TIM_Init( TIM2, &timer );
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VIC_ITCmd( TIM2_ITLine, ENABLE );
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/* Install the default handlers for both VIC's. */
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VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
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VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
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VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
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VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
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TIM_CounterCmd( TIM2, TIM_CLEAR );
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TIM_CounterCmd( TIM2, TIM_START );
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}
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/* Clear the interrupt in the watchdog. */
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TIM2->SR &= ~TIM_FLAG_OC1;
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TIM2->SR &= ~TIM_FLAG_OC1;
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}
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#endif /* USE_WATCHDOG_TICK */
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@ -22,6 +22,7 @@
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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