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Alfred Gedeon 2020-07-07 17:42:07 -07:00 • committed by alfred gedeon
parent 66a815653b
commit 587a83d647
385 changed files with 4714 additions and 4338 deletions
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19
portable/GCC/ARM7_AT91FR40008/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -179,16 +180,16 @@ static void prvSetupTimerInterrupt( void )
volatile uint32_t ulDummy;
/* Enable clock to the tick timer... */
AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
/* Stop the tick timer... */
portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
/* Start with tick timer interrupts disabled... */
portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
/* Clear any pending tick timer interrupts... */
ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
/* Store interrupt handler function address in tick timer vector register...
* The ISR installed depends on whether the preemptive or cooperative
@ -211,10 +212,10 @@ static void prvSetupTimerInterrupt( void )
/* Enable the tick timer interrupt...
*
* First at timer level */
portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
/* Then at the AIC level. */
AT91C_BASE_AIC->AIC_IECR = ( 1 << portTIMER_AIC_CHANNEL );
AT91C_BASE_AIC->AIC_IECR = ( 1 << portTIMER_AIC_CHANNEL );
/* Calculate timer compare value to achieve the desired tick rate... */
if( ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 ) ) <= 0xFFFF )
@ -222,17 +223,17 @@ static void prvSetupTimerInterrupt( void )
/* The tick rate is fast enough for us to use the faster timer input
* clock (main clock / 2). */
portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 );
portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 );
}
else
{
/* We must use a slower timer input clock (main clock / 8) because the
* tick rate is too slow for the faster input clock. */
portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 8 );
portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 8 );
}
/* Start tick timer... */
portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
}
/*-----------------------------------------------------------*/

5
portable/GCC/ARM7_AT91FR40008/portISR.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -111,7 +112,7 @@ void vPortYieldProcessor( void )
static volatile uint32_t ulDummy;
/* Clear tick timer interrupt indication. */
ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
xTaskIncrementTick();
@ -134,7 +135,7 @@ void vPortYieldProcessor( void )
static volatile uint32_t ulDummy;
/* Clear tick timer interrupt indication. */
ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
/* Increment the RTOS tick count, then look for the highest priority
* task that is ready to run. */

5
portable/GCC/ARM7_AT91FR40008/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
@ -115,7 +116,7 @@
#define portRESTORE_CONTEXT() \
{ \
extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Set the LR to the task stack. */ \
asm volatile ( \
@ -152,7 +153,7 @@
#define portSAVE_CONTEXT() \
{ \
extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Push R0 as we are going to use the register. */ \
asm volatile ( \

6
portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
View file

@ -2744,15 +2744,15 @@ typedef struct _AT91S_TDES
{ \
unsigned int mask; \
\
mask = 0x1 << irq_id; \
mask = 0x1 << irq_id; \
/* Disable the interrupt on the interrupt controller */ \
AT91C_BASE_AIC->AIC_IDCR = mask; \
AT91C_BASE_AIC->AIC_IDCR = mask; \
/* Save the interrupt handler routine pointer and the interrupt priority */ \
AT91C_BASE_AIC->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; \
/* Store the Source Mode Register */ \
AT91C_BASE_AIC->AIC_SMR[ irq_id ] = src_type | priority; \
/* Clear the interrupt on the interrupt controller */ \
AT91C_BASE_AIC->AIC_ICCR = mask; \
AT91C_BASE_AIC->AIC_ICCR = mask; \
}

470
portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
View file

@ -2753,46 +2753,46 @@ typedef struct _AT91S_TDES
/* - ***************************************************************************** */
/* - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
#if 0 /*_RB_*/
AT91C_AIC_PRIOR EQU( 0x7 << 0 );
AT91C_AIC_PRIOR EQU( 0x7 << 0 );
- ( AIC ) Priority Level
AT91C_AIC_PRIOR_LOWEST EQU( 0x0 );
AT91C_AIC_PRIOR_LOWEST EQU( 0x0 );
- ( AIC ) Lowest priority level
AT91C_AIC_PRIOR_HIGHEST EQU( 0x7 );
AT91C_AIC_PRIOR_HIGHEST EQU( 0x7 );
- ( AIC ) Highest priority level
AT91C_AIC_SRCTYPE EQU( 0x3 << 5 );
AT91C_AIC_SRCTYPE EQU( 0x3 << 5 );
- ( AIC ) Interrupt Source Type
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU( 0x0 << 5 );
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU( 0x0 << 5 );
- ( AIC ) Internal Sources Code Label High - level Sensitive
AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU( 0x0 << 5 );
AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU( 0x0 << 5 );
- ( AIC ) External Sources Code Label Low - level Sensitive
AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU( 0x1 << 5 );
- ( AIC ) Internal Sources Code Label Positive Edge triggered
AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU( 0x1 << 5 );
- ( AIC ) External Sources Code Label Negative Edge triggered
AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU( 0x2 << 5 );
AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU( 0x2 << 5 );
- ( AIC ) Internal Or External Sources Code Label High - level Sensitive
AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU( 0x3 << 5 );
AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU( 0x3 << 5 );
- ( AIC ) Internal Or External Sources Code Label Positive Edge triggered
/* - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
AT91C_AIC_NFIQ EQU( 0x1 << 0 );
AT91C_AIC_NFIQ EQU( 0x1 << 0 );
- ( AIC ) NFIQ Status
AT91C_AIC_NIRQ EQU( 0x1 << 1 );
AT91C_AIC_NIRQ EQU( 0x1 << 1 );
- ( AIC ) NIRQ Status
/* - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
AT91C_AIC_DCR_PROT EQU( 0x1 << 0 );
AT91C_AIC_DCR_PROT EQU( 0x1 << 0 );
- ( AIC ) Protection Mode
AT91C_AIC_DCR_GMSK EQU( 0x1 << 1 );
AT91C_AIC_DCR_GMSK EQU( 0x1 << 1 );
- ( AIC ) General Mask
#endif /* if 0 */
/* - ***************************************************************************** */
/* - SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
/* - ***************************************************************************** */
/* - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
AT91C_PDC_RXTEN EQU( 0x1 << 0 );
AT91C_PDC_RXTEN EQU( 0x1 << 0 );
- ( PDC ) Receiver Transfer Enable
AT91C_PDC_RXTDIS EQU( 0x1 << 1 );
- ( PDC ) Receiver Transfer Disable
AT91C_PDC_TXTEN EQU( 0x1 << 8 );
AT91C_PDC_TXTEN EQU( 0x1 << 8 );
- ( PDC ) Transmitter Transfer Enable
AT91C_PDC_TXTDIS EQU( 0x1 << 9 );
- ( PDC ) Transmitter Transfer Disable
@ -2802,69 +2802,69 @@ AT91C_PDC_RXTEN EQU( 0x1 << 0 );
/* - SOFTWARE API DEFINITION FOR Debug Unit */
/* - ***************************************************************************** */
/* - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
AT91C_US_RSTRX EQU( 0x1 << 2 );
AT91C_US_RSTRX EQU( 0x1 << 2 );
- ( DBGU ) Reset Receiver
AT91C_US_RSTTX EQU( 0x1 << 3 );
AT91C_US_RSTTX EQU( 0x1 << 3 );
- ( DBGU ) Reset Transmitter
AT91C_US_RXEN EQU( 0x1 << 4 );
AT91C_US_RXEN EQU( 0x1 << 4 );
- ( DBGU ) Receiver Enable
AT91C_US_RXDIS EQU( 0x1 << 5 );
AT91C_US_RXDIS EQU( 0x1 << 5 );
- ( DBGU ) Receiver Disable
AT91C_US_TXEN EQU( 0x1 << 6 );
AT91C_US_TXEN EQU( 0x1 << 6 );
- ( DBGU ) Transmitter Enable
AT91C_US_TXDIS EQU( 0x1 << 7 );
AT91C_US_TXDIS EQU( 0x1 << 7 );
- ( DBGU ) Transmitter Disable
AT91C_US_RSTSTA EQU( 0x1 << 8 );
AT91C_US_RSTSTA EQU( 0x1 << 8 );
- ( DBGU ) Reset Status Bits
/* - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
AT91C_US_PAR EQU( 0x7 << 9 );
AT91C_US_PAR EQU( 0x7 << 9 );
- ( DBGU ) Parity type
AT91C_US_PAR_EVEN EQU( 0x0 << 9 );
AT91C_US_PAR_EVEN EQU( 0x0 << 9 );
- ( DBGU ) Even Parity
AT91C_US_PAR_ODD EQU( 0x1 << 9 );
AT91C_US_PAR_ODD EQU( 0x1 << 9 );
- ( DBGU ) Odd Parity
AT91C_US_PAR_SPACE EQU( 0x2 << 9 );
AT91C_US_PAR_SPACE EQU( 0x2 << 9 );
- ( DBGU ) Parity forced to 0 ( Space )
AT91C_US_PAR_MARK EQU( 0x3 << 9 );
AT91C_US_PAR_MARK EQU( 0x3 << 9 );
- ( DBGU ) Parity forced to 1 ( Mark )
AT91C_US_PAR_NONE EQU( 0x4 << 9 );
AT91C_US_PAR_NONE EQU( 0x4 << 9 );
- ( DBGU ) No Parity
AT91C_US_PAR_MULTI_DROP EQU( 0x6 << 9 );
AT91C_US_PAR_MULTI_DROP EQU( 0x6 << 9 );
- ( DBGU ) Multi - drop mode
AT91C_US_CHMODE EQU( 0x3 << 14 );
AT91C_US_CHMODE EQU( 0x3 << 14 );
- ( DBGU ) Channel Mode
AT91C_US_CHMODE_NORMAL EQU( 0x0 << 14 );
AT91C_US_CHMODE_NORMAL EQU( 0x0 << 14 );
- ( DBGU ) Normal Mode: The USART channel operates as an RX / TX USART.
AT91C_US_CHMODE_AUTO EQU( 0x1 << 14 );
AT91C_US_CHMODE_AUTO EQU( 0x1 << 14 );
- ( DBGU ) Automatic Echo: Receiver Data Input is connected to the TXD pin.
AT91C_US_CHMODE_LOCAL EQU( 0x2 << 14 );
AT91C_US_CHMODE_LOCAL EQU( 0x2 << 14 );
- ( DBGU ) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
AT91C_US_CHMODE_REMOTE EQU( 0x3 << 14 );
- ( DBGU ) Remote Loopback: RXD pin is internally connected to TXD pin.
/* - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
AT91C_US_RXRDY EQU( 0x1 << 0 );
AT91C_US_RXRDY EQU( 0x1 << 0 );
- ( DBGU ) RXRDY Interrupt
AT91C_US_TXRDY EQU( 0x1 << 1 );
AT91C_US_TXRDY EQU( 0x1 << 1 );
- ( DBGU ) TXRDY Interrupt
AT91C_US_ENDRX EQU( 0x1 << 3 );
AT91C_US_ENDRX EQU( 0x1 << 3 );
- ( DBGU ) End of Receive Transfer Interrupt
AT91C_US_ENDTX EQU( 0x1 << 4 );
AT91C_US_ENDTX EQU( 0x1 << 4 );
- ( DBGU ) End of Transmit Interrupt
AT91C_US_OVRE EQU( 0x1 << 5 );
AT91C_US_OVRE EQU( 0x1 << 5 );
- ( DBGU ) Overrun Interrupt
AT91C_US_FRAME EQU( 0x1 << 6 );
AT91C_US_FRAME EQU( 0x1 << 6 );
- ( DBGU ) Framing Error Interrupt
AT91C_US_PARE EQU( 0x1 << 7 );
AT91C_US_PARE EQU( 0x1 << 7 );
- ( DBGU ) Parity Error Interrupt
AT91C_US_TXEMPTY EQU( 0x1 << 9 );
AT91C_US_TXEMPTY EQU( 0x1 << 9 );
- ( DBGU ) TXEMPTY Interrupt
AT91C_US_TXBUFE EQU( 0x1 << 11 );
AT91C_US_TXBUFE EQU( 0x1 << 11 );
- ( DBGU ) TXBUFE Interrupt
AT91C_US_RXBUFF EQU( 0x1 << 12 );
AT91C_US_RXBUFF EQU( 0x1 << 12 );
- ( DBGU ) RXBUFF Interrupt
AT91C_US_COMM_TX EQU( 0x1 << 30 );
AT91C_US_COMM_TX EQU( 0x1 << 30 );
- ( DBGU ) COMM_TX Interrupt
AT91C_US_COMM_RX EQU( 0x1 << 31 );
AT91C_US_COMM_RX EQU( 0x1 << 31 );
- ( DBGU ) COMM_RX Interrupt
/* - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
/* - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
@ -2881,54 +2881,54 @@ AT91C_PDC_RXTEN EQU( 0x1 << 0 );
/* - SOFTWARE API DEFINITION FOR Clock Generator Controler */
/* - ***************************************************************************** */
/* - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
AT91C_CKGR_MOSCEN EQU( 0x1 << 0 );
AT91C_CKGR_MOSCEN EQU( 0x1 << 0 );
- ( CKGR ) Main Oscillator Enable
AT91C_CKGR_OSCBYPASS EQU( 0x1 << 1 );
AT91C_CKGR_OSCBYPASS EQU( 0x1 << 1 );
- ( CKGR ) Main Oscillator Bypass
AT91C_CKGR_OSCOUNT EQU( 0xFF << 8 );
AT91C_CKGR_OSCOUNT EQU( 0xFF << 8 );
- ( CKGR ) Main Oscillator Start - up Time
/* - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
AT91C_CKGR_MAINF EQU( 0xFFFF << 0 );
AT91C_CKGR_MAINF EQU( 0xFFFF << 0 );
- ( CKGR ) Main Clock Frequency
AT91C_CKGR_MAINRDY EQU( 0x1 << 16 );
AT91C_CKGR_MAINRDY EQU( 0x1 << 16 );
- ( CKGR ) Main Clock Ready
/* - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
AT91C_CKGR_DIV EQU( 0xFF << 0 );
AT91C_CKGR_DIV EQU( 0xFF << 0 );
- ( CKGR ) Divider Selected
AT91C_CKGR_DIV_0 EQU( 0x0 );
AT91C_CKGR_DIV_0 EQU( 0x0 );
- ( CKGR ) Divider output is 0
AT91C_CKGR_DIV_BYPASS EQU( 0x1 );
- ( CKGR ) Divider is bypassed
AT91C_CKGR_PLLCOUNT EQU( 0x3F << 8 );
AT91C_CKGR_PLLCOUNT EQU( 0x3F << 8 );
- ( CKGR ) PLL Counter
AT91C_CKGR_OUT EQU( 0x3 << 14 );
AT91C_CKGR_OUT EQU( 0x3 << 14 );
- ( CKGR ) PLL Output Frequency Range
AT91C_CKGR_OUT_0 EQU( 0x0 << 14 );
AT91C_CKGR_OUT_0 EQU( 0x0 << 14 );
- ( CKGR ) Please refer to the PLL datasheet
AT91C_CKGR_OUT_1 EQU( 0x1 << 14 );
AT91C_CKGR_OUT_1 EQU( 0x1 << 14 );
- ( CKGR ) Please refer to the PLL datasheet
AT91C_CKGR_OUT_2 EQU( 0x2 << 14 );
AT91C_CKGR_OUT_2 EQU( 0x2 << 14 );
- ( CKGR ) Please refer to the PLL datasheet
AT91C_CKGR_OUT_3 EQU( 0x3 << 14 );
AT91C_CKGR_OUT_3 EQU( 0x3 << 14 );
- ( CKGR ) Please refer to the PLL datasheet
AT91C_CKGR_MUL EQU( 0x7FF << 16 );
AT91C_CKGR_MUL EQU( 0x7FF << 16 );
- ( CKGR ) PLL Multiplier
AT91C_CKGR_USBDIV EQU( 0x3 << 28 );
AT91C_CKGR_USBDIV EQU( 0x3 << 28 );
- ( CKGR ) Divider for USB Clocks
AT91C_CKGR_USBDIV_0 EQU( 0x0 << 28 );
AT91C_CKGR_USBDIV_0 EQU( 0x0 << 28 );
- ( CKGR ) Divider output is PLL clock output
AT91C_CKGR_USBDIV_1 EQU( 0x1 << 28 );
AT91C_CKGR_USBDIV_1 EQU( 0x1 << 28 );
- ( CKGR ) Divider output is PLL clock output divided by 2
AT91C_CKGR_USBDIV_2 EQU( 0x2 << 28 );
AT91C_CKGR_USBDIV_2 EQU( 0x2 << 28 );
- ( CKGR ) Divider output is PLL clock output divided by 4
/* - ***************************************************************************** */
/* - SOFTWARE API DEFINITION FOR Power Management Controler */
/* - ***************************************************************************** */
/* - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
AT91C_PMC_PCK EQU( 0x1 << 0 );
AT91C_PMC_PCK EQU( 0x1 << 0 );
- ( PMC ) Processor Clock
AT91C_PMC_UDP EQU( 0x1 << 7 );
AT91C_PMC_UDP EQU( 0x1 << 7 );
- ( PMC ) USB Device Port Clock
AT91C_PMC_PCK0 EQU( 0x1 << 8 );
- ( PMC ) Programmable Clock Output
@ -2944,45 +2944,45 @@ AT91C_PDC_RXTEN EQU( 0x1 << 0 );
/* - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
/* - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
/* - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
AT91C_PMC_CSS EQU( 0x3 << 0 );
AT91C_PMC_CSS EQU( 0x3 << 0 );
- ( PMC ) Programmable Clock Selection
AT91C_PMC_CSS_SLOW_CLK EQU( 0x0 );
- ( PMC ) Slow Clock is selected
AT91C_PMC_CSS_MAIN_CLK EQU( 0x1 );
- ( PMC ) Main Clock is selected
AT91C_PMC_CSS_PLL_CLK EQU( 0x3 );
AT91C_PMC_CSS_PLL_CLK EQU( 0x3 );
- ( PMC ) Clock from PLL is selected
AT91C_PMC_PRES EQU( 0x7 << 2 );
AT91C_PMC_PRES EQU( 0x7 << 2 );
- ( PMC ) Programmable Clock Prescaler
AT91C_PMC_PRES_CLK EQU( 0x0 << 2 );
AT91C_PMC_PRES_CLK EQU( 0x0 << 2 );
- ( PMC ) Selected clock
AT91C_PMC_PRES_CLK_2 EQU( 0x1 << 2 );
AT91C_PMC_PRES_CLK_2 EQU( 0x1 << 2 );
- ( PMC ) Selected clock divided by 2
AT91C_PMC_PRES_CLK_4 EQU( 0x2 << 2 );
AT91C_PMC_PRES_CLK_4 EQU( 0x2 << 2 );
- ( PMC ) Selected clock divided by 4
AT91C_PMC_PRES_CLK_8 EQU( 0x3 << 2 );
AT91C_PMC_PRES_CLK_8 EQU( 0x3 << 2 );
- ( PMC ) Selected clock divided by 8
AT91C_PMC_PRES_CLK_16 EQU( 0x4 << 2 );
AT91C_PMC_PRES_CLK_16 EQU( 0x4 << 2 );
- ( PMC ) Selected clock divided by 16
AT91C_PMC_PRES_CLK_32 EQU( 0x5 << 2 );
AT91C_PMC_PRES_CLK_32 EQU( 0x5 << 2 );
- ( PMC ) Selected clock divided by 32
AT91C_PMC_PRES_CLK_64 EQU( 0x6 << 2 );
AT91C_PMC_PRES_CLK_64 EQU( 0x6 << 2 );
- ( PMC ) Selected clock divided by 64
/* - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
/* - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
AT91C_PMC_MOSCS EQU( 0x1 << 0 );
AT91C_PMC_MOSCS EQU( 0x1 << 0 );
- ( PMC ) MOSC Status / Enable / Disable / Mask
AT91C_PMC_LOCK EQU( 0x1 << 2 );
AT91C_PMC_LOCK EQU( 0x1 << 2 );
- ( PMC ) PLL Status / Enable / Disable / Mask
AT91C_PMC_MCKRDY EQU( 0x1 << 3 );
AT91C_PMC_MCKRDY EQU( 0x1 << 3 );
- ( PMC ) MCK_RDY Status / Enable / Disable / Mask
AT91C_PMC_PCK0RDY EQU( 0x1 << 8 );
AT91C_PMC_PCK0RDY EQU( 0x1 << 8 );
- ( PMC ) PCK0_RDY Status / Enable / Disable / Mask
AT91C_PMC_PCK1RDY EQU( 0x1 << 9 );
AT91C_PMC_PCK1RDY EQU( 0x1 << 9 );
- ( PMC ) PCK1_RDY Status / Enable / Disable / Mask
AT91C_PMC_PCK2RDY EQU( 0x1 << 10 );
AT91C_PMC_PCK2RDY EQU( 0x1 << 10 );
- ( PMC ) PCK2_RDY Status / Enable / Disable / Mask
AT91C_PMC_PCK3RDY EQU( 0x1 << 11 );
AT91C_PMC_PCK3RDY EQU( 0x1 << 11 );
- ( PMC ) PCK3_RDY Status / Enable / Disable / Mask
/* - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
/* - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
@ -2992,88 +2992,88 @@ AT91C_PDC_RXTEN EQU( 0x1 << 0 );
/* - SOFTWARE API DEFINITION FOR Reset Controller Interface */
/* - ***************************************************************************** */
/* - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
AT91C_RSTC_PROCRST EQU( 0x1 << 0 );
AT91C_RSTC_PROCRST EQU( 0x1 << 0 );
- ( RSTC ) Processor Reset
AT91C_RSTC_PERRST EQU( 0x1 << 2 );
AT91C_RSTC_PERRST EQU( 0x1 << 2 );
- ( RSTC ) Peripheral Reset
AT91C_RSTC_EXTRST EQU( 0x1 << 3 );
AT91C_RSTC_EXTRST EQU( 0x1 << 3 );
- ( RSTC ) External Reset
AT91C_RSTC_KEY EQU( 0xFF << 24 );
AT91C_RSTC_KEY EQU( 0xFF << 24 );
- ( RSTC ) Password
/* - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
AT91C_RSTC_URSTS EQU( 0x1 << 0 );
AT91C_RSTC_URSTS EQU( 0x1 << 0 );
- ( RSTC ) User Reset Status
AT91C_RSTC_BODSTS EQU( 0x1 << 1 );
AT91C_RSTC_BODSTS EQU( 0x1 << 1 );
- ( RSTC ) Brownout Detection Status
AT91C_RSTC_RSTTYP EQU( 0x7 << 8 );
AT91C_RSTC_RSTTYP EQU( 0x7 << 8 );
- ( RSTC ) Reset Type
AT91C_RSTC_RSTTYP_POWERUP EQU( 0x0 << 8 );
AT91C_RSTC_RSTTYP_POWERUP EQU( 0x0 << 8 );
- ( RSTC ) Power - up Reset.VDDCORE rising.
AT91C_RSTC_RSTTYP_WAKEUP EQU( 0x1 << 8 );
AT91C_RSTC_RSTTYP_WAKEUP EQU( 0x1 << 8 );
- ( RSTC ) WakeUp Reset.VDDCORE rising.
AT91C_RSTC_RSTTYP_WATCHDOG EQU( 0x2 << 8 );
- ( RSTC ) Watchdog Reset.Watchdog overflow occured.
AT91C_RSTC_RSTTYP_SOFTWARE EQU( 0x3 << 8 );
- ( RSTC ) Software Reset.Processor reset required by the software.
AT91C_RSTC_RSTTYP_USER EQU( 0x4 << 8 );
AT91C_RSTC_RSTTYP_USER EQU( 0x4 << 8 );
- ( RSTC ) User Reset.NRST pin detected low.
AT91C_RSTC_RSTTYP_BROWNOUT EQU( 0x5 << 8 );
- ( RSTC ) Brownout Reset occured.
AT91C_RSTC_NRSTL EQU( 0x1 << 16 );
AT91C_RSTC_NRSTL EQU( 0x1 << 16 );
- ( RSTC ) NRST pin level
AT91C_RSTC_SRCMP EQU( 0x1 << 17 );
AT91C_RSTC_SRCMP EQU( 0x1 << 17 );
- ( RSTC ) Software Reset Command in Progress.
/* - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
AT91C_RSTC_URSTEN EQU( 0x1 << 0 );
AT91C_RSTC_URSTEN EQU( 0x1 << 0 );
- ( RSTC ) User Reset Enable
AT91C_RSTC_URSTIEN EQU( 0x1 << 4 );
AT91C_RSTC_URSTIEN EQU( 0x1 << 4 );
- ( RSTC ) User Reset Interrupt Enable
AT91C_RSTC_ERSTL EQU( 0xF << 8 );
AT91C_RSTC_ERSTL EQU( 0xF << 8 );
- ( RSTC ) User Reset Enable
AT91C_RSTC_BODIEN EQU( 0x1 << 16 );
AT91C_RSTC_BODIEN EQU( 0x1 << 16 );
- ( RSTC ) Brownout Detection Interrupt Enable
/* - ***************************************************************************** */
/* - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
/* - ***************************************************************************** */
/* - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
AT91C_RTTC_RTPRES EQU( 0xFFFF << 0 );
AT91C_RTTC_RTPRES EQU( 0xFFFF << 0 );
- ( RTTC ) Real - time Timer Prescaler Value
AT91C_RTTC_ALMIEN EQU( 0x1 << 16 );
AT91C_RTTC_ALMIEN EQU( 0x1 << 16 );
- ( RTTC ) Alarm Interrupt Enable
AT91C_RTTC_RTTINCIEN EQU( 0x1 << 17 );
- ( RTTC ) Real Time Timer Increment Interrupt Enable
AT91C_RTTC_RTTRST EQU( 0x1 << 18 );
AT91C_RTTC_RTTRST EQU( 0x1 << 18 );
- ( RTTC ) Real Time Timer Restart
/* - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
AT91C_RTTC_ALMV EQU( 0x0 << 0 );
AT91C_RTTC_ALMV EQU( 0x0 << 0 );
- ( RTTC ) Alarm Value
/* - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
AT91C_RTTC_CRTV EQU( 0x0 << 0 );
AT91C_RTTC_CRTV EQU( 0x0 << 0 );
- ( RTTC ) Current Real - time Value
/* - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
AT91C_RTTC_ALMS EQU( 0x1 << 0 );
AT91C_RTTC_ALMS EQU( 0x1 << 0 );
- ( RTTC ) Real - time Alarm Status
AT91C_RTTC_RTTINC EQU( 0x1 << 1 );
AT91C_RTTC_RTTINC EQU( 0x1 << 1 );
- ( RTTC ) Real - time Timer Increment
/* - ***************************************************************************** */
/* - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
/* - ***************************************************************************** */
/* - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
AT91C_PITC_PIV EQU( 0xFFFFF << 0 );
AT91C_PITC_PIV EQU( 0xFFFFF << 0 );
- ( PITC ) Periodic Interval Value
AT91C_PITC_PITEN EQU( 0x1 << 24 );
AT91C_PITC_PITEN EQU( 0x1 << 24 );
- ( PITC ) Periodic Interval Timer Enabled
AT91C_PITC_PITIEN EQU( 0x1 << 25 );
- ( PITC ) Periodic Interval Timer Interrupt Enable
/* - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
AT91C_PITC_PITS EQU( 0x1 << 0 );
AT91C_PITC_PITS EQU( 0x1 << 0 );
- ( PITC ) Periodic Interval Timer Status
/* - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
AT91C_PITC_CPIV EQU( 0xFFFFF << 0 );
AT91C_PITC_CPIV EQU( 0xFFFFF << 0 );
- ( PITC ) Current Periodic Interval Value
AT91C_PITC_PICNT EQU( 0xFFF << 20 );
AT91C_PITC_PICNT EQU( 0xFFF << 20 );
- ( PITC ) Periodic Interval Counter
/* - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
@ -3081,31 +3081,31 @@ AT91C_PDC_RXTEN EQU( 0x1 << 0 );
/* - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
/* - ***************************************************************************** */
/* - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
AT91C_WDTC_WDRSTT EQU( 0x1 << 0 );
AT91C_WDTC_WDRSTT EQU( 0x1 << 0 );
- ( WDTC ) Watchdog Restart
AT91C_WDTC_KEY EQU( 0xFF << 24 );
AT91C_WDTC_KEY EQU( 0xFF << 24 );
- ( WDTC ) Watchdog KEY Password
/* - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
AT91C_WDTC_WDV EQU( 0xFFF << 0 );
AT91C_WDTC_WDV EQU( 0xFFF << 0 );
- ( WDTC ) Watchdog Timer Restart
AT91C_WDTC_WDFIEN EQU( 0x1 << 12 );
AT91C_WDTC_WDFIEN EQU( 0x1 << 12 );
- ( WDTC ) Watchdog Fault Interrupt Enable
AT91C_WDTC_WDRSTEN EQU( 0x1 << 13 );
AT91C_WDTC_WDRSTEN EQU( 0x1 << 13 );
- ( WDTC ) Watchdog Reset Enable
AT91C_WDTC_WDRPROC EQU( 0x1 << 14 );
AT91C_WDTC_WDRPROC EQU( 0x1 << 14 );
- ( WDTC ) Watchdog Timer Restart
AT91C_WDTC_WDDIS EQU( 0x1 << 15 );
AT91C_WDTC_WDDIS EQU( 0x1 << 15 );
- ( WDTC ) Watchdog Disable
AT91C_WDTC_WDD EQU( 0xFFF << 16 );
AT91C_WDTC_WDD EQU( 0xFFF << 16 );
- ( WDTC ) Watchdog Delta Value
AT91C_WDTC_WDDBGHLT EQU( 0x1 << 28 );
AT91C_WDTC_WDDBGHLT EQU( 0x1 << 28 );
- ( WDTC ) Watchdog Debug Halt
AT91C_WDTC_WDIDLEHLT EQU( 0x1 << 29 );
- ( WDTC ) Watchdog Idle Halt
/* - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
AT91C_WDTC_WDUNF EQU( 0x1 << 0 );
AT91C_WDTC_WDUNF EQU( 0x1 << 0 );
- ( WDTC ) Watchdog Underflow
AT91C_WDTC_WDERR EQU( 0x1 << 1 );
AT91C_WDTC_WDERR EQU( 0x1 << 1 );
- ( WDTC ) Watchdog Error
/* - ***************************************************************************** */
@ -3119,214 +3119,214 @@ AT91C_PDC_RXTEN EQU( 0x1 << 0 );
/* - SOFTWARE API DEFINITION FOR Memory Controller Interface */
/* - ***************************************************************************** */
/* - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
AT91C_MC_RCB EQU( 0x1 << 0 );
AT91C_MC_RCB EQU( 0x1 << 0 );
- ( MC ) Remap Command Bit
/* - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
AT91C_MC_UNDADD EQU( 0x1 << 0 );
AT91C_MC_UNDADD EQU( 0x1 << 0 );
- ( MC ) Undefined Addess Abort Status
AT91C_MC_MISADD EQU( 0x1 << 1 );
AT91C_MC_MISADD EQU( 0x1 << 1 );
- ( MC ) Misaligned Addess Abort Status
AT91C_MC_ABTSZ EQU( 0x3 << 8 );
AT91C_MC_ABTSZ EQU( 0x3 << 8 );
- ( MC ) Abort Size Status
AT91C_MC_ABTSZ_BYTE EQU( 0x0 << 8 );
AT91C_MC_ABTSZ_BYTE EQU( 0x0 << 8 );
- ( MC ) Byte
AT91C_MC_ABTSZ_HWORD EQU( 0x1 << 8 );
AT91C_MC_ABTSZ_HWORD EQU( 0x1 << 8 );
- ( MC ) Half - word
AT91C_MC_ABTSZ_WORD EQU( 0x2 << 8 );
AT91C_MC_ABTSZ_WORD EQU( 0x2 << 8 );
- ( MC ) Word
AT91C_MC_ABTTYP EQU( 0x3 << 10 );
AT91C_MC_ABTTYP EQU( 0x3 << 10 );
- ( MC ) Abort Type Status
AT91C_MC_ABTTYP_DATAR EQU( 0x0 << 10 );
AT91C_MC_ABTTYP_DATAR EQU( 0x0 << 10 );
- ( MC ) Data Read
AT91C_MC_ABTTYP_DATAW EQU( 0x1 << 10 );
AT91C_MC_ABTTYP_DATAW EQU( 0x1 << 10 );
- ( MC ) Data Write
AT91C_MC_ABTTYP_FETCH EQU( 0x2 << 10 );
AT91C_MC_ABTTYP_FETCH EQU( 0x2 << 10 );
- ( MC ) Code Fetch
AT91C_MC_MST0 EQU( 0x1 << 16 );
AT91C_MC_MST0 EQU( 0x1 << 16 );
- ( MC ) Master 0 Abort Source
AT91C_MC_MST1 EQU( 0x1 << 17 );
AT91C_MC_MST1 EQU( 0x1 << 17 );
- ( MC ) Master 1 Abort Source
AT91C_MC_SVMST0 EQU( 0x1 << 24 );
AT91C_MC_SVMST0 EQU( 0x1 << 24 );
- ( MC ) Saved Master 0 Abort Source
AT91C_MC_SVMST1 EQU( 0x1 << 25 );
AT91C_MC_SVMST1 EQU( 0x1 << 25 );
- ( MC ) Saved Master 1 Abort Source
/* - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
AT91C_MC_FRDY EQU( 0x1 << 0 );
AT91C_MC_FRDY EQU( 0x1 << 0 );
- ( MC ) Flash Ready
AT91C_MC_LOCKE EQU( 0x1 << 2 );
AT91C_MC_LOCKE EQU( 0x1 << 2 );
- ( MC ) Lock Error
AT91C_MC_PROGE EQU( 0x1 << 3 );
AT91C_MC_PROGE EQU( 0x1 << 3 );
- ( MC ) Programming Error
AT91C_MC_NEBP EQU( 0x1 << 7 );
AT91C_MC_NEBP EQU( 0x1 << 7 );
- ( MC ) No Erase Before Programming
AT91C_MC_FWS EQU( 0x3 << 8 );
AT91C_MC_FWS EQU( 0x3 << 8 );
- ( MC ) Flash Wait State
AT91C_MC_FWS_0FWS EQU( 0x0 << 8 );
AT91C_MC_FWS_0FWS EQU( 0x0 << 8 );
- ( MC ) 1 cycle for Read, 2 for Write operations
AT91C_MC_FWS_1FWS EQU( 0x1 << 8 );
AT91C_MC_FWS_1FWS EQU( 0x1 << 8 );
- ( MC ) 2 cycles for Read, 3 for Write operations
AT91C_MC_FWS_2FWS EQU( 0x2 << 8 );
AT91C_MC_FWS_2FWS EQU( 0x2 << 8 );
- ( MC ) 3 cycles for Read, 4 for Write operations
AT91C_MC_FWS_3FWS EQU( 0x3 << 8 );
AT91C_MC_FWS_3FWS EQU( 0x3 << 8 );
- ( MC ) 4 cycles for Read, 4 for Write operations
AT91C_MC_FMCN EQU( 0xFF << 16 );
AT91C_MC_FMCN EQU( 0xFF << 16 );
- ( MC ) Flash Microsecond Cycle Number
/* - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
AT91C_MC_FCMD EQU( 0xF << 0 );
AT91C_MC_FCMD EQU( 0xF << 0 );
- ( MC ) Flash Command
AT91C_MC_FCMD_START_PROG EQU( 0x1 );
AT91C_MC_FCMD_START_PROG EQU( 0x1 );
- ( MC ) Starts the programming of th epage specified by PAGEN.
AT91C_MC_FCMD_LOCK EQU( 0x2 );
AT91C_MC_FCMD_LOCK EQU( 0x2 );
- ( MC ) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
AT91C_MC_FCMD_PROG_AND_LOCK EQU( 0x3 );
- ( MC ) The lock sequence automatically happens after the programming sequence is completed.
AT91C_MC_FCMD_UNLOCK EQU( 0x4 );
AT91C_MC_FCMD_UNLOCK EQU( 0x4 );
- ( MC ) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
AT91C_MC_FCMD_ERASE_ALL EQU( 0x8 );
AT91C_MC_FCMD_ERASE_ALL EQU( 0x8 );
- ( MC ) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
AT91C_MC_FCMD_SET_GP_NVM EQU( 0xB );
AT91C_MC_FCMD_SET_GP_NVM EQU( 0xB );
- ( MC ) Set General Purpose NVM bits.
AT91C_MC_FCMD_CLR_GP_NVM EQU( 0xD );
AT91C_MC_FCMD_CLR_GP_NVM EQU( 0xD );
- ( MC ) Clear General Purpose NVM bits.
AT91C_MC_FCMD_SET_SECURITY EQU( 0xF );
AT91C_MC_FCMD_SET_SECURITY EQU( 0xF );
- ( MC ) Set Security Bit.
AT91C_MC_PAGEN EQU( 0x3FF << 8 );
AT91C_MC_PAGEN EQU( 0x3FF << 8 );
- ( MC ) Page Number
AT91C_MC_KEY EQU( 0xFF << 24 );
AT91C_MC_KEY EQU( 0xFF << 24 );
- ( MC ) Writing Protect Key
/* - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
AT91C_MC_SECURITY EQU( 0x1 << 4 );
AT91C_MC_SECURITY EQU( 0x1 << 4 );
- ( MC ) Security Bit Status
AT91C_MC_GPNVM0 EQU( 0x1 << 8 );
AT91C_MC_GPNVM0 EQU( 0x1 << 8 );
- ( MC ) Sector 0 Lock Status
AT91C_MC_GPNVM1 EQU( 0x1 << 9 );
AT91C_MC_GPNVM1 EQU( 0x1 << 9 );
- ( MC ) Sector 1 Lock Status
AT91C_MC_GPNVM2 EQU( 0x1 << 10 );
AT91C_MC_GPNVM2 EQU( 0x1 << 10 );
- ( MC ) Sector 2 Lock Status
AT91C_MC_GPNVM3 EQU( 0x1 << 11 );
AT91C_MC_GPNVM3 EQU( 0x1 << 11 );
- ( MC ) Sector 3 Lock Status
AT91C_MC_GPNVM4 EQU( 0x1 << 12 );
AT91C_MC_GPNVM4 EQU( 0x1 << 12 );
- ( MC ) Sector 4 Lock Status
AT91C_MC_GPNVM5 EQU( 0x1 << 13 );
AT91C_MC_GPNVM5 EQU( 0x1 << 13 );
- ( MC ) Sector 5 Lock Status
AT91C_MC_GPNVM6 EQU( 0x1 << 14 );
AT91C_MC_GPNVM6 EQU( 0x1 << 14 );
- ( MC ) Sector 6 Lock Status
AT91C_MC_GPNVM7 EQU( 0x1 << 15 );
AT91C_MC_GPNVM7 EQU( 0x1 << 15 );
- ( MC ) Sector 7 Lock Status
AT91C_MC_LOCKS0 EQU( 0x1 << 16 );
AT91C_MC_LOCKS0 EQU( 0x1 << 16 );
- ( MC ) Sector 0 Lock Status
AT91C_MC_LOCKS1 EQU( 0x1 << 17 );
AT91C_MC_LOCKS1 EQU( 0x1 << 17 );
- ( MC ) Sector 1 Lock Status
AT91C_MC_LOCKS2 EQU( 0x1 << 18 );
AT91C_MC_LOCKS2 EQU( 0x1 << 18 );
- ( MC ) Sector 2 Lock Status
AT91C_MC_LOCKS3 EQU( 0x1 << 19 );
AT91C_MC_LOCKS3 EQU( 0x1 << 19 );
- ( MC ) Sector 3 Lock Status
AT91C_MC_LOCKS4 EQU( 0x1 << 20 );
AT91C_MC_LOCKS4 EQU( 0x1 << 20 );
- ( MC ) Sector 4 Lock Status
AT91C_MC_LOCKS5 EQU( 0x1 << 21 );
AT91C_MC_LOCKS5 EQU( 0x1 << 21 );
- ( MC ) Sector 5 Lock Status
AT91C_MC_LOCKS6 EQU( 0x1 << 22 );
AT91C_MC_LOCKS6 EQU( 0x1 << 22 );
- ( MC ) Sector 6 Lock Status
AT91C_MC_LOCKS7 EQU( 0x1 << 23 );
AT91C_MC_LOCKS7 EQU( 0x1 << 23 );
- ( MC ) Sector 7 Lock Status
AT91C_MC_LOCKS8 EQU( 0x1 << 24 );
AT91C_MC_LOCKS8 EQU( 0x1 << 24 );
- ( MC ) Sector 8 Lock Status
AT91C_MC_LOCKS9 EQU( 0x1 << 25 );
AT91C_MC_LOCKS9 EQU( 0x1 << 25 );
- ( MC ) Sector 9 Lock Status
AT91C_MC_LOCKS10 EQU( 0x1 << 26 );
AT91C_MC_LOCKS10 EQU( 0x1 << 26 );
- ( MC ) Sector 10 Lock Status
AT91C_MC_LOCKS11 EQU( 0x1 << 27 );
AT91C_MC_LOCKS11 EQU( 0x1 << 27 );
- ( MC ) Sector 11 Lock Status
AT91C_MC_LOCKS12 EQU( 0x1 << 28 );
AT91C_MC_LOCKS12 EQU( 0x1 << 28 );
- ( MC ) Sector 12 Lock Status
AT91C_MC_LOCKS13 EQU( 0x1 << 29 );
AT91C_MC_LOCKS13 EQU( 0x1 << 29 );
- ( MC ) Sector 13 Lock Status
AT91C_MC_LOCKS14 EQU( 0x1 << 30 );
AT91C_MC_LOCKS14 EQU( 0x1 << 30 );
- ( MC ) Sector 14 Lock Status
AT91C_MC_LOCKS15 EQU( 0x1 << 31 );
AT91C_MC_LOCKS15 EQU( 0x1 << 31 );
- ( MC ) Sector 15 Lock Status
/* - ***************************************************************************** */
/* - SOFTWARE API DEFINITION FOR Serial Parallel Interface */
/* - ***************************************************************************** */
/* - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
AT91C_SPI_SPIEN EQU( 0x1 << 0 );
AT91C_SPI_SPIEN EQU( 0x1 << 0 );
- ( SPI ) SPI Enable
AT91C_SPI_SPIDIS EQU( 0x1 << 1 );
AT91C_SPI_SPIDIS EQU( 0x1 << 1 );
- ( SPI ) SPI Disable
AT91C_SPI_SWRST EQU( 0x1 << 7 );
AT91C_SPI_SWRST EQU( 0x1 << 7 );
- ( SPI ) SPI Software reset
AT91C_SPI_LASTXFER EQU( 0x1 << 24 );
AT91C_SPI_LASTXFER EQU( 0x1 << 24 );
- ( SPI ) SPI Last Transfer
/* - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
AT91C_SPI_MSTR EQU( 0x1 << 0 );
AT91C_SPI_MSTR EQU( 0x1 << 0 );
- ( SPI ) Master / Slave Mode
AT91C_SPI_PS EQU( 0x1 << 1 );
AT91C_SPI_PS EQU( 0x1 << 1 );
- ( SPI ) Peripheral Select
AT91C_SPI_PS_FIXED EQU( 0x0 << 1 );
AT91C_SPI_PS_FIXED EQU( 0x0 << 1 );
- ( SPI ) Fixed Peripheral Select
AT91C_SPI_PS_VARIABLE EQU( 0x1 << 1 );
- ( SPI ) Variable Peripheral Select
AT91C_SPI_PCSDEC EQU( 0x1 << 2 );
AT91C_SPI_PCSDEC EQU( 0x1 << 2 );
- ( SPI ) Chip Select Decode
AT91C_SPI_FDIV EQU( 0x1 << 3 );
AT91C_SPI_FDIV EQU( 0x1 << 3 );
- ( SPI ) Clock Selection
AT91C_SPI_MODFDIS EQU( 0x1 << 4 );
AT91C_SPI_MODFDIS EQU( 0x1 << 4 );
- ( SPI ) Mode Fault Detection
AT91C_SPI_LLB EQU( 0x1 << 7 );
AT91C_SPI_LLB EQU( 0x1 << 7 );
- ( SPI ) Clock Selection
AT91C_SPI_PCS EQU( 0xF << 16 );
AT91C_SPI_PCS EQU( 0xF << 16 );
- ( SPI ) Peripheral Chip Select
AT91C_SPI_DLYBCS EQU( 0xFF << 24 );
AT91C_SPI_DLYBCS EQU( 0xFF << 24 );
- ( SPI ) Delay Between Chip Selects
/* - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
AT91C_SPI_RD EQU( 0xFFFF << 0 );
AT91C_SPI_RD EQU( 0xFFFF << 0 );
- ( SPI ) Receive Data
AT91C_SPI_RPCS EQU( 0xF << 16 );
AT91C_SPI_RPCS EQU( 0xF << 16 );
- ( SPI ) Peripheral Chip Select Status
/* - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
AT91C_SPI_TD EQU( 0xFFFF << 0 );
AT91C_SPI_TD EQU( 0xFFFF << 0 );
- ( SPI ) Transmit Data
AT91C_SPI_TPCS EQU( 0xF << 16 );
AT91C_SPI_TPCS EQU( 0xF << 16 );
- ( SPI ) Peripheral Chip Select Status
/* - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
AT91C_SPI_RDRF EQU( 0x1 << 0 );
AT91C_SPI_RDRF EQU( 0x1 << 0 );
- ( SPI ) Receive Data Register Full
AT91C_SPI_TDRE EQU( 0x1 << 1 );
AT91C_SPI_TDRE EQU( 0x1 << 1 );
- ( SPI ) Transmit Data Register Empty
AT91C_SPI_MODF EQU( 0x1 << 2 );
AT91C_SPI_MODF EQU( 0x1 << 2 );
- ( SPI ) Mode Fault Error
AT91C_SPI_OVRES EQU( 0x1 << 3 );
AT91C_SPI_OVRES EQU( 0x1 << 3 );
- ( SPI ) Overrun Error Status
AT91C_SPI_ENDRX EQU( 0x1 << 4 );
AT91C_SPI_ENDRX EQU( 0x1 << 4 );
- ( SPI ) End of Receiver Transfer
AT91C_SPI_ENDTX EQU( 0x1 << 5 );
AT91C_SPI_ENDTX EQU( 0x1 << 5 );
- ( SPI ) End of Receiver Transfer
AT91C_SPI_RXBUFF EQU( 0x1 << 6 );
AT91C_SPI_RXBUFF EQU( 0x1 << 6 );
- ( SPI ) RXBUFF Interrupt
AT91C_SPI_TXBUFE EQU( 0x1 << 7 );
AT91C_SPI_TXBUFE EQU( 0x1 << 7 );
- ( SPI ) TXBUFE Interrupt
AT91C_SPI_NSSR EQU( 0x1 << 8 );
AT91C_SPI_NSSR EQU( 0x1 << 8 );
- ( SPI ) NSSR Interrupt
AT91C_SPI_TXEMPTY EQU( 0x1 << 9 );
AT91C_SPI_TXEMPTY EQU( 0x1 << 9 );
- ( SPI ) TXEMPTY Interrupt
AT91C_SPI_SPIENS EQU( 0x1 << 16 );
AT91C_SPI_SPIENS EQU( 0x1 << 16 );
- ( SPI ) Enable Status
/* - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
/* - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
/* - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
/* - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
AT91C_SPI_CPOL EQU( 0x1 << 0 );
AT91C_SPI_CPOL EQU( 0x1 << 0 );
- ( SPI ) Clock Polarity
AT91C_SPI_NCPHA EQU( 0x1 << 1 );
AT91C_SPI_NCPHA EQU( 0x1 << 1 );
- ( SPI ) Clock Phase
AT91C_SPI_CSAAT EQU( 0x1 << 3 );
AT91C_SPI_CSAAT EQU( 0x1 << 3 );
- ( SPI ) Chip Select Active After Transfer
AT91C_SPI_BITS EQU( 0xF << 4 );
AT91C_SPI_BITS EQU( 0xF << 4 );
- ( SPI ) Bits Per Transfer
AT91C_SPI_BITS_8 EQU( 0x0 << 4 );
AT91C_SPI_BITS_8 EQU( 0x0 << 4 );
- ( SPI ) 8 Bits Per transfer
AT91C_SPI_BITS_9 EQU( 0x1 << 4 );
AT91C_SPI_BITS_9 EQU( 0x1 << 4 );
- ( SPI ) 9 Bits Per transfer
AT91C_SPI_BITS_10 EQU( 0x2 << 4 );
- ( SPI ) 10 Bits Per transfer
@ -3342,59 +3342,59 @@ AT91C_PDC_RXTEN EQU( 0x1 << 0 );
- ( SPI ) 15 Bits Per transfer
AT91C_SPI_BITS_16 EQU( 0x8 << 4 );
- ( SPI ) 16 Bits Per transfer
AT91C_SPI_SCBR EQU( 0xFF << 8 );
AT91C_SPI_SCBR EQU( 0xFF << 8 );
- ( SPI ) Serial Clock Baud Rate
AT91C_SPI_DLYBS EQU( 0xFF << 16 );
AT91C_SPI_DLYBS EQU( 0xFF << 16 );
- ( SPI ) Delay Before SPCK
AT91C_SPI_DLYBCT EQU( 0xFF << 24 );
AT91C_SPI_DLYBCT EQU( 0xFF << 24 );
- ( SPI ) Delay Between Consecutive Transfers
/* - ***************************************************************************** */
/* - SOFTWARE API DEFINITION FOR Usart */
/* - ***************************************************************************** */
/* - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
AT91C_US_STTBRK EQU( 0x1 << 9 );
AT91C_US_STTBRK EQU( 0x1 << 9 );
- ( USART ) Start Break
AT91C_US_STPBRK EQU( 0x1 << 10 );
AT91C_US_STPBRK EQU( 0x1 << 10 );
- ( USART ) Stop Break
AT91C_US_STTTO EQU( 0x1 << 11 );
AT91C_US_STTTO EQU( 0x1 << 11 );
- ( USART ) Start Time - out
AT91C_US_SENDA EQU( 0x1 << 12 );
AT91C_US_SENDA EQU( 0x1 << 12 );
- ( USART ) Send Address
AT91C_US_RSTIT EQU( 0x1 << 13 );
AT91C_US_RSTIT EQU( 0x1 << 13 );
- ( USART ) Reset Iterations
AT91C_US_RSTNACK EQU( 0x1 << 14 );
AT91C_US_RSTNACK EQU( 0x1 << 14 );
- ( USART ) Reset Non Acknowledge
AT91C_US_RETTO EQU( 0x1 << 15 );
AT91C_US_RETTO EQU( 0x1 << 15 );
- ( USART ) Rearm Time - out
AT91C_US_DTREN EQU( 0x1 << 16 );
AT91C_US_DTREN EQU( 0x1 << 16 );
- ( USART ) Data Terminal ready Enable
AT91C_US_DTRDIS EQU( 0x1 << 17 );
AT91C_US_DTRDIS EQU( 0x1 << 17 );
- ( USART ) Data Terminal ready Disable
AT91C_US_RTSEN EQU( 0x1 << 18 );
AT91C_US_RTSEN EQU( 0x1 << 18 );
- ( USART ) Request to Send enable
AT91C_US_RTSDIS EQU( 0x1 << 19 );
AT91C_US_RTSDIS EQU( 0x1 << 19 );
- ( USART ) Request to Send Disable
/* - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
AT91C_US_USMODE EQU( 0xF << 0 );
AT91C_US_USMODE EQU( 0xF << 0 );
- ( USART ) Usart mode
AT91C_US_USMODE_NORMAL EQU( 0x0 );
AT91C_US_USMODE_NORMAL EQU( 0x0 );
- ( USART ) Normal
AT91C_US_USMODE_RS485 EQU( 0x1 );
AT91C_US_USMODE_RS485 EQU( 0x1 );
- ( USART ) RS485
AT91C_US_USMODE_HWHSH EQU( 0x2 );
AT91C_US_USMODE_HWHSH EQU( 0x2 );
- ( USART ) Hardware Handshaking
AT91C_US_USMODE_MODEM EQU( 0x3 );
AT91C_US_USMODE_MODEM EQU( 0x3 );
- ( USART ) Modem
AT91C_US_USMODE_ISO7816_0 EQU( 0x4 );
- ( USART ) ISO7816 protocol: T = 0
AT91C_US_USMODE_ISO7816_1 EQU( 0x6 );
- ( USART ) ISO7816 protocol: T = 1
AT91C_US_USMODE_IRDA EQU( 0x8 );
AT91C_US_USMODE_IRDA EQU( 0x8 );
- ( USART ) IrDA
AT91C_US_USMODE_SWHSH EQU( 0xC );
- ( USART ) Software Handshaking
AT91C_US_CLKS EQU( 0x3 << 4 );
AT91C_US_CLKS EQU( 0x3 << 4 );
- ( USART ) Clock Selection ( Baud Rate generator Input Clock
AT91C_US_CLKS_CLOCK EQU( 0x0 << 4 );
-( USART ) Clock

50
portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
View file

@ -61,17 +61,17 @@ __inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /*
unsigned int oldHandler;
unsigned int mask;
oldHandler = pAic->AIC_SVR[ irq_id ];
oldHandler = pAic->AIC_SVR[ irq_id ];
mask = 0x1 << irq_id;
mask = 0x1 << irq_id;
/** Disable the interrupt on the interrupt controller */
pAic->AIC_IDCR = mask;
pAic->AIC_IDCR = mask;
/** Save the interrupt handler routine pointer and the interrupt priority */
pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler;
/** Store the Source Mode Register */
pAic->AIC_SMR[ irq_id ] = src_type | priority;
/** Clear the interrupt on the interrupt controller */
pAic->AIC_ICCR = mask;
pAic->AIC_ICCR = mask;
return oldHandler;
}
@ -1123,8 +1123,8 @@ __inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg
return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler;
case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */
reg = pCKGR->CKGR_PLLR;
pllDivider = ( reg & AT91C_CKGR_DIV );
reg = pCKGR->CKGR_PLLR;
pllDivider = ( reg & AT91C_CKGR_DIV );
pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1;
return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler;
}
@ -1141,7 +1141,7 @@ __inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC cont
unsigned int mode )
{
pPMC->PMC_PCKR[ pck ] = mode;
pPMC->PMC_SCER = ( 1 << pck ) << 8;
pPMC->PMC_SCER = ( 1 << pck ) << 8;
}
/**---------------------------------------------------------------------------- */
@ -1399,7 +1399,7 @@ __inline void AT91F_PITInit( AT91PS_PITC pPITC,
unsigned int period,
unsigned int pit_frequency )
{
pPITC->PITC_PIMR = period ? ( period * pit_frequency + 8 ) >> 4 : 0; /* +8 to avoid %10 and /10 */
pPITC->PITC_PIMR = period ? ( period * pit_frequency + 8 ) >> 4 : 0; /* +8 to avoid %10 and /10 */
pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
}
@ -1768,16 +1768,16 @@ __inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI contro
pSPI->SPI_CSR[ 3 ] = 0;
/** Reset the SPI mode */
pSPI->SPI_MR = 0;
pSPI->SPI_MR = 0;
/** Disable all interrupts */
pSPI->SPI_IDR = 0xFFFFFFFF;
pSPI->SPI_IDR = 0xFFFFFFFF;
/** Abort the Peripheral Data Transfers */
AT91F_PDC_Close( ( AT91PS_PDC ) &( pSPI->SPI_RPR ) );
/** Disable receiver and transmitter and stop any activity immediately */
pSPI->SPI_CR = AT91C_SPI_SPIDIS;
pSPI->SPI_CR = AT91C_SPI_SPIDIS;
}
/**---------------------------------------------------------------------------- */
@ -1790,7 +1790,7 @@ __inline void AT91F_SPI_PutChar( AT91PS_SPI pSPI,
{
unsigned int value_for_cs;
value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; /*Place a zero among a 4 ONEs number */
value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; /*Place a zero among a 4 ONEs number */
pSPI->SPI_TDR = ( character & 0xFFFF ) | ( value_for_cs << 16 );
}
@ -1955,7 +1955,7 @@ __inline void AT91F_US_Configure( AT91PS_USART pUSART, /* \arg pointer to a
pUSART->US_IDR = ( unsigned int ) -1;
/** Reset receiver and transmitter */
pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
/** Define the baud rate divisor register */
AT91F_US_SetBaudrate( pUSART, mainClock, baudRate );
@ -1967,7 +1967,7 @@ __inline void AT91F_US_Configure( AT91PS_USART pUSART, /* \arg pointer to a
AT91F_PDC_Open( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
/** Define the USART mode */
pUSART->US_MR = mode;
pUSART->US_MR = mode;
}
/**---------------------------------------------------------------------------- */
@ -2044,19 +2044,19 @@ __inline void AT91F_US_Close( AT91PS_USART pUSART ) /* \arg pointer to a USART c
pUSART->US_BRGR = 0;
/** Reset the USART mode */
pUSART->US_MR = 0;
pUSART->US_MR = 0;
/** Reset the Timeguard Register */
pUSART->US_TTGR = 0;
/** Disable all interrupts */
pUSART->US_IDR = 0xFFFFFFFF;
pUSART->US_IDR = 0xFFFFFFFF;
/** Abort the Peripheral Data Transfers */
AT91F_PDC_Close( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
/** Disable receiver and transmitter and stop any activity immediately */
pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX;
pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX;
}
/**---------------------------------------------------------------------------- */
@ -2230,10 +2230,10 @@ __inline void AT91F_SSC_Configure( AT91PS_SSC pSSC, /* \arg pointer to a
unsigned int mode_tx ) /* \arg mode Register to be programmed */
{
/** Disable interrupts */
pSSC->SSC_IDR = ( unsigned int ) -1;
pSSC->SSC_IDR = ( unsigned int ) -1;
/** Reset receiver and transmitter */
pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS;
pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS;
/** Define the Clock Mode Register */
AT91F_SSC_SetBaudrate( pSSC, syst_clock, baud_rate );
@ -2407,10 +2407,10 @@ __inline void AT91F_TWI_Configure( AT91PS_TWI pTWI ) /* \arg pointer to a TWI co
pTWI->TWI_IDR = ( unsigned int ) -1;
/** Reset peripheral */
pTWI->TWI_CR = AT91C_TWI_SWRST;
pTWI->TWI_CR = AT91C_TWI_SWRST;
/** Set Master mode */
pTWI->TWI_CR = AT91C_TWI_MSEN;
pTWI->TWI_CR = AT91C_TWI_MSEN;
}
/**---------------------------------------------------------------------------- */
@ -2506,7 +2506,7 @@ __inline void AT91F_PWMC_CfgChannel( AT91PS_PWMC pPWM, /* \arg pointer to
unsigned int period, /* \arg PWM period */
unsigned int duty ) /* \arg PWM duty cycle */
{
pPWM->PWMC_CH[ channelId ].PWMC_CMR = mode;
pPWM->PWMC_CH[ channelId ].PWMC_CMR = mode;
pPWM->PWMC_CH[ channelId ].PWMC_CDTYR = duty;
pPWM->PWMC_CH[ channelId ].PWMC_CPRDR = period;
}
@ -3210,9 +3210,9 @@ __inline void AT91F_ADC_CfgTimings( AT91PS_ADC pADC, /* point
{
unsigned int prescal, startup, shtim;
prescal = mck_clock / ( 2 * adc_clock ) - 1;
startup = adc_clock * startup_time / 8 - 1;
shtim = adc_clock * sample_and_hold_time / 1000 - 1;
prescal = mck_clock / ( 2 * adc_clock ) - 1;
startup = adc_clock * startup_time / 8 - 1;
shtim = adc_clock * sample_and_hold_time / 1000 - 1;
/** Write to the MR register */
pADC->ADC_MR = ( ( prescal << 8 ) & AT91C_ADC_PRESCAL ) | ( ( startup << 16 ) & AT91C_ADC_STARTUP ) | ( ( shtim << 24 ) & AT91C_ADC_SHTIM );

3
portable/GCC/ARM7_AT91SAM7S/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -198,7 +199,7 @@ static void prvSetupTimerInterrupt( void )
#endif
/* Configure the PIT period. */
pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
/* Enable the interrupt. Global interrupts are disables at this point so
* this is safe. */

3
portable/GCC/ARM7_AT91SAM7S/portISR.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -118,7 +119,7 @@ void vPortYieldProcessor( void )
xTaskIncrementTick();
/* Clear the PIT interrupt. */
ulDummy = AT91C_BASE_PITC->PITC_PIVR;
ulDummy = AT91C_BASE_PITC->PITC_PIVR;
/* End the interrupt in the AIC. */
AT91C_BASE_AIC->AIC_EOICR = ulDummy;

5
portable/GCC/ARM7_AT91SAM7S/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
@ -106,7 +107,7 @@
#define portRESTORE_CONTEXT() \
{ \
extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Set the LR to the task stack. */ \
__asm volatile ( \
@ -143,7 +144,7 @@
#define portSAVE_CONTEXT() \
{ \
extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Push R0 as we are going to use the register. */ \
__asm volatile ( \

17
portable/GCC/ARM7_LPC2000/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -186,7 +187,7 @@ static void prvSetupTimerInterrupt( void )
/* A 1ms tick does not require the use of the timer prescale. This is
* defaulted to zero but can be used if necessary. */
T0_PR = portPRESCALE_VALUE;
T0_PR = portPRESCALE_VALUE;
/* Calculate the match value required for our wanted tick rate. */
ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
@ -198,23 +199,23 @@ static void prvSetupTimerInterrupt( void )
ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
}
#endif
T0_MR0 = ulCompareMatch;
T0_MR0 = ulCompareMatch;
/* Generate tick with timer 0 compare match. */
T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
/* Setup the VIC for the timer. */
VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
/* The ISR installed depends on whether the preemptive or cooperative
* scheduler is being used. */
VICVectAddr0 = ( int32_t ) vTickISR;
VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
VICVectAddr0 = ( int32_t ) vTickISR;
VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
/* Start the timer - interrupts are disabled when this function is called
* so it is okay to do this here. */
T0_TCR = portENABLE_TIMER;
T0_TCR = portENABLE_TIMER;
}
/*-----------------------------------------------------------*/

3
portable/GCC/ARM7_LPC2000/portISR.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -128,7 +129,7 @@ void vTickISR( void )
);
/* Ready for the next interrupt. */
T0_IR = portTIMER_MATCH_ISR_BIT;
T0_IR = portTIMER_MATCH_ISR_BIT;
VICVectAddr = portCLEAR_VIC_INTERRUPT;
/* Restore the context of the new task. */

5
portable/GCC/ARM7_LPC2000/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H
@ -83,7 +84,7 @@
#define portRESTORE_CONTEXT() \
{ \
extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Set the LR to the task stack. */ \
__asm volatile ( \
@ -120,7 +121,7 @@
#define portSAVE_CONTEXT() \
{ \
extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Push R0 as we are going to use the register. */ \
__asm volatile ( \

19
portable/GCC/ARM7_LPC23xx/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -182,13 +183,13 @@ static void prvSetupTimerInterrupt( void )
{
uint32_t ulCompareMatch;
PCLKSEL0 = ( PCLKSEL0 & ( ~( 0x3 << 2 ) ) ) | ( 0x01 << 2 );
T0TCR = 2; /* Stop and reset the timer */
T0CTCR = 0; /* Timer mode */
PCLKSEL0 = ( PCLKSEL0 & ( ~( 0x3 << 2 ) ) ) | ( 0x01 << 2 );
T0TCR = 2; /* Stop and reset the timer */
T0CTCR = 0; /* Timer mode */
/* A 1ms tick does not require the use of the timer prescale. This is
* defaulted to zero but can be used if necessary. */
T0PR = portPRESCALE_VALUE;
T0PR = portPRESCALE_VALUE;
/* Calculate the match value required for our wanted tick rate. */
ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
@ -200,13 +201,13 @@ static void prvSetupTimerInterrupt( void )
ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
}
#endif
T0MR1 = ulCompareMatch;
T0MR1 = ulCompareMatch;
/* Generate tick with timer 0 compare match. */
T0MCR = ( 3 << 3 ); /* Reset timer on match and generate interrupt */
T0MCR = ( 3 << 3 ); /* Reset timer on match and generate interrupt */
/* Setup the VIC for the timer. */
VICIntEnable = 0x00000010;
VICIntEnable = 0x00000010;
/* The ISR installed depends on whether the preemptive or cooperative
* scheduler is being used. */
@ -222,10 +223,10 @@ static void prvSetupTimerInterrupt( void )
}
#endif
VICVectCntl4 = 1;
VICVectCntl4 = 1;
/* Start the timer - interrupts are disabled when this function is called
* so it is okay to do this here. */
T0TCR = portENABLE_TIMER;
T0TCR = portENABLE_TIMER;
}
/*-----------------------------------------------------------*/

5
portable/GCC/ARM7_LPC23xx/portISR.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -103,7 +104,7 @@ void vPortYieldProcessor( void )
void vNonPreemptiveTick( void )
{
xTaskIncrementTick();
T0IR = 2;
T0IR = 2;
VICVectAddr = portCLEAR_VIC_INTERRUPT;
}
@ -129,7 +130,7 @@ void vPortYieldProcessor( void )
);
/* Ready for the next interrupt. */
T0IR = 2;
T0IR = 2;
VICVectAddr = portCLEAR_VIC_INTERRUPT;
/* Restore the context of the new task. */

5
portable/GCC/ARM7_LPC23xx/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
@ -106,7 +107,7 @@
#define portRESTORE_CONTEXT() \
{ \
extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Set the LR to the task stack. */ \
__asm volatile ( \
@ -143,7 +144,7 @@
#define portSAVE_CONTEXT() \
{ \
extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Push R0 as we are going to use the register. */ \
__asm volatile ( \

25
portable/GCC/ARM_CA53_64_BIT/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */
@ -146,23 +147,23 @@ extern void vPortRestoreTaskContext( void );
* a non zero value to ensure interrupts don't inadvertently become unmasked before
* the scheduler starts. As it is stored as part of the task context it will
* automatically be set to 0 when the first task is started. */
volatile uint64_t ullCriticalNesting = 9999ULL;
volatile uint64_t ullCriticalNesting = 9999ULL;
/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
* then floating point context must be saved and restored for the task. */
uint64_t ullPortTaskHasFPUContext = pdFALSE;
uint64_t ullPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
uint64_t ullPortYieldRequired = pdFALSE;
uint64_t ullPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
* if the nesting depth is 0. */
uint64_t ullPortInterruptNesting = 0;
uint64_t ullPortInterruptNesting = 0;
/* Used in the ASM code. */
__attribute__( ( used ) ) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
/*-----------------------------------------------------------*/
@ -270,21 +271,21 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
volatile uint8_t ucMaxPriorityValue;
volatile uint8_t ucMaxPriorityValue;
/* Determine how many priority bits are implemented in the GIC.
*
* Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
ulOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to
* all possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
/* Shift to the least significant bits. */
while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
@ -473,7 +474,7 @@ UBaseType_t uxPortSetInterruptMask( void )
}
else
{
ulReturn = pdFALSE;
ulReturn = pdFALSE;
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__asm volatile ( "dsb sy \n"
"isb sy \n"::: "memory" );

3
portable/GCC/ARM_CA53_64_BIT/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H
@ -152,7 +153,7 @@
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

27
portable/GCC/ARM_CA9/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */
@ -191,23 +192,23 @@ void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__( ( weak )
* a non zero value to ensure interrupts don't inadvertently become unmasked before
* the scheduler starts. As it is stored as part of the task context it will
* automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
* a floating point context must be saved and restored for the task. */
volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
volatile uint32_t ulPortYieldRequired = pdFALSE;
volatile uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
* if the nesting depth is 0. */
volatile uint32_t ulPortInterruptNesting = 0UL;
volatile uint32_t ulPortInterruptNesting = 0UL;
/* Used in the asm file. */
__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
/*-----------------------------------------------------------*/
@ -291,11 +292,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
{
/* The task will start with a floating point context. Leave enough
* space for the registers - and ensure they are initialised to 0. */
pxTopOfStack -= portFPU_REGISTER_WORDS;
pxTopOfStack -= portFPU_REGISTER_WORDS;
memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
pxTopOfStack--;
*pxTopOfStack = pdTRUE;
*pxTopOfStack = pdTRUE;
ulPortTaskHasFPUContext = pdTRUE;
}
#else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
@ -331,21 +332,21 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
volatile uint8_t ucMaxPriorityValue;
volatile uint8_t ucMaxPriorityValue;
/* Determine how many priority bits are implemented in the GIC.
*
* Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
ulOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to
* all possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
/* Shift to the least significant bits. */
while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
@ -519,7 +520,7 @@ uint32_t ulPortSetInterruptMask( void )
}
else
{
ulReturn = pdFALSE;
ulReturn = pdFALSE;
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__asm volatile ( "dsb \n"
"isb \n"::: "memory" );

3
portable/GCC/ARM_CA9/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H
@ -149,7 +150,7 @@
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

47
portable/GCC/ARM_CM0/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -97,7 +98,7 @@ static void prvTaskExitError( void );
/* Each task maintains its own interrupt status in the critical nesting
* variable. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
/*-----------------------------------------------------------*/
@ -105,7 +106,7 @@ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
* The number of SysTick increments that make up one tick period.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t ulTimerCountsForOneTick = 0;
static uint32_t ulTimerCountsForOneTick = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
@ -121,7 +122,7 @@ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
* power functionality only.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t ulStoppedTimerCompensation = 0;
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@ -224,7 +225,7 @@ BaseType_t xPortStartScheduler( void )
vPortSetupTimerInterrupt();
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
uxCriticalNesting = 0;
/* Start the first task. */
vPortStartFirstTask();
@ -380,19 +381,19 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
{
ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@ -400,7 +401,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@ -418,7 +419,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
/* Calculate the reload value required to wait xExpectedIdleTime
* tick periods. -1 is used because this code will execute part way
* through one of the tick periods. */
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
@ -437,14 +438,14 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
{
/* Restart from whatever is left in the count register to complete
* this tick period. */
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
* periods. */
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Re-enable interrupts - see comments above the cpsid instruction()
* above. */
@ -453,21 +454,21 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
else
{
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
/* Clear the SysTick count flag and set the count value back to
* zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
* set its parameter to 0 to indicate that its implementation contains
* its own wait for interrupt or wait for event instruction, and so wfi
* should not be executed again. However, the original expected idle
* time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
@ -501,7 +502,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
/* Determine if the SysTick clock has already counted to zero and
* been set back to the current reload value (the reload back being
@ -516,7 +517,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
* reloaded with ulReloadValue. Reset the
* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
* period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
@ -531,7 +532,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
/* As the pending tick will be processed as soon as this
* function exits, the tick value maintained by the tick is stepped
* forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
@ -543,20 +544,20 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
/* How many complete tick periods passed while the processor
* was waiting? */
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
/* The reload value is set to whatever fraction of a single tick
* period remains. */
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
* value. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
vTaskStepTick( ulCompleteTickPeriods );
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrpts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );

1
portable/GCC/ARM_CM0/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/

215
portable/GCC/ARM_CM23/non_secure/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
@ -349,7 +350,7 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @brief Each task maintains its own interrupt status in the critical nesting
* variable.
*/
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
#if ( configENABLE_TRUSTZONE == 1 )
@ -365,26 +366,26 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/**
* @brief The number of SysTick increments that make up one tick period.
*/
static uint32_t ulTimerCountsForOneTick = 0;
static uint32_t ulTimerCountsForOneTick = 0;
/**
* @brief The maximum number of tick periods that can be suppressed is
* limited by the 24 bit resolution of the SysTick timer.
*/
static uint32_t xMaximumPossibleSuppressedTicks = 0;
static uint32_t xMaximumPossibleSuppressedTicks = 0;
/**
* @brief Compensate for the CPU cycles that pass while the SysTick is
* stopped (low power functionality only).
*/
static uint32_t ulStoppedTimerCompensation = 0;
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@ -402,7 +403,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* Calculate the reload value required to wait xExpectedIdleTime
* tick periods. -1 is used because this code will execute part way
* through one of the tick periods. */
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
@ -421,14 +422,14 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
{
/* Restart from whatever is left in the count register to complete
* this tick period. */
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
* periods. */
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Re-enable interrupts - see comments above the cpsid instruction()
* above. */
@ -437,14 +438,14 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
else
{
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
/* Clear the SysTick count flag and set the count value back to
* zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
* set its parameter to 0 to indicate that its implementation
@ -452,7 +453,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* instruction, and so wfi should not be executed again. However,
* the original expected idle time variable must remain unmodified,
* so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
@ -486,7 +487,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* best it can be, but using the tickless mode will inevitably
* result in some tiny drift of the time maintained by the kernel
* with respect to calendar time*/
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
/* Determine if the SysTick clock has already counted to zero and
* been set back to the current reload value (the reload back being
@ -501,7 +502,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* reloaded with ulReloadValue. Reset the
* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
* period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
@ -516,7 +517,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* As the pending tick will be processed as soon as this
* function exits, the tick value maintained by the tick is
* stepped forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
@ -528,20 +529,20 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* How many complete tick periods passed while the processor
* was waiting? */
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
/* The reload value is set to whatever fraction of a single tick
* period remains. */
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
* value. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
vTaskStepTick( ulCompleteTickPeriods );
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@ -555,19 +556,19 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
{
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@ -611,72 +612,72 @@ static void prvTaskExitError( void )
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
#else /* if defined( __ARMCC_VERSION ) */
#else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __unprivileged_flash_start__[];
extern uint32_t __unprivileged_flash_end__[];
extern uint32_t __privileged_sram_start__[];
extern uint32_t __privileged_sram_end__[];
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __unprivileged_flash_start__[];
extern uint32_t __unprivileged_flash_end__[];
extern uint32_t __privileged_sram_start__[];
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
/* Setup privileged flash as Read Only so that privileged tasks can
* read it but not modify. */
portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup unprivileged flash as Read Only by both privileged and
* unprivileged tasks. All tasks can read it but no-one can modify. */
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup unprivileged syscalls flash as Read Only by both privileged
* and unprivileged tasks. All tasks can read it but no-one can modify. */
portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup RAM containing kernel data for privileged access only. */
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Enable mem fault. */
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
/* Enable MPU with privileged background access i.e. unmapped
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
@ -771,24 +772,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
extern uint32_t * __syscalls_flash_end__;
#else
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
#endif /* defined( __ARMCC_VERSION ) */
#endif /* configENABLE_MPU */
uint32_t ulPC;
uint32_t ulPC;
#if ( configENABLE_TRUSTZONE == 1 )
uint32_t ulR0;
uint32_t ulR0;
#if ( configENABLE_MPU == 1 )
uint32_t ulControl, ulIsTaskPrivileged;
uint32_t ulControl, ulIsTaskPrivileged;
#endif /* configENABLE_MPU */
#endif /* configENABLE_TRUSTZONE */
uint8_t ucSVCNumber;
/* Register are stored on the stack in the following order - R0, R1, R2, R3,
* R12, LR, PC, xPSR. */
ulPC = pulCallerStackAddress[ 6 ];
ulPC = pulCallerStackAddress[ 6 ];
ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
switch( ucSVCNumber )
@ -801,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
{
/* Read the CONTROL register value. */
__asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
{
/* Read the CONTROL register value. */
__asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
/* The task that raised the SVC is privileged if Bit[0]
* in the CONTROL register is 0. */
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
/* The task that raised the SVC is privileged if Bit[0]
* in the CONTROL register is 0. */
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
}
#else /* if ( configENABLE_MPU == 1 ) */
{
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0 );
}
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
}
#else /* if ( configENABLE_MPU == 1 ) */
{
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0 );
}
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@ -834,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
{
/* De-prioritize the non-secure exceptions so that the
* non-secure pendSV runs at the lowest priority. */
SecureInit_DePrioritizeNSExceptions();
{
/* De-prioritize the non-secure exceptions so that the
* non-secure pendSV runs at the lowest priority. */
SecureInit_DePrioritizeNSExceptions();
/* Initialize the secure context management system. */
SecureContext_Init();
}
/* Initialize the secure context management system. */
SecureContext_Init();
}
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
{
/* Setup the Floating Point Unit (FPU). */
prvSetupFPU();
}
{
/* Setup the Floating Point Unit (FPU). */
prvSetupFPU();
}
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@ -881,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters ) /* PRIVILEGED_FUNCTION */
void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
{
/* Simulate the stack frame as it would be created by a context switch
@ -1015,7 +1016,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
vPortSetupTimerInterrupt();
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
ulCriticalNesting = 0;
/* Start the first task. */
vStartFirstTask();
@ -1049,10 +1050,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
uint32_t ulStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
int32_t lIndex = 0;
/* Setup MAIR0. */
xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
/* This function is called automatically when the task is created - in
@ -1062,9 +1063,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
if( ulStackDepth > 0 )
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
@ -1087,9 +1088,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
/* Translate the generic region definition contained in xRegions
* into the ARMv8 specific MPU settings that are then stored in
* xMPUSettings. */
ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
/* Start address. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
@ -1142,7 +1143,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. Interrupt Program

1
portable/GCC/ARM_CM23/non_secure/portasm.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */

1
portable/GCC/ARM_CM23/non_secure/portasm.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __PORT_ASM_H__

1
portable/GCC/ARM_CM23/non_secure/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H

11
portable/GCC/ARM_CM23/secure/secure_context.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Secure context includes. */
@ -101,12 +102,12 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
#endif /* configENABLE_MPU */
{
uint8_t * pucStackMemory = NULL;
uint32_t ulIPSR;
SecureContextHandle_t xSecureContextHandle = NULL;
uint8_t * pucStackMemory = NULL;
uint32_t ulIPSR;
SecureContextHandle_t xSecureContextHandle = NULL;
#if ( configENABLE_MPU == 1 )
uint32_t * pulCurrentStackPointer = NULL;
uint32_t * pulCurrentStackPointer = NULL;
#endif /* configENABLE_MPU */
/* Read the Interrupt Program Status Register (IPSR) value. */
@ -143,7 +144,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
/* Store the correct CONTROL value for the task on the stack.
* This value is programmed in the CONTROL register on
* context switch. */
pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
pulCurrentStackPointer--;
if( ulIsTaskPrivileged )

1
portable/GCC/ARM_CM23/secure/secure_context.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __SECURE_CONTEXT_H__

1
portable/GCC/ARM_CM23/secure/secure_context_port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Secure context includes. */

73
portable/GCC/ARM_CM23/secure/secure_heap.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */
@ -115,7 +116,7 @@ static BlockLink_t xStart, * pxEnd = NULL;
* @brief Keeps track of the number of free bytes remaining, but says nothing
* about fragmentation.
*/
static size_t xFreeBytesRemaining = 0U;
static size_t xFreeBytesRemaining = 0U;
static size_t xMinimumEverFreeBytesRemaining = 0U;
/**
@ -125,61 +126,61 @@ static size_t xMinimumEverFreeBytesRemaining = 0U;
* then the block belongs to the application. When the bit is free the block is
* still part of the free heap space.
*/
static size_t xBlockAllocatedBit = 0;
static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
{
BlockLink_t * pxFirstFreeBlock;
uint8_t * pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
uint8_t * pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = ( size_t ) ucHeap;
uxAddress = ( size_t ) ucHeap;
if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
{
uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
pucAlignedHeap = ( uint8_t * ) uxAddress;
/* xStart is used to hold a pointer to the first item in the list of free
* blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
xStart.xBlockSize = ( size_t ) 0;
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
xStart.xBlockSize = ( size_t ) 0;
/* pxEnd is used to mark the end of the list of free blocks and is inserted
* at the end of the heap space. */
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
uxAddress -= xHeapStructSize;
uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
pxEnd = ( void * ) uxAddress;
pxEnd->xBlockSize = 0;
pxEnd->pxNextFreeBlock = NULL;
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
uxAddress -= xHeapStructSize;
uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
pxEnd = ( void * ) uxAddress;
pxEnd->xBlockSize = 0;
pxEnd->pxNextFreeBlock = NULL;
/* To start with there is a single free block that is sized to take up the
* entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
{
BlockLink_t * pxIterator;
uint8_t * puc;
uint8_t * puc;
/* Iterate through the list until a block is found that has a higher address
* than the block being inserted. */
@ -195,7 +196,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
pxBlockToInsert = pxIterator;
pxBlockToInsert = pxIterator;
}
else
{
@ -211,7 +212,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
if( pxIterator->pxNextFreeBlock != pxEnd )
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
}
else
@ -242,7 +243,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
void * pvPortMalloc( size_t xWantedSize )
{
BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
void * pvReturn = NULL;
void * pvReturn = NULL;
/* If this is the first call to malloc then the heap will require
* initialisation to setup the list of free blocks. */
@ -290,12 +291,12 @@ void * pvPortMalloc( size_t xWantedSize )
/* Traverse the list from the start (lowest address) block until
* one of adequate size is found. */
pxPreviousBlock = &xStart;
pxBlock = xStart.pxNextFreeBlock;
pxBlock = xStart.pxNextFreeBlock;
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
{
pxPreviousBlock = pxBlock;
pxBlock = pxBlock->pxNextFreeBlock;
pxBlock = pxBlock->pxNextFreeBlock;
}
/* If the end marker was reached then a block of adequate size was
@ -304,7 +305,7 @@ void * pvPortMalloc( size_t xWantedSize )
{
/* Return the memory space pointed to - jumping over the
* BlockLink_t structure at its start. */
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
/* This block is being returned for use so must be taken out
* of the list of free blocks. */
@ -318,13 +319,13 @@ void * pvPortMalloc( size_t xWantedSize )
* block following the number of bytes requested. The void
* cast is used to prevent byte alignment warnings from the
* compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
/* Calculate the sizes of two blocks split from the single
* block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
pxBlock->xBlockSize = xWantedSize;
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList( pxNewBlockLink );
@ -334,7 +335,7 @@ void * pvPortMalloc( size_t xWantedSize )
mtCOVERAGE_TEST_MARKER();
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
xFreeBytesRemaining -= pxBlock->xBlockSize;
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
{
@ -347,8 +348,8 @@ void * pvPortMalloc( size_t xWantedSize )
/* The block is being returned - it is allocated and owned by
* the application and has no "next" block. */
pxBlock->xBlockSize |= xBlockAllocatedBit;
pxBlock->pxNextFreeBlock = NULL;
pxBlock->xBlockSize |= xBlockAllocatedBit;
pxBlock->pxNextFreeBlock = NULL;
}
else
{
@ -388,14 +389,14 @@ void * pvPortMalloc( size_t xWantedSize )
void vPortFree( void * pv )
{
uint8_t * puc = ( uint8_t * ) pv;
uint8_t * puc = ( uint8_t * ) pv;
BlockLink_t * pxLink;
if( pv != NULL )
{
/* The memory being freed will have an BlockLink_t structure immediately
* before it. */
puc -= xHeapStructSize;
puc -= xHeapStructSize;
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;

1
portable/GCC/ARM_CM23/secure/secure_heap.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __SECURE_HEAP_H__

1
portable/GCC/ARM_CM23/secure/secure_init.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */

1
portable/GCC/ARM_CM23/secure/secure_init.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __SECURE_INIT_H__

1
portable/GCC/ARM_CM23/secure/secure_port_macros.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __SECURE_PORT_MACROS_H__

215
portable/GCC/ARM_CM23_NTZ/non_secure/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
@ -349,7 +350,7 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @brief Each task maintains its own interrupt status in the critical nesting
* variable.
*/
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
#if ( configENABLE_TRUSTZONE == 1 )
@ -365,26 +366,26 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/**
* @brief The number of SysTick increments that make up one tick period.
*/
static uint32_t ulTimerCountsForOneTick = 0;
static uint32_t ulTimerCountsForOneTick = 0;
/**
* @brief The maximum number of tick periods that can be suppressed is
* limited by the 24 bit resolution of the SysTick timer.
*/
static uint32_t xMaximumPossibleSuppressedTicks = 0;
static uint32_t xMaximumPossibleSuppressedTicks = 0;
/**
* @brief Compensate for the CPU cycles that pass while the SysTick is
* stopped (low power functionality only).
*/
static uint32_t ulStoppedTimerCompensation = 0;
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@ -402,7 +403,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* Calculate the reload value required to wait xExpectedIdleTime
* tick periods. -1 is used because this code will execute part way
* through one of the tick periods. */
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
@ -421,14 +422,14 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
{
/* Restart from whatever is left in the count register to complete
* this tick period. */
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
* periods. */
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Re-enable interrupts - see comments above the cpsid instruction()
* above. */
@ -437,14 +438,14 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
else
{
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
/* Clear the SysTick count flag and set the count value back to
* zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
* set its parameter to 0 to indicate that its implementation
@ -452,7 +453,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* instruction, and so wfi should not be executed again. However,
* the original expected idle time variable must remain unmodified,
* so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
@ -486,7 +487,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* best it can be, but using the tickless mode will inevitably
* result in some tiny drift of the time maintained by the kernel
* with respect to calendar time*/
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
/* Determine if the SysTick clock has already counted to zero and
* been set back to the current reload value (the reload back being
@ -501,7 +502,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* reloaded with ulReloadValue. Reset the
* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
* period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
@ -516,7 +517,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* As the pending tick will be processed as soon as this
* function exits, the tick value maintained by the tick is
* stepped forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
@ -528,20 +529,20 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* How many complete tick periods passed while the processor
* was waiting? */
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
/* The reload value is set to whatever fraction of a single tick
* period remains. */
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
* value. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
vTaskStepTick( ulCompleteTickPeriods );
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@ -555,19 +556,19 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
{
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@ -611,72 +612,72 @@ static void prvTaskExitError( void )
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
#else /* if defined( __ARMCC_VERSION ) */
#else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __unprivileged_flash_start__[];
extern uint32_t __unprivileged_flash_end__[];
extern uint32_t __privileged_sram_start__[];
extern uint32_t __privileged_sram_end__[];
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __unprivileged_flash_start__[];
extern uint32_t __unprivileged_flash_end__[];
extern uint32_t __privileged_sram_start__[];
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
/* Setup privileged flash as Read Only so that privileged tasks can
* read it but not modify. */
portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup unprivileged flash as Read Only by both privileged and
* unprivileged tasks. All tasks can read it but no-one can modify. */
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup unprivileged syscalls flash as Read Only by both privileged
* and unprivileged tasks. All tasks can read it but no-one can modify. */
portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup RAM containing kernel data for privileged access only. */
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Enable mem fault. */
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
/* Enable MPU with privileged background access i.e. unmapped
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
@ -771,24 +772,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
extern uint32_t * __syscalls_flash_end__;
#else
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
#endif /* defined( __ARMCC_VERSION ) */
#endif /* configENABLE_MPU */
uint32_t ulPC;
uint32_t ulPC;
#if ( configENABLE_TRUSTZONE == 1 )
uint32_t ulR0;
uint32_t ulR0;
#if ( configENABLE_MPU == 1 )
uint32_t ulControl, ulIsTaskPrivileged;
uint32_t ulControl, ulIsTaskPrivileged;
#endif /* configENABLE_MPU */
#endif /* configENABLE_TRUSTZONE */
uint8_t ucSVCNumber;
/* Register are stored on the stack in the following order - R0, R1, R2, R3,
* R12, LR, PC, xPSR. */
ulPC = pulCallerStackAddress[ 6 ];
ulPC = pulCallerStackAddress[ 6 ];
ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
switch( ucSVCNumber )
@ -801,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
{
/* Read the CONTROL register value. */
__asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
{
/* Read the CONTROL register value. */
__asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
/* The task that raised the SVC is privileged if Bit[0]
* in the CONTROL register is 0. */
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
/* The task that raised the SVC is privileged if Bit[0]
* in the CONTROL register is 0. */
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
}
#else /* if ( configENABLE_MPU == 1 ) */
{
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0 );
}
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
}
#else /* if ( configENABLE_MPU == 1 ) */
{
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0 );
}
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@ -834,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
{
/* De-prioritize the non-secure exceptions so that the
* non-secure pendSV runs at the lowest priority. */
SecureInit_DePrioritizeNSExceptions();
{
/* De-prioritize the non-secure exceptions so that the
* non-secure pendSV runs at the lowest priority. */
SecureInit_DePrioritizeNSExceptions();
/* Initialize the secure context management system. */
SecureContext_Init();
}
/* Initialize the secure context management system. */
SecureContext_Init();
}
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
{
/* Setup the Floating Point Unit (FPU). */
prvSetupFPU();
}
{
/* Setup the Floating Point Unit (FPU). */
prvSetupFPU();
}
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@ -881,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters ) /* PRIVILEGED_FUNCTION */
void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
{
/* Simulate the stack frame as it would be created by a context switch
@ -1015,7 +1016,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
vPortSetupTimerInterrupt();
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
ulCriticalNesting = 0;
/* Start the first task. */
vStartFirstTask();
@ -1049,10 +1050,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
uint32_t ulStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
int32_t lIndex = 0;
/* Setup MAIR0. */
xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
/* This function is called automatically when the task is created - in
@ -1062,9 +1063,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
if( ulStackDepth > 0 )
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
@ -1087,9 +1088,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
/* Translate the generic region definition contained in xRegions
* into the ARMv8 specific MPU settings that are then stored in
* xMPUSettings. */
ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
/* Start address. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
@ -1142,7 +1143,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. Interrupt Program

1
portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */

1
portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __PORT_ASM_H__

1
portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H

71
portable/GCC/ARM_CM3/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -130,13 +131,13 @@ static void prvTaskExitError( void );
/* Each task maintains its own interrupt status in the critical nesting
* variable. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
/*
* The number of SysTick increments that make up one tick period.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t ulTimerCountsForOneTick = 0;
static uint32_t ulTimerCountsForOneTick = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
@ -144,7 +145,7 @@ static UBaseType_t uxCriticalNesting = 0xaaaaa
* 24 bit resolution of the SysTick timer.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t xMaximumPossibleSuppressedTicks = 0;
static uint32_t xMaximumPossibleSuppressedTicks = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
@ -152,7 +153,7 @@ static UBaseType_t uxCriticalNesting = 0xaaaaa
* power functionality only.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t ulStoppedTimerCompensation = 0;
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
@ -161,8 +162,8 @@ static UBaseType_t uxCriticalNesting = 0xaaaaa
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
#if ( configASSERT_DEFINED == 1 )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED */
@ -266,9 +267,9 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
* functions can be called. ISR safe functions are those that end in
@ -276,21 +277,21 @@ BaseType_t xPortStartScheduler( void )
* ensure interrupt entry is as fast and simple as possible.
*
* Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
ulOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to all
* possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
@ -318,8 +319,8 @@ BaseType_t xPortStartScheduler( void )
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
/* Restore the clobbered interrupt priority register to its original
* value. */
@ -336,7 +337,7 @@ BaseType_t xPortStartScheduler( void )
vPortSetupTimerInterrupt();
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
uxCriticalNesting = 0;
/* Start the first task. */
prvPortStartFirstTask();
@ -453,7 +454,7 @@ void xPortSysTickHandler( void )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@ -471,7 +472,7 @@ void xPortSysTickHandler( void )
/* Calculate the reload value required to wait xExpectedIdleTime
* tick periods. -1 is used because this code will execute part way
* through one of the tick periods. */
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
@ -490,14 +491,14 @@ void xPortSysTickHandler( void )
{
/* Restart from whatever is left in the count register to complete
* this tick period. */
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
* periods. */
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Re-enable interrupts - see comments above the cpsid instruction()
* above. */
@ -506,21 +507,21 @@ void xPortSysTickHandler( void )
else
{
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
/* Clear the SysTick count flag and set the count value back to
* zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
* set its parameter to 0 to indicate that its implementation contains
* its own wait for interrupt or wait for event instruction, and so wfi
* should not be executed again. However, the original expected idle
* time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
@ -554,7 +555,7 @@ void xPortSysTickHandler( void )
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
/* Determine if the SysTick clock has already counted to zero and
* been set back to the current reload value (the reload back being
@ -569,7 +570,7 @@ void xPortSysTickHandler( void )
* reloaded with ulReloadValue. Reset the
* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
* period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
@ -584,7 +585,7 @@ void xPortSysTickHandler( void )
/* As the pending tick will be processed as soon as this
* function exits, the tick value maintained by the tick is stepped
* forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
@ -596,20 +597,20 @@ void xPortSysTickHandler( void )
/* How many complete tick periods passed while the processor
* was waiting? */
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
/* The reload value is set to whatever fraction of a single tick
* period remains. */
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
* value. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
vTaskStepTick( ulCompleteTickPeriods );
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@ -628,19 +629,19 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
{
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
@ -649,7 +650,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
void vPortValidateInterruptPriority( void )
{
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );

5
portable/GCC/ARM_CM3/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -147,7 +148,7 @@
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
@ -171,7 +172,7 @@
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. */

215
portable/GCC/ARM_CM33/non_secure/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
@ -349,7 +350,7 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @brief Each task maintains its own interrupt status in the critical nesting
* variable.
*/
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
#if ( configENABLE_TRUSTZONE == 1 )
@ -365,26 +366,26 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/**
* @brief The number of SysTick increments that make up one tick period.
*/
static uint32_t ulTimerCountsForOneTick = 0;
static uint32_t ulTimerCountsForOneTick = 0;
/**
* @brief The maximum number of tick periods that can be suppressed is
* limited by the 24 bit resolution of the SysTick timer.
*/
static uint32_t xMaximumPossibleSuppressedTicks = 0;
static uint32_t xMaximumPossibleSuppressedTicks = 0;
/**
* @brief Compensate for the CPU cycles that pass while the SysTick is
* stopped (low power functionality only).
*/
static uint32_t ulStoppedTimerCompensation = 0;
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@ -402,7 +403,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* Calculate the reload value required to wait xExpectedIdleTime
* tick periods. -1 is used because this code will execute part way
* through one of the tick periods. */
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
@ -421,14 +422,14 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
{
/* Restart from whatever is left in the count register to complete
* this tick period. */
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
* periods. */
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Re-enable interrupts - see comments above the cpsid instruction()
* above. */
@ -437,14 +438,14 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
else
{
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
/* Clear the SysTick count flag and set the count value back to
* zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
* set its parameter to 0 to indicate that its implementation
@ -452,7 +453,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* instruction, and so wfi should not be executed again. However,
* the original expected idle time variable must remain unmodified,
* so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
@ -486,7 +487,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* best it can be, but using the tickless mode will inevitably
* result in some tiny drift of the time maintained by the kernel
* with respect to calendar time*/
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
/* Determine if the SysTick clock has already counted to zero and
* been set back to the current reload value (the reload back being
@ -501,7 +502,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* reloaded with ulReloadValue. Reset the
* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
* period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
@ -516,7 +517,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* As the pending tick will be processed as soon as this
* function exits, the tick value maintained by the tick is
* stepped forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
@ -528,20 +529,20 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* How many complete tick periods passed while the processor
* was waiting? */
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
/* The reload value is set to whatever fraction of a single tick
* period remains. */
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
* value. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
vTaskStepTick( ulCompleteTickPeriods );
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@ -555,19 +556,19 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
{
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@ -611,72 +612,72 @@ static void prvTaskExitError( void )
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
#else /* if defined( __ARMCC_VERSION ) */
#else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __unprivileged_flash_start__[];
extern uint32_t __unprivileged_flash_end__[];
extern uint32_t __privileged_sram_start__[];
extern uint32_t __privileged_sram_end__[];
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __unprivileged_flash_start__[];
extern uint32_t __unprivileged_flash_end__[];
extern uint32_t __privileged_sram_start__[];
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
/* Setup privileged flash as Read Only so that privileged tasks can
* read it but not modify. */
portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup unprivileged flash as Read Only by both privileged and
* unprivileged tasks. All tasks can read it but no-one can modify. */
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup unprivileged syscalls flash as Read Only by both privileged
* and unprivileged tasks. All tasks can read it but no-one can modify. */
portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup RAM containing kernel data for privileged access only. */
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Enable mem fault. */
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
/* Enable MPU with privileged background access i.e. unmapped
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
@ -771,24 +772,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
extern uint32_t * __syscalls_flash_end__;
#else
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
#endif /* defined( __ARMCC_VERSION ) */
#endif /* configENABLE_MPU */
uint32_t ulPC;
uint32_t ulPC;
#if ( configENABLE_TRUSTZONE == 1 )
uint32_t ulR0;
uint32_t ulR0;
#if ( configENABLE_MPU == 1 )
uint32_t ulControl, ulIsTaskPrivileged;
uint32_t ulControl, ulIsTaskPrivileged;
#endif /* configENABLE_MPU */
#endif /* configENABLE_TRUSTZONE */
uint8_t ucSVCNumber;
/* Register are stored on the stack in the following order - R0, R1, R2, R3,
* R12, LR, PC, xPSR. */
ulPC = pulCallerStackAddress[ 6 ];
ulPC = pulCallerStackAddress[ 6 ];
ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
switch( ucSVCNumber )
@ -801,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
{
/* Read the CONTROL register value. */
__asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
{
/* Read the CONTROL register value. */
__asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
/* The task that raised the SVC is privileged if Bit[0]
* in the CONTROL register is 0. */
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
/* The task that raised the SVC is privileged if Bit[0]
* in the CONTROL register is 0. */
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
}
#else /* if ( configENABLE_MPU == 1 ) */
{
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0 );
}
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
}
#else /* if ( configENABLE_MPU == 1 ) */
{
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0 );
}
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@ -834,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
{
/* De-prioritize the non-secure exceptions so that the
* non-secure pendSV runs at the lowest priority. */
SecureInit_DePrioritizeNSExceptions();
{
/* De-prioritize the non-secure exceptions so that the
* non-secure pendSV runs at the lowest priority. */
SecureInit_DePrioritizeNSExceptions();
/* Initialize the secure context management system. */
SecureContext_Init();
}
/* Initialize the secure context management system. */
SecureContext_Init();
}
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
{
/* Setup the Floating Point Unit (FPU). */
prvSetupFPU();
}
{
/* Setup the Floating Point Unit (FPU). */
prvSetupFPU();
}
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@ -881,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters ) /* PRIVILEGED_FUNCTION */
void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
{
/* Simulate the stack frame as it would be created by a context switch
@ -1015,7 +1016,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
vPortSetupTimerInterrupt();
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
ulCriticalNesting = 0;
/* Start the first task. */
vStartFirstTask();
@ -1049,10 +1050,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
uint32_t ulStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
int32_t lIndex = 0;
/* Setup MAIR0. */
xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
/* This function is called automatically when the task is created - in
@ -1062,9 +1063,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
if( ulStackDepth > 0 )
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
@ -1087,9 +1088,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
/* Translate the generic region definition contained in xRegions
* into the ARMv8 specific MPU settings that are then stored in
* xMPUSettings. */
ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
/* Start address. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
@ -1142,7 +1143,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. Interrupt Program

1
portable/GCC/ARM_CM33/non_secure/portasm.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */

1
portable/GCC/ARM_CM33/non_secure/portasm.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __PORT_ASM_H__

1
portable/GCC/ARM_CM33/non_secure/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H

11
portable/GCC/ARM_CM33/secure/secure_context.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Secure context includes. */
@ -101,12 +102,12 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
#endif /* configENABLE_MPU */
{
uint8_t * pucStackMemory = NULL;
uint32_t ulIPSR;
SecureContextHandle_t xSecureContextHandle = NULL;
uint8_t * pucStackMemory = NULL;
uint32_t ulIPSR;
SecureContextHandle_t xSecureContextHandle = NULL;
#if ( configENABLE_MPU == 1 )
uint32_t * pulCurrentStackPointer = NULL;
uint32_t * pulCurrentStackPointer = NULL;
#endif /* configENABLE_MPU */
/* Read the Interrupt Program Status Register (IPSR) value. */
@ -143,7 +144,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
/* Store the correct CONTROL value for the task on the stack.
* This value is programmed in the CONTROL register on
* context switch. */
pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
pulCurrentStackPointer--;
if( ulIsTaskPrivileged )

1
portable/GCC/ARM_CM33/secure/secure_context.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __SECURE_CONTEXT_H__

1
portable/GCC/ARM_CM33/secure/secure_context_port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Secure context includes. */

73
portable/GCC/ARM_CM33/secure/secure_heap.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */
@ -115,7 +116,7 @@ static BlockLink_t xStart, * pxEnd = NULL;
* @brief Keeps track of the number of free bytes remaining, but says nothing
* about fragmentation.
*/
static size_t xFreeBytesRemaining = 0U;
static size_t xFreeBytesRemaining = 0U;
static size_t xMinimumEverFreeBytesRemaining = 0U;
/**
@ -125,61 +126,61 @@ static size_t xMinimumEverFreeBytesRemaining = 0U;
* then the block belongs to the application. When the bit is free the block is
* still part of the free heap space.
*/
static size_t xBlockAllocatedBit = 0;
static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
{
BlockLink_t * pxFirstFreeBlock;
uint8_t * pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
uint8_t * pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = ( size_t ) ucHeap;
uxAddress = ( size_t ) ucHeap;
if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
{
uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
pucAlignedHeap = ( uint8_t * ) uxAddress;
/* xStart is used to hold a pointer to the first item in the list of free
* blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
xStart.xBlockSize = ( size_t ) 0;
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
xStart.xBlockSize = ( size_t ) 0;
/* pxEnd is used to mark the end of the list of free blocks and is inserted
* at the end of the heap space. */
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
uxAddress -= xHeapStructSize;
uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
pxEnd = ( void * ) uxAddress;
pxEnd->xBlockSize = 0;
pxEnd->pxNextFreeBlock = NULL;
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
uxAddress -= xHeapStructSize;
uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
pxEnd = ( void * ) uxAddress;
pxEnd->xBlockSize = 0;
pxEnd->pxNextFreeBlock = NULL;
/* To start with there is a single free block that is sized to take up the
* entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
{
BlockLink_t * pxIterator;
uint8_t * puc;
uint8_t * puc;
/* Iterate through the list until a block is found that has a higher address
* than the block being inserted. */
@ -195,7 +196,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
pxBlockToInsert = pxIterator;
pxBlockToInsert = pxIterator;
}
else
{
@ -211,7 +212,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
if( pxIterator->pxNextFreeBlock != pxEnd )
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
}
else
@ -242,7 +243,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
void * pvPortMalloc( size_t xWantedSize )
{
BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
void * pvReturn = NULL;
void * pvReturn = NULL;
/* If this is the first call to malloc then the heap will require
* initialisation to setup the list of free blocks. */
@ -290,12 +291,12 @@ void * pvPortMalloc( size_t xWantedSize )
/* Traverse the list from the start (lowest address) block until
* one of adequate size is found. */
pxPreviousBlock = &xStart;
pxBlock = xStart.pxNextFreeBlock;
pxBlock = xStart.pxNextFreeBlock;
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
{
pxPreviousBlock = pxBlock;
pxBlock = pxBlock->pxNextFreeBlock;
pxBlock = pxBlock->pxNextFreeBlock;
}
/* If the end marker was reached then a block of adequate size was
@ -304,7 +305,7 @@ void * pvPortMalloc( size_t xWantedSize )
{
/* Return the memory space pointed to - jumping over the
* BlockLink_t structure at its start. */
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
/* This block is being returned for use so must be taken out
* of the list of free blocks. */
@ -318,13 +319,13 @@ void * pvPortMalloc( size_t xWantedSize )
* block following the number of bytes requested. The void
* cast is used to prevent byte alignment warnings from the
* compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
/* Calculate the sizes of two blocks split from the single
* block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
pxBlock->xBlockSize = xWantedSize;
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList( pxNewBlockLink );
@ -334,7 +335,7 @@ void * pvPortMalloc( size_t xWantedSize )
mtCOVERAGE_TEST_MARKER();
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
xFreeBytesRemaining -= pxBlock->xBlockSize;
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
{
@ -347,8 +348,8 @@ void * pvPortMalloc( size_t xWantedSize )
/* The block is being returned - it is allocated and owned by
* the application and has no "next" block. */
pxBlock->xBlockSize |= xBlockAllocatedBit;
pxBlock->pxNextFreeBlock = NULL;
pxBlock->xBlockSize |= xBlockAllocatedBit;
pxBlock->pxNextFreeBlock = NULL;
}
else
{
@ -388,14 +389,14 @@ void * pvPortMalloc( size_t xWantedSize )
void vPortFree( void * pv )
{
uint8_t * puc = ( uint8_t * ) pv;
uint8_t * puc = ( uint8_t * ) pv;
BlockLink_t * pxLink;
if( pv != NULL )
{
/* The memory being freed will have an BlockLink_t structure immediately
* before it. */
puc -= xHeapStructSize;
puc -= xHeapStructSize;
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;

1
portable/GCC/ARM_CM33/secure/secure_heap.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __SECURE_HEAP_H__

1
portable/GCC/ARM_CM33/secure/secure_init.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */

1
portable/GCC/ARM_CM33/secure/secure_init.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __SECURE_INIT_H__

1
portable/GCC/ARM_CM33/secure/secure_port_macros.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __SECURE_PORT_MACROS_H__

215
portable/GCC/ARM_CM33_NTZ/non_secure/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
@ -349,7 +350,7 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
* @brief Each task maintains its own interrupt status in the critical nesting
* variable.
*/
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
#if ( configENABLE_TRUSTZONE == 1 )
@ -365,26 +366,26 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/**
* @brief The number of SysTick increments that make up one tick period.
*/
static uint32_t ulTimerCountsForOneTick = 0;
static uint32_t ulTimerCountsForOneTick = 0;
/**
* @brief The maximum number of tick periods that can be suppressed is
* limited by the 24 bit resolution of the SysTick timer.
*/
static uint32_t xMaximumPossibleSuppressedTicks = 0;
static uint32_t xMaximumPossibleSuppressedTicks = 0;
/**
* @brief Compensate for the CPU cycles that pass while the SysTick is
* stopped (low power functionality only).
*/
static uint32_t ulStoppedTimerCompensation = 0;
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@ -402,7 +403,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* Calculate the reload value required to wait xExpectedIdleTime
* tick periods. -1 is used because this code will execute part way
* through one of the tick periods. */
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
@ -421,14 +422,14 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
{
/* Restart from whatever is left in the count register to complete
* this tick period. */
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
* periods. */
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Re-enable interrupts - see comments above the cpsid instruction()
* above. */
@ -437,14 +438,14 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
else
{
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
/* Clear the SysTick count flag and set the count value back to
* zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
* set its parameter to 0 to indicate that its implementation
@ -452,7 +453,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* instruction, and so wfi should not be executed again. However,
* the original expected idle time variable must remain unmodified,
* so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
@ -486,7 +487,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* best it can be, but using the tickless mode will inevitably
* result in some tiny drift of the time maintained by the kernel
* with respect to calendar time*/
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
/* Determine if the SysTick clock has already counted to zero and
* been set back to the current reload value (the reload back being
@ -501,7 +502,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
* reloaded with ulReloadValue. Reset the
* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
* period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
@ -516,7 +517,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* As the pending tick will be processed as soon as this
* function exits, the tick value maintained by the tick is
* stepped forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
@ -528,20 +529,20 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
/* How many complete tick periods passed while the processor
* was waiting? */
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
/* The reload value is set to whatever fraction of a single tick
* period remains. */
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
* value. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
vTaskStepTick( ulCompleteTickPeriods );
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@ -555,19 +556,19 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
{
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@ -611,72 +612,72 @@ static void prvTaskExitError( void )
extern uint32_t * __unprivileged_flash_end__;
extern uint32_t * __privileged_sram_start__;
extern uint32_t * __privileged_sram_end__;
#else /* if defined( __ARMCC_VERSION ) */
#else /* if defined( __ARMCC_VERSION ) */
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __unprivileged_flash_start__[];
extern uint32_t __unprivileged_flash_end__[];
extern uint32_t __privileged_sram_start__[];
extern uint32_t __privileged_sram_end__[];
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __unprivileged_flash_start__[];
extern uint32_t __unprivileged_flash_end__[];
extern uint32_t __privileged_sram_start__[];
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
/* Setup privileged flash as Read Only so that privileged tasks can
* read it but not modify. */
portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup unprivileged flash as Read Only by both privileged and
* unprivileged tasks. All tasks can read it but no-one can modify. */
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup unprivileged syscalls flash as Read Only by both privileged
* and unprivileged tasks. All tasks can read it but no-one can modify. */
portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_READ_ONLY );
portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Setup RAM containing kernel data for privileged access only. */
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
( portMPU_REGION_NON_SHAREABLE ) |
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER );
portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
( portMPU_RLAR_ATTR_INDEX0 ) |
( portMPU_RLAR_REGION_ENABLE );
/* Enable mem fault. */
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
/* Enable MPU with privileged background access i.e. unmapped
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
@ -771,24 +772,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
extern uint32_t * __syscalls_flash_end__;
#else
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
#endif /* defined( __ARMCC_VERSION ) */
#endif /* configENABLE_MPU */
uint32_t ulPC;
uint32_t ulPC;
#if ( configENABLE_TRUSTZONE == 1 )
uint32_t ulR0;
uint32_t ulR0;
#if ( configENABLE_MPU == 1 )
uint32_t ulControl, ulIsTaskPrivileged;
uint32_t ulControl, ulIsTaskPrivileged;
#endif /* configENABLE_MPU */
#endif /* configENABLE_TRUSTZONE */
uint8_t ucSVCNumber;
/* Register are stored on the stack in the following order - R0, R1, R2, R3,
* R12, LR, PC, xPSR. */
ulPC = pulCallerStackAddress[ 6 ];
ulPC = pulCallerStackAddress[ 6 ];
ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
switch( ucSVCNumber )
@ -801,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
{
/* Read the CONTROL register value. */
__asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
{
/* Read the CONTROL register value. */
__asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
/* The task that raised the SVC is privileged if Bit[0]
* in the CONTROL register is 0. */
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
/* The task that raised the SVC is privileged if Bit[0]
* in the CONTROL register is 0. */
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
}
#else /* if ( configENABLE_MPU == 1 ) */
{
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0 );
}
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
}
#else /* if ( configENABLE_MPU == 1 ) */
{
/* Allocate and load a context for the secure task. */
xSecureContext = SecureContext_AllocateContext( ulR0 );
}
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != NULL );
@ -834,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
{
/* De-prioritize the non-secure exceptions so that the
* non-secure pendSV runs at the lowest priority. */
SecureInit_DePrioritizeNSExceptions();
{
/* De-prioritize the non-secure exceptions so that the
* non-secure pendSV runs at the lowest priority. */
SecureInit_DePrioritizeNSExceptions();
/* Initialize the secure context management system. */
SecureContext_Init();
}
/* Initialize the secure context management system. */
SecureContext_Init();
}
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
{
/* Setup the Floating Point Unit (FPU). */
prvSetupFPU();
}
{
/* Setup the Floating Point Unit (FPU). */
prvSetupFPU();
}
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@ -881,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters,
BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
#else
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
StackType_t * pxEndOfStack,
TaskFunction_t pxCode,
void * pvParameters ) /* PRIVILEGED_FUNCTION */
void * pvParameters ) /* PRIVILEGED_FUNCTION */
#endif /* configENABLE_MPU */
{
/* Simulate the stack frame as it would be created by a context switch
@ -1015,7 +1016,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
vPortSetupTimerInterrupt();
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
ulCriticalNesting = 0;
/* Start the first task. */
vStartFirstTask();
@ -1049,10 +1050,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
uint32_t ulStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
int32_t lIndex = 0;
/* Setup MAIR0. */
xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
/* This function is called automatically when the task is created - in
@ -1062,9 +1063,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
if( ulStackDepth > 0 )
{
/* Define the region that allows access to the stack. */
ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
( portMPU_REGION_NON_SHAREABLE ) |
@ -1087,9 +1088,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
/* Translate the generic region definition contained in xRegions
* into the ARMv8 specific MPU settings that are then stored in
* xMPUSettings. */
ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
/* Start address. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
@ -1142,7 +1143,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. Interrupt Program

1
portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */

1
portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef __PORT_ASM_H__

1
portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H

91
portable/GCC/ARM_CM3_MPU/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -174,7 +175,7 @@ extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
/* Each task maintains its own interrupt status in the critical nesting
* variable. Note this is not saved as part of the task context as context
* switches can only occur when uxCriticalNesting is zero. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
/*
* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
@ -182,8 +183,8 @@ static UBaseType_t uxCriticalNesting = 0xaaaaa
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
#if ( configASSERT_DEFINED == 1 )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED */
/*-----------------------------------------------------------*/
@ -242,7 +243,7 @@ void vPortSVCHandler( void )
static void prvSVCHandler( uint32_t * pulParam )
{
uint8_t ucSVCNumber;
uint8_t ucSVCNumber;
uint32_t ulPC;
#if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
@ -254,14 +255,14 @@ static void prvSVCHandler( uint32_t * pulParam )
extern uint32_t * __syscalls_flash_end__;
#else
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
#endif /* #if defined( __ARMCC_VERSION ) */
#endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
/* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
* argument (r0) is pulParam[ 0 ]. */
ulPC = pulParam[ portOFFSET_TO_PC ];
ulPC = pulParam[ portOFFSET_TO_PC ];
ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
switch( ucSVCNumber )
@ -374,9 +375,9 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
* functions can be called. ISR safe functions are those that end in
@ -384,21 +385,21 @@ BaseType_t xPortStartScheduler( void )
* to ensure interrupt entry is as fast and simple as possible.
*
* Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
ulOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to all
* possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
@ -426,8 +427,8 @@ BaseType_t xPortStartScheduler( void )
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
/* Restore the clobbered interrupt priority register to its original
* value. */
@ -449,7 +450,7 @@ BaseType_t xPortStartScheduler( void )
vPortSetupTimerInterrupt();
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
uxCriticalNesting = 0;
/* Start the first task. */
__asm volatile (
@ -588,12 +589,12 @@ void xPortSysTickHandler( void )
__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
{
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
}
/*-----------------------------------------------------------*/
@ -614,10 +615,10 @@ static void prvSetupMPU( void )
( portMPU_REGION_VALID ) |
( portUNPRIVILEGED_FLASH_REGION );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
( portMPU_REGION_ENABLE );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
( portMPU_REGION_ENABLE );
/* Setup the privileged flash for privileged only access. This is where
* the kernel code is * placed. */
@ -625,10 +626,10 @@ static void prvSetupMPU( void )
( portMPU_REGION_VALID ) |
( portPRIVILEGED_FLASH_REGION );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
( portMPU_REGION_ENABLE );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
( portMPU_REGION_ENABLE );
/* Setup the privileged data RAM region. This is where the kernel data
* is placed. */
@ -636,10 +637,10 @@ static void prvSetupMPU( void )
( portMPU_REGION_VALID ) |
( portPRIVILEGED_RAM_REGION );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
( portMPU_REGION_ENABLE );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
( portMPU_REGION_ENABLE );
/* By default allow everything to access the general peripherals. The
* system peripherals and registers are protected. */
@ -647,15 +648,15 @@ static void prvSetupMPU( void )
( portMPU_REGION_VALID ) |
( portGENERAL_PERIPHERALS_REGION );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
( portMPU_REGION_ENABLE );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
( portMPU_REGION_ENABLE );
/* Enable the memory fault exception. */
portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
/* Enable the MPU with the background region configured. */
portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
}
}
/*-----------------------------------------------------------*/
@ -723,8 +724,8 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
extern uint32_t __SRAM_segment_end__[];
extern uint32_t __privileged_data_start__[];
extern uint32_t __privileged_data_end__[];
int32_t lIndex;
uint32_t ul;
int32_t lIndex;
uint32_t ul;
if( xRegions == NULL )
{
@ -734,7 +735,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
( portMPU_REGION_VALID ) |
( portSTACK_REGION );
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
@ -747,7 +748,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
( portMPU_REGION_VALID ) |
( portSTACK_REGION + 1 );
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
@ -757,7 +758,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
{
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
}
else
@ -774,7 +775,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
( portMPU_REGION_VALID ) |
( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) | /* Read and write. */
( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
@ -795,7 +796,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
( portMPU_REGION_VALID ) |
( portSTACK_REGION + ul ); /* Region number. */
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
( xRegions[ lIndex ].ulParameters ) |
( portMPU_REGION_ENABLE );
@ -804,7 +805,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
{
/* Invalidate the region. */
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
lIndex++;
@ -818,7 +819,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
void vPortValidateInterruptPriority( void )
{
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );

7
portable/GCC/ARM_CM3_MPU/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -132,7 +133,7 @@
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@ -183,7 +184,7 @@
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
@ -228,7 +229,7 @@
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. */

73
portable/GCC/ARM_CM4F/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -143,13 +144,13 @@ static void prvTaskExitError( void );
/* Each task maintains its own interrupt status in the critical nesting
* variable. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
/*
* The number of SysTick increments that make up one tick period.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t ulTimerCountsForOneTick = 0;
static uint32_t ulTimerCountsForOneTick = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
@ -157,7 +158,7 @@ static UBaseType_t uxCriticalNesting = 0xaaaaa
* 24 bit resolution of the SysTick timer.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t xMaximumPossibleSuppressedTicks = 0;
static uint32_t xMaximumPossibleSuppressedTicks = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
@ -165,7 +166,7 @@ static UBaseType_t uxCriticalNesting = 0xaaaaa
* power functionality only.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t ulStoppedTimerCompensation = 0;
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
@ -174,8 +175,8 @@ static UBaseType_t uxCriticalNesting = 0xaaaaa
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
#if ( configASSERT_DEFINED == 1 )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED */
@ -302,9 +303,9 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
* functions can be called. ISR safe functions are those that end in
@ -312,21 +313,21 @@ BaseType_t xPortStartScheduler( void )
* ensure interrupt entry is as fast and simple as possible.
*
* Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
ulOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to all
* possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
@ -354,8 +355,8 @@ BaseType_t xPortStartScheduler( void )
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
/* Restore the clobbered interrupt priority register to its original
* value. */
@ -372,13 +373,13 @@ BaseType_t xPortStartScheduler( void )
vPortSetupTimerInterrupt();
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
uxCriticalNesting = 0;
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
/* Start the first task. */
prvPortStartFirstTask();
@ -515,7 +516,7 @@ void xPortSysTickHandler( void )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@ -533,7 +534,7 @@ void xPortSysTickHandler( void )
/* Calculate the reload value required to wait xExpectedIdleTime
* tick periods. -1 is used because this code will execute part way
* through one of the tick periods. */
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
@ -552,14 +553,14 @@ void xPortSysTickHandler( void )
{
/* Restart from whatever is left in the count register to complete
* this tick period. */
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
* periods. */
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Re-enable interrupts - see comments above the cpsid instruction()
* above. */
@ -568,21 +569,21 @@ void xPortSysTickHandler( void )
else
{
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
/* Clear the SysTick count flag and set the count value back to
* zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
* set its parameter to 0 to indicate that its implementation contains
* its own wait for interrupt or wait for event instruction, and so wfi
* should not be executed again. However, the original expected idle
* time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
@ -616,7 +617,7 @@ void xPortSysTickHandler( void )
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
/* Determine if the SysTick clock has already counted to zero and
* been set back to the current reload value (the reload back being
@ -631,7 +632,7 @@ void xPortSysTickHandler( void )
* reloaded with ulReloadValue. Reset the
* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
* period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
@ -646,7 +647,7 @@ void xPortSysTickHandler( void )
/* As the pending tick will be processed as soon as this
* function exits, the tick value maintained by the tick is stepped
* forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
@ -658,20 +659,20 @@ void xPortSysTickHandler( void )
/* How many complete tick periods passed while the processor
* was waiting? */
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
/* The reload value is set to whatever fraction of a single tick
* period remains. */
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
* value. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
vTaskStepTick( ulCompleteTickPeriods );
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@ -690,19 +691,19 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
{
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
@ -727,7 +728,7 @@ static void vPortEnableVFP( void )
void vPortValidateInterruptPriority( void )
{
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );

5
portable/GCC/ARM_CM4F/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -147,7 +148,7 @@
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
@ -169,7 +170,7 @@
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. */

113
portable/GCC/ARM_CM4_MPU/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -187,7 +188,7 @@ extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
/* Each task maintains its own interrupt status in the critical nesting
* variable. Note this is not saved as part of the task context as context
* switches can only occur when uxCriticalNesting is zero. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
/*
* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
@ -195,8 +196,8 @@ static UBaseType_t uxCriticalNesting = 0xaaaaa
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
#if ( configASSERT_DEFINED == 1 )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED */
@ -262,7 +263,7 @@ void vPortSVCHandler( void )
static void prvSVCHandler( uint32_t * pulParam )
{
uint8_t ucSVCNumber;
uint8_t ucSVCNumber;
uint32_t ulPC;
#if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
@ -274,14 +275,14 @@ static void prvSVCHandler( uint32_t * pulParam )
extern uint32_t * __syscalls_flash_end__;
#else
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
extern uint32_t __syscalls_flash_start__[];
extern uint32_t __syscalls_flash_end__[];
#endif /* #if defined( __ARMCC_VERSION ) */
#endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
/* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
* argument (r0) is pulParam[ 0 ]. */
ulPC = pulParam[ portOFFSET_TO_PC ];
ulPC = pulParam[ portOFFSET_TO_PC ];
ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
switch( ucSVCNumber )
@ -392,9 +393,9 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
* functions can be called. ISR safe functions are those that end in
@ -402,21 +403,21 @@ BaseType_t xPortStartScheduler( void )
* ensure interrupt entry is as fast and simple as possible.
*
* Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
ulOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to all
* possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
@ -444,8 +445,8 @@ BaseType_t xPortStartScheduler( void )
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
/* Restore the clobbered interrupt priority register to its original
* value. */
@ -467,13 +468,13 @@ BaseType_t xPortStartScheduler( void )
vPortSetupTimerInterrupt();
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
uxCriticalNesting = 0;
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
/* Start the first task. This also clears the bit that indicates the FPU is
* in use in case the FPU was used before the scheduler was started - which
@ -626,12 +627,12 @@ void xPortSysTickHandler( void )
__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
{
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
}
/*-----------------------------------------------------------*/
@ -665,12 +666,12 @@ static void prvSetupMPU( void )
extern uint32_t * __privileged_data_end__;
#else
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
extern uint32_t __FLASH_segment_start__[];
extern uint32_t __FLASH_segment_end__[];
extern uint32_t __privileged_data_start__[];
extern uint32_t __privileged_data_end__[];
extern uint32_t __privileged_functions_start__[];
extern uint32_t __privileged_functions_end__[];
extern uint32_t __FLASH_segment_start__[];
extern uint32_t __FLASH_segment_end__[];
extern uint32_t __privileged_data_start__[];
extern uint32_t __privileged_data_end__[];
#endif /* if defined( __ARMCC_VERSION ) */
/* Check the expected MPU is present. */
@ -681,10 +682,10 @@ static void prvSetupMPU( void )
( portMPU_REGION_VALID ) |
( portUNPRIVILEGED_FLASH_REGION );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
( portMPU_REGION_ENABLE );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
( portMPU_REGION_ENABLE );
/* Setup the privileged flash for privileged only access. This is where
* the kernel code is placed. */
@ -692,10 +693,10 @@ static void prvSetupMPU( void )
( portMPU_REGION_VALID ) |
( portPRIVILEGED_FLASH_REGION );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
( portMPU_REGION_ENABLE );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
( portMPU_REGION_ENABLE );
/* Setup the privileged data RAM region. This is where the kernel data
* is placed. */
@ -703,10 +704,10 @@ static void prvSetupMPU( void )
( portMPU_REGION_VALID ) |
( portPRIVILEGED_RAM_REGION );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
( portMPU_REGION_ENABLE );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
( portMPU_REGION_ENABLE );
/* By default allow everything to access the general peripherals. The
* system peripherals and registers are protected. */
@ -714,15 +715,15 @@ static void prvSetupMPU( void )
( portMPU_REGION_VALID ) |
( portGENERAL_PERIPHERALS_REGION );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
( portMPU_REGION_ENABLE );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
( portMPU_REGION_ENABLE );
/* Enable the memory fault exception. */
portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
/* Enable the MPU with the background region configured. */
portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
}
}
/*-----------------------------------------------------------*/
@ -796,14 +797,14 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
extern uint32_t * __privileged_data_end__;
#else
/* Declaration when these variable are exported from linker scripts. */
extern uint32_t __SRAM_segment_start__[];
extern uint32_t __SRAM_segment_end__[];
extern uint32_t __privileged_data_start__[];
extern uint32_t __privileged_data_end__[];
extern uint32_t __SRAM_segment_start__[];
extern uint32_t __SRAM_segment_end__[];
extern uint32_t __privileged_data_start__[];
extern uint32_t __privileged_data_end__[];
#endif /* if defined( __ARMCC_VERSION ) */
int32_t lIndex;
uint32_t ul;
int32_t lIndex;
uint32_t ul;
if( xRegions == NULL )
{
@ -813,7 +814,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
( portMPU_REGION_VALID ) |
( portSTACK_REGION );
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
@ -826,7 +827,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
( portMPU_REGION_VALID ) |
( portSTACK_REGION + 1 );
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
@ -836,7 +837,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
{
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
}
else
@ -853,7 +854,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
( portMPU_REGION_VALID ) |
( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) | /* Read and write. */
( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
@ -874,7 +875,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
( portMPU_REGION_VALID ) |
( portSTACK_REGION + ul ); /* Region number. */
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
( xRegions[ lIndex ].ulParameters ) |
( portMPU_REGION_ENABLE );
@ -883,7 +884,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
{
/* Invalidate the region. */
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
lIndex++;
@ -897,7 +898,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
void vPortValidateInterruptPriority( void )
{
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );

7
portable/GCC/ARM_CM4_MPU/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -132,7 +133,7 @@
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@ -183,7 +184,7 @@
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
@ -228,7 +229,7 @@
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. */

73
portable/GCC/ARM_CM7/r0p1/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -137,13 +138,13 @@ static void prvTaskExitError( void );
/* Each task maintains its own interrupt status in the critical nesting
* variable. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
/*
* The number of SysTick increments that make up one tick period.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t ulTimerCountsForOneTick = 0;
static uint32_t ulTimerCountsForOneTick = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
@ -151,7 +152,7 @@ static UBaseType_t uxCriticalNesting = 0xaaaaa
* 24 bit resolution of the SysTick timer.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t xMaximumPossibleSuppressedTicks = 0;
static uint32_t xMaximumPossibleSuppressedTicks = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
@ -159,7 +160,7 @@ static UBaseType_t uxCriticalNesting = 0xaaaaa
* power functionality only.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t ulStoppedTimerCompensation = 0;
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
@ -168,8 +169,8 @@ static UBaseType_t uxCriticalNesting = 0xaaaaa
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
#if ( configASSERT_DEFINED == 1 )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED */
@ -290,9 +291,9 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t ucMaxPriorityValue;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
* functions can be called. ISR safe functions are those that end in
@ -300,21 +301,21 @@ BaseType_t xPortStartScheduler( void )
* ensure interrupt entry is as fast and simple as possible.
*
* Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
ulOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to all
* possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
@ -342,8 +343,8 @@ BaseType_t xPortStartScheduler( void )
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
/* Restore the clobbered interrupt priority register to its original
* value. */
@ -360,13 +361,13 @@ BaseType_t xPortStartScheduler( void )
vPortSetupTimerInterrupt();
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
uxCriticalNesting = 0;
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
/* Start the first task. */
prvPortStartFirstTask();
@ -505,7 +506,7 @@ void xPortSysTickHandler( void )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@ -523,7 +524,7 @@ void xPortSysTickHandler( void )
/* Calculate the reload value required to wait xExpectedIdleTime
* tick periods. -1 is used because this code will execute part way
* through one of the tick periods. */
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
@ -542,14 +543,14 @@ void xPortSysTickHandler( void )
{
/* Restart from whatever is left in the count register to complete
* this tick period. */
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
* periods. */
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Re-enable interrupts - see comments above the cpsid instruction()
* above. */
@ -558,21 +559,21 @@ void xPortSysTickHandler( void )
else
{
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
/* Clear the SysTick count flag and set the count value back to
* zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
* set its parameter to 0 to indicate that its implementation contains
* its own wait for interrupt or wait for event instruction, and so wfi
* should not be executed again. However, the original expected idle
* time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
@ -606,7 +607,7 @@ void xPortSysTickHandler( void )
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
/* Determine if the SysTick clock has already counted to zero and
* been set back to the current reload value (the reload back being
@ -621,7 +622,7 @@ void xPortSysTickHandler( void )
* reloaded with ulReloadValue. Reset the
* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
* period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
@ -636,7 +637,7 @@ void xPortSysTickHandler( void )
/* As the pending tick will be processed as soon as this
* function exits, the tick value maintained by the tick is stepped
* forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
@ -648,20 +649,20 @@ void xPortSysTickHandler( void )
/* How many complete tick periods passed while the processor
* was waiting? */
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
/* The reload value is set to whatever fraction of a single tick
* period remains. */
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
* value. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
vTaskStepTick( ulCompleteTickPeriods );
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@ -680,19 +681,19 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
{
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
@ -717,7 +718,7 @@ static void vPortEnableVFP( void )
void vPortValidateInterruptPriority( void )
{
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );

5
portable/GCC/ARM_CM7/r0p1/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -147,7 +148,7 @@
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
@ -169,7 +170,7 @@
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. */

25
portable/GCC/ARM_CR5/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */
@ -166,23 +167,23 @@ static void prvTaskExitError( void );
* a non zero value to ensure interrupts don't inadvertently become unmasked before
* the scheduler starts. As it is stored as part of the task context it will
* automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
* a floating point context must be saved and restored for the task. */
uint32_t ulPortTaskHasFPUContext = pdFALSE;
uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
uint32_t ulPortYieldRequired = pdFALSE;
uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
* if the nesting depth is 0. */
uint32_t ulPortInterruptNesting = 0UL;
uint32_t ulPortInterruptNesting = 0UL;
/* Used in asm code. */
__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
/*-----------------------------------------------------------*/
@ -287,21 +288,21 @@ BaseType_t xPortStartScheduler( void )
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
volatile uint8_t ucMaxPriorityValue;
volatile uint8_t ucMaxPriorityValue;
/* Determine how many priority bits are implemented in the GIC.
*
* Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
ulOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to
* all possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
/* Shift to the least significant bits. */
while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
@ -479,7 +480,7 @@ uint32_t ulPortSetInterruptMask( void )
}
else
{
ulReturn = pdFALSE;
ulReturn = pdFALSE;
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__asm volatile ( "dsb \n"
"isb \n"::: "memory" );

3
portable/GCC/ARM_CR5/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H
@ -135,7 +136,7 @@
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

7
portable/GCC/ARM_CRx_No_GIC/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */
@ -98,18 +99,18 @@ static void prvTaskExitError( void );
* a non zero value to ensure interrupts don't inadvertently become unmasked before
* the scheduler starts. As it is stored as part of the task context it will
* automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
* a floating point context must be saved and restored for the task. */
volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
volatile uint32_t ulPortYieldRequired = pdFALSE;
volatile uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
* if the nesting depth is 0. */
volatile uint32_t ulPortInterruptNesting = 0UL;
volatile uint32_t ulPortInterruptNesting = 0UL;
/* Used in the asm file to clear an interrupt. */
__attribute__( ( used ) ) const uint32_t ulICCEOIR = configEOI_ADDRESS;

3
portable/GCC/ARM_CRx_No_GIC/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H
@ -165,7 +166,7 @@
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

35
portable/GCC/ATMega323/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
@ -204,11 +205,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/* The start of the task code will be popped off the stack last, so place
* it on first. */
usAddress = ( uint16_t ) pxCode;
usAddress = ( uint16_t ) pxCode;
*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
usAddress >>= 8;
usAddress >>= 8;
*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
@ -271,11 +272,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack--;
/* Place the parameter on the stack in the expected location. */
usAddress = ( uint16_t ) pvParameters;
usAddress = ( uint16_t ) pvParameters;
*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
usAddress >>= 8;
usAddress >>= 8;
*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
pxTopOfStack--;
@ -365,36 +366,36 @@ void vPortYieldFromTick( void )
static void prvSetupTimerInterrupt( void )
{
uint32_t ulCompareMatch;
uint8_t ucHighByte, ucLowByte;
uint8_t ucHighByte, ucLowByte;
/* Using 16bit timer 1 to generate the tick. Correct fuses must be
* selected for the configCPU_CLOCK_HZ clock. */
ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
/* We only have 16 bits so have to scale to get our required tick rate. */
ulCompareMatch /= portCLOCK_PRESCALER;
ulCompareMatch /= portCLOCK_PRESCALER;
/* Adjust for correct value. */
ulCompareMatch -= ( uint32_t ) 1;
ulCompareMatch -= ( uint32_t ) 1;
/* Setup compare match value for compare match A. Interrupts are disabled
* before this is called so we need not worry here. */
ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
ulCompareMatch >>= 8;
ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
OCR1AH = ucHighByte;
OCR1AL = ucLowByte;
ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
OCR1AH = ucHighByte;
OCR1AL = ucLowByte;
/* Setup clock source and compare match behaviour. */
ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
TCCR1B = ucLowByte;
ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
TCCR1B = ucLowByte;
/* Enable the interrupt - this is okay as interrupt are currently globally
* disabled. */
ucLowByte = TIMSK;
ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
TIMSK = ucLowByte;
ucLowByte = TIMSK;
ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
TIMSK = ucLowByte;
}
/*-----------------------------------------------------------*/

1
portable/GCC/ATMega323/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*

21
portable/GCC/AVR32_UC3/port.c
View file

@ -37,6 +37,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -87,11 +88,11 @@ static void prvSetupTimerInterrupt( void );
void _init_startup( void )
{
/* Import the Exception Vector Base Address. */
extern void _evba;
extern void _evba;
#if configHEAP_INIT
extern void __heap_start__;
extern void __heap_end__;
extern void __heap_start__;
extern void __heap_end__;
BaseType_t * pxMem;
#endif
@ -287,7 +288,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */
*pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */
*pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */
*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
return pxTopOfStack;
}
@ -321,7 +322,7 @@ void vPortEndScheduler( void )
{
uint32_t lCycles;
lCycles = Get_system_register( AVR32_COUNT );
lCycles = Get_system_register( AVR32_COUNT );
lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
/* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
@ -338,7 +339,7 @@ void vPortEndScheduler( void )
{
uint32_t lCycles, lCount;
lCycles = Get_system_register( AVR32_COMPARE );
lCycles = Get_system_register( AVR32_COMPARE );
lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
/* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
@ -348,7 +349,7 @@ void vPortEndScheduler( void )
lCycles++;
}
lCount = Get_system_register( AVR32_COUNT );
lCount = Get_system_register( AVR32_COUNT );
if( lCycles < lCount )
{ /* We missed a tick, recover for the next. */
@ -369,10 +370,10 @@ void vPortEndScheduler( void )
static void prvSetupTimerInterrupt( void )
{
#if ( configTICK_USE_TC == 1 )
volatile avr32_tc_t * tc = &AVR32_TC;
volatile avr32_tc_t * tc = &AVR32_TC;
/* Options for waveform genration. */
tc_waveform_opt_t waveform_opt =
tc_waveform_opt_t waveform_opt =
{
.channel = configTICK_TC_CHANNEL, /* Channel selection. */
@ -398,7 +399,7 @@ static void prvSetupTimerInterrupt( void )
.tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
};
tc_interrupt_t tc_interrupt =
tc_interrupt_t tc_interrupt =
{
.etrgs = 0,
.ldrbs = 0,

15
portable/GCC/AVR32_UC3/portmacro.h
View file

@ -37,6 +37,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
@ -160,7 +161,7 @@
*/
#define portRESTORE_CONTEXT() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
__asm__ __volatile__ ( \
@ -266,7 +267,7 @@
*/
#define portSAVE_CONTEXT_OS_INT() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
/* When we come here */ \
@ -318,7 +319,7 @@
*/
#define portRESTORE_CONTEXT_OS_INT() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
@ -384,7 +385,7 @@
*/
#define portSAVE_CONTEXT_SCALL() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
/* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
@ -451,7 +452,7 @@
*/
#define portRESTORE_CONTEXT_SCALL() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
/* Restore all registers */ \
@ -543,7 +544,7 @@
*/
#define portENTER_SWITCHING_ISR() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
/* When we come here */ \
@ -591,7 +592,7 @@
*/
#define portEXIT_SWITCHING_ISR() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
__asm__ __volatile__ ( \

29
portable/GCC/CORTUS_APS3/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */
@ -53,7 +54,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
{
/* Make space on the stack for the context - this leaves a couple of spaces
* empty. */
pxTopOfStack -= 20;
pxTopOfStack -= 20;
/* Fill the registers with known values to assist debugging. */
pxTopOfStack[ 16 ] = 0;
@ -63,16 +64,16 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack[ 12 ] = 0x00000000UL; /* R14. */
pxTopOfStack[ 11 ] = 0x0d0d0d0dUL;
pxTopOfStack[ 10 ] = 0x0c0c0c0cUL;
pxTopOfStack[ 9 ] = 0x0b0b0b0bUL;
pxTopOfStack[ 8 ] = 0x0a0a0a0aUL;
pxTopOfStack[ 7 ] = 0x09090909UL;
pxTopOfStack[ 6 ] = 0x08080808UL;
pxTopOfStack[ 5 ] = 0x07070707UL;
pxTopOfStack[ 4 ] = 0x06060606UL;
pxTopOfStack[ 3 ] = 0x05050505UL;
pxTopOfStack[ 2 ] = 0x04040404UL;
pxTopOfStack[ 1 ] = 0x03030303UL;
pxTopOfStack[ 0 ] = ( uint32_t ) pvParameters;
pxTopOfStack[ 9 ] = 0x0b0b0b0bUL;
pxTopOfStack[ 8 ] = 0x0a0a0a0aUL;
pxTopOfStack[ 7 ] = 0x09090909UL;
pxTopOfStack[ 6 ] = 0x08080808UL;
pxTopOfStack[ 5 ] = 0x07070707UL;
pxTopOfStack[ 4 ] = 0x06060606UL;
pxTopOfStack[ 3 ] = 0x05050505UL;
pxTopOfStack[ 2 ] = 0x04040404UL;
pxTopOfStack[ 1 ] = 0x03030303UL;
pxTopOfStack[ 0 ] = ( uint32_t ) pvParameters;
return pxTopOfStack;
}
@ -97,9 +98,9 @@ BaseType_t xPortStartScheduler( void )
static void prvSetupTimerInterrupt( void )
{
/* Enable timer interrupts */
counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1;
counter1->value = counter1->reload;
counter1->mask = 1;
counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1;
counter1->value = counter1->reload;
counter1->mask = 1;
/* Set the IRQ Handler priority and enable it. */
irq[ IRQ_COUNTER1 ].ien = 1;

1
portable/GCC/CORTUS_APS3/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H

3
portable/GCC/ColdFire_V2/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Kernel includes. */
@ -125,7 +126,7 @@ void vPortYieldHandler( void )
ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
/* Note this will clear all forced interrupts - this is done for speed. */
MCF_INTC0_INTFRCL = 0;
MCF_INTC0_INTFRCL = 0;
vTaskSwitchContext();
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
}

1
portable/GCC/ColdFire_V2/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H

25
portable/GCC/H8S2329/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Scheduler includes. */
@ -69,7 +70,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
uint32_t ulValue;
/* This requires an even address. */
ulValue = ( uint32_t ) pxTopOfStack;
ulValue = ( uint32_t ) pxTopOfStack;
if( ulValue & 1UL )
{
@ -89,15 +90,15 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/* The initial stack mimics an interrupt stack. First there is the program
* counter (24 bits). */
ulValue = ( uint32_t ) pxCode;
ulValue = ( uint32_t ) pxCode;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
pxTopOfStack--;
ulValue >>= 8UL;
ulValue >>= 8UL;
*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
pxTopOfStack--;
ulValue >>= 8UL;
ulValue >>= 8UL;
*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
/* Followed by the CCR. */
@ -119,18 +120,18 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
*pxTopOfStack = 0x66;
/* ER0 */
ulValue = ( uint32_t ) pvParameters;
ulValue = ( uint32_t ) pvParameters;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
pxTopOfStack--;
ulValue >>= 8UL;
ulValue >>= 8UL;
*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
pxTopOfStack--;
ulValue >>= 8UL;
ulValue >>= 8UL;
*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
pxTopOfStack--;
ulValue >>= 8UL;
ulValue >>= 8UL;
*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
/* ER1 */
@ -289,14 +290,14 @@ static void prvSetupTimerInterrupt( void )
MSTPCR &= ~portMSTP13;
/* Configure timer 1. */
TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64;
TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64;
/* Configure the compare match value for a tick of configTICK_RATE_HZ. */
TGR1A = ulCompareMatch;
TGR1A = ulCompareMatch;
/* Start the timer and enable the interrupt - we can do this here as
* interrupts are globally disabled when this function is called. */
TIER1 |= portTGRA_INTERRUPT_ENABLE;
TSTR |= portTIMER_CHANNEL;
TIER1 |= portTGRA_INTERRUPT_ENABLE;
TSTR |= portTIMER_CHANNEL;
}
/*-----------------------------------------------------------*/

1
portable/GCC/H8S2329/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/

23
portable/GCC/HCS12/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* GCC/HCS12 port by Jefferson L Smith, 2005 */
@ -82,28 +83,28 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/* The address of the task function is placed in the stack byte at a time. */
*pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 1 );
*--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 0 );
*pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 1 );
*--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 0 );
/* Next are all the registers that form part of the task context. */
/* Y register */
*--pxTopOfStack = ( StackType_t ) 0xff;
*--pxTopOfStack = ( StackType_t ) 0xee;
*--pxTopOfStack = ( StackType_t ) 0xff;
*--pxTopOfStack = ( StackType_t ) 0xee;
/* X register */
*--pxTopOfStack = ( StackType_t ) 0xdd;
*--pxTopOfStack = ( StackType_t ) 0xcc;
*--pxTopOfStack = ( StackType_t ) 0xdd;
*--pxTopOfStack = ( StackType_t ) 0xcc;
/* A register contains parameter high byte. */
*--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 0 );
*--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 0 );
/* B register contains parameter low byte. */
*--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 1 );
*--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 1 );
/* CCR: Note that when the task starts interrupts will be enabled since
* "I" bit of CCR is cleared */
*--pxTopOfStack = ( StackType_t ) 0x80; /* keeps Stop disabled (MCU default) */
*--pxTopOfStack = ( StackType_t ) 0x80; /* keeps Stop disabled (MCU default) */
/* tmp softregs used by GCC. Values right now don't matter. */
__asm( "\n\
@ -122,7 +123,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/* The critical nesting depth is initialised with 0 (meaning not in
* a critical section). */
*--pxTopOfStack = ( StackType_t ) 0x00;
*--pxTopOfStack = ( StackType_t ) 0x00;
return pxTopOfStack;
@ -139,7 +140,7 @@ static void prvSetupTimerInterrupt( void )
{
/* Enable hardware RTI timer */
/* Ignores configTICK_RATE_HZ */
RTICTL = 0x50; /* 16 MHz xtal: 976.56 Hz, 1024mS */
RTICTL = 0x50; /* 16 MHz xtal: 976.56 Hz, 1024mS */
CRGINT |= 0x80; /* RTIE */
}
/*-----------------------------------------------------------*/

1
portable/GCC/HCS12/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/

1
portable/GCC/IA32_flat/ISR_Support.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
.extern ulTopOfSystemStack

57
portable/GCC/IA32_flat/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */
@ -138,7 +139,7 @@ static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber );
* variable must be initialised to a non zero value to ensure interrupts don't
* inadvertently become unmasked before the scheduler starts. It is set to zero
* before the first task starts executing. */
volatile uint32_t ulCriticalNesting = 9999UL;
volatile uint32_t ulCriticalNesting = 9999UL;
/* A structure used to map the various fields of an IDT entry into separate
* structure members. */
@ -171,7 +172,7 @@ static __attribute__( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[
/* A table in which application defined interrupt handlers are stored. These
* are called by the central interrupt handler if a common interrupt entry
* point it used. */
static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
@ -180,26 +181,26 @@ static __attribute__( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[
/* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL
* then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is
* not NULL then it points to a buffer into which the FPU context can be saved. */
uint8_t * pucPortTaskFPUContextBuffer __attribute__( ( used ) ) = pdFALSE;
uint8_t * pucPortTaskFPUContextBuffer __attribute__( ( used ) ) = pdFALSE;
#endif /* configSUPPORT_FPU */
/* The stack used by interrupt handlers. */
static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__( ( used ) ) = { 0 };
static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__( ( used ) ) = { 0 };
/* Don't use the very top of the system stack so the return address
* appears as 0 if the debugger tries to unwind the stack. */
volatile uint32_t ulTopOfSystemStack __attribute__( ( used ) ) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
volatile uint32_t ulTopOfSystemStack __attribute__( ( used ) ) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
/* If a yield is requested from an interrupt or from a critical section then
* the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
* instead to indicate the yield should be performed at the end of the interrupt
* when the critical section is exited. */
volatile uint32_t ulPortYieldPending __attribute__( ( used ) ) = pdFALSE;
volatile uint32_t ulPortYieldPending __attribute__( ( used ) ) = pdFALSE;
/* Counts the interrupt nesting depth. Used to know when to switch to the
* interrupt/system stack and when to save/restore a complete context. */
volatile uint32_t ulInterruptNesting __attribute__( ( used ) ) = 0;
volatile uint32_t ulInterruptNesting __attribute__( ( used ) ) = 0;
/*-----------------------------------------------------------*/
@ -286,20 +287,20 @@ static void prvSetInterruptGate( uint8_t ucNumber,
uint16_t usCodeSegment;
uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );
xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );
xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );
xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );
/* When the flat model is used the CS will never change. */
__asm volatile ( "mov %%cs, %0" : "=r" ( usCodeSegment ) );
xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment;
xInterruptDescriptorTable[ ucNumber ].ucZero = 0;
xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;
xInterruptDescriptorTable[ ucNumber ].ucZero = 0;
xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;
}
/*-----------------------------------------------------------*/
void vPortSetupIDT( void )
{
uint32_t ulNum;
uint32_t ulNum;
IDTPointer_t xIDT;
#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
@ -316,7 +317,7 @@ void vPortSetupIDT( void )
#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
/* Set IDT address. */
xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable;
xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable;
xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1;
/* Set IDT in CPU. */
@ -347,13 +348,13 @@ static void prvSetupTimerInterrupt( void )
extern void vPortAPICSpuriousHandler( void );
/* Initialise LAPIC to a well known state. */
portAPIC_LDR = 0xFFFFFFFF;
portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 );
portAPIC_LVT_TIMER = portAPIC_DISABLE;
portAPIC_LVT_PERF = portAPIC_NMI;
portAPIC_LVT_LINT0 = portAPIC_DISABLE;
portAPIC_LVT_LINT1 = portAPIC_DISABLE;
portAPIC_TASK_PRIORITY = 0;
portAPIC_LDR = 0xFFFFFFFF;
portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 );
portAPIC_LVT_TIMER = portAPIC_DISABLE;
portAPIC_LVT_PERF = portAPIC_NMI;
portAPIC_LVT_LINT0 = portAPIC_DISABLE;
portAPIC_LVT_LINT1 = portAPIC_DISABLE;
portAPIC_TASK_PRIORITY = 0;
/* Install APIC timer ISR vector. */
prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS );
@ -368,13 +369,13 @@ static void prvSetupTimerInterrupt( void )
prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS );
/* Enable the APIC, mapping the spurious interrupt at the same time. */
portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT;
portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT;
/* Set timer error vector. */
portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR;
portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR;
/* Set the interrupt frequency. */
portAPIC_TMRDIV = portAPIC_DIV_16;
portAPIC_TMRDIV = portAPIC_DIV_16;
portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL;
}
/*-----------------------------------------------------------*/
@ -404,13 +405,13 @@ BaseType_t xPortStartScheduler( void )
/* Make sure the stack used by interrupts is aligned. */
ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK;
ulCriticalNesting = 0;
ulCriticalNesting = 0;
/* Enable LAPIC Counter.*/
portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;
portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;
/* Sometimes needed. */
portAPIC_TMRDIV = portAPIC_DIV_16;
portAPIC_TMRDIV = portAPIC_DIV_16;
/* Should not return from the following function as the scheduler will then
* be executing the tasks. */
@ -506,7 +507,7 @@ uint32_t ulPortSetInterruptMask( void )
#else
{
/* Return original mask. */
ulOriginalMask = portAPIC_TASK_PRIORITY;
ulOriginalMask = portAPIC_TASK_PRIORITY;
portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
}
@ -556,7 +557,7 @@ void vPortAPICErrorHandler( void )
volatile uint32_t ulErrorStatus = 0;
portAPIC_ERROR_STATUS = 0;
ulErrorStatus = portAPIC_ERROR_STATUS;
ulErrorStatus = portAPIC_ERROR_STATUS;
( void ) ulErrorStatus;
/* Force an assert. */

1
portable/GCC/IA32_flat/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H

8
portable/GCC/MCF5235/port.c
View file

@ -253,20 +253,20 @@ BaseType_t xPortStartScheduler( void )
/* Add entry in vector table for yield system call. */
portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield;
/* Add entry in vector table for periodic timer. */
portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick;
portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick;
/* Configure the timer for the system clock. */
if( configTICK_RATE_HZ > 0 )
{
/* Configure prescaler */
MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW;
MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW;
/* Initialize the periodic timer interrupt. */
MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ );
MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ );
/* Configure interrupt priority and level and unmask interrupt. */
MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 );
MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 | MCF_INTC0_IMRH_MASKALL );
/* Enable interrupts */
MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF;
MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF;
}
/* Restore the context of the first task that is going to run. */

13
portable/GCC/MSP430F449/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
@ -260,25 +261,25 @@ void vPortYield( void )
static void prvSetupTimerInterrupt( void )
{
/* Ensure the timer is stopped. */
TACTL = 0;
TACTL = 0;
/* Run the timer of the ACLK. */
TACTL = TASSEL_1;
TACTL = TASSEL_1;
/* Clear everything to start with. */
TACTL |= TACLR;
TACTL |= TACLR;
/* Set the compare match value according to the tick rate we want. */
TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
/* Enable the interrupts. */
TACCTL0 = CCIE;
/* Start up clean. */
TACTL |= TACLR;
TACTL |= TACLR;
/* Up mode. */
TACTL |= MC_1;
TACTL |= MC_1;
}
/*-----------------------------------------------------------*/

1
portable/GCC/MSP430F449/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H

21
portable/GCC/MicroBlaze/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -67,7 +68,7 @@ volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
/* To limit the amount of stack required by each task, this port uses a
* separate stack for interrupts. */
uint32_t * pulISRStack;
uint32_t * pulISRStack;
/*-----------------------------------------------------------*/
@ -88,8 +89,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
extern void * _SDA2_BASE_, * _SDA_BASE_;
const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
extern void * _SDA2_BASE_, * _SDA_BASE_;
const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
/* Place a few bytes of known values on the bottom of the stack.
@ -248,9 +249,9 @@ void vPortYield( void )
*/
static void prvSetupTimerInterrupt( void )
{
XTmrCtr xTimer;
XTmrCtr xTimer;
const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
UBaseType_t uxMask;
UBaseType_t uxMask;
/* The OPB timer1 is used to generate the tick. Use the provided library
* functions to enable the timer and set the tick frequency. */
@ -261,7 +262,7 @@ static void prvSetupTimerInterrupt( void )
/* Set the timer interrupt enable bit while maintaining the other bit
* states. */
uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
@ -287,15 +288,15 @@ void vTaskISRHandler( void )
if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
{
static XIntc_VectorTableEntry * pxTablePtr;
static XIntc_Config * pxConfig;
static uint32_t ulInterruptMask;
static XIntc_Config * pxConfig;
static uint32_t ulInterruptMask;
ulInterruptMask = ( uint32_t ) 1 << ulPending;
/* Get the configuration data using the device ID */
pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
{

1
portable/GCC/MicroBlaze/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H

39
portable/GCC/MicroBlazeV8/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -73,7 +74,7 @@ static int32_t prvEnsureInterruptControllerIsInitialised( void );
/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
* maintains its own count, so this variable is saved as part of the task
* context. */
volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
/* This port uses a separate stack for interrupts. This prevents the stack of
* every task needing to be large enough to hold an entire interrupt stack on top
@ -92,7 +93,7 @@ volatile uint32_t ulTaskSwitchRequested = 0UL;
/* The instance of the interrupt controller used by this port. This is required
* by the Xilinx library API functions. */
static XIntc xInterruptControllerInstance;
static XIntc xInterruptControllerInstance;
/*-----------------------------------------------------------*/
@ -106,18 +107,18 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
extern void * _SDA2_BASE_, * _SDA_BASE_;
const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
extern void * _SDA2_BASE_, * _SDA_BASE_;
const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
/* Place a few bytes of known values on the bottom of the stack.
* This is essential for the Microblaze port and these lines must
* not be omitted. */
*pxTopOfStack = ( StackType_t ) 0x00000000;
*pxTopOfStack = ( StackType_t ) 0x00000000;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x00000000;
*pxTopOfStack = ( StackType_t ) 0x00000000;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x00000000;
*pxTopOfStack = ( StackType_t ) 0x00000000;
pxTopOfStack--;
#if ( XPAR_MICROBLAZE_USE_FPU != 0 )
@ -129,7 +130,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/* The MSR value placed in the initial task context should have interrupts
* disabled. Each task will enable interrupts automatically when it enters
* the running state for the first time. */
*pxTopOfStack = mfmsr() & ~portMSR_IE;
*pxTopOfStack = mfmsr() & ~portMSR_IE;
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
{
@ -142,20 +143,20 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/* First stack an initial value for the critical section nesting. This
* is initialised to zero. */
*pxTopOfStack = ( StackType_t ) 0x00;
*pxTopOfStack = ( StackType_t ) 0x00;
/* R0 is always zero. */
/* R1 is the SP. */
/* Place an initial value for all the general purpose registers. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
*pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
*pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
*pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
pxTopOfStack--;
@ -177,11 +178,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack -= 8;
#endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
*pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
*pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
*pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */
*pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */
#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
pxTopOfStack--;
@ -195,7 +196,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack -= 4;
#endif
*pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
*pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
pxTopOfStack--;
@ -250,7 +251,7 @@ BaseType_t xPortStartScheduler( void )
vApplicationSetupTimerInterrupt();
/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
pulISRStack = ( uint32_t * ) _stack;
pulISRStack = ( uint32_t * ) _stack;
/* Ensure there is enough space for the functions called from the interrupt
* service routines to write back into the stack frame of the caller. */
@ -360,7 +361,7 @@ BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
static int32_t prvEnsureInterruptControllerIsInitialised( void )
{
static int32_t lInterruptControllerInitialised = pdFALSE;
int32_t lReturn;
int32_t lReturn;
/* Ensure the interrupt controller instance variable is initialised before
* it is used, and that the initialisation only happens once. */

87
portable/GCC/MicroBlazeV8/port_exceptions.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Scheduler includes. */
@ -107,55 +108,55 @@
/* First fill in the name and handle of the task that was in the Running
* state when the exception occurred. */
xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
configASSERT( pulStackPointerOnFunctionEntry );
/* Obtain the values of registers that were stacked prior to this function
* being called, and may have changed since they were stacked. */
xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
/* Obtain the value of all other registers. */
xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
xRegisterDump.ulR20 = mfgpr( R20 );
xRegisterDump.ulR21 = mfgpr( R21 );
xRegisterDump.ulR22 = mfgpr( R22 );
xRegisterDump.ulR23 = mfgpr( R23 );
xRegisterDump.ulR24 = mfgpr( R24 );
xRegisterDump.ulR25 = mfgpr( R25 );
xRegisterDump.ulR26 = mfgpr( R26 );
xRegisterDump.ulR27 = mfgpr( R27 );
xRegisterDump.ulR28 = mfgpr( R28 );
xRegisterDump.ulR29 = mfgpr( R29 );
xRegisterDump.ulR30 = mfgpr( R30 );
xRegisterDump.ulR31 = mfgpr( R31 );
xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
xRegisterDump.ulEAR = mfear();
xRegisterDump.ulESR = mfesr();
xRegisterDump.ulEDR = mfedr();
xRegisterDump.ulR20 = mfgpr( R20 );
xRegisterDump.ulR21 = mfgpr( R21 );
xRegisterDump.ulR22 = mfgpr( R22 );
xRegisterDump.ulR23 = mfgpr( R23 );
xRegisterDump.ulR24 = mfgpr( R24 );
xRegisterDump.ulR25 = mfgpr( R25 );
xRegisterDump.ulR26 = mfgpr( R26 );
xRegisterDump.ulR27 = mfgpr( R27 );
xRegisterDump.ulR28 = mfgpr( R28 );
xRegisterDump.ulR29 = mfgpr( R29 );
xRegisterDump.ulR30 = mfgpr( R30 );
xRegisterDump.ulR31 = mfgpr( R31 );
xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
xRegisterDump.ulEAR = mfear();
xRegisterDump.ulESR = mfesr();
xRegisterDump.ulEDR = mfedr();
/* Move the saved program counter back to the instruction that was executed
* when the exception occurred. This is only valid for certain types of
* exception. */
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
#if ( XPAR_MICROBLAZE_USE_FPU != 0 )
{
@ -173,31 +174,31 @@
switch( ( uint32_t ) pvExceptionID )
{
case XEXC_ID_FSL:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
break;
case XEXC_ID_UNALIGNED_ACCESS:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
break;
case XEXC_ID_ILLEGAL_OPCODE:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
break;
case XEXC_ID_M_AXI_I_EXCEPTION:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
break;
case XEXC_ID_M_AXI_D_EXCEPTION:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
break;
case XEXC_ID_DIV_BY_ZERO:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
break;
case XEXC_ID_STACK_VIOLATION:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
break;
#if ( XPAR_MICROBLAZE_USE_FPU != 0 )

5
portable/GCC/MicroBlazeV8/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H
@ -115,7 +116,7 @@
* vTaskSwitchContext() being made from a single interrupt, as a single interrupt
* can result in multiple peripherals being serviced. */
extern volatile uint32_t ulTaskSwitchRequested;
#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
@ -140,7 +141,7 @@
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

39
portable/GCC/MicroBlazeV9/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -74,7 +75,7 @@ static int32_t prvEnsureInterruptControllerIsInitialised( void );
/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
* maintains its own count, so this variable is saved as part of the task
* context. */
volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
/* This port uses a separate stack for interrupts. This prevents the stack of
* every task needing to be large enough to hold an entire interrupt stack on top
@ -93,7 +94,7 @@ volatile uint32_t ulTaskSwitchRequested = 0UL;
/* The instance of the interrupt controller used by this port. This is required
* by the Xilinx library API functions. */
static XIntc xInterruptControllerInstance;
static XIntc xInterruptControllerInstance;
/*-----------------------------------------------------------*/
@ -107,19 +108,19 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
extern void * _SDA2_BASE_, * _SDA_BASE_;
const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
extern void * _SDA2_BASE_, * _SDA_BASE_;
const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
extern void _start1( void );
/* Place a few bytes of known values on the bottom of the stack.
* This is essential for the Microblaze port and these lines must
* not be omitted. */
*pxTopOfStack = ( StackType_t ) 0x00000000;
*pxTopOfStack = ( StackType_t ) 0x00000000;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x00000000;
*pxTopOfStack = ( StackType_t ) 0x00000000;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x00000000;
*pxTopOfStack = ( StackType_t ) 0x00000000;
pxTopOfStack--;
#if ( XPAR_MICROBLAZE_USE_FPU != 0 )
@ -131,7 +132,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/* The MSR value placed in the initial task context should have interrupts
* disabled. Each task will enable interrupts automatically when it enters
* the running state for the first time. */
*pxTopOfStack = mfmsr() & ~portMSR_IE;
*pxTopOfStack = mfmsr() & ~portMSR_IE;
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
{
@ -144,20 +145,20 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
/* First stack an initial value for the critical section nesting. This
* is initialised to zero. */
*pxTopOfStack = ( StackType_t ) 0x00;
*pxTopOfStack = ( StackType_t ) 0x00;
/* R0 is always zero. */
/* R1 is the SP. */
/* Place an initial value for all the general purpose registers. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
*pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
*pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
*pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
pxTopOfStack--;
@ -179,11 +180,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack -= 8;
#endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
*pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
*pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
*pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */
*pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */
#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
pxTopOfStack--;
@ -197,7 +198,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
pxTopOfStack -= 4;
#endif
*pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
*pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
pxTopOfStack--;
@ -252,7 +253,7 @@ BaseType_t xPortStartScheduler( void )
vApplicationSetupTimerInterrupt();
/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
pulISRStack = ( uint32_t * ) _stack;
pulISRStack = ( uint32_t * ) _stack;
/* Ensure there is enough space for the functions called from the interrupt
* service routines to write back into the stack frame of the caller. */
@ -368,7 +369,7 @@ BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
static int32_t prvEnsureInterruptControllerIsInitialised( void )
{
static int32_t lInterruptControllerInitialised = pdFALSE;
int32_t lReturn;
int32_t lReturn;
/* Ensure the interrupt controller instance variable is initialised before
* it is used, and that the initialisation only happens once. */

87
portable/GCC/MicroBlazeV9/port_exceptions.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Scheduler includes. */
@ -107,55 +108,55 @@
/* First fill in the name and handle of the task that was in the Running
* state when the exception occurred. */
xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
configASSERT( pulStackPointerOnFunctionEntry );
/* Obtain the values of registers that were stacked prior to this function
* being called, and may have changed since they were stacked. */
xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
/* Obtain the value of all other registers. */
xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
xRegisterDump.ulR20 = mfgpr( R20 );
xRegisterDump.ulR21 = mfgpr( R21 );
xRegisterDump.ulR22 = mfgpr( R22 );
xRegisterDump.ulR23 = mfgpr( R23 );
xRegisterDump.ulR24 = mfgpr( R24 );
xRegisterDump.ulR25 = mfgpr( R25 );
xRegisterDump.ulR26 = mfgpr( R26 );
xRegisterDump.ulR27 = mfgpr( R27 );
xRegisterDump.ulR28 = mfgpr( R28 );
xRegisterDump.ulR29 = mfgpr( R29 );
xRegisterDump.ulR30 = mfgpr( R30 );
xRegisterDump.ulR31 = mfgpr( R31 );
xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
xRegisterDump.ulEAR = mfear();
xRegisterDump.ulESR = mfesr();
xRegisterDump.ulEDR = mfedr();
xRegisterDump.ulR20 = mfgpr( R20 );
xRegisterDump.ulR21 = mfgpr( R21 );
xRegisterDump.ulR22 = mfgpr( R22 );
xRegisterDump.ulR23 = mfgpr( R23 );
xRegisterDump.ulR24 = mfgpr( R24 );
xRegisterDump.ulR25 = mfgpr( R25 );
xRegisterDump.ulR26 = mfgpr( R26 );
xRegisterDump.ulR27 = mfgpr( R27 );
xRegisterDump.ulR28 = mfgpr( R28 );
xRegisterDump.ulR29 = mfgpr( R29 );
xRegisterDump.ulR30 = mfgpr( R30 );
xRegisterDump.ulR31 = mfgpr( R31 );
xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
xRegisterDump.ulEAR = mfear();
xRegisterDump.ulESR = mfesr();
xRegisterDump.ulEDR = mfedr();
/* Move the saved program counter back to the instruction that was executed
* when the exception occurred. This is only valid for certain types of
* exception. */
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
#if ( XPAR_MICROBLAZE_USE_FPU != 0 )
{
@ -173,31 +174,31 @@
switch( ( uint32_t ) pvExceptionID )
{
case XEXC_ID_FSL:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
break;
case XEXC_ID_UNALIGNED_ACCESS:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
break;
case XEXC_ID_ILLEGAL_OPCODE:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
break;
case XEXC_ID_M_AXI_I_EXCEPTION:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
break;
case XEXC_ID_M_AXI_D_EXCEPTION:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
break;
case XEXC_ID_DIV_BY_ZERO:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
break;
case XEXC_ID_STACK_VIOLATION:
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
break;
#if ( XPAR_MICROBLAZE_USE_FPU != 0 )

5
portable/GCC/MicroBlazeV9/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H
@ -115,7 +116,7 @@
* vTaskSwitchContext() being made from a single interrupt, as a single interrupt
* can result in multiple peripherals being serviced. */
extern volatile uint32_t ulTaskSwitchRequested;
#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
@ -140,7 +141,7 @@
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

9
portable/GCC/NiosII/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -73,7 +74,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
void * pvParameters )
{
StackType_t * pxFramePointer = pxTopOfStack - 1;
StackType_t xGlobalPointer;
StackType_t xGlobalPointer;
prvReadGp( &xGlobalPointer );
@ -181,7 +182,7 @@ int alt_irq_register( alt_u32 id,
void * context,
void ( * handler )( void *, alt_u32 ) )
{
int rc = -EINVAL;
int rc = -EINVAL;
alt_irq_context status;
if( id < ALT_NIRQ )
@ -192,12 +193,12 @@ int alt_irq_register( alt_u32 id,
* state.
*/
status = alt_irq_disable_all();
status = alt_irq_disable_all();
alt_irq[ id ].handler = handler;
alt_irq[ id ].context = context;
rc = ( handler ) ? alt_irq_enable( id ) : alt_irq_disable( id );
rc = ( handler ) ? alt_irq_enable( id ) : alt_irq_disable( id );
/* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */
}

1
portable/GCC/NiosII/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H

1
portable/GCC/PPC405_Xilinx/FPU_Macros.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* When switching out a task, if the task tag contains a buffer address then

11
portable/GCC/PPC405_Xilinx/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -187,9 +188,9 @@ static void prvSetupTimerInterrupt( void )
void vPortISRHandler( void * pvNullDoNotUse )
{
uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
BaseType_t xInterruptNumber;
XIntc_Config * pxInterruptController;
uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
BaseType_t xInterruptNumber;
XIntc_Config * pxInterruptController;
XIntc_VectorTableEntry * pxTable;
/* Just to remove compiler warning. */
@ -200,7 +201,7 @@ void vPortISRHandler( void * pvNullDoNotUse )
pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
/* Which interrupts are pending? */
ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
{
@ -215,7 +216,7 @@ void vPortISRHandler( void * pvNullDoNotUse )
}
/* Check the next interrupt. */
ulInterruptMask <<= 0x01UL;
ulInterruptMask <<= 0x01UL;
ulInterruptStatus >>= 0x01UL;
/* Have we serviced all interrupts? */

1
portable/GCC/PPC405_Xilinx/portmacro.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H

1
portable/GCC/PPC440_Xilinx/FPU_Macros.h
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* When switching out a task, if the task tag contains a buffer address then

11
portable/GCC/PPC440_Xilinx/port.c
View file

@ -22,6 +22,7 @@
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
@ -187,9 +188,9 @@ static void prvSetupTimerInterrupt( void )
void vPortISRHandler( void * pvNullDoNotUse )
{
uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
BaseType_t xInterruptNumber;
XIntc_Config * pxInterruptController;
uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
BaseType_t xInterruptNumber;
XIntc_Config * pxInterruptController;
XIntc_VectorTableEntry * pxTable;
/* Just to remove compiler warning. */
@ -200,7 +201,7 @@ void vPortISRHandler( void * pvNullDoNotUse )
pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
/* Which interrupts are pending? */
ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
{
@ -215,7 +216,7 @@ void vPortISRHandler( void * pvNullDoNotUse )
}
/* Check the next interrupt. */
ulInterruptMask <<= 0x01UL;
ulInterruptMask <<= 0x01UL;
ulInterruptStatus >>= 0x01UL;
/* Have we serviced all interrupts? */

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