mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-20 01:58:32 -04:00
Style: uncrustify kernel files
This commit is contained in:
Alfred Gedeon
alfred gedeon
parent
66a815653b
commit
587a83d647
385 changed files with 4714 additions and 4338 deletions
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@ -22,6 +22,7 @@
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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@ -349,7 +350,7 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
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* @brief Each task maintains its own interrupt status in the critical nesting
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* variable.
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*/
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static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
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static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
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#if ( configENABLE_TRUSTZONE == 1 )
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@ -365,26 +366,26 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
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/**
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* @brief The number of SysTick increments that make up one tick period.
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*/
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static uint32_t ulTimerCountsForOneTick = 0;
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static uint32_t ulTimerCountsForOneTick = 0;
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/**
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* @brief The maximum number of tick periods that can be suppressed is
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* limited by the 24 bit resolution of the SysTick timer.
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*/
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static uint32_t xMaximumPossibleSuppressedTicks = 0;
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static uint32_t xMaximumPossibleSuppressedTicks = 0;
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/**
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* @brief Compensate for the CPU cycles that pass while the SysTick is
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* stopped (low power functionality only).
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*/
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static uint32_t ulStoppedTimerCompensation = 0;
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static uint32_t ulStoppedTimerCompensation = 0;
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#endif /* configUSE_TICKLESS_IDLE */
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/*-----------------------------------------------------------*/
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#if ( configUSE_TICKLESS_IDLE == 1 )
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__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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{
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uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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TickType_t xModifiableIdleTime;
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/* Make sure the SysTick reload value does not overflow the counter. */
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@ -402,7 +403,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
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/* Calculate the reload value required to wait xExpectedIdleTime
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* tick periods. -1 is used because this code will execute part way
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* through one of the tick periods. */
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ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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if( ulReloadValue > ulStoppedTimerCompensation )
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{
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@ -421,14 +422,14 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
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{
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/* Restart from whatever is left in the count register to complete
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* this tick period. */
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portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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/* Restart SysTick. */
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portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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/* Reset the reload register to the value required for normal tick
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* periods. */
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portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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/* Re-enable interrupts - see comments above the cpsid instruction()
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* above. */
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@ -437,14 +438,14 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
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else
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{
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/* Set the new reload value. */
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portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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/* Clear the SysTick count flag and set the count value back to
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* zero. */
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Restart SysTick. */
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portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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* set its parameter to 0 to indicate that its implementation
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@ -452,7 +453,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
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* instruction, and so wfi should not be executed again. However,
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* the original expected idle time variable must remain unmodified,
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* so a copy is taken. */
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xModifiableIdleTime = xExpectedIdleTime;
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xModifiableIdleTime = xExpectedIdleTime;
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configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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if( xModifiableIdleTime > 0 )
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@ -486,7 +487,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
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* best it can be, but using the tickless mode will inevitably
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* result in some tiny drift of the time maintained by the kernel
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* with respect to calendar time*/
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portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
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portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
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/* Determine if the SysTick clock has already counted to zero and
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* been set back to the current reload value (the reload back being
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@ -501,7 +502,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
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* reloaded with ulReloadValue. Reset the
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* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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* period. */
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ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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/* Don't allow a tiny value, or values that have somehow
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* underflowed because the post sleep hook did something
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@ -516,7 +517,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
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/* As the pending tick will be processed as soon as this
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* function exits, the tick value maintained by the tick is
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* stepped forward by one less than the time spent waiting. */
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ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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}
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else
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{
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@ -528,20 +529,20 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaU
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/* How many complete tick periods passed while the processor
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* was waiting? */
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ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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/* The reload value is set to whatever fraction of a single tick
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* period remains. */
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portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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}
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/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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* value. */
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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vTaskStepTick( ulCompleteTickPeriods );
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portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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/* Exit with interrupts enabled. */
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__asm volatile ( "cpsie i" ::: "memory" );
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@ -555,19 +556,19 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
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/* Calculate the constants required to configure the tick interrupt. */
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#if ( configUSE_TICKLESS_IDLE == 1 )
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{
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ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
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ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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}
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#endif /* configUSE_TICKLESS_IDLE */
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/* Stop and reset the SysTick. */
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portNVIC_SYSTICK_CTRL_REG = 0UL;
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portNVIC_SYSTICK_CTRL_REG = 0UL;
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Configure SysTick to interrupt at the requested rate. */
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portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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}
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/*-----------------------------------------------------------*/
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@ -611,72 +612,72 @@ static void prvTaskExitError( void )
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extern uint32_t * __unprivileged_flash_end__;
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extern uint32_t * __privileged_sram_start__;
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extern uint32_t * __privileged_sram_end__;
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#else /* if defined( __ARMCC_VERSION ) */
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#else /* if defined( __ARMCC_VERSION ) */
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/* Declaration when these variable are exported from linker scripts. */
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extern uint32_t __privileged_functions_start__[];
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extern uint32_t __privileged_functions_end__[];
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extern uint32_t __syscalls_flash_start__[];
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extern uint32_t __syscalls_flash_end__[];
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extern uint32_t __unprivileged_flash_start__[];
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extern uint32_t __unprivileged_flash_end__[];
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extern uint32_t __privileged_sram_start__[];
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extern uint32_t __privileged_sram_end__[];
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extern uint32_t __privileged_functions_start__[];
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extern uint32_t __privileged_functions_end__[];
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extern uint32_t __syscalls_flash_start__[];
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extern uint32_t __syscalls_flash_end__[];
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extern uint32_t __unprivileged_flash_start__[];
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extern uint32_t __unprivileged_flash_end__[];
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extern uint32_t __privileged_sram_start__[];
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extern uint32_t __privileged_sram_end__[];
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#endif /* defined( __ARMCC_VERSION ) */
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/* Check that the MPU is present. */
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if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
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{
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/* MAIR0 - Index 0. */
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portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
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portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
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/* MAIR0 - Index 1. */
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portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
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portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
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/* Setup privileged flash as Read Only so that privileged tasks can
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* read it but not modify. */
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portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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( portMPU_REGION_NON_SHAREABLE ) |
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( portMPU_REGION_PRIVILEGED_READ_ONLY );
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portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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( portMPU_REGION_NON_SHAREABLE ) |
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( portMPU_REGION_PRIVILEGED_READ_ONLY );
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portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* Setup unprivileged flash as Read Only by both privileged and
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* unprivileged tasks. All tasks can read it but no-one can modify. */
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portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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( portMPU_REGION_NON_SHAREABLE ) |
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( portMPU_REGION_READ_ONLY );
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portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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( portMPU_REGION_NON_SHAREABLE ) |
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( portMPU_REGION_READ_ONLY );
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portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* Setup unprivileged syscalls flash as Read Only by both privileged
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* and unprivileged tasks. All tasks can read it but no-one can modify. */
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portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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( portMPU_REGION_NON_SHAREABLE ) |
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( portMPU_REGION_READ_ONLY );
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portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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( portMPU_REGION_NON_SHAREABLE ) |
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( portMPU_REGION_READ_ONLY );
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portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* Setup RAM containing kernel data for privileged access only. */
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portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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( portMPU_REGION_NON_SHAREABLE ) |
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( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
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( portMPU_REGION_EXECUTE_NEVER );
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portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
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portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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( portMPU_REGION_NON_SHAREABLE ) |
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( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
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( portMPU_REGION_EXECUTE_NEVER );
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portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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( portMPU_RLAR_ATTR_INDEX0 ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* Enable mem fault. */
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portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
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/* Enable MPU with privileged background access i.e. unmapped
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* regions have privileged access. */
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portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
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portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
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}
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}
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#endif /* configENABLE_MPU */
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@ -771,24 +772,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
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extern uint32_t * __syscalls_flash_end__;
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#else
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/* Declaration when these variable are exported from linker scripts. */
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extern uint32_t __syscalls_flash_start__[];
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extern uint32_t __syscalls_flash_end__[];
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extern uint32_t __syscalls_flash_start__[];
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extern uint32_t __syscalls_flash_end__[];
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#endif /* defined( __ARMCC_VERSION ) */
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#endif /* configENABLE_MPU */
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uint32_t ulPC;
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uint32_t ulPC;
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#if ( configENABLE_TRUSTZONE == 1 )
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uint32_t ulR0;
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uint32_t ulR0;
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#if ( configENABLE_MPU == 1 )
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uint32_t ulControl, ulIsTaskPrivileged;
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uint32_t ulControl, ulIsTaskPrivileged;
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#endif /* configENABLE_MPU */
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#endif /* configENABLE_TRUSTZONE */
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uint8_t ucSVCNumber;
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/* Register are stored on the stack in the following order - R0, R1, R2, R3,
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* R12, LR, PC, xPSR. */
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ulPC = pulCallerStackAddress[ 6 ];
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ulPC = pulCallerStackAddress[ 6 ];
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ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
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switch( ucSVCNumber )
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@ -801,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
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ulR0 = pulCallerStackAddress[ 0 ];
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#if ( configENABLE_MPU == 1 )
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{
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/* Read the CONTROL register value. */
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__asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
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{
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/* Read the CONTROL register value. */
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||||
__asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
|
||||
|
||||
/* The task that raised the SVC is privileged if Bit[0]
|
||||
* in the CONTROL register is 0. */
|
||||
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
|
||||
/* The task that raised the SVC is privileged if Bit[0]
|
||||
* in the CONTROL register is 0. */
|
||||
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
|
||||
|
||||
/* Allocate and load a context for the secure task. */
|
||||
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
|
||||
}
|
||||
#else /* if ( configENABLE_MPU == 1 ) */
|
||||
{
|
||||
/* Allocate and load a context for the secure task. */
|
||||
xSecureContext = SecureContext_AllocateContext( ulR0 );
|
||||
}
|
||||
/* Allocate and load a context for the secure task. */
|
||||
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
|
||||
}
|
||||
#else /* if ( configENABLE_MPU == 1 ) */
|
||||
{
|
||||
/* Allocate and load a context for the secure task. */
|
||||
xSecureContext = SecureContext_AllocateContext( ulR0 );
|
||||
}
|
||||
#endif /* configENABLE_MPU */
|
||||
|
||||
configASSERT( xSecureContext != NULL );
|
||||
|
|
@ -834,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
|
||||
case portSVC_START_SCHEDULER:
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
{
|
||||
/* De-prioritize the non-secure exceptions so that the
|
||||
* non-secure pendSV runs at the lowest priority. */
|
||||
SecureInit_DePrioritizeNSExceptions();
|
||||
{
|
||||
/* De-prioritize the non-secure exceptions so that the
|
||||
* non-secure pendSV runs at the lowest priority. */
|
||||
SecureInit_DePrioritizeNSExceptions();
|
||||
|
||||
/* Initialize the secure context management system. */
|
||||
SecureContext_Init();
|
||||
}
|
||||
/* Initialize the secure context management system. */
|
||||
SecureContext_Init();
|
||||
}
|
||||
#endif /* configENABLE_TRUSTZONE */
|
||||
|
||||
#if ( configENABLE_FPU == 1 )
|
||||
{
|
||||
/* Setup the Floating Point Unit (FPU). */
|
||||
prvSetupFPU();
|
||||
}
|
||||
{
|
||||
/* Setup the Floating Point Unit (FPU). */
|
||||
prvSetupFPU();
|
||||
}
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
/* Setup the context of the first task so that the first task starts
|
||||
|
|
@ -881,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
StackType_t * pxEndOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters,
|
||||
BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
|
||||
BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
|
||||
#else
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
StackType_t * pxEndOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters ) /* PRIVILEGED_FUNCTION */
|
||||
void * pvParameters ) /* PRIVILEGED_FUNCTION */
|
||||
#endif /* configENABLE_MPU */
|
||||
{
|
||||
/* Simulate the stack frame as it would be created by a context switch
|
||||
|
|
@ -1015,7 +1016,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
vPortSetupTimerInterrupt();
|
||||
|
||||
/* Initialize the critical nesting count ready for the first task. */
|
||||
ulCriticalNesting = 0;
|
||||
ulCriticalNesting = 0;
|
||||
|
||||
/* Start the first task. */
|
||||
vStartFirstTask();
|
||||
|
|
@ -1049,10 +1050,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
uint32_t ulStackDepth )
|
||||
{
|
||||
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
|
||||
int32_t lIndex = 0;
|
||||
int32_t lIndex = 0;
|
||||
|
||||
/* Setup MAIR0. */
|
||||
xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
|
||||
xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
|
||||
xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
|
||||
|
||||
/* This function is called automatically when the task is created - in
|
||||
|
|
@ -1062,9 +1063,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
if( ulStackDepth > 0 )
|
||||
{
|
||||
/* Define the region that allows access to the stack. */
|
||||
ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
|
||||
ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
|
||||
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
|
||||
ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
|
||||
ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
|
||||
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
|
||||
|
||||
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
|
||||
( portMPU_REGION_NON_SHAREABLE ) |
|
||||
|
|
@ -1087,9 +1088,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
/* Translate the generic region definition contained in xRegions
|
||||
* into the ARMv8 specific MPU settings that are then stored in
|
||||
* xMPUSettings. */
|
||||
ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
|
||||
ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
|
||||
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
|
||||
ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
|
||||
ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
|
||||
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
|
||||
|
||||
/* Start address. */
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
|
||||
|
|
@ -1142,7 +1143,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
|
||||
BaseType_t xPortIsInsideInterrupt( void )
|
||||
{
|
||||
uint32_t ulCurrentInterrupt;
|
||||
uint32_t ulCurrentInterrupt;
|
||||
BaseType_t xReturn;
|
||||
|
||||
/* Obtain the number of the currently executing interrupt. Interrupt Program
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue