Update the Microblaze hardware design and BSP to the latest IP and tool versions.

2025-09-02 04:13:54 -04:00 · 2016-05-09 15:55:51 +00:00 · 2016-05-09 15:55:51 +00:00 · 501be60574
commit 501be60574
parent 324127837c
165 changed files with 3287 additions and 15005 deletions
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include/xparameters.h
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include/xparameters.h
@ -15,59 +15,72 @@


 /* Definitions for peripheral MICROBLAZE_0 */
-#define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 15
+#define XPAR_MICROBLAZE_0_ADDR_SIZE 32
+#define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 16
 #define XPAR_MICROBLAZE_0_ALLOW_DCACHE_WR 1
 #define XPAR_MICROBLAZE_0_ALLOW_ICACHE_WR 1
 #define XPAR_MICROBLAZE_0_AREA_OPTIMIZED 0
 #define XPAR_MICROBLAZE_0_ASYNC_INTERRUPT 1
+#define XPAR_MICROBLAZE_0_ASYNC_WAKEUP 3
 #define XPAR_MICROBLAZE_0_AVOID_PRIMITIVES 0
-#define XPAR_MICROBLAZE_0_BASE_VECTORS 0x00000000
+#define XPAR_MICROBLAZE_0_BASE_VECTORS 0x0000000000000000
 #define XPAR_MICROBLAZE_0_BRANCH_TARGET_CACHE_SIZE 0
 #define XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE 32768
+#define XPAR_MICROBLAZE_0_DADDR_SIZE 32
 #define XPAR_MICROBLAZE_0_DATA_SIZE 32
-#define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 15
+#define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 16
 #define XPAR_MICROBLAZE_0_DCACHE_ALWAYS_USED 1
 #define XPAR_MICROBLAZE_0_DCACHE_BASEADDR 0x80000000
 #define XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE 32768
 #define XPAR_MICROBLAZE_0_DCACHE_DATA_WIDTH 0
 #define XPAR_MICROBLAZE_0_DCACHE_FORCE_TAG_LUTRAM 0
-#define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0xBFFFFFFF
+#define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0xFFFFFFFF
 #define XPAR_MICROBLAZE_0_DCACHE_LINE_LEN 8
-#define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 1
-#define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 8
+#define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 0
+#define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 0
+#define XPAR_MICROBLAZE_0_DC_AXI_MON 0
 #define XPAR_MICROBLAZE_0_DEBUG_COUNTER_WIDTH 32
-#define XPAR_MICROBLAZE_0_DEBUG_ENABLED 1
+#define XPAR_MICROBLAZE_0_DEBUG_ENABLED 2
 #define XPAR_MICROBLAZE_0_DEBUG_EVENT_COUNTERS 5
 #define XPAR_MICROBLAZE_0_DEBUG_EXTERNAL_TRACE 0
 #define XPAR_MICROBLAZE_0_DEBUG_LATENCY_COUNTERS 1
 #define XPAR_MICROBLAZE_0_DEBUG_PROFILE_SIZE 0
 #define XPAR_MICROBLAZE_0_DEBUG_TRACE_SIZE 8192
-#define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 1
+#define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 0
+#define XPAR_MICROBLAZE_0_DP_AXI_MON 0
 #define XPAR_MICROBLAZE_0_DYNAMIC_BUS_SIZING 0
 #define XPAR_MICROBLAZE_0_D_AXI 1
 #define XPAR_MICROBLAZE_0_D_LMB 1
+#define XPAR_MICROBLAZE_0_D_LMB_MON 0
 #define XPAR_MICROBLAZE_0_ECC_USE_CE_EXCEPTION 0
 #define XPAR_MICROBLAZE_0_EDGE_IS_POSITIVE 1
 #define XPAR_MICROBLAZE_0_ENABLE_DISCRETE_PORTS 0
 #define XPAR_MICROBLAZE_0_ENDIANNESS 1
 #define XPAR_MICROBLAZE_0_FAULT_TOLERANT 0
-#define XPAR_MICROBLAZE_0_FPU_EXCEPTION 1
+#define XPAR_MICROBLAZE_0_FPU_EXCEPTION 0
 #define XPAR_MICROBLAZE_0_FREQ 100000000
 #define XPAR_MICROBLAZE_0_FSL_EXCEPTION 0
 #define XPAR_MICROBLAZE_0_FSL_LINKS 0
+#define XPAR_MICROBLAZE_0_IADDR_SIZE 32
 #define XPAR_MICROBLAZE_0_ICACHE_ALWAYS_USED 1
 #define XPAR_MICROBLAZE_0_ICACHE_BASEADDR 0x80000000
 #define XPAR_MICROBLAZE_0_ICACHE_DATA_WIDTH 0
 #define XPAR_MICROBLAZE_0_ICACHE_FORCE_TAG_LUTRAM 0
-#define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0xBFFFFFFF
+#define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0xFFFFFFFF
 #define XPAR_MICROBLAZE_0_ICACHE_LINE_LEN 8
-#define XPAR_MICROBLAZE_0_ICACHE_STREAMS 1
-#define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 8
-#define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 1
+#define XPAR_MICROBLAZE_0_ICACHE_STREAMS 0
+#define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 0
+#define XPAR_MICROBLAZE_0_IC_AXI_MON 0
+#define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 0
+#define XPAR_MICROBLAZE_0_IMPRECISE_EXCEPTIONS 0
+#define XPAR_MICROBLAZE_0_INSTR_SIZE 32
 #define XPAR_MICROBLAZE_0_INTERCONNECT 2
 #define XPAR_MICROBLAZE_0_INTERRUPT_IS_EDGE 0
+#define XPAR_MICROBLAZE_0_INTERRUPT_MON 0
+#define XPAR_MICROBLAZE_0_IP_AXI_MON 0
 #define XPAR_MICROBLAZE_0_I_AXI 0
 #define XPAR_MICROBLAZE_0_I_LMB 1
+#define XPAR_MICROBLAZE_0_I_LMB_MON 0
 #define XPAR_MICROBLAZE_0_LOCKSTEP_SELECT 0
 #define XPAR_MICROBLAZE_0_LOCKSTEP_SLAVE 0
 #define XPAR_MICROBLAZE_0_M0_AXIS_DATA_WIDTH 32
@ -106,7 +119,7 @@
 #define XPAR_MICROBLAZE_0_MMU_ITLB_SIZE 2
 #define XPAR_MICROBLAZE_0_MMU_PRIVILEGED_INSTR 0
 #define XPAR_MICROBLAZE_0_MMU_TLB_ACCESS 3
-#define XPAR_MICROBLAZE_0_MMU_ZONES 2
+#define XPAR_MICROBLAZE_0_MMU_ZONES 16
 #define XPAR_MICROBLAZE_0_M_AXI_DC_ADDR_WIDTH 32
 #define XPAR_MICROBLAZE_0_M_AXI_DC_ARUSER_WIDTH 5
 #define XPAR_MICROBLAZE_0_M_AXI_DC_AWUSER_WIDTH 5
@ -122,7 +135,7 @@
 #define XPAR_MICROBLAZE_0_M_AXI_DP_DATA_WIDTH 32
 #define XPAR_MICROBLAZE_0_M_AXI_DP_EXCLUSIVE_ACCESS 0
 #define XPAR_MICROBLAZE_0_M_AXI_DP_THREAD_ID_WIDTH 1
-#define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 1
+#define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 0
 #define XPAR_MICROBLAZE_0_M_AXI_IC_ADDR_WIDTH 32
 #define XPAR_MICROBLAZE_0_M_AXI_IC_ARUSER_WIDTH 5
 #define XPAR_MICROBLAZE_0_M_AXI_IC_AWUSER_WIDTH 5
@ -136,7 +149,7 @@
 #define XPAR_MICROBLAZE_0_M_AXI_IP_ADDR_WIDTH 32
 #define XPAR_MICROBLAZE_0_M_AXI_IP_DATA_WIDTH 32
 #define XPAR_MICROBLAZE_0_M_AXI_IP_THREAD_ID_WIDTH 1
-#define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 1
+#define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 0
 #define XPAR_MICROBLAZE_0_NUMBER_OF_PC_BRK 8
 #define XPAR_MICROBLAZE_0_NUMBER_OF_RD_ADDR_BRK 2
 #define XPAR_MICROBLAZE_0_NUMBER_OF_WR_ADDR_BRK 2
@ -144,7 +157,7 @@
 #define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_DEBUG 2
 #define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_IRQ 1
 #define XPAR_MICROBLAZE_0_NUM_SYNC_FF_DBG_CLK 1
-#define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 1
+#define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 0
 #define XPAR_MICROBLAZE_0_OPTIMIZATION 0
 #define XPAR_MICROBLAZE_0_PC_WIDTH 32
 #define XPAR_MICROBLAZE_0_PVR 0
@ -184,8 +197,8 @@
 #define XPAR_MICROBLAZE_0_S15_AXIS_DATA_WIDTH 32
 #define XPAR_MICROBLAZE_0_S15_AXIS_PROTOCOL GENERIC
 #define XPAR_MICROBLAZE_0_SCO 0
-#define XPAR_MICROBLAZE_0_TRACE 1
-#define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 1
+#define XPAR_MICROBLAZE_0_TRACE 0
+#define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 0
 #define XPAR_MICROBLAZE_0_USE_BARREL 1
 #define XPAR_MICROBLAZE_0_USE_BRANCH_TARGET_CACHE 1
 #define XPAR_MICROBLAZE_0_USE_CONFIG_RESET 0
@ -194,78 +207,92 @@
 #define XPAR_MICROBLAZE_0_USE_EXTENDED_FSL_INSTR 0
 #define XPAR_MICROBLAZE_0_USE_EXT_BRK 0
 #define XPAR_MICROBLAZE_0_USE_EXT_NM_BRK 0
-#define XPAR_MICROBLAZE_0_USE_FPU 2
-#define XPAR_MICROBLAZE_0_USE_HW_MUL 2
+#define XPAR_MICROBLAZE_0_USE_FPU 0
+#define XPAR_MICROBLAZE_0_USE_HW_MUL 0
 #define XPAR_MICROBLAZE_0_USE_ICACHE 1
-#define XPAR_MICROBLAZE_0_USE_INTERRUPT 1
+#define XPAR_MICROBLAZE_0_USE_INTERRUPT 0
 #define XPAR_MICROBLAZE_0_USE_MMU 0
 #define XPAR_MICROBLAZE_0_USE_MSR_INSTR 1
+#define XPAR_MICROBLAZE_0_USE_NON_SECURE 0
 #define XPAR_MICROBLAZE_0_USE_PCMP_INSTR 1
 #define XPAR_MICROBLAZE_0_USE_REORDER_INSTR 1
-#define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 1
-#define XPAR_MICROBLAZE_0_COMPONENT_NAME base_microblaze_design_microblaze_0_0
+#define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 0
+#define XPAR_MICROBLAZE_0_COMPONENT_NAME mb_subsystem_microblaze_0_0
 #define XPAR_MICROBLAZE_0_EDK_IPTYPE PROCESSOR
 #define XPAR_MICROBLAZE_0_EDK_SPECIAL microblaze
-#define XPAR_MICROBLAZE_0_G_TEMPLATE_LIST 2
-#define XPAR_MICROBLAZE_0_G_USE_EXCEPTIONS 1
+#define XPAR_MICROBLAZE_0_G_TEMPLATE_LIST 0
+#define XPAR_MICROBLAZE_0_G_USE_EXCEPTIONS 0

 /******************************************************************/

 #define XPAR_CPU_ID 0
 #define XPAR_MICROBLAZE_ID 0
-#define XPAR_MICROBLAZE_ADDR_TAG_BITS 15
+#define XPAR_MICROBLAZE_ADDR_SIZE 32
+#define XPAR_MICROBLAZE_ADDR_TAG_BITS 16
 #define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
 #define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
 #define XPAR_MICROBLAZE_AREA_OPTIMIZED 0
 #define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1
+#define XPAR_MICROBLAZE_ASYNC_WAKEUP 3
 #define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0
-#define XPAR_MICROBLAZE_BASE_VECTORS 0x00000000
+#define XPAR_MICROBLAZE_BASE_VECTORS 0x0000000000000000
 #define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
 #define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 32768
+#define XPAR_MICROBLAZE_DADDR_SIZE 32
 #define XPAR_MICROBLAZE_DATA_SIZE 32
-#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 15
+#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 16
 #define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 1
 #define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x80000000
 #define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 32768
 #define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0
 #define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
-#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xBFFFFFFF
+#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xFFFFFFFF
 #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 8
-#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 1
-#define XPAR_MICROBLAZE_DCACHE_VICTIMS 8
+#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 0
+#define XPAR_MICROBLAZE_DCACHE_VICTIMS 0
+#define XPAR_MICROBLAZE_DC_AXI_MON 0
 #define XPAR_MICROBLAZE_DEBUG_COUNTER_WIDTH 32
-#define XPAR_MICROBLAZE_DEBUG_ENABLED 1
+#define XPAR_MICROBLAZE_DEBUG_ENABLED 2
 #define XPAR_MICROBLAZE_DEBUG_EVENT_COUNTERS 5
 #define XPAR_MICROBLAZE_DEBUG_EXTERNAL_TRACE 0
 #define XPAR_MICROBLAZE_DEBUG_LATENCY_COUNTERS 1
 #define XPAR_MICROBLAZE_DEBUG_PROFILE_SIZE 0
 #define XPAR_MICROBLAZE_DEBUG_TRACE_SIZE 8192
-#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 1
+#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 0
+#define XPAR_MICROBLAZE_DP_AXI_MON 0
 #define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0
 #define XPAR_MICROBLAZE_D_AXI 1
 #define XPAR_MICROBLAZE_D_LMB 1
+#define XPAR_MICROBLAZE_D_LMB_MON 0
 #define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
 #define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
 #define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 0
 #define XPAR_MICROBLAZE_ENDIANNESS 1
 #define XPAR_MICROBLAZE_FAULT_TOLERANT 0
-#define XPAR_MICROBLAZE_FPU_EXCEPTION 1
+#define XPAR_MICROBLAZE_FPU_EXCEPTION 0
 #define XPAR_MICROBLAZE_FREQ 100000000
 #define XPAR_MICROBLAZE_FSL_EXCEPTION 0
 #define XPAR_MICROBLAZE_FSL_LINKS 0
+#define XPAR_MICROBLAZE_IADDR_SIZE 32
 #define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 1
 #define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x80000000
 #define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0
 #define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
-#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xBFFFFFFF
+#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xFFFFFFFF
 #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 8
-#define XPAR_MICROBLAZE_ICACHE_STREAMS 1
-#define XPAR_MICROBLAZE_ICACHE_VICTIMS 8
-#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1
+#define XPAR_MICROBLAZE_ICACHE_STREAMS 0
+#define XPAR_MICROBLAZE_ICACHE_VICTIMS 0
+#define XPAR_MICROBLAZE_IC_AXI_MON 0
+#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 0
+#define XPAR_MICROBLAZE_IMPRECISE_EXCEPTIONS 0
+#define XPAR_MICROBLAZE_INSTR_SIZE 32
 #define XPAR_MICROBLAZE_INTERCONNECT 2
 #define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
+#define XPAR_MICROBLAZE_INTERRUPT_MON 0
+#define XPAR_MICROBLAZE_IP_AXI_MON 0
 #define XPAR_MICROBLAZE_I_AXI 0
 #define XPAR_MICROBLAZE_I_LMB 1
+#define XPAR_MICROBLAZE_I_LMB_MON 0
 #define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0
 #define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
 #define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32
@ -304,7 +331,7 @@
 #define XPAR_MICROBLAZE_MMU_ITLB_SIZE 2
 #define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
 #define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
-#define XPAR_MICROBLAZE_MMU_ZONES 2
+#define XPAR_MICROBLAZE_MMU_ZONES 16
 #define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32
 #define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5
 #define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5
@ -320,7 +347,7 @@
 #define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32
 #define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0
 #define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1
-#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 1
+#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 0
 #define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32
 #define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5
 #define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5
@ -334,7 +361,7 @@
 #define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32
 #define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32
 #define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1
-#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 1
+#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 0
 #define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 8
 #define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 2
 #define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 2
@ -342,7 +369,7 @@
 #define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_DEBUG 2
 #define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_IRQ 1
 #define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_CLK 1
-#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1
+#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 0
 #define XPAR_MICROBLAZE_OPTIMIZATION 0
 #define XPAR_MICROBLAZE_PC_WIDTH 32
 #define XPAR_MICROBLAZE_PVR 0
@ -382,8 +409,8 @@
 #define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32
 #define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC
 #define XPAR_MICROBLAZE_SCO 0
-#define XPAR_MICROBLAZE_TRACE 1
-#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1
+#define XPAR_MICROBLAZE_TRACE 0
+#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 0
 #define XPAR_MICROBLAZE_USE_BARREL 1
 #define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 1
 #define XPAR_MICROBLAZE_USE_CONFIG_RESET 0
@ -392,23 +419,26 @@
 #define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
 #define XPAR_MICROBLAZE_USE_EXT_BRK 0
 #define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
-#define XPAR_MICROBLAZE_USE_FPU 2
-#define XPAR_MICROBLAZE_USE_HW_MUL 2
+#define XPAR_MICROBLAZE_USE_FPU 0
+#define XPAR_MICROBLAZE_USE_HW_MUL 0
 #define XPAR_MICROBLAZE_USE_ICACHE 1
-#define XPAR_MICROBLAZE_USE_INTERRUPT 1
+#define XPAR_MICROBLAZE_USE_INTERRUPT 0
 #define XPAR_MICROBLAZE_USE_MMU 0
 #define XPAR_MICROBLAZE_USE_MSR_INSTR 1
+#define XPAR_MICROBLAZE_USE_NON_SECURE 0
 #define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
 #define XPAR_MICROBLAZE_USE_REORDER_INSTR 1
-#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 1
-#define XPAR_MICROBLAZE_COMPONENT_NAME base_microblaze_design_microblaze_0_0
+#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 0
+#define XPAR_MICROBLAZE_COMPONENT_NAME mb_subsystem_microblaze_0_0
 #define XPAR_MICROBLAZE_EDK_IPTYPE PROCESSOR
 #define XPAR_MICROBLAZE_EDK_SPECIAL microblaze
-#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 2
-#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1
+#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 0
+#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 0

 /******************************************************************/

+#define STDIN_BASEADDRESS 0x40600000
+#define STDOUT_BASEADDRESS 0x40600000

 /******************************************************************/

@ -428,7 +458,7 @@
 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1
 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS 2
 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR 0x00000000
-#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF
+#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0000FFFF
 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF 
 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF 

@ -446,7 +476,7 @@
 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1
 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS 2
 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR 0x00000000
-#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF
+#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0000FFFF
 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF 
 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF 

@ -466,7 +496,7 @@
 #define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 1
 #define XPAR_BRAM_0_WRITE_ACCESS 2
 #define XPAR_BRAM_0_BASEADDR 0x00000000
-#define XPAR_BRAM_0_HIGHADDR 0x0003FFFF
+#define XPAR_BRAM_0_HIGHADDR 0x0000FFFF

 /* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
 #define XPAR_BRAM_1_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID
@ -481,7 +511,7 @@
 #define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 1
 #define XPAR_BRAM_1_WRITE_ACCESS 2
 #define XPAR_BRAM_1_BASEADDR 0x00000000
-#define XPAR_BRAM_1_HIGHADDR 0x0003FFFF
+#define XPAR_BRAM_1_HIGHADDR 0x0000FFFF


 /******************************************************************/
@ -534,55 +564,6 @@
 #define XPAR_GPIO_0_IS_DUAL 0


-/******************************************************************/
-
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
-#define XPAR_XINTC_HAS_IPR 1
-#define XPAR_XINTC_HAS_SIE 1
-#define XPAR_XINTC_HAS_CIE 1
-#define XPAR_XINTC_HAS_IVR 1
-/* Definitions for driver INTC */
-#define XPAR_XINTC_NUM_INSTANCES 1
-
-/* Definitions for peripheral AXI_INTC_0 */
-#define XPAR_AXI_INTC_0_DEVICE_ID 0
-#define XPAR_AXI_INTC_0_BASEADDR 0x41200000
-#define XPAR_AXI_INTC_0_HIGHADDR 0x4120FFFF
-#define XPAR_AXI_INTC_0_KIND_OF_INTR 0xFFFFFFFE
-#define XPAR_AXI_INTC_0_HAS_FAST 0
-#define XPAR_AXI_INTC_0_IVAR_RESET_VALUE 0x00000010
-#define XPAR_AXI_INTC_0_NUM_INTR_INPUTS 3
-
-
-/******************************************************************/
-
-#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
-#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
-#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
-#define XPAR_AXI_INTC_0_TYPE 0
-#define XPAR_AXI_TIMER_0_INTERRUPT_MASK 0X000001
-#define XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR 0
-#define XPAR_AXI_UARTLITE_0_INTERRUPT_MASK 0X000002
-#define XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR 1
-#define XPAR_AXI_ETHERNETLITE_0_IP2INTC_IRPT_MASK 0X000004
-#define XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR 2
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral AXI_INTC_0 */
-#define XPAR_INTC_0_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
-#define XPAR_INTC_0_BASEADDR 0x41200000
-#define XPAR_INTC_0_HIGHADDR 0x4120FFFF
-#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFFE
-#define XPAR_INTC_0_HAS_FAST 0
-#define XPAR_INTC_0_IVAR_RESET_VALUE 0x00000010
-#define XPAR_INTC_0_NUM_INTR_INPUTS 3
-#define XPAR_INTC_0_INTC_TYPE 0
-
-#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR
-#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR
-#define XPAR_INTC_0_EMACLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR
-
 /******************************************************************/

 /* Definitions for driver MIG_7SERIES */
@ -601,7 +582,7 @@

 /* Definitions for peripheral MIG_7SERIES_0 */
 #define XPAR_MIG_7SERIES_0_BASEADDR 0x80000000
-#define XPAR_MIG_7SERIES_0_HIGHADDR 0xBFFFFFFF
+#define XPAR_MIG_7SERIES_0_HIGHADDR 0x9FFFFFFF


 /******************************************************************/
@ -613,29 +594,9 @@
 #define XPAR_MIG7SERIES_0_DDR_BANK_WIDTH 3
 #define XPAR_MIG7SERIES_0_DDR_DQ_WIDTH 64
 #define XPAR_MIG7SERIES_0_BASEADDR 0x80000000
-#define XPAR_MIG7SERIES_0_HIGHADDR 0xBFFFFFFF
+#define XPAR_MIG7SERIES_0_HIGHADDR 0x9FFFFFFF


-/******************************************************************/
-
-/* Definitions for driver TMRCTR */
-#define XPAR_XTMRCTR_NUM_INSTANCES 1
-
-/* Definitions for peripheral AXI_TIMER_0 */
-#define XPAR_AXI_TIMER_0_DEVICE_ID 0
-#define XPAR_AXI_TIMER_0_BASEADDR 0x41C00000
-#define XPAR_AXI_TIMER_0_HIGHADDR 0x41C0FFFF
-#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral AXI_TIMER_0 */
-#define XPAR_TMRCTR_0_DEVICE_ID 0
-#define XPAR_TMRCTR_0_BASEADDR 0x41C00000
-#define XPAR_TMRCTR_0_HIGHADDR 0x41C0FFFF
-#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ
-
 /******************************************************************/

 /* Definitions for driver UARTLITE */
@ -645,7 +606,7 @@
 #define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000
 #define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060FFFF
 #define XPAR_AXI_UARTLITE_0_DEVICE_ID 0
-#define XPAR_AXI_UARTLITE_0_BAUDRATE 115200
+#define XPAR_AXI_UARTLITE_0_BAUDRATE 9600
 #define XPAR_AXI_UARTLITE_0_USE_PARITY 0
 #define XPAR_AXI_UARTLITE_0_ODD_PARITY 0
 #define XPAR_AXI_UARTLITE_0_DATA_BITS 8
@ -657,7 +618,7 @@
 #define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID
 #define XPAR_UARTLITE_0_BASEADDR 0x40600000
 #define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF
-#define XPAR_UARTLITE_0_BAUDRATE 115200
+#define XPAR_UARTLITE_0_BAUDRATE 9600
 #define XPAR_UARTLITE_0_USE_PARITY 0
 #define XPAR_UARTLITE_0_ODD_PARITY 0
 #define XPAR_UARTLITE_0_DATA_BITS 8