diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.cproject b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.cproject index 9e3529d0e..e8461948d 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.cproject +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.cproject @@ -1,8 +1,8 @@ - - + + diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.project b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.project index c2e688345..deb175a44 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.project +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.project @@ -1,7 +1,7 @@ BSP - Created by SDK v2014.4 + Created by SDK v2016.1 diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/Makefile b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/Makefile index 2c54e151e..58469a55c 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/Makefile +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/Makefile @@ -21,11 +21,11 @@ $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) @echo "Running Make include in $(subst /make.include,,$@)" - $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.4 -mhard-float -mlittle-endian -mno-xl-soft-div -mno-xl-soft-mul -mxl-barrel-shift -mxl-float-convert -mxl-float-sqrt -mxl-multiply-high -mxl-pattern-compare" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.6 -mlittle-endian -mno-xl-soft-div -mxl-barrel-shift -mxl-pattern-compare -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-g" %/make.libs: include @echo "Running Make libs in $(subst /make.libs,,$@)" - $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.4 -mhard-float -mlittle-endian -mno-xl-soft-div -mno-xl-soft-mul -mxl-barrel-shift -mxl-float-convert -mxl-float-sqrt -mxl-multiply-high -mxl-pattern-compare" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.6 -mlittle-endian -mno-xl-soft-div -mxl-barrel-shift -mxl-pattern-compare -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-g" clean: rm -f ${PROCESSOR}/lib/libxil.a diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include/xparameters.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include/xparameters.h index a2bb142c9..59c464bc7 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include/xparameters.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include/xparameters.h @@ -15,59 +15,72 @@ /* Definitions for peripheral MICROBLAZE_0 */ -#define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 15 +#define XPAR_MICROBLAZE_0_ADDR_SIZE 32 +#define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 16 #define XPAR_MICROBLAZE_0_ALLOW_DCACHE_WR 1 #define XPAR_MICROBLAZE_0_ALLOW_ICACHE_WR 1 #define XPAR_MICROBLAZE_0_AREA_OPTIMIZED 0 #define XPAR_MICROBLAZE_0_ASYNC_INTERRUPT 1 +#define XPAR_MICROBLAZE_0_ASYNC_WAKEUP 3 #define XPAR_MICROBLAZE_0_AVOID_PRIMITIVES 0 -#define XPAR_MICROBLAZE_0_BASE_VECTORS 0x00000000 +#define XPAR_MICROBLAZE_0_BASE_VECTORS 0x0000000000000000 #define XPAR_MICROBLAZE_0_BRANCH_TARGET_CACHE_SIZE 0 #define XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE 32768 +#define XPAR_MICROBLAZE_0_DADDR_SIZE 32 #define XPAR_MICROBLAZE_0_DATA_SIZE 32 -#define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 15 +#define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 16 #define XPAR_MICROBLAZE_0_DCACHE_ALWAYS_USED 1 #define XPAR_MICROBLAZE_0_DCACHE_BASEADDR 0x80000000 #define XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE 32768 #define XPAR_MICROBLAZE_0_DCACHE_DATA_WIDTH 0 #define XPAR_MICROBLAZE_0_DCACHE_FORCE_TAG_LUTRAM 0 -#define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0xBFFFFFFF +#define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0xFFFFFFFF #define XPAR_MICROBLAZE_0_DCACHE_LINE_LEN 8 -#define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 1 -#define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 8 +#define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 0 +#define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 0 +#define XPAR_MICROBLAZE_0_DC_AXI_MON 0 #define XPAR_MICROBLAZE_0_DEBUG_COUNTER_WIDTH 32 -#define XPAR_MICROBLAZE_0_DEBUG_ENABLED 1 +#define XPAR_MICROBLAZE_0_DEBUG_ENABLED 2 #define XPAR_MICROBLAZE_0_DEBUG_EVENT_COUNTERS 5 #define XPAR_MICROBLAZE_0_DEBUG_EXTERNAL_TRACE 0 #define XPAR_MICROBLAZE_0_DEBUG_LATENCY_COUNTERS 1 #define XPAR_MICROBLAZE_0_DEBUG_PROFILE_SIZE 0 #define XPAR_MICROBLAZE_0_DEBUG_TRACE_SIZE 8192 -#define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 1 +#define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 0 +#define XPAR_MICROBLAZE_0_DP_AXI_MON 0 #define XPAR_MICROBLAZE_0_DYNAMIC_BUS_SIZING 0 #define XPAR_MICROBLAZE_0_D_AXI 1 #define XPAR_MICROBLAZE_0_D_LMB 1 +#define XPAR_MICROBLAZE_0_D_LMB_MON 0 #define XPAR_MICROBLAZE_0_ECC_USE_CE_EXCEPTION 0 #define XPAR_MICROBLAZE_0_EDGE_IS_POSITIVE 1 #define XPAR_MICROBLAZE_0_ENABLE_DISCRETE_PORTS 0 #define XPAR_MICROBLAZE_0_ENDIANNESS 1 #define XPAR_MICROBLAZE_0_FAULT_TOLERANT 0 -#define XPAR_MICROBLAZE_0_FPU_EXCEPTION 1 +#define XPAR_MICROBLAZE_0_FPU_EXCEPTION 0 #define XPAR_MICROBLAZE_0_FREQ 100000000 #define XPAR_MICROBLAZE_0_FSL_EXCEPTION 0 #define XPAR_MICROBLAZE_0_FSL_LINKS 0 +#define XPAR_MICROBLAZE_0_IADDR_SIZE 32 #define XPAR_MICROBLAZE_0_ICACHE_ALWAYS_USED 1 #define XPAR_MICROBLAZE_0_ICACHE_BASEADDR 0x80000000 #define XPAR_MICROBLAZE_0_ICACHE_DATA_WIDTH 0 #define XPAR_MICROBLAZE_0_ICACHE_FORCE_TAG_LUTRAM 0 -#define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0xBFFFFFFF +#define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0xFFFFFFFF #define XPAR_MICROBLAZE_0_ICACHE_LINE_LEN 8 -#define XPAR_MICROBLAZE_0_ICACHE_STREAMS 1 -#define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 8 -#define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 1 +#define XPAR_MICROBLAZE_0_ICACHE_STREAMS 0 +#define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 0 +#define XPAR_MICROBLAZE_0_IC_AXI_MON 0 +#define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 0 +#define XPAR_MICROBLAZE_0_IMPRECISE_EXCEPTIONS 0 +#define XPAR_MICROBLAZE_0_INSTR_SIZE 32 #define XPAR_MICROBLAZE_0_INTERCONNECT 2 #define XPAR_MICROBLAZE_0_INTERRUPT_IS_EDGE 0 +#define XPAR_MICROBLAZE_0_INTERRUPT_MON 0 +#define XPAR_MICROBLAZE_0_IP_AXI_MON 0 #define XPAR_MICROBLAZE_0_I_AXI 0 #define XPAR_MICROBLAZE_0_I_LMB 1 +#define XPAR_MICROBLAZE_0_I_LMB_MON 0 #define XPAR_MICROBLAZE_0_LOCKSTEP_SELECT 0 #define XPAR_MICROBLAZE_0_LOCKSTEP_SLAVE 0 #define XPAR_MICROBLAZE_0_M0_AXIS_DATA_WIDTH 32 @@ -106,7 +119,7 @@ #define XPAR_MICROBLAZE_0_MMU_ITLB_SIZE 2 #define XPAR_MICROBLAZE_0_MMU_PRIVILEGED_INSTR 0 #define XPAR_MICROBLAZE_0_MMU_TLB_ACCESS 3 -#define XPAR_MICROBLAZE_0_MMU_ZONES 2 +#define XPAR_MICROBLAZE_0_MMU_ZONES 16 #define XPAR_MICROBLAZE_0_M_AXI_DC_ADDR_WIDTH 32 #define XPAR_MICROBLAZE_0_M_AXI_DC_ARUSER_WIDTH 5 #define XPAR_MICROBLAZE_0_M_AXI_DC_AWUSER_WIDTH 5 @@ -122,7 +135,7 @@ #define XPAR_MICROBLAZE_0_M_AXI_DP_DATA_WIDTH 32 #define XPAR_MICROBLAZE_0_M_AXI_DP_EXCLUSIVE_ACCESS 0 #define XPAR_MICROBLAZE_0_M_AXI_DP_THREAD_ID_WIDTH 1 -#define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 1 +#define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 0 #define XPAR_MICROBLAZE_0_M_AXI_IC_ADDR_WIDTH 32 #define XPAR_MICROBLAZE_0_M_AXI_IC_ARUSER_WIDTH 5 #define XPAR_MICROBLAZE_0_M_AXI_IC_AWUSER_WIDTH 5 @@ -136,7 +149,7 @@ #define XPAR_MICROBLAZE_0_M_AXI_IP_ADDR_WIDTH 32 #define XPAR_MICROBLAZE_0_M_AXI_IP_DATA_WIDTH 32 #define XPAR_MICROBLAZE_0_M_AXI_IP_THREAD_ID_WIDTH 1 -#define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 1 +#define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 0 #define XPAR_MICROBLAZE_0_NUMBER_OF_PC_BRK 8 #define XPAR_MICROBLAZE_0_NUMBER_OF_RD_ADDR_BRK 2 #define XPAR_MICROBLAZE_0_NUMBER_OF_WR_ADDR_BRK 2 @@ -144,7 +157,7 @@ #define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_DEBUG 2 #define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_IRQ 1 #define XPAR_MICROBLAZE_0_NUM_SYNC_FF_DBG_CLK 1 -#define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 1 +#define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 0 #define XPAR_MICROBLAZE_0_OPTIMIZATION 0 #define XPAR_MICROBLAZE_0_PC_WIDTH 32 #define XPAR_MICROBLAZE_0_PVR 0 @@ -184,8 +197,8 @@ #define XPAR_MICROBLAZE_0_S15_AXIS_DATA_WIDTH 32 #define XPAR_MICROBLAZE_0_S15_AXIS_PROTOCOL GENERIC #define XPAR_MICROBLAZE_0_SCO 0 -#define XPAR_MICROBLAZE_0_TRACE 1 -#define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 1 +#define XPAR_MICROBLAZE_0_TRACE 0 +#define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 0 #define XPAR_MICROBLAZE_0_USE_BARREL 1 #define XPAR_MICROBLAZE_0_USE_BRANCH_TARGET_CACHE 1 #define XPAR_MICROBLAZE_0_USE_CONFIG_RESET 0 @@ -194,78 +207,92 @@ #define XPAR_MICROBLAZE_0_USE_EXTENDED_FSL_INSTR 0 #define XPAR_MICROBLAZE_0_USE_EXT_BRK 0 #define XPAR_MICROBLAZE_0_USE_EXT_NM_BRK 0 -#define XPAR_MICROBLAZE_0_USE_FPU 2 -#define XPAR_MICROBLAZE_0_USE_HW_MUL 2 +#define XPAR_MICROBLAZE_0_USE_FPU 0 +#define XPAR_MICROBLAZE_0_USE_HW_MUL 0 #define XPAR_MICROBLAZE_0_USE_ICACHE 1 -#define XPAR_MICROBLAZE_0_USE_INTERRUPT 1 +#define XPAR_MICROBLAZE_0_USE_INTERRUPT 0 #define XPAR_MICROBLAZE_0_USE_MMU 0 #define XPAR_MICROBLAZE_0_USE_MSR_INSTR 1 +#define XPAR_MICROBLAZE_0_USE_NON_SECURE 0 #define XPAR_MICROBLAZE_0_USE_PCMP_INSTR 1 #define XPAR_MICROBLAZE_0_USE_REORDER_INSTR 1 -#define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 1 -#define XPAR_MICROBLAZE_0_COMPONENT_NAME base_microblaze_design_microblaze_0_0 +#define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 0 +#define XPAR_MICROBLAZE_0_COMPONENT_NAME mb_subsystem_microblaze_0_0 #define XPAR_MICROBLAZE_0_EDK_IPTYPE PROCESSOR #define XPAR_MICROBLAZE_0_EDK_SPECIAL microblaze -#define XPAR_MICROBLAZE_0_G_TEMPLATE_LIST 2 -#define XPAR_MICROBLAZE_0_G_USE_EXCEPTIONS 1 +#define XPAR_MICROBLAZE_0_G_TEMPLATE_LIST 0 +#define XPAR_MICROBLAZE_0_G_USE_EXCEPTIONS 0 /******************************************************************/ #define XPAR_CPU_ID 0 #define XPAR_MICROBLAZE_ID 0 -#define XPAR_MICROBLAZE_ADDR_TAG_BITS 15 +#define XPAR_MICROBLAZE_ADDR_SIZE 32 +#define XPAR_MICROBLAZE_ADDR_TAG_BITS 16 #define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1 #define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1 #define XPAR_MICROBLAZE_AREA_OPTIMIZED 0 #define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1 +#define XPAR_MICROBLAZE_ASYNC_WAKEUP 3 #define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0 -#define XPAR_MICROBLAZE_BASE_VECTORS 0x00000000 +#define XPAR_MICROBLAZE_BASE_VECTORS 0x0000000000000000 #define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0 #define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 32768 +#define XPAR_MICROBLAZE_DADDR_SIZE 32 #define XPAR_MICROBLAZE_DATA_SIZE 32 -#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 15 +#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 16 #define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 1 #define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x80000000 #define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 32768 #define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0 #define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0 -#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xBFFFFFFF +#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xFFFFFFFF #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 8 -#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 1 -#define XPAR_MICROBLAZE_DCACHE_VICTIMS 8 +#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 0 +#define XPAR_MICROBLAZE_DCACHE_VICTIMS 0 +#define XPAR_MICROBLAZE_DC_AXI_MON 0 #define XPAR_MICROBLAZE_DEBUG_COUNTER_WIDTH 32 -#define XPAR_MICROBLAZE_DEBUG_ENABLED 1 +#define XPAR_MICROBLAZE_DEBUG_ENABLED 2 #define XPAR_MICROBLAZE_DEBUG_EVENT_COUNTERS 5 #define XPAR_MICROBLAZE_DEBUG_EXTERNAL_TRACE 0 #define XPAR_MICROBLAZE_DEBUG_LATENCY_COUNTERS 1 #define XPAR_MICROBLAZE_DEBUG_PROFILE_SIZE 0 #define XPAR_MICROBLAZE_DEBUG_TRACE_SIZE 8192 -#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 1 +#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 0 +#define XPAR_MICROBLAZE_DP_AXI_MON 0 #define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0 #define XPAR_MICROBLAZE_D_AXI 1 #define XPAR_MICROBLAZE_D_LMB 1 +#define XPAR_MICROBLAZE_D_LMB_MON 0 #define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0 #define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1 #define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 0 #define XPAR_MICROBLAZE_ENDIANNESS 1 #define XPAR_MICROBLAZE_FAULT_TOLERANT 0 -#define XPAR_MICROBLAZE_FPU_EXCEPTION 1 +#define XPAR_MICROBLAZE_FPU_EXCEPTION 0 #define XPAR_MICROBLAZE_FREQ 100000000 #define XPAR_MICROBLAZE_FSL_EXCEPTION 0 #define XPAR_MICROBLAZE_FSL_LINKS 0 +#define XPAR_MICROBLAZE_IADDR_SIZE 32 #define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 1 #define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x80000000 #define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0 #define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0 -#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xBFFFFFFF +#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xFFFFFFFF #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 8 -#define XPAR_MICROBLAZE_ICACHE_STREAMS 1 -#define XPAR_MICROBLAZE_ICACHE_VICTIMS 8 -#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1 +#define XPAR_MICROBLAZE_ICACHE_STREAMS 0 +#define XPAR_MICROBLAZE_ICACHE_VICTIMS 0 +#define XPAR_MICROBLAZE_IC_AXI_MON 0 +#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 0 +#define XPAR_MICROBLAZE_IMPRECISE_EXCEPTIONS 0 +#define XPAR_MICROBLAZE_INSTR_SIZE 32 #define XPAR_MICROBLAZE_INTERCONNECT 2 #define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0 +#define XPAR_MICROBLAZE_INTERRUPT_MON 0 +#define XPAR_MICROBLAZE_IP_AXI_MON 0 #define XPAR_MICROBLAZE_I_AXI 0 #define XPAR_MICROBLAZE_I_LMB 1 +#define XPAR_MICROBLAZE_I_LMB_MON 0 #define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0 #define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0 #define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32 @@ -304,7 +331,7 @@ #define XPAR_MICROBLAZE_MMU_ITLB_SIZE 2 #define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0 #define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3 -#define XPAR_MICROBLAZE_MMU_ZONES 2 +#define XPAR_MICROBLAZE_MMU_ZONES 16 #define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32 #define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5 #define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5 @@ -320,7 +347,7 @@ #define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32 #define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0 #define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1 -#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 1 +#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 0 #define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32 #define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5 #define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5 @@ -334,7 +361,7 @@ #define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32 #define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32 #define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1 -#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 1 +#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 0 #define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 8 #define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 2 #define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 2 @@ -342,7 +369,7 @@ #define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_DEBUG 2 #define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_IRQ 1 #define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_CLK 1 -#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1 +#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 0 #define XPAR_MICROBLAZE_OPTIMIZATION 0 #define XPAR_MICROBLAZE_PC_WIDTH 32 #define XPAR_MICROBLAZE_PVR 0 @@ -382,8 +409,8 @@ #define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32 #define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC #define XPAR_MICROBLAZE_SCO 0 -#define XPAR_MICROBLAZE_TRACE 1 -#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1 +#define XPAR_MICROBLAZE_TRACE 0 +#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 0 #define XPAR_MICROBLAZE_USE_BARREL 1 #define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 1 #define XPAR_MICROBLAZE_USE_CONFIG_RESET 0 @@ -392,23 +419,26 @@ #define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0 #define XPAR_MICROBLAZE_USE_EXT_BRK 0 #define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0 -#define XPAR_MICROBLAZE_USE_FPU 2 -#define XPAR_MICROBLAZE_USE_HW_MUL 2 +#define XPAR_MICROBLAZE_USE_FPU 0 +#define XPAR_MICROBLAZE_USE_HW_MUL 0 #define XPAR_MICROBLAZE_USE_ICACHE 1 -#define XPAR_MICROBLAZE_USE_INTERRUPT 1 +#define XPAR_MICROBLAZE_USE_INTERRUPT 0 #define XPAR_MICROBLAZE_USE_MMU 0 #define XPAR_MICROBLAZE_USE_MSR_INSTR 1 +#define XPAR_MICROBLAZE_USE_NON_SECURE 0 #define XPAR_MICROBLAZE_USE_PCMP_INSTR 1 #define XPAR_MICROBLAZE_USE_REORDER_INSTR 1 -#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 1 -#define XPAR_MICROBLAZE_COMPONENT_NAME base_microblaze_design_microblaze_0_0 +#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 0 +#define XPAR_MICROBLAZE_COMPONENT_NAME mb_subsystem_microblaze_0_0 #define XPAR_MICROBLAZE_EDK_IPTYPE PROCESSOR #define XPAR_MICROBLAZE_EDK_SPECIAL microblaze -#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 2 -#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1 +#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 0 +#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 0 /******************************************************************/ +#define STDIN_BASEADDRESS 0x40600000 +#define STDOUT_BASEADDRESS 0x40600000 /******************************************************************/ @@ -428,7 +458,7 @@ #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS 2 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR 0x00000000 -#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF +#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0000FFFF #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF @@ -446,7 +476,7 @@ #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS 2 #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR 0x00000000 -#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF +#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0000FFFF #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF #define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF @@ -466,7 +496,7 @@ #define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 1 #define XPAR_BRAM_0_WRITE_ACCESS 2 #define XPAR_BRAM_0_BASEADDR 0x00000000 -#define XPAR_BRAM_0_HIGHADDR 0x0003FFFF +#define XPAR_BRAM_0_HIGHADDR 0x0000FFFF /* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */ #define XPAR_BRAM_1_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID @@ -481,7 +511,7 @@ #define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 1 #define XPAR_BRAM_1_WRITE_ACCESS 2 #define XPAR_BRAM_1_BASEADDR 0x00000000 -#define XPAR_BRAM_1_HIGHADDR 0x0003FFFF +#define XPAR_BRAM_1_HIGHADDR 0x0000FFFF /******************************************************************/ @@ -534,55 +564,6 @@ #define XPAR_GPIO_0_IS_DUAL 0 -/******************************************************************/ - -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3 -#define XPAR_XINTC_HAS_IPR 1 -#define XPAR_XINTC_HAS_SIE 1 -#define XPAR_XINTC_HAS_CIE 1 -#define XPAR_XINTC_HAS_IVR 1 -/* Definitions for driver INTC */ -#define XPAR_XINTC_NUM_INSTANCES 1 - -/* Definitions for peripheral AXI_INTC_0 */ -#define XPAR_AXI_INTC_0_DEVICE_ID 0 -#define XPAR_AXI_INTC_0_BASEADDR 0x41200000 -#define XPAR_AXI_INTC_0_HIGHADDR 0x4120FFFF -#define XPAR_AXI_INTC_0_KIND_OF_INTR 0xFFFFFFFE -#define XPAR_AXI_INTC_0_HAS_FAST 0 -#define XPAR_AXI_INTC_0_IVAR_RESET_VALUE 0x00000010 -#define XPAR_AXI_INTC_0_NUM_INTR_INPUTS 3 - - -/******************************************************************/ - -#define XPAR_INTC_SINGLE_BASEADDR 0x41200000 -#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF -#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID -#define XPAR_AXI_INTC_0_TYPE 0 -#define XPAR_AXI_TIMER_0_INTERRUPT_MASK 0X000001 -#define XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR 0 -#define XPAR_AXI_UARTLITE_0_INTERRUPT_MASK 0X000002 -#define XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR 1 -#define XPAR_AXI_ETHERNETLITE_0_IP2INTC_IRPT_MASK 0X000004 -#define XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR 2 - -/******************************************************************/ - -/* Canonical definitions for peripheral AXI_INTC_0 */ -#define XPAR_INTC_0_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID -#define XPAR_INTC_0_BASEADDR 0x41200000 -#define XPAR_INTC_0_HIGHADDR 0x4120FFFF -#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFFE -#define XPAR_INTC_0_HAS_FAST 0 -#define XPAR_INTC_0_IVAR_RESET_VALUE 0x00000010 -#define XPAR_INTC_0_NUM_INTR_INPUTS 3 -#define XPAR_INTC_0_INTC_TYPE 0 - -#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR -#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR -#define XPAR_INTC_0_EMACLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR - /******************************************************************/ /* Definitions for driver MIG_7SERIES */ @@ -601,7 +582,7 @@ /* Definitions for peripheral MIG_7SERIES_0 */ #define XPAR_MIG_7SERIES_0_BASEADDR 0x80000000 -#define XPAR_MIG_7SERIES_0_HIGHADDR 0xBFFFFFFF +#define XPAR_MIG_7SERIES_0_HIGHADDR 0x9FFFFFFF /******************************************************************/ @@ -613,29 +594,9 @@ #define XPAR_MIG7SERIES_0_DDR_BANK_WIDTH 3 #define XPAR_MIG7SERIES_0_DDR_DQ_WIDTH 64 #define XPAR_MIG7SERIES_0_BASEADDR 0x80000000 -#define XPAR_MIG7SERIES_0_HIGHADDR 0xBFFFFFFF +#define XPAR_MIG7SERIES_0_HIGHADDR 0x9FFFFFFF -/******************************************************************/ - -/* Definitions for driver TMRCTR */ -#define XPAR_XTMRCTR_NUM_INSTANCES 1 - -/* Definitions for peripheral AXI_TIMER_0 */ -#define XPAR_AXI_TIMER_0_DEVICE_ID 0 -#define XPAR_AXI_TIMER_0_BASEADDR 0x41C00000 -#define XPAR_AXI_TIMER_0_HIGHADDR 0x41C0FFFF -#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000 - - -/******************************************************************/ - -/* Canonical definitions for peripheral AXI_TIMER_0 */ -#define XPAR_TMRCTR_0_DEVICE_ID 0 -#define XPAR_TMRCTR_0_BASEADDR 0x41C00000 -#define XPAR_TMRCTR_0_HIGHADDR 0x41C0FFFF -#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ - /******************************************************************/ /* Definitions for driver UARTLITE */ @@ -645,7 +606,7 @@ #define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000 #define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060FFFF #define XPAR_AXI_UARTLITE_0_DEVICE_ID 0 -#define XPAR_AXI_UARTLITE_0_BAUDRATE 115200 +#define XPAR_AXI_UARTLITE_0_BAUDRATE 9600 #define XPAR_AXI_UARTLITE_0_USE_PARITY 0 #define XPAR_AXI_UARTLITE_0_ODD_PARITY 0 #define XPAR_AXI_UARTLITE_0_DATA_BITS 8 @@ -657,7 +618,7 @@ #define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID #define XPAR_UARTLITE_0_BASEADDR 0x40600000 #define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF -#define XPAR_UARTLITE_0_BAUDRATE 115200 +#define XPAR_UARTLITE_0_BAUDRATE 9600 #define XPAR_UARTLITE_0_USE_PARITY 0 #define XPAR_UARTLITE_0_ODD_PARITY 0 #define XPAR_UARTLITE_0_DATA_BITS 8 diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/Makefile b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/Makefile similarity index 100% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/Makefile rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/Makefile diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram.c similarity index 95% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram.c index 34b470913..432070827 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,6 +32,8 @@ /** * @file xbram.c +* @addtogroup bram_v4_0 +* @{ * * The implementation of the XBram driver's basic functionality. * See xbram.h for more information about the driver. @@ -49,6 +51,8 @@ * 3.01a sa 13/01/12 Added CorrectableFailingDataRegs and * UncorrectableFailingDataRegs in * XBram_CfgInitialize API. +* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototype of XBram_CfgInitialize API. * * *****************************************************************************/ @@ -104,7 +108,7 @@ *****************************************************************************/ int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config, - u32 EffectiveAddr) + UINTPTR EffectiveAddr) { /* * Assert arguments @@ -142,3 +146,4 @@ int XBram_CfgInitialize(XBram *InstancePtr, return (XST_SUCCESS); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram.h similarity index 95% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram.h index cbbe4d84a..8335cd188 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,6 +32,9 @@ /*****************************************************************************/ /** * @file xbram.h +* @addtogroup bram_v4_0 +* @{ +* @details * * If ECC is not enabled, this driver exists only to allow the tools to * create a memory test application and to populate xparameters.h with memory @@ -108,6 +111,8 @@ * flush the Cache after writing to BRAM in InjectErrors * API(CR #719011) * 4.0 adk 19/12/13 Updated as per the New Tcl API's +* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototype of XBram_CfgInitialize API. * *****************************************************************************/ #ifndef XBRAM_H /* prevent circular inclusions */ @@ -158,8 +163,8 @@ typedef struct { * h/w */ u32 MemBaseAddress; /**< Device memory base address */ u32 MemHighAddress; /**< Device memory high address */ - u32 CtrlBaseAddress; /**< Device register base address.*/ - u32 CtrlHighAddress; /**< Device register base address.*/ + UINTPTR CtrlBaseAddress; /**< Device register base address.*/ + UINTPTR CtrlHighAddress; /**< Device register base address.*/ } XBram_Config; /** @@ -187,7 +192,7 @@ XBram_Config *XBram_LookupConfig(u16 DeviceId); * Functions implemented in xbram.c */ int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config, - u32 EffectiveAddr); + UINTPTR EffectiveAddr); /* * Functions implemented in xbram_selftest.c @@ -208,3 +213,4 @@ u32 XBram_InterruptGetStatus(XBram *InstancePtr); #endif #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c similarity index 94% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_g.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c index ff57a20dc..aa923f4f9 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_g.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -22,8 +22,8 @@ * *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_hw.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_hw.h similarity index 99% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_hw.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_hw.h index fc0e8f6e5..44c5897f8 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_hw.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,8 @@ /** * * @file xbram_hw.h +* @addtogroup bram_v4_0 +* @{ * * This header file contains identifiers and driver functions (or * macros) that can be used to access the device. The user should refer to the @@ -404,3 +406,4 @@ extern "C" { #endif #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_intr.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_intr.c similarity index 98% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_intr.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_intr.c index a411eb93d..a4b2e0ef8 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_intr.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_intr.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,8 @@ /*****************************************************************************/ /** * @file xbram_intr.c +* @addtogroup bram_v4_0 +* @{ * * Implements BRAM interrupt processing functions for the * XBram driver. See xbram.h for more information @@ -233,3 +235,4 @@ u32 XBram_InterruptGetStatus(XBram * InstancePtr) return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress, XBRAM_ECC_EN_IRQ_OFFSET); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_selftest.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_selftest.c similarity index 99% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_selftest.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_selftest.c index a812c3299..0b5f3b412 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_selftest.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_selftest.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,6 +32,8 @@ /*****************************************************************************/ /** * @file xbram_selftest.c +* @addtogroup bram_v4_0 +* @{ * * The implementation of the XBram driver's self test function. This SelfTest * is only applicable if ECC is enabled. @@ -554,3 +556,4 @@ int XBram_SelfTest(XBram *InstancePtr, u8 IntMask) return (XST_SUCCESS); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_sinit.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_sinit.c similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_sinit.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_sinit.c index bae977a57..f44fc5ce3 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_sinit.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_sinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,6 +32,8 @@ /*****************************************************************************/ /** * @file xbram_sinit.c +* @addtogroup bram_v4_0 +* @{ * * The implementation of the XBram driver's static initialzation * functionality. @@ -99,3 +101,4 @@ XBram_Config *XBram_LookupConfig(u16 DeviceId) return CfgPtr; } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/Makefile b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/Makefile similarity index 87% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/Makefile rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/Makefile index 280556566..dd934f662 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/Makefile +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/Makefile @@ -17,10 +17,10 @@ INCLUDEFILES=xio.h libs: echo "Compiling cpu" $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} make clean -include: +include: ${CP} ${INCLUDEFILES} ${INCLUDEDIR} clean: diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/fsl.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/fsl.h similarity index 99% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/fsl.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/fsl.h index d13b3d52d..c3b5c0235 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/fsl.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/fsl.h @@ -32,6 +32,8 @@ /*****************************************************************************/ /** * @file fsl.h +* @addtogroup cpu_v2_3 +* @{ * * This file contains macros for interfacing to the Fast Simplex Link (FSL) * interface.. @@ -167,4 +169,4 @@ extern "C" { } #endif #endif /* _FSL_H */ - +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/xio.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/xio.c similarity index 99% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/xio.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/xio.c index b71887d17..086c3129b 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/xio.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/xio.c @@ -33,6 +33,8 @@ /** * * @file xio.c +* @addtogroup cpu_v2_3 +* @{ * * Contains I/O functions for memory-mapped or non-memory-mapped I/O * architectures. These functions encapsulate generic CPU I/O requirements. @@ -225,3 +227,4 @@ void XIo_OutSwap32(XIo_Address OutAddress, u32 Value) XIo_EndianSwap32(Value, &OutData); XIo_Out32(OutAddress, OutData); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/xio.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/xio.h similarity index 95% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/xio.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/xio.h index 77ab04681..0d55bbd86 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/xio.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/xio.h @@ -33,6 +33,9 @@ /** * * @file xio.h +* @addtogroup cpu_v2_3 +* @{ +* @details * * This file contains the interface for the XIo component, which encapsulates * the Input/Output functions for processors that do not require any special @@ -59,6 +62,12 @@ * CR#794205 * 2.2 bss 08/04/14 Updated driver tcl to add protection macros for * xparameters.h (CR#802257). +* 2.3 sk 12/15/14 Updated mdd file to delete �ffunction-sections & +* -fdata-sections flags from extra compiler flags CR#838648 +* Changed default os to latest version in mdd file. +* 2.4 nsk 11/05/15 Updated generate and post_generate procs in driver tcl +* not to generate cpu macros, when microblaze is connected +* as one of the streaming slaves to itself. CR#876604 * * * @@ -261,3 +270,4 @@ void XIo_OutSwap32(XIo_Address OutAddress, u32 Value); #endif #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/Makefile b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/Makefile similarity index 84% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/Makefile rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/Makefile index 69f2191df..1822ca81d 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/Makefile +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/Makefile @@ -11,17 +11,16 @@ INCLUDES=-I./. -I${INCLUDEDIR} INCLUDEFILES=*.h LIBSOURCES=*.c -OUTS = *.o +OUTS = *.o libs: echo "Compiling emaclite" $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} make clean -include: +include: ${CP} $(INCLUDEFILES) $(INCLUDEDIR) clean: rm -rf ${OUTS} - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite.c similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite.c index 5b5381159..0a17e22d0 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite.c @@ -33,6 +33,8 @@ /** * * @file xemaclite.c +* @addtogroup emaclite_v4_1 +* @{ * * Functions in this file are the minimum required functions for the EmacLite * driver. See xemaclite.h for a detailed description of the driver. @@ -62,6 +64,9 @@ * 3.02a sdm 07/22/11 Removed redundant code in XEmacLite_Recv functions for * CR617290 * 3.04a srt 04/13/13 Removed warnings (CR 705000). +* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototypes of XEmacLite_GetReceiveDataLength, +* XEmacLite_CfgInitialize API's. * * ******************************************************************************/ @@ -82,7 +87,7 @@ /************************** Function Prototypes ******************************/ -static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress); +static u16 XEmacLite_GetReceiveDataLength(UINTPTR BaseAddress); /************************** Variable Definitions *****************************/ @@ -113,7 +118,7 @@ static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress); ******************************************************************************/ int XEmacLite_CfgInitialize(XEmacLite *InstancePtr, XEmacLite_Config *EmacLiteConfigPtr, - u32 EffectiveAddr) + UINTPTR EffectiveAddr) { /* @@ -185,8 +190,8 @@ int XEmacLite_CfgInitialize(XEmacLite *InstancePtr, int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount) { u32 Register; - u32 BaseAddress; - u32 EmacBaseAddress; + UINTPTR BaseAddress; + UINTPTR EmacBaseAddress; u32 IntrEnableStatus; /* @@ -232,7 +237,7 @@ int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount) /* * Write the frame to the buffer. */ - XEmacLite_AlignedWrite(FramePtr, (u32 *) BaseAddress, + XEmacLite_AlignedWrite(FramePtr, (UINTPTR *) BaseAddress, ByteCount); @@ -241,7 +246,7 @@ int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount) */ XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET, (ByteCount & (XEL_TPLR_LENGTH_MASK_HI | - XEL_TPLR_LENGTH_MASK_LO))); + XEL_TPLR_LENGTH_MASK_LO))); /* * Update the Tx Status Register to indicate that there is a @@ -285,7 +290,7 @@ int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount) /* * Write the frame to the buffer. */ - XEmacLite_AlignedWrite(FramePtr, (u32 *) BaseAddress, + XEmacLite_AlignedWrite(FramePtr, (UINTPTR *) BaseAddress, ByteCount); /* @@ -361,7 +366,7 @@ u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr) u16 LengthType; u16 Length; u32 Register; - u32 BaseAddress; + UINTPTR BaseAddress; /* * Verify that each of the inputs are valid. @@ -460,7 +465,7 @@ u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr) /* * Field contains type other than IP or ARP, use max * frame size and let user parse it. - */ + */ Length = XEL_MAX_FRAME_SIZE; } @@ -475,7 +480,7 @@ u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr) /* * Read from the EmacLite. */ - XEmacLite_AlignedRead(((u32 *) (BaseAddress + XEL_RXBUFF_OFFSET)), + XEmacLite_AlignedRead(((UINTPTR *) (BaseAddress + XEL_RXBUFF_OFFSET)), FramePtr, Length); /* @@ -512,7 +517,7 @@ u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr) ******************************************************************************/ void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr) { - u32 BaseAddress; + UINTPTR BaseAddress; /* * Verify that each of the inputs are valid. @@ -528,7 +533,7 @@ void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr) * Copy the MAC address to the Transmit buffer. */ XEmacLite_AlignedWrite(AddressPtr, - (u32 *) BaseAddress, + (UINTPTR *) BaseAddress, XEL_MAC_ADDR_SIZE); /* @@ -610,8 +615,8 @@ int XEmacLite_TxBufferAvailable(XEmacLite *InstancePtr) /* - * Read the Tx Status of the second buffer register and determine if the - * buffer is available. + * Read the Tx Status of the second buffer register and determine if the + * buffer is available. */ if (InstancePtr->EmacLiteConfig.TxPingPong != 0) { Register = XEmacLite_GetTxStatus(InstancePtr->EmacLiteConfig. @@ -946,7 +951,7 @@ void XEmacLite_DisableLoopBack(XEmacLite *InstancePtr) * @note None. * ******************************************************************************/ -static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress) +static u16 XEmacLite_GetReceiveDataLength(UINTPTR BaseAddress) { u16 Length; @@ -965,3 +970,4 @@ static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress) return Length; } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite.h similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite.h index 4de21a59b..bed806698 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite.h @@ -33,6 +33,9 @@ /** * * @file xemaclite.h +* @addtogroup emaclite_v4_1 +* @{ +* @details * * The Xilinx Ethernet Lite (EmacLite) driver. This driver supports the Xilinx * Ethernet Lite 10/100 MAC (EmacLite). @@ -190,6 +193,15 @@ * driver is compiled with ARM toolchain. * 3.04a srt 04/13/13 Removed warnings (CR 705000). * 4.0 adk 19/12/13 Updated as per the New Tcl API's +* 4.1 nsk 07/13/15 Added Length check in XEmacLite_AlignedWrite function +* in xemaclite_l.c file to avoid extra write operation +* (CR 843707). +* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototype of XEmacLite_CfgInitialize API. +* 4.2 adk 11/18/15 Fix compilation errors due to conflicting data types +* CR#917930 +* 4.2 adk 29/02/16 Updated interrupt example to support Zynq and ZynqMP +* CR#938244. * * * @@ -229,7 +241,7 @@ extern "C" { */ typedef struct { u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Device base address */ + UINTPTR BaseAddress; /**< Device base address */ u8 TxPingPong; /**< 1 if TX Pong buffer configured, 0 otherwise */ u8 RxPingPong; /**< 1 if RX Pong buffer configured, 0 otherwise */ u8 MdioInclude; /**< 1 if MDIO is enabled, 0 otherwise */ @@ -355,7 +367,7 @@ typedef struct { */ int XEmacLite_CfgInitialize(XEmacLite *InstancePtr, XEmacLite_Config *EmacLiteConfigPtr, - u32 EffectiveAddr); + UINTPTR EffectiveAddr); void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr); int XEmacLite_TxBufferAvailable(XEmacLite *InstancePtr); void XEmacLite_FlushReceive(XEmacLite *InstancePtr); @@ -402,3 +414,4 @@ int XEmacLite_SelfTest(XEmacLite *InstancePtr); #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_g.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c index 9e9c1ea08..a082ce0fd 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_g.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -22,8 +22,8 @@ * *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_i.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_i.h similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_i.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_i.h index 6bfa1714d..0eab0edb5 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_i.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_i.h @@ -32,6 +32,8 @@ /******************************************************************************/ /** * @file xemaclite_i.h +* @addtogroup emaclite_v4_1 +* @{ * * This header file contains internal identifiers, which are those shared * between the files of the driver. It is intended for internal use only. @@ -123,8 +125,8 @@ extern XEmacLite_Config XEmacLite_ConfigTable[]; /************************** Function Prototypes ******************************/ -void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount); -void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount); +void XEmacLite_AlignedWrite(void *SrcPtr, UINTPTR *DestPtr, unsigned ByteCount); +void XEmacLite_AlignedRead(UINTPTR *SrcPtr, void *DestPtr, unsigned ByteCount); void StubHandler(void *CallBackRef); @@ -134,3 +136,4 @@ void StubHandler(void *CallBackRef); #endif #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_intr.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_intr.c similarity index 98% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_intr.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_intr.c index 5f979e7e8..d42d4efeb 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_intr.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_intr.c @@ -33,6 +33,8 @@ /** * * @file xemaclite_intr.c +* @addtogroup emaclite_v4_1 +* @{ * * Functions in this file are for the interrupt driven processing functionality. * See xemaclite.h for a detailed description of the driver. @@ -52,6 +54,7 @@ * the HW. * 3.00a ktn 10/22/09 Updated file to use the HAL Processor APIs/macros. * The macros have been renamed to remove _m from the name. +* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. * * ******************************************************************************/ @@ -94,7 +97,7 @@ int XEmacLite_EnableInterrupts(XEmacLite *InstancePtr) { u32 Register; - u32 BaseAddress; + UINTPTR BaseAddress; /* * Verify that each of the inputs are valid. @@ -156,7 +159,7 @@ int XEmacLite_EnableInterrupts(XEmacLite *InstancePtr) void XEmacLite_DisableInterrupts(XEmacLite *InstancePtr) { u32 Register; - u32 BaseAddress; + UINTPTR BaseAddress; /* * Verify that each of the inputs are valid. @@ -216,7 +219,7 @@ void XEmacLite_InterruptHandler(void *InstancePtr) XEmacLite *EmacLitePtr; int TxCompleteIntr = FALSE; - u32 BaseAddress; + UINTPTR BaseAddress; u32 TxStatus; /* @@ -357,3 +360,4 @@ void XEmacLite_SetSendHandler(XEmacLite *InstancePtr, void *CallBackRef, InstancePtr->SendHandler = FuncPtr; InstancePtr->SendRef = CallBackRef; } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_l.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_l.c similarity index 91% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_l.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_l.c index 689c39675..6073e1328 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_l.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_l.c @@ -33,6 +33,8 @@ /** * * @file xemaclite_l.c +* @addtogroup emaclite_v4_1 +* @{ * * This file contains the minimal, polled functions to send and receive Ethernet * frames. @@ -52,6 +54,12 @@ * XEmacLite_AlignedRead functions to use volatile * variables so that they are not optimized. * 3.00a ktn 10/22/09 The macros have been renamed to remove _m from the name. +* 4.1 nsk 07/13/15 Added Length check in XEmacLite_AlignedWrite function +* to avoid extra write operation (CR 843707). +* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototypes of XEmacLite_SendFrame, +* XEmacLite_RecvFrame, XEmacLite_AlignedWrite, +* XEmacLite_AlignedRead APIs. * * * @@ -71,8 +79,8 @@ /***************** Macros (Inline Functions) Definitions *********************/ /************************** Function Prototypes ******************************/ -void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount); -void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount); +void XEmacLite_AlignedWrite(void *SrcPtr, UINTPTR *DestPtr, unsigned ByteCount); +void XEmacLite_AlignedRead(UINTPTR *SrcPtr, void *DestPtr, unsigned ByteCount); /************************** Variable Definitions *****************************/ @@ -101,20 +109,20 @@ void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount); * The function does not take the different buffers into consideration. * ******************************************************************************/ -void XEmacLite_SendFrame(u32 BaseAddress, u8 *FramePtr, unsigned ByteCount) +void XEmacLite_SendFrame(UINTPTR BaseAddress, u8 *FramePtr, unsigned ByteCount) { u32 Register; /* * Write data to the EmacLite */ - XEmacLite_AlignedWrite(FramePtr, (u32 *) (BaseAddress), ByteCount); + XEmacLite_AlignedWrite(FramePtr, (UINTPTR *) (BaseAddress), ByteCount); /* * The frame is in the buffer, now send it */ XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET, - (ByteCount & (XEL_TPLR_LENGTH_MASK_HI | + (ByteCount & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); @@ -156,7 +164,7 @@ void XEmacLite_SendFrame(u32 BaseAddress, u8 *FramePtr, unsigned ByteCount) * The function does not take the different buffers into consideration. * ******************************************************************************/ -u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr) +u16 XEmacLite_RecvFrame(UINTPTR BaseAddress, u8 *FramePtr) { u16 LengthType; u16 Length; @@ -196,7 +204,7 @@ u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr) /* * Read each byte from the EmacLite */ - XEmacLite_AlignedRead((u32 *) (BaseAddress + XEL_RXBUFF_OFFSET), + XEmacLite_AlignedRead((UINTPTR *) (BaseAddress + XEL_RXBUFF_OFFSET), FramePtr, Length); /* @@ -224,7 +232,7 @@ u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr) * @note None. * ******************************************************************************/ -void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount) +void XEmacLite_AlignedWrite(void *SrcPtr, UINTPTR *DestPtr, unsigned ByteCount) { unsigned Index; unsigned Length = ByteCount; @@ -364,9 +372,9 @@ void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount) for (Index = 0; Index < Length; Index++) { *To8Ptr++ = *From8Ptr++; } - - *To32Ptr++ = AlignBuffer; - + if (Length) { + *To32Ptr++ = AlignBuffer; + } } /******************************************************************************/ @@ -384,7 +392,7 @@ void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount) * @note None. * ******************************************************************************/ -void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount) +void XEmacLite_AlignedRead(UINTPTR *SrcPtr, void *DestPtr, unsigned ByteCount) { unsigned Index; unsigned Length = ByteCount; @@ -501,3 +509,4 @@ void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount) *To8Ptr++ = *From8Ptr++; } } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_l.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_l.h similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_l.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_l.h index a0b812105..eb1a5231a 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_l.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_l.h @@ -33,6 +33,8 @@ /** * * @file xemaclite_l.h +* @addtogroup emaclite_v4_1 +* @{ * * This header file contains identifiers and basic driver functions and macros * that can be used to access the Xilinx Ethernet Lite 10/100 MAC (EmacLite). @@ -71,6 +73,9 @@ * XEmacLite_mSetRxStatus changed to XEmacLite_SetRxStatus, * XEmacLite_mIsTxDone changed to XEmacLite_IsTxDone and * XEmacLite_mIsRxEmpty changed to XEmacLite_IsRxEmpty. +* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototypes of XEmacLite_SendFrame, +* XEmacLite_RecvFrame APIs. * * ******************************************************************************/ @@ -361,11 +366,12 @@ extern "C" { /************************** Function Prototypes ******************************/ -void XEmacLite_SendFrame(u32 BaseAddress, u8 *FramePtr, unsigned ByteCount); -u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr); +void XEmacLite_SendFrame(UINTPTR BaseAddress, u8 *FramePtr, unsigned ByteCount); +u16 XEmacLite_RecvFrame(UINTPTR BaseAddress, u8 *FramePtr); #ifdef __cplusplus } #endif #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_selftest.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_selftest.c similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_selftest.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_selftest.c index b8891b814..ada2cae79 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_selftest.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_selftest.c @@ -33,6 +33,8 @@ /** * * @file xemaclite_selftest.c +* @addtogroup emaclite_v4_1 +* @{ * * Function(s) in this file are the required functions for the EMAC Lite * driver sefftest for the hardware. @@ -46,6 +48,7 @@ * 1.01a ecm 01/31/04 First release * 1.11a mta 03/21/07 Updated to new coding style * 3.00a ktn 10/22/09 Updated driver to use the HAL Processor APIs/macros. +* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. * ******************************************************************************/ @@ -86,7 +89,7 @@ ******************************************************************************/ int XEmacLite_SelfTest(XEmacLite * InstancePtr) { - u32 BaseAddress; + UINTPTR BaseAddress; u8 Index; u8 TestString[4] = { 0xDE, 0xAD, 0xBE, 0xEF }; u8 ReturnString[4] = { 0x0, 0x0, 0x0, 0x0 }; @@ -106,9 +109,9 @@ int XEmacLite_SelfTest(XEmacLite * InstancePtr) * Write the TestString to the TX buffer in EMAC Lite then * back from the EMAC Lite and verify */ - XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress, + XEmacLite_AlignedWrite(TestString, (UINTPTR *) BaseAddress, sizeof(TestString)); - XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString, + XEmacLite_AlignedRead((UINTPTR *) BaseAddress, ReturnString, sizeof(ReturnString)); for (Index = 0; Index < 4; Index++) { @@ -132,9 +135,9 @@ int XEmacLite_SelfTest(XEmacLite * InstancePtr) * Write the TestString to the optional TX buffer in EMAC Lite * then back from the EMAC Lite and verify */ - XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress, + XEmacLite_AlignedWrite(TestString, (UINTPTR *) BaseAddress, sizeof(TestString)); - XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString, + XEmacLite_AlignedRead((UINTPTR *) BaseAddress, ReturnString, sizeof(ReturnString)); for (Index = 0; Index < 4; Index++) { @@ -160,9 +163,9 @@ int XEmacLite_SelfTest(XEmacLite * InstancePtr) * Write the TestString to the RX buffer in EMAC Lite then * back from the EMAC Lite and verify */ - XEmacLite_AlignedWrite(TestString, (u32 *) (BaseAddress), + XEmacLite_AlignedWrite(TestString, (UINTPTR *) (BaseAddress), sizeof(TestString)); - XEmacLite_AlignedRead((u32 *) (BaseAddress), ReturnString, + XEmacLite_AlignedRead((UINTPTR *) (BaseAddress), ReturnString, sizeof(ReturnString)); for (Index = 0; Index < 4; Index++) { @@ -186,9 +189,9 @@ int XEmacLite_SelfTest(XEmacLite * InstancePtr) * Write the TestString to the optional RX buffer in EMAC Lite * then back from the EMAC Lite and verify */ - XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress, + XEmacLite_AlignedWrite(TestString, (UINTPTR *) BaseAddress, sizeof(TestString)); - XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString, + XEmacLite_AlignedRead((UINTPTR *) BaseAddress, ReturnString, sizeof(ReturnString)); for (Index = 0; Index < 4; Index++) { @@ -206,3 +209,4 @@ int XEmacLite_SelfTest(XEmacLite * InstancePtr) return XST_SUCCESS; } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_sinit.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_sinit.c similarity index 99% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_sinit.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_sinit.c index 4c3df772e..73fd46014 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_sinit.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_sinit.c @@ -33,6 +33,8 @@ /** * * @file xemaclite_sinit.c +* @addtogroup emaclite_v4_1 +* @{ * * This file contains the implementation of the XEmacLite driver's static * initialization functionality. @@ -151,3 +153,4 @@ int XEmacLite_Initialize(XEmacLite *InstancePtr, u16 DeviceId) } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/Makefile b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/Makefile similarity index 100% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/Makefile rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/Makefile diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio.c similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio.c index 6df98d000..b9f4beb0a 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,6 +32,8 @@ /*****************************************************************************/ /** * @file xgpio.c +* @addtogroup gpio_v4_1 +* @{ * * The implementation of the XGpio driver's basic functionality. See xgpio.h * for more information about the driver. @@ -58,6 +60,8 @@ * 2.12a sv 11/21/07 Updated driver to support access through DCR bus * 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the * macros to remove _m from the name. +* 4.1 lks 11/18/15 Clean up of the comments in the code and +* removed support for DCR bridge * * *****************************************************************************/ @@ -106,7 +110,7 @@ * address instead. * * @return -* - XST_SUCCESS Initialization was successfull. +* - XST_SUCCESS if the initialization is successfull. * * @note None. * @@ -114,19 +118,11 @@ int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config, u32 EffectiveAddr) { - /* - * Assert arguments - */ + /* Assert arguments */ Xil_AssertNonvoid(InstancePtr != NULL); - /* - * Set some default values. - */ -#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0) - InstancePtr->BaseAddress = ((EffectiveAddr >> 2)) & 0xFFF; -#else + /* Set some default values. */ InstancePtr->BaseAddress = EffectiveAddr; -#endif InstancePtr->InterruptPresent = Config->InterruptPresent; InstancePtr->IsDual = Config->IsDual; @@ -157,7 +153,7 @@ int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config, * function will assert. * *****************************************************************************/ -void XGpio_SetDataDirection(XGpio * InstancePtr, unsigned Channel, +void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel, u32 DirectionMask) { Xil_AssertVoid(InstancePtr != NULL); @@ -253,3 +249,4 @@ void XGpio_DiscreteWrite(XGpio * InstancePtr, unsigned Channel, u32 Data) ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET, Data); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio.h similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio.h index 5116edb25..a7628d57d 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,6 +32,9 @@ /*****************************************************************************/ /** * @file xgpio.h +* @addtogroup gpio_v4_1 +* @{ +* @details * * This file contains the software API definition of the Xilinx General Purpose * I/O (XGpio) device driver. @@ -100,6 +103,10 @@ * 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in * xparameters.h. CR#698589 * 4.0 adk 19/12/13 Updated as per the New Tcl API's +* 4.1 lks 11/18/15 Updated to use cannonical xparameters in examples and +* clean up of the comments, removed support for DCR bridge +* and removed xgpio_intr_example for CR 900381 +* * *****************************************************************************/ @@ -193,3 +200,4 @@ u32 XGpio_InterruptGetStatus(XGpio *InstancePtr); #endif #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_extra.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_extra.c similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_extra.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_extra.c index 9c8a6b580..915ccd41f 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_extra.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_extra.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,6 +32,8 @@ /*****************************************************************************/ /** * @file xgpio_extra.c +* @addtogroup gpio_v4_1 +* @{ * * The implementation of the XGpio driver's advanced discrete functions. * See xgpio.h for more information about the driver. @@ -104,9 +106,7 @@ void XGpio_DiscreteSet(XGpio * InstancePtr, unsigned Channel, u32 Mask) Xil_AssertVoid((Channel == 1) || ((Channel == 2) && (InstancePtr->IsDual == TRUE))); - /* - * Calculate the offset to the data register of the GPIO once - */ + /* Calculate the offset to the data register of the GPIO */ DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET; /* @@ -150,9 +150,7 @@ void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask) Xil_AssertVoid((Channel == 1) || ((Channel == 2) && (InstancePtr->IsDual == TRUE))); - /* - * Calculate the offset to the data register of the GPIO once - */ + /* Calculate the offset to the data register of the GPIO */ DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET; /* @@ -163,3 +161,4 @@ void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask) Current &= ~Mask; XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_g.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c index b508b8dcd..219b80d7f 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_g.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -22,8 +22,8 @@ * *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_i.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_i.h similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_i.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_i.h index a94bec41a..5e18e0c8d 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_i.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_i.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,6 +32,8 @@ /******************************************************************************/ /** * @file xgpio_i.h +* @addtogroup gpio_v4_1 +* @{ * * This header file contains internal identifiers, which are those shared * between the files of the driver. It is intended for internal use only. @@ -82,3 +84,4 @@ extern XGpio_Config XGpio_ConfigTable[]; #endif #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_intr.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_intr.c similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_intr.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_intr.c index f53a36969..11ce9a94c 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_intr.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_intr.c @@ -32,6 +32,8 @@ /*****************************************************************************/ /** * @file xgpio_intr.c +* @addtogroup gpio_v4_1 +* @{ * * Implements GPIO interrupt processing functions for the XGpio driver. * See xgpio.h for more information about the driver. @@ -88,7 +90,7 @@ * @note None. * *****************************************************************************/ -void XGpio_InterruptGlobalEnable(XGpio * InstancePtr) +void XGpio_InterruptGlobalEnable(XGpio *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -115,7 +117,7 @@ void XGpio_InterruptGlobalEnable(XGpio * InstancePtr) * @note None. * *****************************************************************************/ -void XGpio_InterruptGlobalDisable(XGpio * InstancePtr) +void XGpio_InterruptGlobalDisable(XGpio *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -143,7 +145,7 @@ void XGpio_InterruptGlobalDisable(XGpio * InstancePtr) * @note None. * *****************************************************************************/ -void XGpio_InterruptEnable(XGpio * InstancePtr, u32 Mask) +void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask) { u32 Register; @@ -179,7 +181,7 @@ void XGpio_InterruptEnable(XGpio * InstancePtr, u32 Mask) * @note None. * *****************************************************************************/ -void XGpio_InterruptDisable(XGpio * InstancePtr, u32 Mask) +void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask) { u32 Register; @@ -289,3 +291,4 @@ u32 XGpio_InterruptGetStatus(XGpio * InstancePtr) return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_l.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_l.h similarity index 88% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_l.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_l.h index 3f4e82ee7..d2032a4dd 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_l.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_l.h @@ -33,6 +33,8 @@ /** * * @file xgpio_l.h +* @addtogroup gpio_v4_1 +* @{ * * This header file contains identifiers and driver functions (or * macros) that can be used to access the device. The user should refer to the @@ -66,6 +68,7 @@ * XGpio_mGetDataReg and XGpio_mSetDataReg. Users * should use XGpio_WriteReg/XGpio_ReadReg to achieve the * same functionality. +* 4.1 lks 11/18/15 Removed support for DCR bridge * * ******************************************************************************/ @@ -83,16 +86,6 @@ extern "C" { #include "xil_assert.h" #include "xil_io.h" -/* - * XPAR_XGPIO_USE_DCR_BRIDGE has to be set to 1 if the GPIO device is - * accessed through a DCR bus connected to a bridge - */ -#define XPAR_XGPIO_USE_DCR_BRIDGE 0 - - -#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0) -#include "xio_dcr.h" -#endif /************************** Constant Definitions *****************************/ @@ -101,19 +94,6 @@ extern "C" { * Register offsets for this device. * @{ */ -#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0) - -#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */ -#define XGPIO_TRI_OFFSET 0x1 /**< I/O direction reg for 1st channel */ -#define XGPIO_DATA2_OFFSET 0x2 /**< Data register for 2nd channel */ -#define XGPIO_TRI2_OFFSET 0x3 /**< I/O direction reg for 2nd channel */ - -#define XGPIO_GIE_OFFSET 0x47 /**< Global interrupt enable register */ -#define XGPIO_ISR_OFFSET 0x48 /**< Interrupt status register */ -#define XGPIO_IER_OFFSET 0x4A /**< Interrupt enable register */ - -#else - #define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */ #define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */ #define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */ @@ -123,8 +103,6 @@ extern "C" { #define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */ #define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */ -#endif - /* @} */ /* The following constant describes the offset of each channels data and @@ -159,21 +137,9 @@ extern "C" { /***************** Macros (Inline Functions) Definitions *********************/ - /* - * Define the appropriate I/O access method to memory mapped I/O or DCR. - */ -#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0) - -#define XGpio_In32 XIo_DcrIn -#define XGpio_Out32 XIo_DcrOut - -#else - #define XGpio_In32 Xil_In32 #define XGpio_Out32 Xil_Out32 -#endif - /****************************************************************************/ /** @@ -224,3 +190,4 @@ extern "C" { #endif #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_selftest.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_selftest.c similarity index 99% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_selftest.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_selftest.c index 798f18064..69cab70f9 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_selftest.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_selftest.c @@ -32,6 +32,8 @@ /*****************************************************************************/ /** * @file xgpio_selftest.c +* @addtogroup gpio_v4_1 +* @{ * * The implementation of the XGpio driver's self test function. * See xgpio.h for more information about the driver. @@ -105,3 +107,4 @@ int XGpio_SelfTest(XGpio * InstancePtr) return (XST_SUCCESS); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_sinit.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_sinit.c similarity index 95% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_sinit.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_sinit.c index 514633585..52bab6bde 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_sinit.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_sinit.c @@ -32,6 +32,8 @@ /*****************************************************************************/ /** * @file xgpio_sinit.c +* @addtogroup gpio_v4_1 +* @{ * * The implementation of the XGpio driver's static initialzation * functionality. @@ -47,6 +49,8 @@ * ----- ---- -------- ----------------------------------------------- * 2.01a jvb 10/13/05 First release * 2.11a mta 03/21/07 Updated to new coding style +* 4.0 sha 07/15/15 Defined macro XPAR_XGPIO_NUM_INSTANCES if not +* defined in xparameters.h * * *****************************************************************************/ @@ -59,6 +63,10 @@ /************************** Constant Definitions ****************************/ +#ifndef XPAR_XGPIO_NUM_INSTANCES +#define XPAR_XGPIO_NUM_INSTANCES 0 +#endif + /**************************** Type Definitions ******************************/ /***************** Macros (Inline Functions) Definitions ********************/ @@ -148,3 +156,4 @@ int XGpio_Initialize(XGpio * InstancePtr, u16 DeviceId) return XGpio_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddress); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/Makefile b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/Makefile deleted file mode 100644 index 7b8304542..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a -LEVEL=0 - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -INCLUDEFILES=*.h -LIBSOURCES=*.c - -OUTS = *.o - -libs: - echo "Compiling intc" - $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} - make clean - -include: - ${CP} $(INCLUDEFILES) $(INCLUDEDIR) - -clean: - rm -rf ${OUTS} - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc.c deleted file mode 100644 index a6d1b7872..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc.c +++ /dev/null @@ -1,1078 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xintc.c -* -* Contains required functions for the XIntc driver for the Xilinx Interrupt -* Controller. See xintc.h for a detailed description of the driver. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.00a ecm  08/16/01 First release
-* 1.00b jhl  02/21/02 Repartitioned the driver for smaller files
-* 1.00b jhl  04/24/02 Made LookupConfig global and compressed ack before table
-*                     in the configuration into a bit mask
-* 1.00c rpm  10/17/03 New release. Support the static vector table created
-*                     in the xintc_g.c configuration table.
-* 1.00c rpm  04/23/04 Removed check in XIntc_Connect for a previously connected
-*                     handler. Always overwrite the vector table handler with
-*                     the handler provided as an argument.
-* 1.10c mta  03/21/07 Updated to new coding style
-* 1.11a sv   11/21/07 Updated driver to support access through a DCR bridge
-* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs.
-* 2.04a bss  01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
-*		      and XIntc_SetNormalIntrMode for setting to normal
-*		      interrupt mode.
-* 2.05a bss  08/16/12 Updated to support relocatable vectors in Microblaze,
-*		      updated XIntc_SetNormalIntrMode to use IntVectorAddr
-*		      which is the interrupt vector address
-* 2.06a bss  01/28/13 To support Cascade mode:
-*		      Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
-*		      XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
-*		      XIntc_Acknowledge,XIntc_ConnectFastHandler and
-*		      XIntc_SetNormalIntrMode APIs.
-*		      Added XIntc_InitializeSlaves API.
-* 3.0   bss  01/28/13 Modified to initialize IVAR register with
-*		      XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
-*		      CR#765931
-*
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xintc.h" -#include "xintc_l.h" -#include "xintc_i.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Variable Definitions *****************************/ - -/* - * Array of masks associated with the bit position, improves performance - * in the ISR and acknowledge functions, this table is shared between all - * instances of the driver. XIN_CONTROLLER_MAX_INTRS is the maximum number of - * sources of Interrupt controller - */ -u32 XIntc_BitPosMask[XIN_CONTROLLER_MAX_INTRS]; - -/************************** Function Prototypes ******************************/ - -static void StubHandler(void *CallBackRef); -static void XIntc_InitializeSlaves(XIntc * InstancePtr); - -/*****************************************************************************/ -/** -* -* Initialize a specific interrupt controller instance/driver. The -* initialization entails: -* -* - Initialize fields of the XIntc structure -* - Initial vector table with stub function calls -* - All interrupt sources are disabled -* - Interrupt output is disabled -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* @param DeviceId is the unique id of the device controlled by this XIntc -* instance. Passing in a device id associates the generic XIntc -* instance to a specific device, as chosen by the caller or -* application developer. -* -* @return -* - XST_SUCCESS if initialization was successful -* - XST_DEVICE_IS_STARTED if the device has already been started -* - XST_DEVICE_NOT_FOUND if device configuration information was -* not found for a device with the supplied device ID. -* -* @note In Cascade mode this function calls XIntc_InitializeSlaves to -* initialiaze Slave Interrupt controllers. -* -******************************************************************************/ -int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId) -{ - u8 Id; - XIntc_Config *CfgPtr; - u32 NextBitMask = 1; - - Xil_AssertNonvoid(InstancePtr != NULL); - - /* - * If the device is started, disallow the initialize and return a status - * indicating it is started. This allows the user to stop the device - * and reinitialize, but prevents a user from inadvertently initializing - */ - if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; - } - - /* - * Lookup the device configuration in the CROM table. Use this - * configuration info down below when initializing this component. - */ - CfgPtr = XIntc_LookupConfig(DeviceId); - if (CfgPtr == NULL) { - return XST_DEVICE_NOT_FOUND; - } - - /* - * Set some default values - */ - InstancePtr->IsReady = 0; - InstancePtr->IsStarted = 0; /* not started */ - InstancePtr->CfgPtr = CfgPtr; - - InstancePtr->CfgPtr->Options = XIN_SVC_SGL_ISR_OPTION; - InstancePtr->CfgPtr->IntcType = CfgPtr->IntcType; - - /* - * Save the base address pointer such that the registers of the - * interrupt can be accessed - */ -#if (XPAR_XINTC_USE_DCR_BRIDGE != 0) - InstancePtr->BaseAddress = ((CfgPtr->BaseAddress >> 2)) & 0xFFF; -#else - InstancePtr->BaseAddress = CfgPtr->BaseAddress; -#endif - - /* - * Initialize all the data needed to perform interrupt processing for - * each interrupt ID up to the maximum used - */ - for (Id = 0; Id < CfgPtr->NumberofIntrs; Id++) { - - /* - * Initalize the handler to point to a stub to handle an - * interrupt which has not been connected to a handler. Only - * initialize it if the handler is 0 or XNullHandler, which - * means it was not initialized statically by the tools/user. - * Set the callback reference to this instance so that - * unhandled interrupts can be tracked. - */ - if ((InstancePtr->CfgPtr->HandlerTable[Id].Handler == 0) || - (InstancePtr->CfgPtr->HandlerTable[Id].Handler == - XNullHandler)) { - InstancePtr->CfgPtr->HandlerTable[Id].Handler = - StubHandler; - } - InstancePtr->CfgPtr->HandlerTable[Id].CallBackRef = InstancePtr; - - /* - * Initialize the bit position mask table such that bit - * positions are lookups only for each interrupt id, with 0 - * being a special case - * (XIntc_BitPosMask[] = { 1, 2, 4, 8, ... }) - */ - XIntc_BitPosMask[Id] = NextBitMask; - NextBitMask *= 2; - } - - /* - * Disable IRQ output signal - * Disable all interrupt sources - * Acknowledge all sources - */ - XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, 0); - XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET, 0); - XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, 0xFFFFFFFF); - - /* - * If the fast Interrupt mode is enabled then set all the - * interrupts as normal mode. - */ - if(InstancePtr->CfgPtr->FastIntr == TRUE) { - XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET, 0); - -#ifdef XPAR_MICROBLAZE_BASE_VECTORS - for (Id = 0; Id < 32 ; Id++) - { - XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET - + (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS - + 0x10); - } -#else - for (Id = 0; Id < 32 ; Id++) - { - XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET - + (Id * 4), 0x10); - } -#endif - } - - /* Initialize slaves in Cascade mode*/ - if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) { - XIntc_InitializeSlaves(InstancePtr); - } - - /* - * Indicate the instance is now ready to use, successfully initialized - */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Starts the interrupt controller by enabling the output from the controller -* to the processor. Interrupts may be generated by the interrupt controller -* after this function is called. -* -* It is necessary for the caller to connect the interrupt handler of this -* component to the proper interrupt source. This function also starts Slave -* controllers in Cascade mode. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* @param Mode determines if software is allowed to simulate interrupts or -* real interrupts are allowed to occur. Note that these modes are -* mutually exclusive. The interrupt controller hardware resets in -* a mode that allows software to simulate interrupts until this -* mode is exited. It cannot be reentered once it has been exited. -* -* One of the following values should be used for the mode. -* - XIN_SIMULATION_MODE enables simulation of interrupts only -* - XIN_REAL_MODE enables hardware interrupts only -* -* @return -* - XST_SUCCESS if the device was started successfully -* - XST_FAILURE if simulation mode was specified and it could not -* be set because real mode has already been entered. -* -* @note Must be called after XIntc initialization is completed. -* -******************************************************************************/ -int XIntc_Start(XIntc * InstancePtr, u8 Mode) -{ - u32 MasterEnable = XIN_INT_MASTER_ENABLE_MASK; - XIntc_Config *CfgPtr; - int Index; - - /* - * Assert the arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid((Mode == XIN_SIMULATION_MODE) || - (Mode == XIN_REAL_MODE)) - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Check for simulation mode - */ - if (Mode == XIN_SIMULATION_MODE) { - if (MasterEnable & XIN_INT_HARDWARE_ENABLE_MASK) { - return XST_FAILURE; - } - } - else { - MasterEnable |= XIN_INT_HARDWARE_ENABLE_MASK; - } - - /* - * Indicate the instance is ready to be used and is started before we - * enable the device. - */ - InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED; - - /* Start the Slaves for Cascade Mode */ - if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) { - for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; Index++) - { - CfgPtr = XIntc_LookupConfig(Index); - XIntc_Out32(CfgPtr->BaseAddress + XIN_MER_OFFSET, - MasterEnable); - } - } - - /* Start the master */ - XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, MasterEnable); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Stops the interrupt controller by disabling the output from the controller -* so that no interrupts will be caused by the interrupt controller. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XIntc_Stop(XIntc * InstancePtr) -{ - /* - * Assert the arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Stop all interrupts from occurring thru the interrupt controller by - * disabling all interrupts in the MER register - */ - XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, 0); - - InstancePtr->IsStarted = 0; -} - -/*****************************************************************************/ -/** -* -* Makes the connection between the Id of the interrupt source and the -* associated handler that is to run when the interrupt is recognized. The -* argument provided in this call as the Callbackref is used as the argument -* for the handler when it is called. In Cascade mode, connects handler to -* Slave controller handler table depending on the interrupt Id. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* @param Id contains the ID of the interrupt source and should be in the -* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being -* the highest priority interrupt. -* @param Handler to the handler for that interrupt. -* @param CallBackRef is the callback reference, usually the instance -* pointer of the connecting driver. -* -* @return -* -* - XST_SUCCESS if the handler was connected correctly. -* -* @note -* -* WARNING: The handler provided as an argument will overwrite any handler -* that was previously connected. -* -****************************************************************************/ -int XIntc_Connect(XIntc * InstancePtr, u8 Id, - XInterruptHandler Handler, void *CallBackRef) -{ - XIntc_Config *CfgPtr; - /* - * Assert the arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS); - Xil_AssertNonvoid(Handler != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* Connect Handlers for Slave controllers in Cascade Mode */ - if (Id > 31) { - - CfgPtr = XIntc_LookupConfig(Id/32); - - CfgPtr->HandlerTable[Id%32].Handler = Handler; - CfgPtr->HandlerTable[Id%32].CallBackRef = CallBackRef; - } - /* Connect Handlers for Master/primary controller */ - else { - /* - * The Id is used as an index into the table to select the - * proper handler - */ - InstancePtr->CfgPtr->HandlerTable[Id].Handler = Handler; - InstancePtr->CfgPtr->HandlerTable[Id].CallBackRef = - CallBackRef; - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Updates the interrupt table with the Null Handler and NULL arguments at the -* location pointed at by the Id. This effectively disconnects that interrupt -* source from any handler. The interrupt is disabled also. In Cascade mode, -* disconnects handler from Slave controller handler table depending on the -* interrupt Id. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* @param Id contains the ID of the interrupt source and should be in the -* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being -* the highest priority interrupt. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XIntc_Disconnect(XIntc * InstancePtr, u8 Id) -{ - u32 CurrentIER; - u32 Mask; - XIntc_Config *CfgPtr; - - /* - * Assert the arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Disable the interrupt such that it won't occur while disconnecting - * the handler, only disable the specified interrupt id without - * modifying the other interrupt ids - */ - - /* Disconnect Handlers for Slave controllers in Cascade Mode */ - if (Id > 31) { - - CfgPtr = XIntc_LookupConfig(Id/32); - - CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET); - - /* Convert from integer id to bit mask */ - Mask = XIntc_BitPosMask[(Id%32)]; - - XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET, - (CurrentIER & ~Mask)); - /* - * Disconnect the handler and connect a stub, the callback - * reference must be set to this instance to allow unhandled - * interrupts to be tracked - */ - CfgPtr->HandlerTable[Id%32].Handler = StubHandler; - CfgPtr->HandlerTable[Id%32].CallBackRef = InstancePtr; - } - /* Disconnect Handlers for Master/primary controller */ - else { - CurrentIER = XIntc_In32(InstancePtr->BaseAddress + - XIN_IER_OFFSET); - - /* Convert from integer id to bit mask */ - Mask = XIntc_BitPosMask[Id]; - - XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET, - (CurrentIER & ~Mask)); - InstancePtr->CfgPtr->HandlerTable[Id%32].Handler = - StubHandler; - InstancePtr->CfgPtr->HandlerTable[Id%32].CallBackRef = - InstancePtr; - } - -} - -/*****************************************************************************/ -/** -* -* Enables the interrupt source provided as the argument Id. Any pending -* interrupt condition for the specified Id will occur after this function is -* called. In Cascade mode, enables corresponding interrupt of Slave controllers -* depending on the Id. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* @param Id contains the ID of the interrupt source and should be in the -* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being -* the highest priority interrupt. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XIntc_Enable(XIntc * InstancePtr, u8 Id) -{ - u32 CurrentIER; - u32 Mask; - XIntc_Config *CfgPtr; - - /* - * Assert the arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - if (Id > 31) { - - /* Enable user required Id in Slave controller */ - CfgPtr = XIntc_LookupConfig(Id/32); - - CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET); - - /* Convert from integer id to bit mask */ - Mask = XIntc_BitPosMask[(Id%32)]; - - XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET, - (CurrentIER | Mask)); - } - else { - /* - * The Id is used to create the appropriate mask for the - * desired bit position. - */ - Mask = XIntc_BitPosMask[Id]; - - /* - * Enable the selected interrupt source by reading the - * interrupt enable register and then modifying only the - * specified interrupt id enable - */ - CurrentIER = XIntc_In32(InstancePtr->BaseAddress + - XIN_IER_OFFSET); - XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET, - (CurrentIER | Mask)); - } -} - -/*****************************************************************************/ -/** -* -* Disables the interrupt source provided as the argument Id such that the -* interrupt controller will not cause interrupts for the specified Id. The -* interrupt controller will continue to hold an interrupt condition for the -* Id, but will not cause an interrupt.In Cascade mode, disables corresponding -* interrupt of Slave controllers depending on the Id. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* @param Id contains the ID of the interrupt source and should be in the -* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the -* highest priority interrupt. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XIntc_Disable(XIntc * InstancePtr, u8 Id) -{ - u32 CurrentIER; - u32 Mask; - XIntc_Config *CfgPtr; - - /* - * Assert the arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - if (Id > 31) { - /* Enable user required Id in Slave controller */ - CfgPtr = XIntc_LookupConfig(Id/32); - - CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET); - - /* Convert from integer id to bit mask */ - Mask = XIntc_BitPosMask[(Id%32)]; - - XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET, - (CurrentIER & ~Mask)); - } else { - /* - * The Id is used to create the appropriate mask for the - * desired bit position. Id currently limited to 0 - 31 - */ - Mask = XIntc_BitPosMask[Id]; - - /* - * Disable the selected interrupt source by reading the - * interrupt enable register and then modifying only the - * specified interrupt id - */ - CurrentIER = XIntc_In32(InstancePtr->BaseAddress + - XIN_IER_OFFSET); - XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET, - (CurrentIER & ~Mask)); - } -} - -/*****************************************************************************/ -/** -* -* Acknowledges the interrupt source provided as the argument Id. When the -* interrupt is acknowledged, it causes the interrupt controller to clear its -* interrupt condition.In Cascade mode, acknowledges corresponding interrupt -* source of Slave controllers depending on the Id. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* @param Id contains the ID of the interrupt source and should be in the -* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being -* the highest priority interrupt. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id) -{ - u32 Mask; - XIntc_Config *CfgPtr; - - /* - * Assert the arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - if (Id > 31) { - /* Enable user required Id in Slave controller */ - CfgPtr = XIntc_LookupConfig(Id/32); - - /* Convert from integer id to bit mask */ - Mask = XIntc_BitPosMask[(Id%32)]; - - XIntc_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET, Mask); - } else { - /* - * The Id is used to create the appropriate mask for the - * desired bit position. - */ - Mask = XIntc_BitPosMask[Id]; - - /* - * Acknowledge the selected interrupt source, no read of the - * acknowledge register is necessary since only the bits set - * in the mask will be affected by the write - */ - XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Mask); - } -} - -/*****************************************************************************/ -/** -* -* A stub for the asynchronous callback. The stub is here in case the upper -* layers forget to set the handler. -* -* @param CallBackRef is a pointer to the upper layer callback reference -* -* @return None. -* -* @note None. -* -******************************************************************************/ -static void StubHandler(void *CallBackRef) -{ - /* - * Verify that the inputs are valid - */ - Xil_AssertVoid(CallBackRef != NULL); - - /* - * Indicate another unhandled interrupt for stats - */ - ((XIntc *) CallBackRef)->UnhandledInterrupts++; -} - -/*****************************************************************************/ -/** -* -* Looks up the device configuration based on the unique device ID. A table -* contains the configuration info for each device in the system. -* -* @param DeviceId is the unique identifier for a device. -* -* @return A pointer to the XIntc configuration structure for the specified -* device, or NULL if the device was not found. -* -* @note None. -* -******************************************************************************/ -XIntc_Config *XIntc_LookupConfig(u16 DeviceId) -{ - XIntc_Config *CfgPtr = NULL; - int Index; - - for (Index = 0; Index < XPAR_XINTC_NUM_INSTANCES; Index++) { - if (XIntc_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XIntc_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} - -/*****************************************************************************/ -/** -* -* Makes the connection between the Id of the interrupt source and the -* associated handler that is to run when the interrupt is recognized.In Cascade -* mode, connects handler to corresponding Slave controller IVAR register -* depending on the Id and sets all interrupt sources of the Slave controller as -* fast interrupts. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* @param Id contains the ID of the interrupt source and should be in the -* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being -* the highest priority interrupt. -* @param Handler to the handler for that interrupt. -* -* @return -* - XST_SUCCESS -* -* @note -* Slave controllers in Cascade Mode should have all as Fast -* interrupts or Normal interrupts, mixed interrupts are not -* supported -* -* WARNING: The handler provided as an argument will overwrite any handler -* that was previously connected. -* -****************************************************************************/ -int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id, - XFastInterruptHandler Handler) -{ - u32 Imr; - u32 CurrentIER; - u32 Mask; - XIntc_Config *CfgPtr; - - /* - * Assert the arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS); - Xil_AssertNonvoid(Handler != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(InstancePtr->CfgPtr->FastIntr == TRUE); - - - if (Id > 31) { - /* Enable user required Id in Slave controller */ - CfgPtr = XIntc_LookupConfig(Id/32); - - if (CfgPtr->FastIntr != TRUE) { - /*Fast interrupts of slave controller are not enabled*/ - return XST_FAILURE; - } - - /* Get the Enabled Interrupts */ - CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET); - - /* Convert from integer id to bit mask */ - Mask = XIntc_BitPosMask[(Id%32)]; - - /* Disable the Interrupt if it was enabled before calling - * this function - */ - if (CurrentIER & Mask) { - XIntc_Disable(InstancePtr, Id); - } - - XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET + - ((Id%32) * 4), (u32) Handler); - - /* Slave controllers in Cascade Mode should have all as Fast - * interrupts or Normal interrupts, mixed interrupts are not - * supported - */ - XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF); - - /* Enable the Interrupt if it was enabled before calling this - * function - */ - if (CurrentIER & Mask) { - XIntc_Enable(InstancePtr, Id); - } - } - else { - /* Get the Enabled Interrupts */ - CurrentIER = XIntc_In32(InstancePtr->BaseAddress + - XIN_IER_OFFSET); - /* Convert from integer id to bit mask */ - Mask = XIntc_BitPosMask[Id]; - - /* Disable the Interrupt if it was enabled before calling - * this function - */ - if (CurrentIER & Mask) { - XIntc_Disable(InstancePtr, Id); - } - - XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET + - (Id * 4), (u32) Handler); - - Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET); - XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET, - Imr | Mask); - - /* Enable the Interrupt if it was enabled before - * calling this function - */ - if (CurrentIER & Mask) { - XIntc_Enable(InstancePtr, Id); - } - - } - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** -* -* Sets the normal interrupt mode for the specified interrupt in the Interrupt -* Mode Register. In Cascade mode disconnects handler from corresponding Slave -* controller IVAR register depending on the Id and sets all interrupt sources -* of the Slave controller as normal interrupts. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* @param Id contains the ID of the interrupt source and should be in the -* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the -* highest priority interrupt. -* -* @return None. -* -* @note -* Slave controllers in Cascade Mode should have all as Fast -* interrupts or Normal interrupts, mixed interrupts are not -* supported -* -****************************************************************************/ -void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id) -{ - u32 Imr; - u32 CurrentIER; - u32 Mask; - XIntc_Config *CfgPtr; - - /* - * Assert the arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(InstancePtr->CfgPtr->FastIntr == TRUE); - - if (Id > 31) { - /* Enable user required Id in Slave controller */ - CfgPtr = XIntc_LookupConfig(Id/32); - - /* Get the Enabled Interrupts */ - CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET); - - /* Convert from integer id to bit mask */ - Mask = XIntc_BitPosMask[(Id%32)]; - - /* Disable the Interrupt if it was enabled before calling - * this function - */ - if (CurrentIER & Mask) { - XIntc_Disable(InstancePtr, Id); - } - - /* Slave controllers in Cascade Mode should have all as Fast - * interrupts or Normal interrupts, mixed interrupts are not - * supported - */ - XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0x0); - -#ifdef XPAR_MICROBLAZE_BASE_VECTORS - for (Id = 0; Id < 32 ; Id++) - { - XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET - + (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS - + 0x10); - } -#else - for (Id = 0; Id < 32 ; Id++) - { - XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET - + (Id * 4), 0x10); - } -#endif - - /* Enable the Interrupt if it was enabled before calling this - * function - */ - if (CurrentIER & Mask) { - XIntc_Enable(InstancePtr, Id); - } - - } - else { - - /* Get the Enabled Interrupts */ - CurrentIER = XIntc_In32(InstancePtr->BaseAddress + XIN_IER_OFFSET); - Mask = XIntc_BitPosMask[Id];/* Convert from integer id to bit mask */ - - - /* Disable the Interrupt if it was enabled before - * calling this function - */ - if (CurrentIER & Mask) { - XIntc_Disable(InstancePtr, Id); - } - - /* - * Disable the selected interrupt as Fast Interrupt by reading the - * interrupt mode register and then modifying only the - * specified interrupt id - */ - Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET); - XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET, - Imr & ~Mask); - -#ifdef XPAR_MICROBLAZE_BASE_VECTORS - for (Id = 0; Id < 32 ; Id++) - { - XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET - + (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS - + 0x10); - } -#else - for (Id = 0; Id < 32 ; Id++) - { - XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET - + (Id * 4), 0x10); - } -#endif - /* Enable the Interrupt if it was enabled before - * calling this function - */ - if (CurrentIER & Mask) { - XIntc_Enable(InstancePtr, Id); - } - } -} - -/*****************************************************************************/ -/** -* -* Initializes Slave controllers in Cascade mode. The initialization entails: -* - Initial vector table with stub function calls -* - All interrupt sources are disabled for last controller. -* - All interrupt sources are disabled except sources to 31 pin of -* primary and secondary controllers -* - Interrupt outputs are disabled -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* -* @return None -* -* @note None. -* -******************************************************************************/ -static void XIntc_InitializeSlaves(XIntc * InstancePtr) -{ - int Index; - u32 Mask; - XIntc_Config *CfgPtr; - int Id; - - Mask = XIntc_BitPosMask[31]; /* Convert from integer id to bit mask */ - - /* Enable interrupt id with 31 for Master - * interrupt controller - */ - XIntc_Out32(InstancePtr->CfgPtr->BaseAddress + XIN_IER_OFFSET, Mask); - - for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; Index++) { - CfgPtr = XIntc_LookupConfig(Index); - - XIntc_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET, - 0xFFFFFFFF); - if (CfgPtr->IntcType != XIN_INTC_LAST) { - - /* Enable interrupt ids with 31 for secondary - * interrupt controllers - */ - XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET, - Mask); - } else { - XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET, 0x0); - } - - /* Disable Interrupt output */ - XIntc_Out32(CfgPtr->BaseAddress + XIN_MER_OFFSET, 0); - - /* Set all interrupts as normal mode if Fast Interrupts - * are enabled - */ - if(CfgPtr->FastIntr == TRUE) { - XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0); - -#ifdef XPAR_MICROBLAZE_BASE_VECTORS - for (Id = 0; Id < 32 ; Id++) - { - XIntc_Out32(CfgPtr->BaseAddress + - XIN_IVAR_OFFSET + (Id * 4), - XPAR_MICROBLAZE_BASE_VECTORS + 0x10); - } -#else - for (Id = 0; Id < 32 ; Id++) - { - XIntc_Out32(CfgPtr->BaseAddress + - XIN_IVAR_OFFSET + (Id * 4), 0x10); - } -#endif - } - - /* - * Initialize all the data needed to perform interrupt - * processing for each interrupt ID up to the maximum used - */ - for (Id = 0; Id < CfgPtr->NumberofIntrs; Id++) { - - /* - * Initalize the handler to point to a stub to handle an - * interrupt which has not been connected to a handler. - * Only initialize it if the handler is 0 or - * XNullHandler, which means it was not initialized - * statically by the tools/user.Set the callback - * reference to this instance so that unhandled - * interrupts can be tracked. - */ - if ((CfgPtr->HandlerTable[Id].Handler == 0) || - (CfgPtr->HandlerTable[Id].Handler == - XNullHandler)) { - CfgPtr->HandlerTable[Id].Handler = StubHandler; - } - CfgPtr->HandlerTable[Id].CallBackRef = InstancePtr; - } - } -} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc.h deleted file mode 100644 index ff6797d5c..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc.h +++ /dev/null @@ -1,363 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xintc.h -* -* The Xilinx interrupt controller driver component. This component supports the -* Xilinx interrupt controller. -* -* The interrupt controller driver uses the idea of priority for the various -* handlers. Priority is an integer within the range of 0 and 31 inclusive with -* 0 being the highest priority interrupt source. -* -* The Xilinx interrupt controller supports the following features: -* -* - specific individual interrupt enabling/disabling -* - specific individual interrupt acknowledging -* - attaching specific callback function to handle interrupt source -* - master enable/disable -* - single callback per interrupt or all pending interrupts handled for -* each interrupt of the processor -* -* The acknowledgement of the interrupt within the interrupt controller is -* selectable, either prior to the device's handler being called or after -* the handler is called. This is necessary to support interrupt signal inputs -* which are either edge or level signals. Edge driven interrupt signals -* require that the interrupt is acknowledged prior to the interrupt being -* serviced in order to prevent the loss of interrupts which are occurring -* extremely close together. A level driven interrupt input signal requires -* the interrupt to acknowledged after servicing the interrupt to ensure that -* the interrupt only generates a single interrupt condition. -* -* Details about connecting the interrupt handler of the driver are contained -* in the source file specific to interrupt processing, xintc_intr.c. -* -* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads -* or thread mutual exclusion, virtual memory, or cache control must be -* satisfied by the layer above this driver. -* -* Interrupt Vector Tables -* -* The interrupt vector table for each interrupt controller device is declared -* statically in xintc_g.c within the configuration data for each instance. -* The device ID of the interrupt controller device is used by the driver as a -* direct index into the configuration data table - to retrieve the vector table -* for an instance of the interrupt controller. The user should populate the -* vector table with handlers and callbacks at run-time using the XIntc_Connect() -* and XIntc_Disconnect() functions. -* -* Each vector table entry corresponds to a device that can generate an -* interrupt. Each entry contains an interrupt handler function and an argument -* to be passed to the handler when an interrupt occurs. The tools default this -* argument to the base address of the interrupting device. Note that the -* device driver interrupt handlers given in this file do not take a base -* address as an argument, but instead take a pointer to the driver instance. -* This means that although the table is created statically, the user must still -* use XIntc_Connect() when the interrupt handler takes an argument other than -* the base address. This is only to say that the existence of the static vector -* tables should not mislead the user into thinking they no longer need to -* register/connect interrupt handlers with this driver. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm  08/16/01 First release
-* 1.00a rpm  01/09/02 Removed the AckLocation argument from XIntc_Connect().
-*                     This information is now internal in xintc_g.c.
-* 1.00b jhl  02/13/02 Repartitioned the driver for smaller files
-* 1.00b jhl  04/24/02 Made LookupConfig function global and relocated config
-*                     data type
-* 1.00c rpm  10/17/03 New release. Support the static vector table created
-*                     in the xintc_g.c configuration table. Moved vector
-*                     table and options out of instance structure and into
-*                     the configuration table.
-* 1.10c mta  03/21/07 Updated to new coding style
-* 1.11a sv   11/21/07 Updated driver to support access through a DCR bridge
-* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs and _m is removed from
-*		      all the macro names/definitions.
-* 2.01a sdm  04/27/10 Updated the tcl so that the defintions are generated in
-*		      the xparameters.h to know whether the optional registers
-*		      SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
-*		      This driver doesnot make use of these definitions and does
-*		      not use the optional registers.
-* 2.03a hvm  05/24/11 Updated the tcl to generate vector Ids for external
-*		      interrupts. CR565336
-* 2.04a bss  01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
-*		      and XIntc_SetNormalIntrMode for setting to normal
-*		      interrupt mode.
-* 2.04a asa  03/19/12 Changed the XIntc_Config struct. The order of entries
-*		      declared in the structure now matches with the
-*		      XIntc_ConfigTable generated by the driver tcl.
-* 2.05a bss  08/16/12 Updated to support relocatable vectors in Microblaze,
-*		      added IntVectorAddr to XIntc_Config for this.
-*		      Added XIntc_RegisterFastHandler API to register fast
-*		      interrupt handlers using base address.
-* 2.06a bss  01/28/13 To support Cascade mode:
-* 		      Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
-*		      XIN_INTC_SECONDARY,XIN_INTC_LAST and
-*		      XIN_CONTROLLER_MAX_INTRS  macros
-*		      Added NumberofIntrs and IntcType fields in XIntc_Config
-*		      structure.
-*		      Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
-*		      XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
-*		      XIntc_Acknowledge,XIntc_ConnectFastHandler and
-*		      XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
-*		      API in xintc.c
-*  		      Modified XIntc_DeviceInterruptHandler,
-*  		      XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
-*		      XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
-*		      API in xintc_l.c.
-*		      Modified XIntc_SetOptions API in xintc_options.c.
-*		      Modified XIntc_SimulateIntr API in xintc_selftest.c.
-*		      Modified driver tcl:
-*			to check for Cascade mode and generate XPAR_INTC_TYPE
-*			for each controller.
-*			Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
-*			interrupt sources of all Controllers in Cascade mode.
-* 2.07a bss  10/18/13 To support Nested interrupts:
-*		      Modified XIntc_DeviceInterruptHandler API.
-*		      Added XIN_ILR_OFFSET macro in xintc_l.h.
-*		      Modified driver tcl to generate HAS_ILR parameter in
-*		      xparameters.h
-* 3.0   bss  01/28/13 Modified xintc.c to initialize IVAR register with
-*		      XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
-*		      CR#765931.
-*		      Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
-*		      correctly(CR#764865).
-*
-* @note
-*		For Cascade mode, Interrupt IDs are generated in xparameters.h
-*		as shown below:
-*
-*	    Master/Primary INTC
-*		 ______
-*		|      |-0      Secondary INTC
-*		|      |-.         ______
-*		|      |-.        |      |-32        Last INTC
-*		|      |-.        |      |-.          ______
-*		|______|<-31------|      |-.         |      |-64
-*			          |      |-.         |      |-.
-*			          |______|<-63-------|      |-.
-*                                                    |      |-.
-*                                                    |______|-95
-*
-*		All driver functions has to be called using DeviceId/
-*		InstancePtr/BaseAddress of Primary/Master Controller and
-*		Interrupts IDs generated in xparameters.h only.
-*		Driver functions takes care of Slave Controllers based on
-*		Interrupt ID passed. User must not use Interrupt source/ID
-*		31 of Primary and Secondary controllers to call driver
-*		functions.
-*
-*		For nested interrupts, XIntc_DeviceInterruptHandler saves
-*		microblaze r14 register on entry and restores on exit. This is
-*		required since compiler does not support nesting. It enables
-*		Microblaze interrupts after blocking further interrupts from
-*		the current interrupt number and interrupts below current
-*		interrupt proirity by writing to Interrupt Level Register of
-*		INTC on entry. On exit, it disables microblaze interrupts and
-*		restores ILR register default value(0xFFFFFFFF)back. It is
-*		recommended to increase STACK_SIZE in linker script for nested
-*		interrupts.
-* 3.0     adk    12/10/13  Updated as per the New Tcl API's
-* 3.0 	  adk 	 17/02/14  Fixed the CR:771287 Changes are made in the intc
-* 		           driver tcl.
-* 3.1     adk    8/4/14    Fixed the CR:783248 Changes are made in
-*			   the test-app tcl
-* 3.2     bss    4/8/14    Fixed driver tcl to handle external interrupt pins
-*			   correctly (CR#799609).
-*
-*
-* -******************************************************************************/ - -#ifndef XINTC_H /* prevent circular inclusions */ -#define XINTC_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xparameters.h" -#include "xstatus.h" -#include "xintc_l.h" - -/************************** Constant Definitions *****************************/ - -/** - * @name Configuration options - * These options are used in XIntc_SetOptions() to configure the device. - * @{ - */ -/** - * 
- * XIN_SVC_SGL_ISR_OPTION	Service the highest priority pending interrupt
- *				and then return.
- * XIN_SVC_ALL_ISRS_OPTION	Service all of the pending interrupts and then
- *				return.
- *
- */ -#define XIN_SVC_SGL_ISR_OPTION 1UL -#define XIN_SVC_ALL_ISRS_OPTION 2UL -/*@}*/ - -/** - * @name Start modes - * One of these values is passed to XIntc_Start() to start the device. - * @{ - */ -/** Simulation only mode, no hardware interrupts recognized */ -#define XIN_SIMULATION_MODE 0 -/** Real mode, no simulation allowed, hardware interrupts recognized */ -#define XIN_REAL_MODE 1 -/*@}*/ - -/** - * @name Masks to specify Interrupt Controller Mode - * @{ - */ -#define XIN_INTC_NOCASCADE 0 /* Normal - No Cascade Mode */ -#define XIN_INTC_PRIMARY 1 /* Master/Primary controller */ -#define XIN_INTC_SECONDARY 2 /* Secondary Slave Controllers */ -#define XIN_INTC_LAST 3 /* Last Slave Controller */ - -/*@}*/ - -/** - * @name Mask to specify maximum number of interrupt sources per controller - * @{ - */ -#define XIN_CONTROLLER_MAX_INTRS 32 /* Each Controller has 32 - interrupt pins */ -/*@}*/ - -/**************************** Type Definitions *******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Register base address */ - u32 AckBeforeService; /**< Ack location per interrupt */ - int FastIntr; /**< Fast Interrupt enabled */ - u32 IntVectorAddr; /**< Interrupt Vector Address */ - int NumberofIntrs; /**< Number of Interrupt sources */ - u32 Options; /**< Device options */ - int IntcType; /**< Intc type 0 - No Cascade Mode - 1 - primary instance - 2 - secondary instance - 3 - last instance */ - -/** Static vector table of interrupt handlers */ -#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE - XIntc_VectorTableEntry HandlerTable[XIN_CONTROLLER_MAX_INTRS]; -#else - XIntc_VectorTableEntry HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS]; -#endif - -} XIntc_Config; - -/** - * The XIntc driver instance data. The user is required to allocate a - * variable of this type for every intc device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct { - u32 BaseAddress; /**< Base address of registers */ - u32 IsReady; /**< Device is initialized and ready */ - u32 IsStarted; /**< Device has been started */ - u32 UnhandledInterrupts; /**< Intc Statistics */ - XIntc_Config *CfgPtr; /**< Pointer to instance config entry */ - -} XIntc; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/* - * Required functions in xintc.c - */ -int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId); - -int XIntc_Start(XIntc * InstancePtr, u8 Mode); -void XIntc_Stop(XIntc * InstancePtr); - -int XIntc_Connect(XIntc * InstancePtr, u8 Id, - XInterruptHandler Handler, void *CallBackRef); -void XIntc_Disconnect(XIntc * InstancePtr, u8 Id); - -void XIntc_Enable(XIntc * InstancePtr, u8 Id); -void XIntc_Disable(XIntc * InstancePtr, u8 Id); - -void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id); - -XIntc_Config *XIntc_LookupConfig(u16 DeviceId); - -int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id, - XFastInterruptHandler Handler); -void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id); - -/* - * Interrupt functions in xintr_intr.c - */ -void XIntc_VoidInterruptHandler(void); -void XIntc_InterruptHandler(XIntc * InstancePtr); - -/* - * Options functions in xintc_options.c - */ -int XIntc_SetOptions(XIntc * InstancePtr, u32 Options); -u32 XIntc_GetOptions(XIntc * InstancePtr); - -/* - * Self-test functions in xintc_selftest.c - */ -int XIntc_SelfTest(XIntc * InstancePtr); -int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_g.c deleted file mode 100644 index 46e1132d9..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_g.c +++ /dev/null @@ -1,78 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by HSI. -* Version: -* DO NOT EDIT. -* -* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* -*Permission is hereby granted, free of charge, to any person obtaining a copy -*of this software and associated documentation files (the Software), to deal -*in the Software without restriction, including without limitation the rights -*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -*copies of the Software, and to permit persons to whom the Software is -*furnished to do so, subject to the following conditions: -* -*The above copyright notice and this permission notice shall be included in -*all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -*(a) running on a Xilinx device, or -*(b) that interact with a Xilinx device through a bus or interconnect. -* -*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*Except as contained in this notice, the name of the Xilinx shall not be used -*in advertising or otherwise to promote the sale, use or other dealings in -*this Software without prior written authorization from Xilinx. -* - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xintc.h" - - -extern void XNullHandler (void *); - -/* -* The configuration table for devices -*/ - -XIntc_Config XIntc_ConfigTable[] = -{ - { - XPAR_AXI_INTC_0_DEVICE_ID, - XPAR_AXI_INTC_0_BASEADDR, - XPAR_AXI_INTC_0_KIND_OF_INTR, - XPAR_AXI_INTC_0_HAS_FAST, - XPAR_AXI_INTC_0_IVAR_RESET_VALUE, - XPAR_AXI_INTC_0_NUM_INTR_INPUTS, - XIN_SVC_SGL_ISR_OPTION, - XPAR_AXI_INTC_0_TYPE, - { - { - XNullHandler, - (void *) XNULL - }, - { - XNullHandler, - (void *) XNULL - }, - { - XNullHandler, - (void *) XNULL - } - } - - } -}; - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_intr.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_intr.c deleted file mode 100644 index 3e74c0bba..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_intr.c +++ /dev/null @@ -1,173 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xintc_intr.c -* -* This file contains the interrupt processing for the XIntc component which -* is the driver for the Xilinx Interrupt Controller. The interrupt -* processing is partitioned seperately such that users are not required to -* use the provided interrupt processing. This file requires other files of -* the driver to be linked in also. -* -* Two different interrupt handlers are provided for this driver such that the -* user must select the appropriate handler for the application. The first -* interrupt handler, XIntc_VoidInterruptHandler, is provided for systems -* which use only a single interrupt controller or for systems that cannot -* otherwise provide an argument to the XIntc interrupt handler (e.g., the RTOS -* interrupt vector handler may not provide such a facility). The constant -* XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in -* the driver. The second interrupt handler, XIntc_InterruptHandler, uses an -* input argument which is an instance pointer to an interrupt controller driver -* such that multiple interrupt controllers can be supported. This handler -* requires the calling function to pass it the appropriate argument, so another -* level of indirection may be required. -* -* Note that both of these handlers are now only provided for backward -* compatibility. The handler defined in xintc_l.c is the recommended handler. -* -* The interrupt processing may be used by connecting one of the interrupt -* handlers to the interrupt system. These handlers do not save and restore -* the processor context but only handle the processing of the Interrupt -* Controller. The two handlers are provided as working examples. The user is -* encouraged to supply their own interrupt handler when performance tuning is -* deemed necessary. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00b jhl  02/13/02 First release
-* 1.00c rpm  10/17/03 New release. Support the static vector table created
-*                     in the xintc_g.c configuration table. Collapse handlers
-*                     to use the XIntc_DeviceInterruptHandler() in xintc_l.c.
-* 1.00c rpm  04/09/04 Added conditional compilation around the old handler
-*                     XIntc_VoidInterruptHandler(). This handler will only be
-*                     include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is defined.
-* 1.10c mta  03/21/07 Updated to new coding style
-* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs.
-*
-*
-* -* @internal -* -* This driver assumes that the context of the processor has been saved prior to -* the calling of the Interrupt Controller interrupt handler and then restored -* after the handler returns. This requires either the running RTOS to save the -* state of the machine or that a wrapper be used as the destination of the -* interrupt vector to save the state of the processor and restore the state -* after the interrupt handler returns. -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xparameters.h" -#include "xintc.h" - -/************************** Constant Definitions *****************************/ - - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Interrupt handler for the driver used when there can be no argument passed -* to the handler. This function is provided mostly for backward compatibility. -* The user should use XIntc_DeviceInterruptHandler(), defined in xintc_l.c, -* if possible. -* -* The user must connect this function to the interrupt system such that it is -* called whenever the devices which are connected to it cause an interrupt. -* -* @return None. -* -* @note -* -* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler -* to be included in the driver compilation. -* -******************************************************************************/ -#ifdef XPAR_INTC_SINGLE_DEVICE_ID -void XIntc_VoidInterruptHandler(void) -{ - /* Use the single instance to call the main interrupt handler */ - XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID); -} -#endif - -/*****************************************************************************/ -/** -* -* The interrupt handler for the driver. This function is provided mostly for -* backward compatibility. The user should use XIntc_DeviceInterruptHandler(), -* defined in xintc_l.c when possible and pass the device ID of the interrupt -* controller device as its argument. -* -* The user must connect this function to the interrupt system such that it is -* called whenever the devices which are connected to it cause an interrupt. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XIntc_InterruptHandler(XIntc * InstancePtr) -{ - /* Assert that the pointer to the instance is valid - */ - Xil_AssertVoid(InstancePtr != NULL); - - /* Use the instance's device ID to call the main interrupt handler. - * (the casts are to avoid a compiler warning) - */ - XIntc_DeviceInterruptHandler((void *) - ((u32) (InstancePtr->CfgPtr->DeviceId))); -} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_l.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_l.c deleted file mode 100644 index db3b3e258..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_l.c +++ /dev/null @@ -1,662 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xintc_l.c -* -* This file contains low-level driver functions that can be used to access the -* device. The user should refer to the hardware device specification for more -* details of the device operation. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b jhl  04/24/02 First release
-* 1.00c rpm  10/17/03 New release. Support the static vector table created
-*                     in the xintc_g.c configuration table.
-* 1.00c rpm  04/09/04 Added conditional compilation around the old handler
-*                     XIntc_LowLevelInterruptHandler(). This handler will only
-*                     be include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is
-*                     defined.
-* 1.10c mta  03/21/07 Updated to new coding style
-* 1.10c ecm  07/09/07 Read the ISR after the Acknowledge in the interrupt
-*		      handler to support architectures with posted write bus
-*		      access issues.
-* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs and  _m is removed
-*		      from all the macro definitions.
-* 2.04a bss  01/13/12 Removed the unused Register variable for warnings.
-* 2.05a bss  08/18/12 Added XIntc_RegisterFastHandler API to register fast
-*		      interrupt handlers using base address.
-* 2.06a bss  01/28/13 To support Cascade mode:
-*		      Modified XIntc_DeviceInterruptHandler,
-*		      XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
-*		      XIntc_RegisterFastHandler APIs.
-*		      Added XIntc_CascadeHandler API.
-* 2.07a bss  10/18/13 Modified XIntc_DeviceInterruptHandler to support
-*		      nested interrupts.
-*
-*
-* -******************************************************************************/ - - -/***************************** Include Files *********************************/ - -#include "xparameters.h" -#include "xil_types.h" -#include "xil_assert.h" -#include "xintc.h" -#include "xintc_i.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress); - -#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE -static void XIntc_CascadeHandler(void *DeviceId); -#endif - -/************************** Variable Definitions *****************************/ - -/*****************************************************************************/ -/** -* -* This is the interrupt handler for the driver interface provided in this file -* when there can be no argument passed to the handler. In this case, we just -* use the globally defined device ID for the interrupt controller. This function -* is provided mostly for backward compatibility. The user should use -* XIntc_DeviceInterruptHandler() if possible. -* -* This function does not support multiple interrupt controller instances to be -* handled. -* -* The user must connect this function to the interrupt system such that it is -* called whenever the devices which are connected to it cause an interrupt. -* -* @return None. -* -* @note -* -* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler -* to be included in the driver compilation. -* -******************************************************************************/ -#ifdef XPAR_INTC_SINGLE_DEVICE_ID -void XIntc_LowLevelInterruptHandler(void) -{ - /* - * A level of indirection here because the interrupt handler used with - * the driver interface given in this file needs to remain void - no - * arguments. So we need the globally defined device ID of THE - * interrupt controller. - */ - XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID); -} -#endif - -/*****************************************************************************/ -/** -* -* This function is the primary interrupt handler for the driver. It must be -* connected to the interrupt source such that is called when an interrupt of -* the interrupt controller is active. It will resolve which interrupts are -* active and enabled and call the appropriate interrupt handler. It uses -* the AckBeforeService flag in the configuration data to determine when to -* acknowledge the interrupt. Highest priority interrupts are serviced first. -* This function assumes that an interrupt vector table has been previously -* initialized.It does not verify that entries in the table are valid before -* calling an interrupt handler. In Cascade mode this function calls -* XIntc_CascadeHandler to handle interrupts of Master and Slave controllers. -* This functions also handles interrupts nesting by saving and restoring link -* register of Microblaze and Interrupt Level register of interrupt controller -* properly. - -* @param DeviceId is the zero-based device ID defined in xparameters.h -* of the interrupting interrupt controller. It is used as a direct -* index into the configuration data, which contains the vector -* table for the interrupt controller. Note that even though the -* argument is a void pointer, the value is not a pointer but the -* actual device ID. The void pointer type is necessary to meet -* the XInterruptHandler typedef for interrupt handlers. -* -* @return None. -* -* @note For nested interrupts, this function saves microblaze r14 -* register on entry and restores on exit. This is required since -* compiler does not support nesting. This function enables -* Microblaze interrupts after blocking further interrupts -* from the current interrupt number and interrupts below current -* interrupt proirity by writing to Interrupt Level Register of -* INTC on entry. On exit, it disables microblaze interrupts and -* restores ILR register default value(0xFFFFFFFF)back. It is -* recommended to increase STACK_SIZE in linker script for nested -* interrupts. -* -******************************************************************************/ -void XIntc_DeviceInterruptHandler(void *DeviceId) -{ - u32 IntrStatus; - u32 IntrMask = 1; - int IntrNumber; - XIntc_Config *CfgPtr; - u32 Imr; - - /* Get the configuration data using the device ID */ - CfgPtr = &XIntc_ConfigTable[(u32)DeviceId]; - -#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE - if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) { - XIntc_CascadeHandler(DeviceId); - } - else -#endif - { /* This extra brace is required for compilation in Cascade Mode */ - -#if XPAR_XINTC_HAS_ILR == TRUE -#ifdef __MICROBLAZE__ - volatile u32 R14_register; - /* Save r14 register */ - R14_register = mfgpr(r14); -#endif - volatile u32 ILR_reg; - /* Save ILR register */ - ILR_reg = Xil_In32(CfgPtr->BaseAddress + XIN_ILR_OFFSET); -#endif - /* Get the interrupts that are waiting to be serviced */ - IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress); - - /* Mask the Fast Interrupts */ - if (CfgPtr->FastIntr == TRUE) { - Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET); - IntrStatus &= ~Imr; - } - - /* Service each interrupt that is active and enabled by - * checking each bit in the register from LSB to MSB which - * corresponds to an interrupt input signal - */ - for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs; - IntrNumber++) { - if (IntrStatus & 1) { - XIntc_VectorTableEntry *TablePtr; -#if XPAR_XINTC_HAS_ILR == TRUE - /* Write to ILR the current interrupt - * number - */ - Xil_Out32(CfgPtr->BaseAddress + - XIN_ILR_OFFSET, IntrNumber); - - /* Read back ILR to ensure the value - * has been updated and it is safe to - * enable interrupts - */ - - Xil_In32(CfgPtr->BaseAddress + - XIN_ILR_OFFSET); - - /* Enable interrupts */ - Xil_ExceptionEnable(); -#endif - /* If the interrupt has been setup to - * acknowledge it before servicing the - * interrupt, then ack it */ - if (CfgPtr->AckBeforeService & IntrMask) { - XIntc_AckIntr(CfgPtr->BaseAddress, - IntrMask); - } - - /* The interrupt is active and enabled, call - * the interrupt handler that was setup with - * the specified parameter - */ - TablePtr = &(CfgPtr->HandlerTable[IntrNumber]); - TablePtr->Handler(TablePtr->CallBackRef); - - /* If the interrupt has been setup to - * acknowledge it after it has been serviced - * then ack it - */ - if ((CfgPtr->AckBeforeService & - IntrMask) == 0) { - XIntc_AckIntr(CfgPtr->BaseAddress, - IntrMask); - } - -#if XPAR_XINTC_HAS_ILR == TRUE - /* Disable interrupts */ - Xil_ExceptionDisable(); - /* Restore ILR */ - Xil_Out32(CfgPtr->BaseAddress + XIN_ILR_OFFSET, - ILR_reg); -#endif - /* - * Read the ISR again to handle architectures - * with posted write bus access issues. - */ - XIntc_GetIntrStatus(CfgPtr->BaseAddress); - - /* - * If only the highest priority interrupt is to - * be serviced, exit loop and return after - * servicing - * the interrupt - */ - if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) { - -#if XPAR_XINTC_HAS_ILR == TRUE -#ifdef __MICROBLAZE__ - /* Restore r14 */ - mtgpr(r14, R14_register); -#endif -#endif - return; - } - } - - /* Move to the next interrupt to check */ - IntrMask <<= 1; - IntrStatus >>= 1; - - /* If there are no other bits set indicating that all - * interrupts have been serviced, then exit the loop - */ - if (IntrStatus == 0) { - break; - } - } -#if XPAR_XINTC_HAS_ILR == TRUE -#ifdef __MICROBLAZE__ - /* Restore r14 */ - mtgpr(r14, R14_register); -#endif -#endif - } -} - -/*****************************************************************************/ -/** -* -* Set the interrupt service option, which can configure the driver so that it -* services only a single interrupt at a time when an interrupt occurs, or -* services all pending interrupts when an interrupt occurs. The default -* behavior when using the driver interface given in xintc.h file is to service -* only a single interrupt, whereas the default behavior when using the driver -* interface given in this file is to service all outstanding interrupts when an -* interrupt occurs. In Cascade mode same Option is set to Slave controllers. -* -* @param BaseAddress is the unique identifier for a device. -* @param Option is XIN_SVC_SGL_ISR_OPTION if you want only a single -* interrupt serviced when an interrupt occurs, or -* XIN_SVC_ALL_ISRS_OPTION if you want all pending interrupts -* serviced when an interrupt occurs. -* -* @return None. -* -* @note -* -* Note that this function has no effect if the input base address is invalid. -* -******************************************************************************/ -void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option) -{ - XIntc_Config *CfgPtr; - - CfgPtr = LookupConfigByBaseAddress(BaseAddress); - if (CfgPtr != NULL) { - CfgPtr->Options = Option; - /* If Cascade mode set the option for all Slaves */ - if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) { - int Index; - for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; - Index++) { - CfgPtr = XIntc_LookupConfig(Index); - CfgPtr->Options = Option; - } - } - } -} - -/*****************************************************************************/ -/** -* -* Register a handler function for a specific interrupt ID. The vector table -* of the interrupt controller is updated, overwriting any previous handler. -* The handler function will be called when an interrupt occurs for the given -* interrupt ID. -* -* This function can also be used to remove a handler from the vector table -* by passing in the XIntc_DefaultHandler() as the handler and NULL as the -* callback reference. -* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave -* Controller -* -* @param BaseAddress is the base address of the interrupt controller -* whose vector table will be modified. -* @param InterruptId is the interrupt ID to be associated with the input -* handler. -* @param Handler is the function pointer that will be added to -* the vector table for the given interrupt ID. -* @param CallBackRef is the argument that will be passed to the new -* handler function when it is called. This is user-specific. -* -* @return None. -* -* @note -* -* Note that this function has no effect if the input base address is invalid. -* -******************************************************************************/ -void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId, - XInterruptHandler Handler, void *CallBackRef) -{ - XIntc_Config *CfgPtr; - - CfgPtr = LookupConfigByBaseAddress(BaseAddress); - - if (CfgPtr != NULL) { - - if (InterruptId > 31) { - CfgPtr = XIntc_LookupConfig(InterruptId/32); - CfgPtr->HandlerTable[InterruptId%32].Handler = Handler; - CfgPtr->HandlerTable[InterruptId%32].CallBackRef = - CallBackRef; - } - else { - CfgPtr->HandlerTable[InterruptId].Handler = Handler; - CfgPtr->HandlerTable[InterruptId].CallBackRef = - CallBackRef; - } - } -} - - -/*****************************************************************************/ -/** -* -* Looks up the device configuration based on the base address of the device. -* A table contains the configuration info for each device in the system. -* -* @param BaseAddress is the unique identifier for a device. -* -* @return -* -* A pointer to the configuration structure for the specified device, or -* NULL if the device was not found. -* -* @note None. -* -******************************************************************************/ -static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress) -{ - XIntc_Config *CfgPtr = NULL; - int Index; - - for (Index = 0; Index < XPAR_XINTC_NUM_INSTANCES; Index++) { - if (XIntc_ConfigTable[Index].BaseAddress == BaseAddress) { - CfgPtr = &XIntc_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} - -/*****************************************************************************/ -/** -* -* Register a fast handler function for a specific interrupt ID. The handler -* function will be called when an interrupt occurs for the given interrupt ID. -* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave -* Controller -* -* @param BaseAddress is the base address of the interrupt controller -* whose vector table will be modified. -* @param InterruptId is the interrupt ID to be associated with the input -* handler. -* @param FastHandler is the function pointer that will be called when -* interrupt occurs -* -* @return None. -* -* @note -* -* Note that this function has no effect if the input base address is invalid. -* -******************************************************************************/ -void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id, - XFastInterruptHandler FastHandler) -{ - u32 CurrentIER; - u32 Mask; - u32 Imr; - XIntc_Config *CfgPtr; - - - if (Id > 31) { - /* Enable user required Id in Slave controller */ - CfgPtr = XIntc_LookupConfig(Id/32); - - /* Get the Enabled Interrupts */ - CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET); - - /* Convert from integer id to bit mask */ - Mask = XIntc_BitPosMask[(Id%32)]; - - /* Disable the Interrupt if it was enabled before calling - * this function - */ - if (CurrentIER & Mask) { - XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET, - (CurrentIER & ~Mask)); - } - - XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET + - ((Id%32) * 4), (u32) FastHandler); - - /* Slave controllers in Cascade Mode should have all as Fast - * interrupts or Normal interrupts, mixed interrupts are not - * supported - */ - XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF); - - /* Enable the Interrupt if it was enabled before calling this - * function - */ - if (CurrentIER & Mask) { - XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET, - (CurrentIER | Mask)); - } - } - else { - - CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET); - - /* Convert from integer id to bit mask */ - Mask = XIntc_BitPosMask[Id]; - - if (CurrentIER & Mask) { - /* Disable Interrupt if it was enabled */ - CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET); - XIntc_Out32(BaseAddress + XIN_IER_OFFSET, - (CurrentIER & ~Mask)); - } - - XIntc_Out32(BaseAddress + XIN_IVAR_OFFSET + (Id * 4), - (u32) FastHandler); - - Imr = XIntc_In32(BaseAddress + XIN_IMR_OFFSET); - XIntc_Out32(BaseAddress + XIN_IMR_OFFSET, Imr | Mask); - - - /* Enable Interrupt if it was enabled before calling - * this function - */ - if (CurrentIER & Mask) { - CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET); - XIntc_Out32(BaseAddress + XIN_IER_OFFSET, - (CurrentIER | Mask)); - } - } -} - -#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE -/*****************************************************************************/ -/** -* -* This function is called by primary interrupt handler for the driver to handle -* all Controllers in Cascade mode.It will resolve which interrupts are active -* and enabled and call the appropriate interrupt handler. It uses the -* AckBeforeService flag in the configuration data to determine when to -* acknowledge the interrupt. Highest priority interrupts are serviced first. -* This function assumes that an interrupt vector table has been previously -* initialized. It does not verify that entries in the table are valid before -* calling an interrupt handler.This function calls itself recursively to handle -* all interrupt controllers. -* -* @param DeviceId is the zero-based device ID defined in xparameters.h -* of the interrupting interrupt controller. It is used as a direct -* index into the configuration data, which contains the vector -* table for the interrupt controller. -* -* @return None. -* -* @note -* -******************************************************************************/ -static void XIntc_CascadeHandler(void *DeviceId) -{ - u32 IntrStatus; - u32 IntrMask = 1; - int IntrNumber; - u32 Imr; - XIntc_Config *CfgPtr; - static int Id = 0; - - /* Get the configuration data using the device ID */ - CfgPtr = &XIntc_ConfigTable[(u32)DeviceId]; - - /* Get the interrupts that are waiting to be serviced */ - IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress); - - /* Mask the Fast Interrupts */ - if (CfgPtr->FastIntr == TRUE) { - Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET); - IntrStatus &= ~Imr; - } - - /* Service each interrupt that is active and enabled by - * checking each bit in the register from LSB to MSB which - * corresponds to an interrupt input signal - */ - for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs; IntrNumber++) { - if (IntrStatus & 1) { - XIntc_VectorTableEntry *TablePtr; - - /* In Cascade mode call this function recursively - * for interrupt id 31 and until interrupts of last - * instance/controller are handled - */ - if ((IntrNumber == 31) && - (CfgPtr->IntcType != XIN_INTC_LAST) && - (CfgPtr->IntcType != XIN_INTC_NOCASCADE)) { - XIntc_CascadeHandler((void *)++Id); - Id--; - } - - /* If the interrupt has been setup to - * acknowledge it before servicing the - * interrupt, then ack it */ - if (CfgPtr->AckBeforeService & IntrMask) { - XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask); - } - - /* Handler of 31 interrupt Id has to be called only - * for Last controller in cascade Mode - */ - if (!((IntrNumber == 31) && - (CfgPtr->IntcType != XIN_INTC_LAST) && - (CfgPtr->IntcType != XIN_INTC_NOCASCADE))) { - - /* The interrupt is active and enabled, call - * the interrupt handler that was setup with - * the specified parameter - */ - TablePtr = &(CfgPtr->HandlerTable[IntrNumber]); - TablePtr->Handler(TablePtr->CallBackRef); - } - /* If the interrupt has been setup to acknowledge it - * after it has been serviced then ack it - */ - if ((CfgPtr->AckBeforeService & IntrMask) == 0) { - XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask); - } - - /* - * Read the ISR again to handle architectures with - * posted write bus access issues. - */ - XIntc_GetIntrStatus(CfgPtr->BaseAddress); - - /* - * If only the highest priority interrupt is to be - * serviced, exit loop and return after servicing - * the interrupt - */ - if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) { - return; - } - } - - /* Move to the next interrupt to check */ - IntrMask <<= 1; - IntrStatus >>= 1; - - /* If there are no other bits set indicating that all interrupts - * have been serviced, then exit the loop - */ - if (IntrStatus == 0) { - break; - } - } -} -#endif diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_l.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_l.h deleted file mode 100644 index 65b660b4e..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_l.h +++ /dev/null @@ -1,327 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xintc_l.h -* -* This header file contains identifiers and low-level driver functions (or -* macros) that can be used to access the device. The user should refer to the -* hardware device specification for more details of the device operation. -* -* -* Note that users of the driver interface given in this file can register -* an interrupt handler dynamically (at run-time) using the -* XIntc_RegisterHandler() function. -* User of the driver interface given in xintc.h should still use -* XIntc_Connect(), as always. -* Also see the discussion of the interrupt vector tables in xintc.h. -* -* There are currently two interrupt handlers specified in this interface. -* -* - XIntc_LowLevelInterruptHandler() is a handler without any arguments that -* is used in cases where there is a single interrupt controller device in -* the system and the handler cannot be passed an argument. This function is -* provided mostly for backward compatibility. -* -* - XIntc_DeviceInterruptHandler() is a handler that takes a device ID as an -* argument, indicating which interrupt controller device in the system is -* causing the interrupt - thereby supporting multiple interrupt controllers. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00b jhl  04/24/02 First release
-* 1.00c rpm  10/17/03 New release. Support the static vector table created
-*                     in the xintc_g.c configuration table.
-* 1.10c mta  03/21/07 Updated to new coding style
-* 1.11a sv   11/21/07 Updated driver to support access through a DCR bridge
-* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs. _m is removed from all
-*		      the macro definitions.
-* 2.04a bss  01/13/12 Updated for adding defines for IMR and IVAR for
-*                     the FAST Interrupt
-* 2.05a bss  08/18/12 Added XIntc_RegisterFastHandler API to register fast
-*		      interrupt handlers using base address.
-* 2.07a bss  10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.
-*
-*
-* -******************************************************************************/ - -#ifndef XINTC_L_H /* prevent circular inclusions */ -#define XINTC_L_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xparameters.h" -#include "xil_io.h" - -/* - * XPAR_XINTC_USE_DCR_BRIDGE has to be set to 1 if the Intc device will be - * accessed through a DCR bus connected to a bridge. - */ -#define XPAR_XINTC_USE_DCR_BRIDGE 0 - -#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) -#include "xio_dcr.h" -#endif - -/************************** Constant Definitions *****************************/ - -/* define the offsets from the base address for all the registers of the - * interrupt controller, some registers may be optional in the hardware device - */ -#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) - -#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */ -#define XIN_IPR_OFFSET 1 /* Interrupt Pending Register */ -#define XIN_IER_OFFSET 2 /* Interrupt Enable Register */ -#define XIN_IAR_OFFSET 3 /* Interrupt Acknowledge Register */ -#define XIN_SIE_OFFSET 4 /* Set Interrupt Enable Register */ -#define XIN_CIE_OFFSET 5 /* Clear Interrupt Enable Register */ -#define XIN_IVR_OFFSET 6 /* Interrupt Vector Register */ -#define XIN_MER_OFFSET 7 /* Master Enable Register */ -#define XIN_IMR_OFFSET 8 /* Interrupt Mode Register , this is present - * only for Fast Interrupt */ -#define XIN_IVAR_OFFSET 64 /* Interrupt Vector Address Register - * Interrupt 0 Offest, this is present - * only for Fast Interrupt */ - -#else /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */ - -#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */ -#define XIN_IPR_OFFSET 4 /* Interrupt Pending Register */ -#define XIN_IER_OFFSET 8 /* Interrupt Enable Register */ -#define XIN_IAR_OFFSET 12 /* Interrupt Acknowledge Register */ -#define XIN_SIE_OFFSET 16 /* Set Interrupt Enable Register */ -#define XIN_CIE_OFFSET 20 /* Clear Interrupt Enable Register */ -#define XIN_IVR_OFFSET 24 /* Interrupt Vector Register */ -#define XIN_MER_OFFSET 28 /* Master Enable Register */ -#define XIN_IMR_OFFSET 32 /* Interrupt Mode Register , this is present - * only for Fast Interrupt */ -#define XIN_ILR_OFFSET 36 /* Interrupt level register */ -#define XIN_IVAR_OFFSET 0x100 /* Interrupt Vector Address Register - * Interrupt 0 Offest, this is present - * only for Fast Interrupt */ - - - -#endif /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */ - -/* Bit definitions for the bits of the MER register */ - -#define XIN_INT_MASTER_ENABLE_MASK 0x1UL -#define XIN_INT_HARDWARE_ENABLE_MASK 0x2UL /* once set cannot be cleared */ - -/**************************** Type Definitions *******************************/ - -/* The following data type defines each entry in an interrupt vector table. - * The callback reference is the base address of the interrupting device - * for the driver interface given in this file and an instance pointer for the - * driver interface given in xintc.h file. - */ -typedef struct { - XInterruptHandler Handler; - void *CallBackRef; -} XIntc_VectorTableEntry; - -typedef void (*XFastInterruptHandler) (void); - -/***************** Macros (Inline Functions) Definitions *********************/ - -/* - * Define the appropriate I/O access method to memory mapped I/O or DCR. - */ -#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) - -#define XIntc_In32 XIo_DcrIn -#define XIntc_Out32 XIo_DcrOut - -#else - -#define XIntc_In32 Xil_In32 -#define XIntc_Out32 Xil_Out32 - -#endif - -/****************************************************************************/ -/** -* -* Enable all interrupts in the Master Enable register of the interrupt -* controller. The interrupt controller defaults to all interrupts disabled -* from reset such that this macro must be used to enable interrupts. -* -* @param BaseAddress is the base address of the device. -* -* @return None. -* -* @note C-style signature: -* void XIntc_MasterEnable(u32 BaseAddress); -* -*****************************************************************************/ -#define XIntc_MasterEnable(BaseAddress) \ - XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, \ - XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK) - -/****************************************************************************/ -/** -* -* Disable all interrupts in the Master Enable register of the interrupt -* controller. -* -* @param BaseAddress is the base address of the device. -* -* @return None. -* -* @note C-style signature: -* void XIntc_MasterDisable(u32 BaseAddress); -* -*****************************************************************************/ -#define XIntc_MasterDisable(BaseAddress) \ - XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0) - -/****************************************************************************/ -/** -* -* Enable specific interrupt(s) in the interrupt controller. -* -* @param BaseAddress is the base address of the device -* @param EnableMask is the 32-bit value to write to the enable register. -* Each bit of the mask corresponds to an interrupt input signal -* that is connected to the interrupt controller (INT0 = LSB). -* Only the bits which are set in the mask will enable interrupts. -* -* @return None. -* -* @note C-style signature: -* void XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask); -* -*****************************************************************************/ -#define XIntc_EnableIntr(BaseAddress, EnableMask) \ - XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask)) - -/****************************************************************************/ -/** -* -* Disable specific interrupt(s) in the interrupt controller. -* -* @param BaseAddress is the base address of the device -* @param DisableMask is the 32-bit value to write to the enable register. -* Each bit of the mask corresponds to an interrupt input signal -* that is connected to the interrupt controller (INT0 = LSB). -* Only the bits which are set in the mask will disable interrupts. -* -* @return None. -* -* @note C-style signature: -* void XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask); -* -*****************************************************************************/ -#define XIntc_DisableIntr(BaseAddress, DisableMask) \ - XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask)) - -/****************************************************************************/ -/** -* -* Acknowledge specific interrupt(s) in the interrupt controller. -* -* @param BaseAddress is the base address of the device -* @param AckMask is the 32-bit value to write to the acknowledge -* register. Each bit of the mask corresponds to an interrupt input -* signal that is connected to the interrupt controller (INT0 = -* LSB). Only the bits which are set in the mask will acknowledge -* interrupts. -* -* @return None. -* -* @note C-style signature: -* void XIntc_AckIntr(u32 BaseAddress, u32 AckMask); -* -*****************************************************************************/ -#define XIntc_AckIntr(BaseAddress, AckMask) \ - XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask)) - -/****************************************************************************/ -/** -* -* Get the interrupt status from the interrupt controller which indicates -* which interrupts are active and enabled. -* -* @param BaseAddress is the base address of the device -* -* @return The 32-bit contents of the interrupt status register. Each bit -* corresponds to an interrupt input signal that is connected to -* the interrupt controller (INT0 = LSB). Bits which are set -* indicate an active interrupt which is also enabled. -* -* @note C-style signature: -* u32 XIntc_GetIntrStatus(u32 BaseAddress); -* -*****************************************************************************/ -#define XIntc_GetIntrStatus(BaseAddress) \ - (XIntc_In32((BaseAddress) + XIN_ISR_OFFSET) & \ - XIntc_In32((BaseAddress) + XIN_IER_OFFSET)) - -/************************** Function Prototypes ******************************/ - -/* - * Interrupt controller handlers, to be connected to processor exception - * handling code. - */ -void XIntc_LowLevelInterruptHandler(void); -void XIntc_DeviceInterruptHandler(void *DeviceId); - -/* Various configuration functions */ -void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option); - -void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId, - XInterruptHandler Handler, void *CallBackRef); - -void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id, - XFastInterruptHandler FastHandler); - -/************************** Variable Definitions *****************************/ - - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_options.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_options.c deleted file mode 100644 index d366b42d4..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_options.c +++ /dev/null @@ -1,146 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xintc_options.c -* -* Contains option functions for the XIntc driver. These functions allow the -* user to configure an instance of the XIntc driver. This file requires other -* files of the component to be linked in also. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00b jhl  02/21/02 First release
-* 1.00c rpm  10/17/03 New release. Support the relocation of the options flag
-*                     from the instance structure to the xintc_g.c
-*                     configuration table.
-* 1.10c mta  03/21/07 Updated to new coding style
-* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs
-* 2.06a bss  01/28/13 To support Cascade mode:
-*		      Modified XIntc_SetOptions API.
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xintc.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Set the options for the interrupt controller driver. In Cascade mode same -* Option is set to Slave controllers. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* @param Options to be set. The available options are described in -* xintc.h. -* -* @return -* - XST_SUCCESS if the options were set successfully -* - XST_INVALID_PARAM if the specified option was not valid -* -* @note None. -* -****************************************************************************/ -int XIntc_SetOptions(XIntc * InstancePtr, u32 Options) -{ - XIntc_Config *CfgPtr; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Make sure option request is valid - */ - if ((Options == XIN_SVC_SGL_ISR_OPTION) || - (Options == XIN_SVC_ALL_ISRS_OPTION)) { - InstancePtr->CfgPtr->Options = Options; - /* If Cascade mode set the option for all Slaves */ - if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) { - int Index; - for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; - Index++) { - CfgPtr = XIntc_LookupConfig(Index); - CfgPtr->Options = Options; - } - } - return XST_SUCCESS; - } - else { - return XST_INVALID_PARAM; - } -} - -/*****************************************************************************/ -/** -* -* Return the currently set options. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* -* @return The currently set options. The options are described in xintc.h. -* -* @note None. -* -****************************************************************************/ -u32 XIntc_GetOptions(XIntc * InstancePtr) -{ - /* - * Assert the arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - return InstancePtr->CfgPtr->Options; -} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_selftest.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_selftest.c deleted file mode 100644 index f6ced2928..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_selftest.c +++ /dev/null @@ -1,252 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xintc_selftest.c -* -* Contains diagnostic self-test functions for the XIntc component. This file -* requires other files of the component to be linked in also. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl  02/21/02 First release
-* 1.10c mta  03/21/07 Updated to new coding style
-* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs
-* 2.04a bss  01/16/12 Removed CurrentMIE variable and reading of the
-*                     MER register to remove warnings
-* 2.06a bss  01/28/13 To support Cascade mode:
-*		      Modified XIntc_SimulateIntr API.
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xintc.h" -#include "xintc_i.h" - -/************************** Constant Definitions *****************************/ - -#define XIN_TEST_MASK 1 - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Run a self-test on the driver/device. This is a destructive test. -* -* This involves forcing interrupts into the controller and verifying that they -* are recognized and can be acknowledged. This test will not succeed if the -* interrupt controller has been started in real mode such that interrupts -* cannot be forced. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* -* @return -* - XST_SUCCESS if self-test is successful. -* - XST_INTC_FAIL_SELFTEST if the Interrupt controller fails the -* self-test. It will fail the self test if the device has -* previously been started in real mode. -* -* @note None. -* -******************************************************************************/ -int XIntc_SelfTest(XIntc * InstancePtr) -{ - u32 CurrentISR; - u32 Temp; - - /* - * Assert the arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - - /* - * Acknowledge all pending interrupts by reading the interrupt status - * register and writing the value to the acknowledge register - */ - Temp = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET); - - XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Temp); - - /* - * Verify that there are no interrupts by reading the interrupt status - */ - CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET); - - /* - * ISR should be zero after all interrupts are acknowledged - */ - if (CurrentISR != 0) { - return XST_INTC_FAIL_SELFTEST; - } - - /* - * Set a bit in the ISR which simulates an interrupt - */ - XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, XIN_TEST_MASK); - - /* - * Verify that it was set - */ - CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET); - - if (CurrentISR != XIN_TEST_MASK) { - return XST_INTC_FAIL_SELFTEST; - } - - /* - * Acknowledge the interrupt - */ - XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, XIN_TEST_MASK); - - /* - * Read back the ISR to verify that the interrupt is gone - */ - CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET); - - if (CurrentISR != 0) { - return XST_INTC_FAIL_SELFTEST; - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Allows software to simulate an interrupt in the interrupt controller. This -* function will only be successful when the interrupt controller has been -* started in simulation mode. Once it has been started in real mode, -* interrupts cannot be simulated. A simulated interrupt allows the interrupt -* controller to be tested without any device to drive an interrupt input -* signal into it. In Cascade mode writes to ISR of appropraite Slave -* controller depending on Id. -* -* @param InstancePtr is a pointer to the XIntc instance to be worked on. -* @param Id is the interrupt ID for which to simulate an interrupt. -* -* @return -* - XST_SUCCESS if successful -* - XST_FAILURE if the interrupt could not be -* simulated because the interrupt controller is or -* has previously been in real mode. -* -* @note None. -* -******************************************************************************/ -int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id) -{ - u32 Mask; - u32 MasterEnable; - XIntc_Config *CfgPtr; - int Index; - int DeviceId; - - /* - * Assert the arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS); - - - /* Get the contents of the master enable register and determine if - * hardware interrupts have already been enabled, if so, this is a write - * once bit such that simulation can't be done at this point because - * the ISR register is no longer writable by software - */ - MasterEnable = XIntc_In32(InstancePtr->BaseAddress + XIN_MER_OFFSET); - if (MasterEnable & XIN_INT_HARDWARE_ENABLE_MASK) { - return XST_FAILURE; - } - - - if (Id > 31) { - - DeviceId = Id/32; - - CfgPtr = XIntc_LookupConfig(Id/32); - Mask = XIntc_BitPosMask[Id%32]; - XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET, Mask); - - /* Generate interrupt for 31 by writing to Interrupt Status - * register of parent controllers. Primary controller ISR - * will be written last in the loop - */ - Mask = XIntc_BitPosMask[31]; - for (Index = DeviceId - 1; Index >= 0; Index--) - { - CfgPtr = XIntc_LookupConfig(Index); - - XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET, - Mask); - } - } - else { - /* - * The Id is used to create the appropriate mask for the - * desired bit position. - */ - Mask = XIntc_BitPosMask[Id]; - - /* - * Enable the selected interrupt source by reading the interrupt - * enable register and then modifying only the specified - * interrupt id enable - */ - XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, Mask); - - } - /* indicate the interrupt was successfully simulated */ - - return XST_SUCCESS; -} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/mig_7series_v2_0/src/xmig_7series.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/mig_7series_v2_0/src/xmig_7series.h index dcd05c100..12b2884c2 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/mig_7series_v2_0/src/xmig_7series.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/mig_7series_v2_0/src/xmig_7series.h @@ -33,6 +33,9 @@ /** * * @file xmig_7series.h +* @addtogroup mig_7series_v2_0 +* @{ +* @details * This driver exists only to allow the SDK tools to create a memory test * application and to populate xparameters.h with memory range constants. * There is no source code. @@ -40,3 +43,4 @@ * 2.0 adk 19/12/13 Updated as per the New Tcl API's * ******************************************************************************/ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_dcache.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_dcache.S deleted file mode 100644 index e47160be9..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_dcache.S +++ /dev/null @@ -1,68 +0,0 @@ -/****************************************************************************** -* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. -* -* Xilinx, Inc. -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -* AND FITNESS FOR A PARTICULAR PURPOSE. -* -* File : microblaze_disable_dcache.s -* Date : 2002, March 20. -* Company: Xilinx -* Group : Emerging Software Technologies -* -* Summary: -* Disable the L1 dcache on the microblaze. -* -*******************************************************************************/ - -#include "xparameters.h" - - .text - .globl microblaze_disable_dcache - .ent microblaze_disable_dcache - .align 2 -microblaze_disable_dcache: -#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 - -#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 - addik r1, r1, -4 - swi r15, r1, 0 - brlid r15, microblaze_flush_dcache /* microblaze_flush_dcache does not use r1*/ - nop - lwi r15, r1, 0 - addi r1, r1, 4 -#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */ - rtsd r15, 8 - msrclr r0, 0x80 - -#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 1 */ - - addik r1, r1, -4 - -#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 - swi r15, r1, 0 - brlid r15, microblaze_flush_dcache - nop -#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */ - mfs r11, rmsr - andi r11, r11, ~(0x80) - mts rmsr, r11 - -#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 - lwi r15, r1, 0 -#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */ - - rtsd r15, 8 - addi r1, r1, 4 - -#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ - .end microblaze_disable_dcache diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_timer_hw.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_timer_hw.c deleted file mode 100644 index f3552b8c8..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_timer_hw.c +++ /dev/null @@ -1,360 +0,0 @@ -// $Id: _profile_timer_hw.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $ -/****************************************************************************** -* -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -****************************************************************************** -* -* _program_timer_hw.c: -* Timer related functions -* -******************************************************************************/ - -#include "profile.h" -#include "_profile_timer_hw.h" - -#include "xil_exception.h" - -#ifdef PROC_PPC -#include "xtime_l.h" -#include "xpseudo_asm.h" -#endif - -#ifdef TIMER_CONNECT_INTC -#include "xintc_l.h" -#include "xintc.h" -#endif // TIMER_CONNECT_INTC - -//#ifndef PPC_PIT_INTERRUPT -#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) -#include "xtmrctr_l.h" -#endif - -extern unsigned int timer_clk_ticks ; - -//-------------------------------------------------------------------- -// PowerPC Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_PPC405 - - -//-------------------------------------------------------------------- -// PowerPC PIT Timer Init. -// Defined only if PIT Timer is used for Profiling -// -//-------------------------------------------------------------------- -#ifdef PPC_PIT_INTERRUPT -int ppc_pit_init( void ) -{ - // 1. Register Profile_intr_handler as Interrupt handler - // 2. Set PIT Timer Interrupt and Enable it. - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); - XTime_PITSetInterval( timer_clk_ticks ) ; - XTime_PITEnableAutoReload() ; - return 0; -} -#endif - - -//-------------------------------------------------------------------- -// PowerPC Timer Initialization functions. -// For PowerPC, PIT and opb_timer can be used for Profiling. This -// is selected by the user in standalone BSP -// -//-------------------------------------------------------------------- -int powerpc405_init() -{ - Xil_ExceptionInit() ; - Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ; - - // Initialize the Timer. - // 1. If PowerPC PIT Timer has to be used, initialize PIT timer. - // 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC -#ifdef PPC_PIT_INTERRUPT - ppc_pit_init(); -#else -#ifdef TIMER_CONNECT_INTC - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0); - XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, - (XInterruptHandler)profile_intr_handler,(void*)0); -#else - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); -#endif - // Initialize the timer with Timer Ticks - opb_timer_init() ; -#endif - - // Enable Interrupts in the System, if Profile Timer is the only Interrupt - // in the System. -#ifdef ENABLE_SYS_INTR -#ifdef PPC_PIT_INTERRUPT - XTime_PITEnableInterrupt() ; -#elif TIMER_CONNECT_INTC - XIntc_MasterEnable( INTC_BASEADDR ); - XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); - XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); -#endif - Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ; -#endif - return 0; -} - -#endif // PROC_PPC - - - -//-------------------------------------------------------------------- -// PowerPC440 Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_PPC440 - - -//-------------------------------------------------------------------- -// PowerPC DEC Timer Init. -// Defined only if DEC Timer is used for Profiling -// -//-------------------------------------------------------------------- -#ifdef PPC_PIT_INTERRUPT -int ppc_dec_init( void ) -{ - // 1. Register Profile_intr_handler as Interrupt handler - // 2. Set DEC Timer Interrupt and Enable it. - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); - XTime_DECSetInterval( timer_clk_ticks ) ; - XTime_DECEnableAutoReload() ; - return 0; -} -#endif - - -//-------------------------------------------------------------------- -// PowerPC Timer Initialization functions. -// For PowerPC, DEC and opb_timer can be used for Profiling. This -// is selected by the user in standalone BSP -// -//-------------------------------------------------------------------- -int powerpc405_init(void) -{ - Xil_ExceptionInit(); - Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ; - - // Initialize the Timer. - // 1. If PowerPC DEC Timer has to be used, initialize DEC timer. - // 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC -#ifdef PPC_PIT_INTERRUPT - ppc_dec_init(); -#else -#ifdef TIMER_CONNECT_INTC - Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0); - - XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, - (XInterruptHandler)profile_intr_handler,(void*)0); -#else - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); -#endif - // Initialize the timer with Timer Ticks - opb_timer_init() ; -#endif - - // Enable Interrupts in the System, if Profile Timer is the only Interrupt - // in the System. -#ifdef ENABLE_SYS_INTR -#ifdef PPC_PIT_INTERRUPT - XTime_DECEnableInterrupt() ; -#elif TIMER_CONNECT_INTC - XIntc_MasterEnable( INTC_BASEADDR ); - XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); - XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); -#endif - Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ; -#endif - return 0; -} - -#endif // PROC_PPC440 - -//-------------------------------------------------------------------- -// opb_timer Initialization for PowerPC and MicroBlaze. This function -// is not needed if DEC timer is used in PowerPC -// -//-------------------------------------------------------------------- -//#ifndef PPC_PIT_INTERRUPT -#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) -int opb_timer_init( void ) -{ - // set the number of cycles the timer counts before interrupting - XTmrCtr_SetLoadReg(PROFILE_TIMER_BASEADDR, 0, timer_clk_ticks); - - // reset the timers, and clear interrupts - XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, - XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK ); - - // start the timers - XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK - | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); - return 0; -} -#endif - - -//-------------------------------------------------------------------- -// MicroBlaze Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_MICROBLAZE - -//-------------------------------------------------------------------- -// Initialize the Profile Timer for MicroBlaze Target. -// For MicroBlaze, opb_timer is used. The opb_timer can be directly -// connected to MicroBlaze or connected through Interrupt Controller. -// -//-------------------------------------------------------------------- -int microblaze_init(void) -{ - // Register profile_intr_handler - // 1. If timer is connected to Interrupt Controller, register the handler - // to Interrupt Controllers vector table. - // 2. If timer is directly connected to MicroBlaze, register the handler - // as Interrupt handler - Xil_ExceptionInit(); - -#ifdef TIMER_CONNECT_INTC - XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, - (XInterruptHandler)profile_intr_handler,(void*)0); -#else - Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, - (Xil_ExceptionHandler)profile_intr_handler, - (void *)0) ; -#endif - - // Initialize the timer with Timer Ticks - opb_timer_init() ; - - // Enable Interrupts in the System, if Profile Timer is the only Interrupt - // in the System. -#ifdef ENABLE_SYS_INTR -#ifdef TIMER_CONNECT_INTC - XIntc_MasterEnable( INTC_BASEADDR ); - XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); - XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); - Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, - (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0); -#endif - -#endif - - Xil_ExceptionEnable(); - - return 0; - -} - -#endif // PROC_MICROBLAZE - - - -//-------------------------------------------------------------------- -// Cortex A9 Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_CORTEXA9 - -//-------------------------------------------------------------------- -// Initialize the Profile Timer for Cortex A9 Target. -// The scu private timer is connected to the Scu GIC controller. -// -//-------------------------------------------------------------------- -int scu_timer_init( void ) -{ - // set the number of cycles the timer counts before interrupting - // scu timer runs at half the cpu clock - XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2); - - // clear any pending interrupts - XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1); - - // enable interrupts, auto-reload mode and start the timer - XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK | - XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK); - - return 0; -} - -int cortexa9_init(void) -{ - - Xil_ExceptionInit(); - - XScuGic_DeviceInitialize(0); - - /* - * Connect the interrupt controller interrupt handler to the hardware - * interrupt handling logic in the processor. - */ - Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, - (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler, - (void *)0); - - /* - * Connect the device driver handler that will be called when an - * interrupt for the device occurs, the handler defined above performs - * the specific interrupt processing for the device. - */ - XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR, - PROFILE_TIMER_INTR_ID, - (Xil_ExceptionHandler)profile_intr_handler, - (void *)0); - - /* - * Enable the interrupt for scu timer. - */ - XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID); - - /* - * Enable interrupts in the Processor. - */ - Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ); - - /* - * Initialize the timer with Timer Ticks - */ - scu_timer_init() ; - - Xil_ExceptionEnable(); - - return 0; -} - -#endif // PROC_CORTEXA9 diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xdebug.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xdebug.h deleted file mode 100644 index 899173cf0..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xdebug.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef XDEBUG -#define XDEBUG - -#if defined(DEBUG) && !defined(NDEBUG) - -#ifndef XDEBUG_WARNING -#define XDEBUG_WARNING -#warning DEBUG is enabled -#endif - -int printf(const char *format, ...); - -#define XDBG_DEBUG_ERROR 0x00000001 /* error condition messages */ -#define XDBG_DEBUG_GENERAL 0x00000002 /* general debug messages */ -#define XDBG_DEBUG_ALL 0xFFFFFFFF /* all debugging data */ - -#define XDBG_DEBUG_FIFO_REG 0x00000100 /* display register reads/writes */ -#define XDBG_DEBUG_FIFO_RX 0x00000101 /* receive debug messages */ -#define XDBG_DEBUG_FIFO_TX 0x00000102 /* transmit debug messages */ -#define XDBG_DEBUG_FIFO_ALL 0x0000010F /* all fifo debug messages */ - -#define XDBG_DEBUG_TEMAC_REG 0x00000400 /* display register reads/writes */ -#define XDBG_DEBUG_TEMAC_RX 0x00000401 /* receive debug messages */ -#define XDBG_DEBUG_TEMAC_TX 0x00000402 /* transmit debug messages */ -#define XDBG_DEBUG_TEMAC_ALL 0x0000040F /* all temac debug messages */ - -#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800 /* receive debug messages */ -#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801 /* transmit debug messages */ -#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802 /* ioctl debug messages */ -#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803 /* debug msg for other routines */ -#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080F /* all temac adapter debug messages */ - -#define xdbg_current_types (XDBG_DEBUG_ERROR) - -#define xdbg_stmnt(x) x - -/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for - * macros that accept variable number of arguments - */ -#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) -#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0) -#else /* ANSI Syntax */ -#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) -#endif - -#else /* defined(DEBUG) && !defined(NDEBUG) */ - -#define xdbg_stmnt(x) - -/* See VxWorks comments above */ -#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) -#define xdbg_printf(type, args...) -#else /* ANSI Syntax */ -#define xdbg_printf(...) -#endif - -#endif /* defined(DEBUG) && !defined(NDEBUG) */ - -#endif /* XDEBUG */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/Makefile b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/Makefile similarity index 94% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/Makefile rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/Makefile index fd759d6e3..40c3c82dd 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/Makefile +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/Makefile @@ -1,6 +1,6 @@ ############################################################################### # -# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal @@ -27,11 +27,12 @@ # Except as contained in this notice, the name of the Xilinx shall not be used # in advertising or otherwise to promote the sale, use or other dealings in # this Software without prior written authorization from Xilinx. -###################################################################### +# +############################################################################### # The following are defined in config.make # LIBSOURCES - Based on if MicroBlaze support Exceptions -# LIBS - Do Build Profile Libraries +# LIBS - Do Build Profile Libraries include config.make AS=mb-as @@ -49,7 +50,7 @@ RELEASEDIR=../../../lib INCLUDEDIR=../../../include INCLUDES=-I./. -I${INCLUDEDIR} -OUTS = *.o +OUTS = *.o INCLUDEFILES=*.h @@ -58,7 +59,7 @@ libs: $(LIBS) standalone_libs: $(LIBSOURCES) echo "Compiling standalone"; $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ - $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS} + $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS} profile_libs: $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" libs diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/_exit.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/_exit.c similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/_exit.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/_exit.c index 3ffa16786..3fb2ec63a 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/_exit.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/_exit.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,11 +31,16 @@ ******************************************************************************/ #include +#include "xil_types.h" +void _exit (sint32 status); /* _exit - Simple implementation. Does not return. */ -void _exit (int status) +void _exit (sint32 status) { (void) status; - while (1); + while (1) + { + ; + } } diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/bspconfig.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h similarity index 89% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/bspconfig.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h index 855a33c15..4dd178f04 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/bspconfig.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -22,8 +22,8 @@ * *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/changelog.txt b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/changelog.txt similarity index 58% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/changelog.txt rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/changelog.txt index f985a0910..ad9c771e1 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/changelog.txt +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/changelog.txt @@ -3,7 +3,7 @@ * * Ver Who Date Changes * ----- ---- -------- --------------------------------------------------- - * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros + * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but * cacheable regions @@ -94,13 +94,13 @@ * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This * fixes the CR #692094. * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552. - * 3.10a srt 04/18/13 Implemented ARM Erratas. + * 3.10a srt 04/18/13 Implemented ARM Erratas. * Cortex A9 Errata - 742230, 743622, 775420, 794073 * L2Cache PL310 Errata - 588369, 727915, 759370 * Please refer to file 'xil_errata.h' for errata * description. * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older - * cache APIs were corresponding to only Layer 1 cache + * cache APIs were corresponding to only Layer 1 cache * memories. New APIs were now added and the existing cache * related APIs were changed to provide a uniform interface * to flush/invalidate/enable/disable the complete cache @@ -115,13 +115,13 @@ * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache * microblaze_invalidate_cache_ext_range -> Invalidates a * range of memory in L2 cache. - * These changes are done to implement PR #697214. + * These changes are done to implement PR #697214. * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to * fix the CR #706464. L2 cache disabling happens independent * of L1 data cache disable operation. Changes are done in the - * same file in cache handling APIs to do a L2 cache sync - * (poll reg7_?cache_?sync). This fixes CR #700542. - * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested + * same file in cache handling APIs to do a L2 cache sync + * (poll reg7_?cache_?sync). This fixes CR #700542. + * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested * interrupts for ARM. These are done to fix the CR#699680. * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach * sync operation. This fixes the CR# 716781. @@ -131,11 +131,11 @@ * fix issues related to NEON context saving. The assembly * routines for IRQ and FIQ handling are modified. * Deprecated the older BSP (3.10a). - * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid + * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid * various potential issues. Made changes in the function * Xil_SetAttributes in file xil_mmu.c. * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h - * in src\cortexa9 and src\microblaze folders. + * in src\cortexa9 and src\microblaze folders. * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of * L2 cache sync operation and to fix issues around complete * L2 cache flush/invalidation by ways. @@ -143,23 +143,23 @@ * to fix linking issues with armcc/DS-5. Modified the armcc * makefile to fix issues. * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB. - * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used. + * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used. * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler - * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and + * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and * src\cortexa9\armcc\) to fix CR#767251 - * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and + * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs. * Few cache lines were missed to invalidate when unaligned address - * invalidation was accommodated in Xil_DCacheInvalidateRange. + * invalidation was accommodated in Xil_DCacheInvalidateRange. * In Xil_L1DCacheInvalidate, while invalidating all L1D cache * stack memory (which contains return address) was invalidated. So * stack memory is flushed first and then L1D cache is invalidated. * This is done to fix CR #763829 - * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from - * mblaze_nt_types.h file and replace uint32_t with u32 in the - * profile_hist.c to fix the above CR. + * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from + * mblaze_nt_types.h file and replace uint32_t with u32 in the + * profile_hist.c to fix the above CR. * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a - * instead of libxil.a and added prototypes for + * instead of libxil.a and added prototypes for * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in * mb_interface.h * 4.1 hk 04/18/14 Add sleep function. @@ -173,28 +173,28 @@ * Fix for CR#764881. * 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to * output the DEBUG logs when -DDEBUG flag is enabled in BSP. - * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm. + * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm. * Also added explanatory notes in cortexa9/xil_cache.c for CR#785243. * 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and - * cortexa9/armcc/boot.s. Added default exception handlers for data + * cortexa9/armcc/boot.s. Added default exception handlers for data * abort and prefetch abort using handlers called - * DataAbortHandler and PrefetchAbortHandler respectively in + * DataAbortHandler and PrefetchAbortHandler respectively in * cortexa9/xil_exception.c to fix CR#802862. - * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the - * issue of improper linking of translation_table.s + * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the + * issue of improper linking of translation_table.s * 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present * in tool chain to avoid conflicts into some special cases - * 4.2 pkp 07/21/14 Corrected reset value of event counter in function + * 4.2 pkp 07/21/14 Corrected reset value of event counter in function * Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275 - * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function - * containing type def u32 defined in xil_types.g to resolve issue of + * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function + * containing type def u32 defined in xil_types.g to resolve issue of * CR#805869 - * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as + * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as * it is not possible to generate timer in nanosecond due to limited * cpu frequency - * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of + * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of * uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s - * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also + * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also * removed function definition of XSmc_NorInit and XSmc_NorInit from * cortexa9/smc.h * 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_ @@ -209,4 +209,116 @@ * 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s * and cortexa9/armcc/translation_table.s to resolve compilation * error for solving CR#822897 -******************************************************************************************/ + * 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for + * MISRA-C:2012 compliance. + * 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by + * adding src/common/xplatform_info.*s + * 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and + * removed incorrect initialization of TLB lockdown register to fix + * CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S + * and iccarm/boot.s + * 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile + * for iccarm and armcc compiler of cortexA9 + * 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s + * and armcc/boot.s so to first invalidate caches and TLB, enable MMU and + * caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling + * of L2Cache is done later. + * 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and + * Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily + * taking long time to fix CR#853097. L2CacheSync is added into + * Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and + * Xil_L2CacheInvalidate APIs are modified to flush the complete stack + * instead of just System Stack + * 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler + * to update ECC_FLAGS and also take the compiler and archiver as specified + * in settings instead of hardcoding it. + * 5.2 pkp 06/08/15 Modified cortexa9/gcc/translation_table.S to put a check for + * XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and + * accordingly generate the translation table + * 5.2 pkp 23/07/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler + * to update ECC_FLAGS to fix a bug introduced during new version creation + * of BSP. + * 5.3 pkp 10/07/15 Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache + * functionalities are avoided for the OpenAMP slave application(when + * USE_AMP flag is defined for BSP) as master CPU would be utilizing L2 + * cache for its operation. Also file operations such as read, write, + * close, open are also avoided for OpenAMP support(when USE_AMP flag is + * defined for BSP) because XilOpenAMP library contains own file operation. + * The xil-crt0.S file is modified for not initializing global timer for + * OpenAMP application as it might be already in use by master CPU + * 5.3 pkp 10/09/15 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function + * definition for dsb, isb and dmb to fix the compilation error when used + * kvn 16/10/15 Encapsulated assembly code into macros for R5 xil_cache file. + * 5.4 pkp 09/11/15 Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential + * R5 deadlock for errata 780125 + * 5.4 pkp 09/11/15 Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53 + * 32 bit BSP in the initialization + * 5.4 pkp 09/11/15 Modified cortexa9/xil_misc_psreset_api.c file to change the description + * for XOcm_Remap function + * 5.4 pkp 16/11/15 Modified microblaze/xil_misc_psreset_api.c file to change the description + * for XOcm_Remap function + * kvn 21/11/15 Added volatile keyword for ADDR varibles in Xil_Out API + * kvn 21/11/15 Changed ADDR variable type from u32 to UINTPTR. This is + * required for MISRA-C:2012 Compliance. + * 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9 + * in cortexa9/xil_mmu.h + * 5.4 pkp 23/11/15 Added default undefined exception handler for Cortex-A9 + * 5.4 pkp 11/12/15 Modified common/xplatform_info.h to add #defines for silicon for + * checking the current executing platform + * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S + * to initialize global constructor for C++ applications + * 5.4 pkp 18/12/15 Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for + * C++ applications + * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/ + * translation_table.S to update the translation table according to proper + * address map + * 5.4 pkp 18/12/15 Modified cortexar5/mpu.c to initialize the MPU according to proper + * address map + * 5.4 pkp 05/01/16 Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR + * equivalent to vector table base address + * 5.4 pkp 08/01/16 Modified cortexa9/gcc/Makefile to update the extra compiler flag + * as per the toolchain update + * 5.4 pkp 12/01/16 Changed common/xplatform_info.* to add platform information support + * for Cortex-A53 32bit mode + * 5.4 pkp 28/01/16 Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c + * and usleep.c to correct routines to avoid hardcoding the timer frequency, + * instead take it from xparameters.h to properly configure the timestamp + * clock frequency + * 5.4 asa 29/01/16 Modified microblaze/mb_interface.h to add macros that support the + * new instructions for MB address extension feature + * 5.4 kvn 30/01/16 Modified xparameters_ps.h file to add interrupt ID number for + * system monitor. + * 5.4 pkp 04/02/16 Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode + * 5.4 pkp 19/02/16 Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated + * cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified + * cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise + * use set of assembly instructions to provide required delay to fix + * CR#913249. + * 5.4 asa 25/02/16 Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace + * _exit with exit. We should not be directly calling _exit and should + * always use the library exit. This fixes the CR#937036. + * 5.4 pkp 25/02/16 Made change to cortexr5/gcc/boot.S to initialize the floating point + * registers, banked registers for various modes and enabled + * the cache ECC check before enabling the fault log for lock step mode + * Also modified the cortexr5/gcc/Makefile to support floating point + * registers initialization in boot code. + * 5.4 pkp 03/01/16 Updated the exit function in cortexr5/gcc/_exit.c to enable the debug + * logic in case of lock-step mode when fault log is enabled to fix + * CR#938281 + * 5.4 pkp 03/02/16 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include + * header file instrinsics.h which contains assembly instructions + * definitions which can be used by C + * 5.4 asa 03/02/16 Added print.c in MB BSP. Made other cosmetic changes to have uniform + * proto for all print.c across the BSPs. This patch fixes CR#938738. + * 5.4 pkp 03/09/16 Modified cortexr5/sleep.c and usleep.c to avoid disabling the + * interrupts when sleep/usleep is being executed using assembly + * instructions to fix CR#913249. + * 5.4 pkp 03/11/16 Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt, + * instead modified cortexr5/sleep.c and usleep.c to poll the counter + * value and compare it with previous value to detect the overflow + * to fix CR#940209. + * 5.4 pkp 03/24/16 Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling + * the fault log to avoid intervention for lock-step mode and cortexr5/ + * _exit.c to enable the dbg_lpd_reset once the fault log is disabled + * to fix CR#947335 + *****************************************************************************************/ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/config.make b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/config.make similarity index 100% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/config.make rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/config.make diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/errno.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/errno.c similarity index 75% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/errno.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/errno.c index 9fa8f6a32..3d6fb2027 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/errno.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/errno.c @@ -4,9 +4,11 @@ #include #include +#include "xil_types.h" +sint32 * __errno (void); -int * -__errno () +sint32 * +__errno (void) { return &_REENT->_errno; } diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/fcntl.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/fcntl.c similarity index 60% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/fcntl.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/fcntl.c index 1ee9a86e5..257cee565 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/fcntl.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/fcntl.c @@ -1,10 +1,12 @@ #include +#include "xil_types.h" +sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg); /* * fcntl -- Manipulate a file descriptor. * We don't have a filesystem, so we do nothing. */ -int fcntl (int fd, int cmd, long arg) +sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg) { (void) fd; (void) cmd; diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/fsl.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/fsl.h similarity index 95% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/fsl.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/fsl.h index 2215732c8..29906d956 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/fsl.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/fsl.h @@ -1,5 +1,5 @@ -#ifndef _FSL_H -#define _FSL_H +#ifndef FSL_H +#define FSL_H #include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */ @@ -8,7 +8,7 @@ extern "C" { #endif /* Extended FSL macros. These now replace all of the previous FSL macros */ -#define FSL_DEFAULT +#define FSL_DEFAULT #define FSL_NONBLOCKING n #define FSL_EXCEPTION e #define FSL_CONTROL c @@ -44,5 +44,4 @@ extern "C" { #ifdef __cplusplus } #endif -#endif /* _FSL_H */ - +#endif /* FSL_H */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/hw_exception_handler.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/hw_exception_handler.S similarity index 68% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/hw_exception_handler.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/hw_exception_handler.S index 12bbf2c6c..7db0afd65 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/hw_exception_handler.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/hw_exception_handler.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,7 +29,7 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ -/* +/****************************************************************************** * Microblaze HW Exception Handler * - Non self-modifying exception handler for the following exception conditions * - Unalignment @@ -38,7 +38,7 @@ * - Illegal instruction opcode * - Divide-by-zero * - Stack protection violation - */ + *******************************************************************************/ #include "microblaze_exceptions_g.h" #include "xparameters.h" @@ -46,129 +46,129 @@ /* Helpful Macros */ #define EX_HANDLER_STACK_SIZ (4*21) #define RMSR_OFFSET (20 * 4) -#define R17_OFFSET (0) +#define R17_OFFSET (0) #define REG_OFFSET(regnum) (4 * (regnum + 1)) #define NUM_TO_REG(num) r ## num #define R3_TO_STACK(regnum) swi r3, r1, REG_OFFSET(regnum) -#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum) +#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum) #define PUSH_REG(regnum) swi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum) #define POP_REG(regnum) lwi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum) - + /* Uses r5 */ #define PUSH_MSR \ mfs r5, rmsr; \ swi r5, r1, RMSR_OFFSET; - + #define PUSH_MSR_AND_ENABLE_EXC \ mfs r5, rmsr; \ swi r5, r1, RMSR_OFFSET; \ ori r5, r5, 0x100; /* Turn ON the EE bit*/ \ mts rmsr, r5; - + /* Uses r5 */ #define POP_MSR \ lwi r5, r1, RMSR_OFFSET; \ - mts rmsr, r5; + mts rmsr, r5; -/* Push r17 */ +/* Push r17 */ #define PUSH_R17 swi r17, r1, R17_OFFSET -/* Pop r17 */ +/* Pop r17 */ #define POP_R17 lwi r17, r1, R17_OFFSET - + #define LWREG_NOP \ bri ex_handler_unhandled; \ nop; #define SWREG_NOP \ bri ex_handler_unhandled; \ - nop; - + nop; + /* r3 is the source */ #define R3_TO_LWREG_V(regnum) \ R3_TO_STACK (regnum); \ - bri ex_handler_done; + bri ex_handler_done; /* r3 is the source */ #define R3_TO_LWREG(regnum) \ or NUM_TO_REG (regnum), r0, r3; \ - bri ex_handler_done; + bri ex_handler_done; -/* r3 is the target */ +/* r3 is the target */ #define SWREG_TO_R3_V(regnum) \ R3_FROM_STACK (regnum); \ - bri ex_sw_tail; - -/* r3 is the target */ + bri ex_sw_tail; + +/* r3 is the target */ #define SWREG_TO_R3(regnum) \ or r3, r0, NUM_TO_REG (regnum); \ - bri ex_sw_tail; + bri ex_sw_tail; -/* regnum is the source */ +/* regnum is the source */ #define FP_EX_OPB_SAVE(regnum) \ swi NUM_TO_REG (regnum), r0, mb_fpex_op_b; \ nop; \ - bri handle_fp_ex_opa; + bri handle_fp_ex_opa; -/* regnum is the source */ +/* regnum is the source */ #define FP_EX_OPB_SAVE_V(regnum) \ R3_FROM_STACK (regnum); \ swi r3, r0, mb_fpex_op_b; \ - bri handle_fp_ex_opa; - -/* regnum is the source */ + bri handle_fp_ex_opa; + +/* regnum is the source */ #define FP_EX_OPA_SAVE(regnum) \ swi NUM_TO_REG (regnum), r0, mb_fpex_op_a; \ nop; \ - bri handle_fp_ex_done; - -/* regnum is the source */ + bri handle_fp_ex_done; + +/* regnum is the source */ #define FP_EX_OPA_SAVE_V(regnum) \ R3_FROM_STACK (regnum); \ swi r3, r0, mb_fpex_op_a; \ - bri handle_fp_ex_done; + bri handle_fp_ex_done; #define FP_EX_UNHANDLED \ bri fp_ex_unhandled; \ nop; \ nop; -/* ESR masks */ +/* ESR masks */ #define ESR_EXC_MASK 0x0000001F #define ESR_REG_MASK 0x000003E0 #define ESR_LW_SW_MASK 0x00000400 #define ESR_WORD_MASK 0x00000800 #define ESR_DS_MASK 0x00001000 - + /* Extern declarations */ .extern XNullHandler #ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */ - -/* + +/* * hw_exception_handler - Handler for unaligned exceptions - * Exception handler notes: + * Exception handler notes: * - Does not handle exceptions other than unaligned exceptions * - Does not handle exceptions during load into r17, r1, r0. * - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case) * * Relevant register structures - * - * EAR - |----|----|----|----|----|----|----|----| - * - < ## 32 bit faulting address ## > - * - * ESR - |----|----|----|----|----| - | - |-----|-----| + * + * EAR - |----|----|----|----|----|----|----|----| + * - < ## 32 bit faulting address ## > + * + * ESR - |----|----|----|----|----| - | - |-----|-----| * - W S REG EXC * - * + * * STACK FRAME STRUCTURE * --------------------- * * +-------------+ + 0 * | r17 | - * +-------------+ + 4 + * +-------------+ + 4 * | Args for | * | next func | * +-------------+ + 8 @@ -179,19 +179,19 @@ * | . | * | r18 | * +-------------+ + 80 - * | MSR | - * +-------------+ + 84 - * | . | - * | . | - */ + * | MSR | + * +-------------+ + 84 + * | . | + * | . | + */ - -.global _hw_exception_handler -.section .text + +.global _hw_exception_handler +.section .text .align 2 .ent _hw_exception_handler -.type _hw_exception_handler, @function -_hw_exception_handler: +.type _hw_exception_handler, @function +_hw_exception_handler: #if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) /* Immediately halt for stack protection violation exception without using any stack */ @@ -207,33 +207,33 @@ ex_handler_not_sp_violation: #endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */ addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */ - PUSH_REG(3); - PUSH_REG(4); - PUSH_REG(5); + PUSH_REG(3); + PUSH_REG(4); + PUSH_REG(5); PUSH_REG(6); #ifdef MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS mfs r6, resr; andi r6, r6, ESR_DS_MASK; beqi r6, ex_handler_no_ds; mfs r17, rbtr; -ex_handler_no_ds: +ex_handler_no_ds: #endif - PUSH_R17; + PUSH_R17; PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */ - - mfs r3, resr; + + mfs r3, resr; andi r5, r3, ESR_EXC_MASK; /* Extract ESR[EXC] */ #ifndef NO_UNALIGNED_EXCEPTIONS - xori r6, r5, 1; /* 00001 = Unaligned Exception */ - bnei r6, handle_ex_regular; + xori r6, r5, 1; /* 00001 = Unaligned Exception */ + bnei r6, handle_ex_regular; la r4, r0, MB_ExceptionVectorTable; /* Check if user has registered an unaligned exception handler */ - lwi r4, r4, 8; + lwi r4, r4, 8; la r6, r0, XNullHandler; /* If exceptionvectortable entry is still XNullHandler, use */ xor r6, r4, r6; /* the default exception handler */ - beqi r6, handle_unaligned_ex ; - -handle_ex_regular: + beqi r6, handle_unaligned_ex ; + +handle_ex_regular: #endif /* ! NO_UNALIGNED_EXCEPTIONS */ #if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) @@ -241,29 +241,29 @@ handle_ex_regular: beqi r6, handle_fp_ex; /* Go and decode the FP exception */ #endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */ -handle_other_ex: /* Handle Other exceptions here */ - ori r6, r0, 20; +handle_other_ex: /* Handle Other exceptions here */ + ori r6, r0, 20; cmp r6, r5, r6; /* >= 20 are exceptions we do not handle. */ blei r6, ex_handler_unhandled; ori r6, r0, 7; cmp r6, r5, r6; /* Convert MMU exception indices into an ordinal of 7 */ bgti r6, handle_other_ex_tail; - ori r5, r0, 0x7; - -handle_other_ex_tail: + ori r5, r0, 0x7; + +handle_other_ex_tail: PUSH_REG(7); /* Save other volatiles before we make procedure calls below */ - PUSH_REG(8); - PUSH_REG(9); - PUSH_REG(10); - PUSH_REG(11); + PUSH_REG(8); + PUSH_REG(9); + PUSH_REG(10); + PUSH_REG(11); PUSH_REG(12); PUSH_REG(15); - PUSH_REG(18); + PUSH_REG(18); la r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */ addk r7, r5, r5; /* Calculate exception vector offset = r5 * 8 */ - addk r7, r7, r7; + addk r7, r7, r7; addk r7, r7, r7; addk r7, r7, r4; /* Get pointer to exception vector */ lwi r5, r7, 4; /* Load argument to exception handler from table */ @@ -271,20 +271,20 @@ handle_other_ex_tail: brald r15, r7; /* Branch to handler */ nop; - + POP_REG(7); /* Restore other volatiles */ - POP_REG(8); - POP_REG(9); - POP_REG(10); - POP_REG(11); + POP_REG(8); + POP_REG(9); + POP_REG(10); + POP_REG(11); POP_REG(12); POP_REG(15); - POP_REG(18); + POP_REG(18); - bri ex_handler_done; /* Complete exception handling */ + bri ex_handler_done; /* Complete exception handling */ #ifndef NO_UNALIGNED_EXCEPTIONS -handle_unaligned_ex: +handle_unaligned_ex: andi r6, r3, ESR_REG_MASK; /* Mask and extract the register operand */ srl r6, r6; /* r6 >> 5 */ srl r6, r6; @@ -292,14 +292,14 @@ handle_unaligned_ex: srl r6, r6; srl r6, r6; sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */ - mfs r4, rear; + mfs r4, rear; andi r6, r3, ESR_LW_SW_MASK; /* Extract ESR[S] */ bnei r6, ex_sw; -ex_lw: +ex_lw: andi r6, r3, ESR_WORD_MASK; /* Extract ESR[W] */ beqi r6, ex_lhw; lbui r5, r4, 0; /* Exception address in r4 */ - sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */ + sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */ lbui r5, r4, 1; sbi r5, r0, ex_tmp_data_loc_1; lbui r5, r4, 2; @@ -307,32 +307,32 @@ ex_lw: lbui r5, r4, 3; sbi r5, r0, ex_tmp_data_loc_3; lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */ - bri ex_lw_tail; -ex_lhw: + bri ex_lw_tail; +ex_lhw: lbui r5, r4, 0; /* Exception address in r4 */ - sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */ - lbui r5, r4, 1; + sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */ + lbui r5, r4, 1; sbi r5, r0, ex_tmp_data_loc_1; lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */ ex_lw_tail: lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */ la r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */ - addk r5, r5, r5; + addk r5, r5, r5; addk r5, r5, r5; addk r5, r5, r5; addk r5, r5, r6; bra r5; ex_lw_end: /* Exception handling of load word, ends */ -ex_sw: +ex_sw: lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */ la r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */ - add r5, r5, r5; + add r5, r5, r5; add r5, r5, r5; add r5, r5, r5; add r5, r5, r6; bra r5; -ex_sw_tail: - mfs r6, resr; +ex_sw_tail: + mfs r6, resr; andi r6, r6, ESR_WORD_MASK; /* Extract ESR[W] */ beqi r6, ex_shw; swi r3, r0, ex_tmp_data_loc_0; @@ -341,13 +341,13 @@ ex_sw_tail: lbui r3, r0, ex_tmp_data_loc_1; sbi r3, r4, 1; lbui r3, r0, ex_tmp_data_loc_2; - sbi r3, r4, 2; + sbi r3, r4, 2; lbui r3, r0, ex_tmp_data_loc_3; - sbi r3, r4, 3; + sbi r3, r4, 3; bri ex_handler_done; -ex_shw: +ex_shw: swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */ - + #ifdef __LITTLE_ENDIAN__ lbui r3, r0, ex_tmp_data_loc_0; #else @@ -361,7 +361,7 @@ ex_shw: #endif sbi r3, r4, 1; ex_sw_end: /* Exception handling of store word, ends. */ - bri ex_handler_done; + bri ex_handler_done; #endif /* !NO_UNALIGNED_EXCEPTIONS */ #if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) @@ -371,76 +371,76 @@ handle_fp_ex: handle_fp_ex_opb: la r6, r0, fp_table_opb; /* Decode opB and store its value in mb_fpex_op_b */ - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; andi r3, r4, 0x1F; add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */ add r3, r3, r3; add r5, r3, r3; add r5, r5, r3; add r5, r5, r6; - bra r5; + bra r5; handle_fp_ex_opa: la r6, r0, fp_table_opa; /* Decode opA and store its value in mb_fpex_op_a */ - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; andi r3, r4, 0x1F; add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */ add r3, r3, r3; add r5, r3, r3; add r5, r5, r3; add r5, r5, r6; - bra r5; + bra r5; handle_fp_ex_done: ori r5, r0, 6; /* Set exception number back to 6 */ - bri handle_other_ex_tail; - -fp_ex_unhandled: - bri 0; + bri handle_other_ex_tail; + +fp_ex_unhandled: + bri 0; #endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */ - + ex_handler_done: POP_R17; POP_MSR; - POP_REG(3); - POP_REG(4); - POP_REG(5); - POP_REG(6); + POP_REG(3); + POP_REG(4); + POP_REG(5); + POP_REG(6); rted r17, 0 - addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */ -ex_handler_unhandled: - bri 0 /* UNHANDLED. TRAP HERE */ -.end _hw_exception_handler + addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */ +ex_handler_unhandled: + bri 0 /* UNHANDLED. TRAP HERE */ +.end _hw_exception_handler -#ifndef NO_UNALIGNED_EXCEPTIONS +#ifndef NO_UNALIGNED_EXCEPTIONS -/* +/* * hw_exception_handler Jump Table * - Contains code snippets for each register that caused the unaligned exception. * - Hence exception handler is NOT self-modifying * - Separate table for load exceptions and store exceptions. * - Each table is of size: (8 * 32) = 256 bytes */ - + .section .text .align 4 lw_table: -lw_r0: R3_TO_LWREG (0); +lw_r0: R3_TO_LWREG (0); lw_r1: LWREG_NOP; lw_r2: R3_TO_LWREG (2); lw_r3: R3_TO_LWREG_V (3); @@ -451,30 +451,30 @@ lw_r7: R3_TO_LWREG (7); lw_r8: R3_TO_LWREG (8); lw_r9: R3_TO_LWREG (9); lw_r10: R3_TO_LWREG (10); -lw_r11: R3_TO_LWREG (11); +lw_r11: R3_TO_LWREG (11); lw_r12: R3_TO_LWREG (12); lw_r13: R3_TO_LWREG (13); -lw_r14: R3_TO_LWREG (14); -lw_r15: R3_TO_LWREG (15); -lw_r16: R3_TO_LWREG (16); +lw_r14: R3_TO_LWREG (14); +lw_r15: R3_TO_LWREG (15); +lw_r16: R3_TO_LWREG (16); lw_r17: LWREG_NOP; -lw_r18: R3_TO_LWREG (18); -lw_r19: R3_TO_LWREG (19); -lw_r20: R3_TO_LWREG (20); +lw_r18: R3_TO_LWREG (18); +lw_r19: R3_TO_LWREG (19); +lw_r20: R3_TO_LWREG (20); lw_r21: R3_TO_LWREG (21); lw_r22: R3_TO_LWREG (22); -lw_r23: R3_TO_LWREG (23); -lw_r24: R3_TO_LWREG (24); -lw_r25: R3_TO_LWREG (25); -lw_r26: R3_TO_LWREG (26); -lw_r27: R3_TO_LWREG (27); -lw_r28: R3_TO_LWREG (28); -lw_r29: R3_TO_LWREG (29); +lw_r23: R3_TO_LWREG (23); +lw_r24: R3_TO_LWREG (24); +lw_r25: R3_TO_LWREG (25); +lw_r26: R3_TO_LWREG (26); +lw_r27: R3_TO_LWREG (27); +lw_r28: R3_TO_LWREG (28); +lw_r29: R3_TO_LWREG (29); lw_r30: R3_TO_LWREG (30); lw_r31: R3_TO_LWREG (31); sw_table: -sw_r0: SWREG_TO_R3 (0); +sw_r0: SWREG_TO_R3 (0); sw_r1: SWREG_NOP; sw_r2: SWREG_TO_R3 (2); sw_r3: SWREG_TO_R3_V (3); @@ -485,128 +485,128 @@ sw_r7: SWREG_TO_R3 (7); sw_r8: SWREG_TO_R3 (8); sw_r9: SWREG_TO_R3 (9); sw_r10: SWREG_TO_R3 (10); -sw_r11: SWREG_TO_R3 (11); +sw_r11: SWREG_TO_R3 (11); sw_r12: SWREG_TO_R3 (12); sw_r13: SWREG_TO_R3 (13); -sw_r14: SWREG_TO_R3 (14); -sw_r15: SWREG_TO_R3 (15); -sw_r16: SWREG_TO_R3 (16); -sw_r17: SWREG_NOP; -sw_r18: SWREG_TO_R3 (18); -sw_r19: SWREG_TO_R3 (19); -sw_r20: SWREG_TO_R3 (20); +sw_r14: SWREG_TO_R3 (14); +sw_r15: SWREG_TO_R3 (15); +sw_r16: SWREG_TO_R3 (16); +sw_r17: SWREG_NOP; +sw_r18: SWREG_TO_R3 (18); +sw_r19: SWREG_TO_R3 (19); +sw_r20: SWREG_TO_R3 (20); sw_r21: SWREG_TO_R3 (21); sw_r22: SWREG_TO_R3 (22); -sw_r23: SWREG_TO_R3 (23); -sw_r24: SWREG_TO_R3 (24); -sw_r25: SWREG_TO_R3 (25); -sw_r26: SWREG_TO_R3 (26); -sw_r27: SWREG_TO_R3 (27); -sw_r28: SWREG_TO_R3 (28); -sw_r29: SWREG_TO_R3 (29); +sw_r23: SWREG_TO_R3 (23); +sw_r24: SWREG_TO_R3 (24); +sw_r25: SWREG_TO_R3 (25); +sw_r26: SWREG_TO_R3 (26); +sw_r27: SWREG_TO_R3 (27); +sw_r28: SWREG_TO_R3 (28); +sw_r29: SWREG_TO_R3 (29); sw_r30: SWREG_TO_R3 (30); sw_r31: SWREG_TO_R3 (31); /* Temporary data structures used in the handler */ .section .data .align 2 -ex_tmp_data_loc_0: +ex_tmp_data_loc_0: .byte 0 -ex_tmp_data_loc_1: +ex_tmp_data_loc_1: .byte 0 -ex_tmp_data_loc_2: +ex_tmp_data_loc_2: + .byte 0 +ex_tmp_data_loc_3: .byte 0 -ex_tmp_data_loc_3: - .byte 0 ex_reg_op: .byte 0 - + #endif /* ! NO_UNALIGNED_EXCEPTIONS */ - + #if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) -/* +/* * FP exception decode jump table. * - Contains code snippets for each register that could have been a source operand for an excepting FP instruction * - Hence exception handler is NOT self-modifying * - Separate table for opA and opB * - Each table is of size: (12 * 32) = 384 bytes */ - + .section .text .align 4 fp_table_opa: -opa_r0: FP_EX_OPA_SAVE (0); -opa_r1: FP_EX_UNHANDLED; -opa_r2: FP_EX_OPA_SAVE (2); -opa_r3: FP_EX_OPA_SAVE_V (3); -opa_r4: FP_EX_OPA_SAVE_V (4); -opa_r5: FP_EX_OPA_SAVE_V (5); -opa_r6: FP_EX_OPA_SAVE_V (6); -opa_r7: FP_EX_OPA_SAVE (7); -opa_r8: FP_EX_OPA_SAVE (8); -opa_r9: FP_EX_OPA_SAVE (9); -opa_r10: FP_EX_OPA_SAVE (10); -opa_r11: FP_EX_OPA_SAVE (11); -opa_r12: FP_EX_OPA_SAVE (12); -opa_r13: FP_EX_OPA_SAVE (13); -opa_r14: FP_EX_UNHANDLED; -opa_r15: FP_EX_UNHANDLED; -opa_r16: FP_EX_UNHANDLED; -opa_r17: FP_EX_UNHANDLED; -opa_r18: FP_EX_OPA_SAVE (18); -opa_r19: FP_EX_OPA_SAVE (19); -opa_r20: FP_EX_OPA_SAVE (20); -opa_r21: FP_EX_OPA_SAVE (21); -opa_r22: FP_EX_OPA_SAVE (22); -opa_r23: FP_EX_OPA_SAVE (23); -opa_r24: FP_EX_OPA_SAVE (24); -opa_r25: FP_EX_OPA_SAVE (25); -opa_r26: FP_EX_OPA_SAVE (26); -opa_r27: FP_EX_OPA_SAVE (27); -opa_r28: FP_EX_OPA_SAVE (28); -opa_r29: FP_EX_OPA_SAVE (29); -opa_r30: FP_EX_OPA_SAVE (30); -opa_r31: FP_EX_OPA_SAVE (31); +opa_r0: FP_EX_OPA_SAVE (0); +opa_r1: FP_EX_UNHANDLED; +opa_r2: FP_EX_OPA_SAVE (2); +opa_r3: FP_EX_OPA_SAVE_V (3); +opa_r4: FP_EX_OPA_SAVE_V (4); +opa_r5: FP_EX_OPA_SAVE_V (5); +opa_r6: FP_EX_OPA_SAVE_V (6); +opa_r7: FP_EX_OPA_SAVE (7); +opa_r8: FP_EX_OPA_SAVE (8); +opa_r9: FP_EX_OPA_SAVE (9); +opa_r10: FP_EX_OPA_SAVE (10); +opa_r11: FP_EX_OPA_SAVE (11); +opa_r12: FP_EX_OPA_SAVE (12); +opa_r13: FP_EX_OPA_SAVE (13); +opa_r14: FP_EX_UNHANDLED; +opa_r15: FP_EX_UNHANDLED; +opa_r16: FP_EX_UNHANDLED; +opa_r17: FP_EX_UNHANDLED; +opa_r18: FP_EX_OPA_SAVE (18); +opa_r19: FP_EX_OPA_SAVE (19); +opa_r20: FP_EX_OPA_SAVE (20); +opa_r21: FP_EX_OPA_SAVE (21); +opa_r22: FP_EX_OPA_SAVE (22); +opa_r23: FP_EX_OPA_SAVE (23); +opa_r24: FP_EX_OPA_SAVE (24); +opa_r25: FP_EX_OPA_SAVE (25); +opa_r26: FP_EX_OPA_SAVE (26); +opa_r27: FP_EX_OPA_SAVE (27); +opa_r28: FP_EX_OPA_SAVE (28); +opa_r29: FP_EX_OPA_SAVE (29); +opa_r30: FP_EX_OPA_SAVE (30); +opa_r31: FP_EX_OPA_SAVE (31); + +fp_table_opb: +opb_r0: FP_EX_OPB_SAVE (0); +opb_r1: FP_EX_UNHANDLED; +opb_r2: FP_EX_OPB_SAVE (2); +opb_r3: FP_EX_OPB_SAVE_V (3); +opb_r4: FP_EX_OPB_SAVE_V (4); +opb_r5: FP_EX_OPB_SAVE_V (5); +opb_r6: FP_EX_OPB_SAVE_V (6); +opb_r7: FP_EX_OPB_SAVE (7); +opb_r8: FP_EX_OPB_SAVE (8); +opb_r9: FP_EX_OPB_SAVE (9); +opb_r10: FP_EX_OPB_SAVE (10); +opb_r11: FP_EX_OPB_SAVE (11); +opb_r12: FP_EX_OPB_SAVE (12); +opb_r13: FP_EX_OPB_SAVE (13); +opb_r14: FP_EX_UNHANDLED; +opb_r15: FP_EX_UNHANDLED; +opb_r16: FP_EX_UNHANDLED; +opb_r17: FP_EX_UNHANDLED; +opb_r18: FP_EX_OPB_SAVE (18); +opb_r19: FP_EX_OPB_SAVE (19); +opb_r20: FP_EX_OPB_SAVE (20); +opb_r21: FP_EX_OPB_SAVE (21); +opb_r22: FP_EX_OPB_SAVE (22); +opb_r23: FP_EX_OPB_SAVE (23); +opb_r24: FP_EX_OPB_SAVE (24); +opb_r25: FP_EX_OPB_SAVE (25); +opb_r26: FP_EX_OPB_SAVE (26); +opb_r27: FP_EX_OPB_SAVE (27); +opb_r28: FP_EX_OPB_SAVE (28); +opb_r29: FP_EX_OPB_SAVE (29); +opb_r30: FP_EX_OPB_SAVE (30); +opb_r31: FP_EX_OPB_SAVE (31); -fp_table_opb: -opb_r0: FP_EX_OPB_SAVE (0); -opb_r1: FP_EX_UNHANDLED; -opb_r2: FP_EX_OPB_SAVE (2); -opb_r3: FP_EX_OPB_SAVE_V (3); -opb_r4: FP_EX_OPB_SAVE_V (4); -opb_r5: FP_EX_OPB_SAVE_V (5); -opb_r6: FP_EX_OPB_SAVE_V (6); -opb_r7: FP_EX_OPB_SAVE (7); -opb_r8: FP_EX_OPB_SAVE (8); -opb_r9: FP_EX_OPB_SAVE (9); -opb_r10: FP_EX_OPB_SAVE (10); -opb_r11: FP_EX_OPB_SAVE (11); -opb_r12: FP_EX_OPB_SAVE (12); -opb_r13: FP_EX_OPB_SAVE (13); -opb_r14: FP_EX_UNHANDLED; -opb_r15: FP_EX_UNHANDLED; -opb_r16: FP_EX_UNHANDLED; -opb_r17: FP_EX_UNHANDLED; -opb_r18: FP_EX_OPB_SAVE (18); -opb_r19: FP_EX_OPB_SAVE (19); -opb_r20: FP_EX_OPB_SAVE (20); -opb_r21: FP_EX_OPB_SAVE (21); -opb_r22: FP_EX_OPB_SAVE (22); -opb_r23: FP_EX_OPB_SAVE (23); -opb_r24: FP_EX_OPB_SAVE (24); -opb_r25: FP_EX_OPB_SAVE (25); -opb_r26: FP_EX_OPB_SAVE (26); -opb_r27: FP_EX_OPB_SAVE (27); -opb_r28: FP_EX_OPB_SAVE (28); -opb_r29: FP_EX_OPB_SAVE (29); -opb_r30: FP_EX_OPB_SAVE (30); -opb_r31: FP_EX_OPB_SAVE (31); - #endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */ - + #if defined(MICROBLAZE_FP_EXCEPTION_ENABLED) && defined(MICROBLAZE_FP_EXCEPTION_DECODE) /* This is where we store the opA and opB of the last excepting FP instruction */ -.section .data +.section .data .align 2 .global mb_fpex_op_a .global mb_fpex_op_b @@ -644,19 +644,16 @@ MB_ExceptionVectorTable: .long XNullHandler .long 6 /* -- FPU Exception -- */ .long XNullHandler - .long 7 /* -- MMU Exceptions -- */ + .long 7 /* -- MMU Exceptions -- */ #else /* Dummy exception handler, in case exceptions are not present in the processor */ -.global _hw_exception_handler -.section .text +.global _hw_exception_handler +.section .text .align 2 .ent _hw_exception_handler _hw_exception_handler: - bri 0; -.end _hw_exception_handler - + bri 0; +.end _hw_exception_handler + #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */ - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/inbyte.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/inbyte.c new file mode 100644 index 000000000..b75a2376f --- /dev/null +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/inbyte.c @@ -0,0 +1,14 @@ +#include "xparameters.h" +#include "xuartlite_l.h" + +#ifdef __cplusplus +extern "C" { +#endif +char inbyte(void); +#ifdef __cplusplus +} +#endif + +char inbyte(void) { + return XUartLite_RecvByte(STDIN_BASEADDRESS); +} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/mb_interface.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/mb_interface.h similarity index 80% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/mb_interface.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/mb_interface.h index 33cd25dac..77005880a 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/mb_interface.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/mb_interface.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -54,22 +54,22 @@ extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_Exception extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */ extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */ extern void microblaze_flush_dcache(void); /* Flush the whole dcache */ -extern void microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the icache */ -extern void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the dcache */ -extern void microblaze_flush_dcache_range(unsigned int cacheaddr, unsigned int len); /* Flush a part of the dcache */ +extern void microblaze_invalidate_icache_range(u32 cacheaddr, u32 len); /* Invalidate a part of the icache */ +extern void microblaze_invalidate_dcache_range(u32 cacheaddr, u32 len); /* Invalidate a part of the dcache */ +extern void microblaze_flush_dcache_range(u32 cacheaddr, u32 len); /* Flush a part of the dcache */ extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */ extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */ extern void microblaze_flush_cache_ext(void); /* Flush cache ext */ -extern void microblaze_flush_cache_ext_range(unsigned int cacheaddr, - unsigned int len); /* Flush cache ext range */ -extern void microblaze_invalidate_cache_ext_range(unsigned int cacheaddr, - unsigned int len); /* Invalidate cache ext range */ +extern void microblaze_flush_cache_ext_range(u32 cacheaddr, + u32 len); /* Flush cache ext range */ +extern void microblaze_invalidate_cache_ext_range(u32 cacheaddr, + u32 len); /* Invalidate cache ext range */ /* Deprecated */ -extern void microblaze_update_icache (int , int , int ) __attribute__((deprecated)); -extern void microblaze_init_icache_range (int , int ) __attribute__((deprecated)); -extern void microblaze_update_dcache (int , int , int ) __attribute__((deprecated)); -extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated)); +extern void microblaze_update_icache (s32 , s32 , s32 ) __attribute__((deprecated)); +extern void microblaze_init_icache_range (s32 , s32 ) __attribute__((deprecated)); +extern void microblaze_update_dcache (s32 , s32 , s32 ) __attribute__((deprecated)); +extern void microblaze_init_dcache_range (s32 , s32 ) __attribute__((deprecated)); /* necessary for pre-processor */ #define stringify(s) tostring(s) @@ -119,7 +119,7 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated "andi\t%0,%0,0x10" : "=d" (error)) /* Pseudo assembler instructions */ -#define clz(v) ({ unsigned int _rval; \ +#define clz(v) ({ u32 _rval; \ __asm__ __volatile__ ( \ "clz\t%0,%1\n" : "=d"(_rval): "d" (v) \ ); \ @@ -129,119 +129,133 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated #define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); }) #define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); }) -#define mb_swapb(v) ({ unsigned int _rval; \ +#define mb_swapb(v) ({ u32 _rval; \ __asm__ __volatile__ ( \ "swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \ ); \ _rval; \ }) -#define mb_swaph(v) ({ unsigned int _rval; \ +#define mb_swaph(v) ({ u32 _rval; \ __asm__ __volatile__ ( \ "swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \ ); \ _rval; \ }) -#define mfgpr(rn) ({ unsigned int _rval; \ +#define mfgpr(rn) ({ u32 _rval; \ __asm__ __volatile__ ( \ "or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfmsr() ({ unsigned int _rval; \ +#define mfmsr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rmsr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfear() ({ unsigned int _rval; \ +#define mfear() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rear\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfesr() ({ unsigned int _rval; \ +#define mfeare() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfse\t%0,rear\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mfesr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,resr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mffsr() ({ unsigned int _rval; \ +#define mffsr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rfsr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfpvr(rn) ({ unsigned int _rval; \ +#define mfpvr(rn) ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfbtr() ({ unsigned int _rval; \ +#define mfpvre(rn) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfse\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mfbtr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rbtr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfedr() ({ unsigned int _rval; \ +#define mfedr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,redr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfpid() ({ unsigned int _rval; \ +#define mfpid() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rpid\n" : "=d"(_rval)\ ); \ _rval; \ }) -#define mfzpr() ({ unsigned int _rval; \ +#define mfzpr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rzpr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mftlbx() ({ unsigned int _rval; \ +#define mftlbx() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rtlbx\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mftlblo() ({ unsigned int _rval; \ +#define mftlblo() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rtlblo\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mftlbhi() ({ unsigned int _rval; \ +#define mftlbhi() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rtlbhi\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfslr() ({ unsigned int _rval; \ +#define mfslr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rslr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfshr() ({ unsigned int _rval; \ +#define mfshr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rshr\n" : "=d"(_rval) \ ); \ @@ -304,34 +318,56 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated ); \ }) -#define lwx(address) ({ unsigned int _rval; \ +#define lwx(address) ({ u32 _rval; \ __asm__ __volatile__ ( \ "lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ ); \ _rval; \ }) -#define lwr(address) ({ unsigned int _rval; \ +#define lwr(address) ({ u32 _rval; \ __asm__ __volatile__ ( \ "lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ ); \ _rval; \ }) -#define lhur(address) ({ unsigned int _rval; \ + +#define lwea(lladdr) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "lwea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \ + ); \ + _rval; \ + }) + +#define lhur(address) ({ u32 _rval; \ __asm__ __volatile__ ( \ "lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ ); \ _rval; \ }) -#define lbur(address) ({ unsigned int _rval; \ +#define lhuea(lladdr) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "lhuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \ + ); \ + _rval; \ + }) + +#define lbur(address) ({ u32 _rval; \ __asm__ __volatile__ ( \ "lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ ); \ _rval; \ }) +#define lbuea(lladdr) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "lbuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \ + ); \ + _rval; \ + }) + #define swx(address, data) ({ __asm__ __volatile__ ( \ "swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \ ); \ @@ -342,23 +378,38 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated ); \ }) +#define swea(lladdr, data) ({ __asm__ __volatile__ ( \ + "swea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \ + ); \ + }) + #define shr(address, data) ({ __asm__ __volatile__ ( \ "shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \ ); \ }) +#define shea(lladdr, data) ({ __asm__ __volatile__ ( \ + "shea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \ + ); \ + }) + #define sbr(address, data) ({ __asm__ __volatile__ ( \ "sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \ ); \ }) +#define sbea(lladdr, data) ({ __asm__ __volatile__ ( \ + "sbea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \ + ); \ + }) + #define microblaze_getfpex_operand_a() ({ \ - extern unsigned int mb_fpex_op_a; \ + extern u32 mb_fpex_op_a; \ mb_fpex_op_a; \ }) #define microblaze_getfpex_operand_b() ({ \ - extern unsigned int mb_fpex_op_b; \ + extern u32 mb_fpex_op_b; \ mb_fpex_op_b; \ }) diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_i.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_dcache.S similarity index 56% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_i.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_dcache.S index a6f9bc559..af9d41bd0 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_i.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_dcache.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,51 +29,56 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ -/*****************************************************************************/ -/** +/****************************************************************************** +* File : microblaze_disable_dcache.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies * -* @file xtmrctr_i.h +* Summary: +* Disable the L1 dcache on the microblaze. * -* This file contains data which is shared between files internal to the -* XTmrCtr component. It is intended for internal use only. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl  02/06/02 First release
-* 1.10b mta  03/21/07 Updated to new coding style
-* 2.00a ktn  10/30/09 _m is removed from all the macro definitions.
-*
-* -******************************************************************************/ +*******************************************************************************/ -#ifndef XTMRCTR_I_H /* prevent circular inclusions */ -#define XTMRCTR_I_H /* by using protection macros */ +#include "xparameters.h" -#ifdef __cplusplus -extern "C" { -#endif + .text + .globl microblaze_disable_dcache + .ent microblaze_disable_dcache + .align 2 +microblaze_disable_dcache: +#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 -/***************************** Include Files *********************************/ +#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 + addik r1, r1, -4 + swi r15, r1, 0 + brlid r15, microblaze_flush_dcache /* microblaze_flush_dcache does not use r1*/ + nop + lwi r15, r1, 0 + addi r1, r1, 4 +#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */ + rtsd r15, 8 + msrclr r0, 0x80 -#include "xil_types.h" +#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 1 */ -/************************** Constant Definitions *****************************/ + addik r1, r1, -4 +#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 + swi r15, r1, 0 + brlid r15, microblaze_flush_dcache + nop +#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */ + mfs r11, rmsr + andi r11, r11, ~(0x80) + mts rmsr, r11 -/************************** Function Prototypes ******************************/ +#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 + lwi r15, r1, 0 +#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */ + rtsd r15, 8 + addi r1, r1, 4 -/************************** Variable Definitions *****************************/ - -extern XTmrCtr_Config XTmrCtr_ConfigTable[]; - -extern u8 XTmrCtr_Offsets[]; - -#ifdef __cplusplus -} -#endif - -#endif +#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + .end microblaze_disable_dcache diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_exceptions.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_exceptions.S similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_exceptions.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_exceptions.S index e28a7db86..60efc72b9 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_exceptions.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_exceptions.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,11 +29,12 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# Disable exceptions on microblaze. -# -# -#################################################################### +/****************************************************************************** +* +* Disable exceptions on microblaze. +* +* +******************************************************************************/ #include "xparameters.h" @@ -45,14 +46,11 @@ microblaze_disable_exceptions: #if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 rtsd r15, 8 msrclr r0, 0x100 -#else +#else mfs r4, rmsr; andi r4, r4, ~(0x100); /* Turn OFF the EE bit */ mts rmsr, r4; rtsd r15, 8; - nop; + nop; #endif .end microblaze_disable_exceptions - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_icache.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_icache.S similarity index 84% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_icache.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_icache.S index c5b5cf6e0..da946fc76 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_icache.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_icache.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,17 +29,18 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# File : microblaze_disable_icache.s -# Date : 2002, March 20. -# Company: Xilinx -# Group : Emerging Software Technologies -# -# Summary: -# Disable L1 icache on the microblaze. -# -# -#################################################################### +/****************************************************************************** +* +* File : microblaze_disable_icache.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Disable L1 icache on the microblaze. +* +* +******************************************************************************/ #include "xparameters.h" @@ -47,7 +48,7 @@ .globl microblaze_disable_icache .ent microblaze_disable_icache .align 2 -microblaze_disable_icache: +microblaze_disable_icache: #if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 rtsd r15, 8 msrclr r0, 0x20 @@ -63,6 +64,3 @@ microblaze_disable_icache: nop #endif .end microblaze_disable_icache - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_interrupts.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_interrupts.S similarity index 84% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_interrupts.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_interrupts.S index ae28d9d87..08f6ecafe 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_interrupts.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_interrupts.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,17 +29,18 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# File : microblaze_disable_interrupts.s -# Date : 2002, March 20. -# Company: Xilinx -# Group : Emerging Software Technologies -# -# Summary: -# Disable interrupts on the microblaze. -# -# -#################################################################### +/****************************************************************************** +* +* File : microblaze_disable_interrupts.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Disable interrupts on the microblaze. +* +* +******************************************************************************/ #include "xparameters.h" @@ -47,7 +48,7 @@ .globl microblaze_disable_interrupts .ent microblaze_disable_interrupts .align 2 -microblaze_disable_interrupts: +microblaze_disable_interrupts: #if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 rtsd r15, 8 msrclr r0, 0x2 @@ -63,6 +64,3 @@ microblaze_disable_interrupts: nop #endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ .end microblaze_disable_interrupts - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_dcache.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_dcache.S similarity index 84% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_dcache.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_dcache.S index 862fcdafa..cf0991e62 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_dcache.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_dcache.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,25 +29,26 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# File : microblaze_enable_dcache.s -# Date : 2002, March 20. -# Company: Xilinx -# Group : Emerging Software Technologies -# -# Summary: -# Enable L1 dcache on the microblaze. -# -# -#################################################################### +/****************************************************************************** +* +* File : microblaze_enable_dcache.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Enable L1 dcache on the microblaze. +* +* +******************************************************************************/ -#include "xparameters.h" +#include "xparameters.h" .text .globl microblaze_enable_dcache .ent microblaze_enable_dcache .align 2 -microblaze_enable_dcache: +microblaze_enable_dcache: #if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 rtsd r15, 8 @@ -64,6 +65,3 @@ microblaze_enable_dcache: nop #endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ .end microblaze_enable_dcache - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_exceptions.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_exceptions.S similarity index 91% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_exceptions.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_exceptions.S index df298fc02..8e1ea080d 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_exceptions.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_exceptions.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,11 +29,12 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# Enable exceptions on microblaze. -# -# -#################################################################### +/****************************************************************************** +* +* Enable exceptions on microblaze. +* +* +******************************************************************************/ #include "xparameters.h" @@ -50,9 +51,6 @@ microblaze_enable_exceptions: ori r4, r4, 0x100; /* Turn ON the EE bit */ mts rmsr, r4; rtsd r15, 8; - nop; + nop; #endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ .end microblaze_enable_exceptions - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_icache.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_icache.S similarity index 86% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_icache.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_icache.S index ce8f58a72..a398f1fd4 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_icache.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_icache.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,18 +29,18 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# File : microblaze_enable_icache.s -# Date : 2002, March 20. -# Company: Xilinx -# Group : Emerging Software Technologies -# -# Summary: -# Enable icache on the microblaze. -# -# -#################################################################### - +/****************************************************************************** +* +* File : microblaze_enable_icache.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Enable icache on the microblaze. +* +* +******************************************************************************/ #include "xparameters.h" .text @@ -63,6 +63,3 @@ microblaze_enable_icache: nop #endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ .end microblaze_enable_icache - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_interrupts.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_interrupts.S similarity index 83% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_interrupts.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_interrupts.S index e65d183c7..11c8c667b 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_interrupts.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_interrupts.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,25 +29,26 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# File : microblaze_enable_interrupts.s -# Date : 2002, March 20. -# Company: Xilinx -# Group : Emerging Software Technologies -# -# Summary: -# Enable interrupts on the microblaze. -# -# -#################################################################### +/****************************************************************************** +* +* File : microblaze_enable_interrupts.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Enable interrupts on the microblaze. +* +* +******************************************************************************/ -#include "xparameters.h" +#include "xparameters.h" .text .globl microblaze_enable_interrupts .ent microblaze_enable_interrupts .align 2 -microblaze_enable_interrupts: +microblaze_enable_interrupts: #if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 rtsd r15, 8 msrset r0, 0x2 @@ -63,6 +64,3 @@ microblaze_enable_interrupts: nop #endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ .end microblaze_enable_interrupts - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exception_handler.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exception_handler.c similarity index 98% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exception_handler.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exception_handler.c index 426f7c12c..a504f2729 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exception_handler.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exception_handler.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exceptions_g.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h similarity index 83% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exceptions_g.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h index a7bfea40d..f5f0c6e63 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exceptions_g.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -22,8 +22,8 @@ * *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * @@ -37,8 +37,3 @@ * *******************************************************************/ -#define MICROBLAZE_EXCEPTIONS_ENABLED 1 -#define MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS -#define MICROBLAZE_FP_EXCEPTION_ENABLED 1 - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exceptions_i.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_i.h similarity index 83% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exceptions_i.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_i.h index c6b616b5f..b7e0d9635 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exceptions_i.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_i.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -67,17 +67,17 @@ typedef struct } MB_ExceptionVectorTableEntry; /* Exception IDs */ -#define XEXC_ID_FSL 0 -#define XEXC_ID_UNALIGNED_ACCESS 1 -#define XEXC_ID_ILLEGAL_OPCODE 2 -#define XEXC_ID_M_AXI_I_EXCEPTION 3 -#define XEXC_ID_IPLB_EXCEPTION 3 -#define XEXC_ID_M_AXI_D_EXCEPTION 4 -#define XEXC_ID_DPLB_EXCEPTION 4 -#define XEXC_ID_DIV_BY_ZERO 5 -#define XEXC_ID_FPU 6 -#define XEXC_ID_STACK_VIOLATION 7 -#define XEXC_ID_MMU 7 +#define XEXC_ID_FSL 0U +#define XEXC_ID_UNALIGNED_ACCESS 1U +#define XEXC_ID_ILLEGAL_OPCODE 2U +#define XEXC_ID_M_AXI_I_EXCEPTION 3U +#define XEXC_ID_IPLB_EXCEPTION 3U +#define XEXC_ID_M_AXI_D_EXCEPTION 4U +#define XEXC_ID_DPLB_EXCEPTION 4U +#define XEXC_ID_DIV_BY_ZERO 5U +#define XEXC_ID_FPU 6U +#define XEXC_ID_STACK_VIOLATION 7U +#define XEXC_ID_MMU 7U void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_cache_ext.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_cache_ext.S similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_cache_ext.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_cache_ext.S index e47b0a37a..a22576888 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_cache_ext.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_cache_ext.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,9 +28,12 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * microblaze_flush_cache_ext() * -* Flush the entire L2 Cache +* Flush the entire L2 Cache * * *******************************************************************************/ @@ -48,7 +51,7 @@ microblaze_flush_cache_ext: #if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1)) addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) - + addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) @@ -60,6 +63,3 @@ Loop_start: rtsd r15, 8 nop .end microblaze_flush_cache_ext - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_cache_ext_range.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_cache_ext_range.S similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_cache_ext_range.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_cache_ext_range.S index b315c3d9a..9251db20c 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_cache_ext_range.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_cache_ext_range.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,11 +28,14 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len) * *Flush a L2 Cache range * -*Parameters: +*Parameters: * 'cacheaddr' - address in the L2 cache where the flush begins * 'len ' - length (in bytes) worth of L2 cache to be flushed * @@ -63,12 +66,9 @@ Loop_start: bneid r6, Loop_start addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) -Loop_done: +Loop_done: #endif rtsd r15, 8 nop .end microblaze_flush_cache_ext_range - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_dcache.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_dcache.S similarity index 80% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_dcache.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_dcache.S index ed89fad2c..1f18cce78 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_dcache.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_dcache.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,9 +28,13 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* +* * microblaze_flush_dcache() -* -* Flush the L1 DCache +* +* Flush the L1 DCache * *******************************************************************************/ @@ -38,11 +42,11 @@ #define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif - + .text .globl microblaze_flush_dcache .ent microblaze_flush_dcache @@ -50,21 +54,18 @@ microblaze_flush_dcache: addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Align to cache line */ - addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */ - + addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */ + L_start: wdc.flush r5, r0 /* Flush the Cache */ - - cmpu r18, r5, r6 /* Are we at the end? */ - blei r18, L_done - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ -L_done: +L_done: rtsd r15, 8 /* Return */ nop .end microblaze_flush_dcache - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_dcache_range.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_dcache_range.S similarity index 85% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_dcache_range.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_dcache_range.S index 1919a950c..0bb81cd34 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_dcache_range.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_dcache_range.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,11 +28,14 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * microblaze_flush_dcache_range (unsigned int cacheaddr, unsigned int len) -* +* * Flush a L1 DCache range -* -* Parameters: +* +* Parameters: * 'cacheaddr' - address in the Dcache where the flush begins * 'len ' - length (in bytes) worth of Dcache to be flushed * @@ -42,7 +45,7 @@ #define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif @@ -61,32 +64,32 @@ microblaze_flush_dcache_range: -#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ - mfs r9, rmsr +#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ + mfs r9, rmsr andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) mts rmsr, r10 #endif beqi r6, L_done /* Skip loop if size is zero */ - + add r6, r5, r6 /* Compute end address */ addik r6, r6, -1 - - andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */ + + andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */ andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */ #if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */ - + L_start: - cmpu r18, r5, r6 /* Are we at the end? */ - blti r18, L_done - + cmpu r18, r5, r6 /* Are we at the end? */ + blti r18, L_done + wdc r5, r0 /* Invalidate the cache line */ - - brid L_start /* Branch to the beginning of the loop */ + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ #else - rsubk r6, r5, r6 + rsubk r6, r5, r6 /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */ L_start: wdc.flush r5, r6 /* Flush the cache line */ @@ -94,15 +97,12 @@ L_start: addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) #endif - -L_done: - rtsd r15, 8 + +L_done: + rtsd r15, 8 #ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ mts rmsr, r9 #else nop #endif .end microblaze_flush_dcache_range - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_init_dcache_range.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_init_dcache_range.S similarity index 84% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_init_dcache_range.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_init_dcache_range.S index dd23ee354..925a387f4 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_init_dcache_range.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_init_dcache_range.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,11 +28,14 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * microblaze_init_dcache_range (unsigned int cache_start, unsigned int cache_len) -* +* * Invalidate dcache on the microblaze -* -* Parameters: +* +* Parameters: * 'cache_start' - address in the Dcache where invalidation begins * 'cache_len' - length (in bytes) worth of Dcache to be invalidated * @@ -43,11 +46,11 @@ #define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif - + .text .globl microblaze_init_dcache_range .ent microblaze_init_dcache_range @@ -61,22 +64,19 @@ microblaze_init_dcache_range: andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */ - add r6, r5, r6 /* Compute end */ + add r6, r5, r6 /* Compute end */ andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */ - + L_start: wdc r5, r0 /* Invalidate the Cache (delay slot) */ - - cmpu r18, r5, r6 /* Are we at the end ? */ - blei r18, L_done - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end ? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ -L_done: +L_done: rtsd r15, 8 /* Return */ mts rmsr, r9 .end microblaze_init_dcache_range - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_init_icache_range.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_init_icache_range.S similarity index 84% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_init_icache_range.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_init_icache_range.S index 982fea356..15563f871 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_init_icache_range.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_init_icache_range.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,12 +28,15 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * * microblaze_init_icache_range (unsigned int cache_start, unsigned int cache_len) -* +* * Invalidate icache on the microblaze -* -* Parameters: +* +* Parameters: * 'cache_start' - address in the Icache where invalidation begins * 'cache_len' - length (in bytes) worth of Icache to be invalidated * @@ -44,11 +47,11 @@ #define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 #endif - + .text .globl microblaze_init_icache_range .ent microblaze_init_icache_range @@ -62,22 +65,19 @@ microblaze_init_icache_range: andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */ - add r6, r5, r6 /* Compute end */ + add r6, r5, r6 /* Compute end */ andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */ - + L_start: wic r5, r0 /* Invalidate the Cache (delay slot) */ - - cmpu r18, r5, r6 /* Are we at the end ? */ - blei r18, L_done - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end ? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ -L_done: +L_done: rtsd r15, 8 /* Return */ mts rmsr, r9 .end microblaze_init_icache_range - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupt_handler.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupt_handler.c similarity index 95% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupt_handler.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupt_handler.c index 6465494ab..a8a8e7b85 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupt_handler.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupt_handler.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -64,6 +64,7 @@ /************************** Function Prototypes ******************************/ void __interrupt_handler (void) __attribute__ ((interrupt_handler)); +void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /************************** Variable Definitions *****************************/ @@ -91,7 +92,7 @@ extern MB_InterruptVectorTableEntry MB_InterruptVectorTable; void __interrupt_handler(void) { /* The compiler saves all volatiles and the MSR */ - MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef); + (void)MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef); /* The compiler restores all volatiles and MSR, and returns from interrupt */ } @@ -119,4 +120,3 @@ void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr) MB_InterruptVectorTable.Handler = Handler; MB_InterruptVectorTable.CallBackRef = DataPtr; } - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupts_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c similarity index 85% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupts_g.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c index b022071fc..dda78bce7 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupts_g.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -22,8 +22,8 @@ * *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * @@ -41,7 +41,7 @@ #include "xparameters.h" -extern void XIntc_DeviceInterruptHandler (void *); +extern void XNullHandler (void *); /* * The interrupt handler table for microblaze processor @@ -49,7 +49,7 @@ extern void XIntc_DeviceInterruptHandler (void *); MB_InterruptVectorTableEntry MB_InterruptVectorTable[] = { -{ XIntc_DeviceInterruptHandler, - (void*) XPAR_AXI_INTC_0_DEVICE_ID} +{ XNullHandler, + (void*) XNULL} }; diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupts_i.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_i.h similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupts_i.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_i.h index 6f0c7faf6..d0fecdbc5 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupts_i.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_i.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_cache_ext.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_cache_ext.S similarity index 87% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_cache_ext.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_cache_ext.S index 82d76a7a3..d806519a7 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_cache_ext.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_cache_ext.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,9 +28,12 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * microblaze_invalidate_cache_ext() * -*Invalidate the entire L2 Cache +*Invalidate the entire L2 Cache * * *******************************************************************************/ @@ -48,19 +51,16 @@ microblaze_invalidate_cache_ext: #if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1)) addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)) - + addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) - andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) Loop_start: wdc.ext.clear r5, r6 bgtid r6,Loop_start addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) -#endif +#endif rtsd r15, 8 nop .end microblaze_invalidate_cache_ext - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_cache_ext_range.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_cache_ext_range.S similarity index 91% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_cache_ext_range.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_cache_ext_range.S index 3f2fd92fc..13ce65e17 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_cache_ext_range.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_cache_ext_range.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,6 +28,9 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * microblaze_invalidate_cache_ext_range (unsigned int cacheaddr, unsigned int len) * *Invalidate an L2 cache range @@ -64,12 +67,9 @@ Loop_start: bneid r6, Loop_start addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) -Loop_done: +Loop_done: #endif rtsd r15, 8 nop .end microblaze_invalidate_cache_ext_range - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_dcache.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_dcache.S similarity index 78% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_dcache.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_dcache.S index 78bf07813..6a51217ff 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_dcache.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_dcache.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,9 +28,12 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * microblaze_invalidate_dcache() -* -* Invalidate the entire L1 DCache +* +* Invalidate the entire L1 DCache * * *******************************************************************************/ @@ -39,7 +42,7 @@ #define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif @@ -47,7 +50,7 @@ #ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK #define MB_VERSION_LT_v720 #endif - + .text .globl microblaze_invalidate_dcache .ent microblaze_invalidate_dcache @@ -55,24 +58,24 @@ microblaze_invalidate_dcache: -#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ - mfs r9, rmsr +#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ + mfs r9, rmsr andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) mts rmsr, r10 #endif - addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) - addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */ - + addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) + addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */ + L_start: wdc r5, r0 /* Invalidate the Cache */ - - cmpu r18, r5, r6 /* Are we at the end? */ - blei r18, L_done - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ -L_done: +L_done: rtsd r15, 8 /* Return */ #ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ mts rmsr, r9 @@ -81,6 +84,3 @@ L_done: #endif .end microblaze_invalidate_dcache - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_dcache_range.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_dcache_range.S similarity index 84% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_dcache_range.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_dcache_range.S index 3766063e9..7c455c653 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_dcache_range.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_dcache_range.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,12 +28,15 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * * microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len) -* +* * Invalidate a Dcache range -* -* Parameters: +* +* Parameters: * 'cacheaddr' - address in the Dcache where invalidation begins * 'len ' - length (in bytes) worth of Dcache to be invalidated * @@ -44,7 +47,7 @@ #define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif @@ -55,7 +58,7 @@ #else #define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK #endif - + .text .globl microblaze_invalidate_dcache_range .ent microblaze_invalidate_dcache_range @@ -63,34 +66,34 @@ microblaze_invalidate_dcache_range: - -#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ - mfs r9, rmsr + +#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ + mfs r9, rmsr andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) mts rmsr, r10 #endif beqi r6, L_done /* Skip loop if size is zero */ - + add r6, r5, r6 /* Compute end address */ addik r6, r6, -1 - - andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */ + + andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */ andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */ - + #if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */ - + L_start: - cmpu r18, r5, r6 /* Are we at the end? */ - blti r18, L_done - - wdc r5, r0 - - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end? */ + blti r18, L_done + + wdc r5, r0 + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ #else - rsubk r6, r5, r6 + rsubk r6, r5, r6 /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */ L_start: wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */ @@ -98,15 +101,12 @@ L_start: addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) #endif - -L_done: - rtsd r15, 8 + +L_done: + rtsd r15, 8 #ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ mts rmsr, r9 #else nop #endif .end microblaze_invalidate_dcache_range - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_icache.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_icache.S similarity index 80% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_icache.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_icache.S index f0013e891..d244e6677 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_icache.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_icache.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,9 +28,12 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * * microblaze_invalidate_icache() -* +* * Invalidate the entire ICache * * @@ -40,7 +43,7 @@ #define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 #endif @@ -48,7 +51,7 @@ #ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK #define MB_VERSION_LT_v720 #endif - + .text .globl microblaze_invalidate_icache .ent microblaze_invalidate_icache @@ -56,23 +59,23 @@ microblaze_invalidate_icache: -#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */ +#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */ mfs r9, rmsr andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) mts rmsr, r10 #endif - addik r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */ - addik r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */ + addik r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */ + addik r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */ L_start: wic r5, r0 /* Invalidate the Cache */ - - cmpu r18, r5, r6 /* Are we at the end? */ - blei r18, L_done - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ -L_done: +L_done: rtsd r15, 8 /* Return */ #ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ @@ -81,6 +84,3 @@ L_done: nop #endif .end microblaze_invalidate_icache - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_icache_range.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_icache_range.S similarity index 85% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_icache_range.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_icache_range.S index 63515598b..5a82d261a 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_icache_range.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_icache_range.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,12 +28,15 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * * microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len) -* +* * Invalidate an ICache range -* -* Parameters: +* +* Parameters: * 'cacheaddr' - address in the Icache where invalidation begins * 'len' - length (in bytes) worth of Icache to be invalidated * @@ -44,7 +47,7 @@ #define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 #endif @@ -52,7 +55,7 @@ #ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK #define MB_VERSION_LT_v720 #endif - + .text .globl microblaze_invalidate_icache_range .ent microblaze_invalidate_icache_range @@ -60,27 +63,27 @@ microblaze_invalidate_icache_range: -#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */ - mfs r9, rmsr +#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */ + mfs r9, rmsr andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) mts rmsr, r10 #endif beqi r6, L_done /* Skip loop if size is zero */ - + add r6, r5, r6 /* Compute end address */ addik r6, r6, -1 - - andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */ + + andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */ andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align start down to cache line */ L_start: - cmpu r18, r5, r6 /* Are we at the end? */ - blti r18, L_done + cmpu r18, r5, r6 /* Are we at the end? */ + blti r18, L_done wic r5, r0 /* Invalidate the cache line */ - - brid L_start /* Branch to the beginning of the loop */ + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ L_done: @@ -91,6 +94,3 @@ L_done: nop #endif .end microblaze_invalidate_icache_range - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_scrub.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_scrub.S similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_scrub.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_scrub.S index fb5bf93f0..6c1512abd 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_scrub.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_scrub.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,6 +28,9 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * microblaze_scrub () * * Scrub LMB memory and all internal BRAMs (data cache, instruction cache, diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_sleep.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_sleep.c similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_sleep.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_sleep.c index d75600f2a..0e34cc628 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_sleep.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_sleep.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -80,9 +80,9 @@ * @note Instruction cache should be enabled for this to work. * ******************************************************************************/ -void MB_Sleep(unsigned int MilliSeconds) +void MB_Sleep(u32 MilliSeconds) { - if (((mfmsr() & 0x20) == 0)) { + if (((mfmsr() & 0x20U) == 0U)) { /* * Instruction cache not enabled. * Delay will be much higher than expected. diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_sleep.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_sleep.h similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_sleep.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_sleep.h index 285055397..ab4e8f444 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_sleep.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_sleep.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -74,7 +74,7 @@ extern "C" { /************************** Function Prototypes ******************************/ -void MB_Sleep(unsigned int MilliSeconds); +void MB_Sleep(u32 MilliSeconds); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_update_dcache.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_update_dcache.S similarity index 92% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_update_dcache.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_update_dcache.S index 91d8d7b7c..0d497e74c 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_update_dcache.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_update_dcache.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,7 +28,10 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * -* +******************************************************************************/ +/****************************************************************************** +* +* * File : microblaze_update_dcache.s * Date : 2003, September 24 * Company: Xilinx @@ -49,14 +52,14 @@ * | 0 | 0 | Invalidate Cache * | 0 | 1 | Valid, but unlocked cacheline * | 1 | 0 | Invalidate Cache, No effect of lock -* | 1 | 1 | Valid cache. Locked to a +* | 1 | 1 | Valid cache. Locked to a * | | | particular addrees * -------------------------------------------------------------- * * **********************************************************************************/ #include "xparameters.h" - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif @@ -97,7 +100,7 @@ microblaze_update_dcache: addik r6, r0, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* We don't have a return instruction here. This is tail call optimization :) */ - + #endif /* XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1 */ .end microblaze_update_dcache diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_update_icache.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_update_icache.S similarity index 91% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_update_icache.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_update_icache.S index 79d70ee92..789f6bb8d 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_update_icache.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_update_icache.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,6 +28,9 @@ * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * +******************************************************************************/ +/****************************************************************************** +* * File : microblaze_update_icache.s * Date : 2003, September 24 * Company: Xilinx @@ -48,14 +51,14 @@ * | 0 | 0 | Invalidate Cache * | 0 | 1 | Valid, but unlocked cacheline * | 1 | 0 | Invalidate Cache, No effect of lock -* | 1 | 1 | Valid cache. Locked to a +* | 1 | 1 | Valid cache. Locked to a * | | | particular addrees * -------------------------------------------------------------- * * **********************************************************************************/ #include "xparameters.h" - + #ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 #endif @@ -67,7 +70,7 @@ microblaze_update_icache: #if XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 - + /* Read the MSR register into a temp register */ mfs r18, rmsr @@ -96,8 +99,7 @@ microblaze_update_icache: addik r6, r0, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* We don't have a return instruction here. This is tail call optimization :) */ - + #endif /* XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 */ - .end microblaze_update_icache - + .end microblaze_update_icache diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/outbyte.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/outbyte.c new file mode 100644 index 000000000..094da9a92 --- /dev/null +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/outbyte.c @@ -0,0 +1,15 @@ +#include "xparameters.h" +#include "xuartlite_l.h" + +#ifdef __cplusplus +extern "C" { +#endif +void outbyte(char c); + +#ifdef __cplusplus +} +#endif + +void outbyte(char c) { + XUartLite_SendByte(STDOUT_BASEADDRESS, c); +} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/print.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/print.c new file mode 100644 index 000000000..31d7b1989 --- /dev/null +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/print.c @@ -0,0 +1,32 @@ +/* print.c -- print a string on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + */ + +/* + * print -- do a raw print of a string + */ +#include "xil_printf.h" + +void print(const char8 *ptr) +{ +#ifdef STDOUT_BASEADDRESS + while (*ptr != (char8)0) { + outbyte (*ptr); + *ptr++; + } +#else +(void)ptr; +#endif +} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/Makefile b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/Makefile similarity index 93% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/Makefile rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/Makefile index 6182558b5..891fdf643 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/Makefile +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/Makefile @@ -1,7 +1,6 @@ -#$Id: Makefile,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $ ############################################################################### # -# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal @@ -32,17 +31,17 @@ ############################################################################### # # Makefile for profiler -# +# ####################################################################### # PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here include ../config.make AS=mb-as -COMPILER = mb-gcc +COMPILER = mb-gcc ARCHIVER = mb-ar CP = cp -COMPILER_FLAGS=-O2 +COMPILER_FLAGS=-O2 EXTRA_COMPILER_FLAGS= LIB = libxil.a DUMMYLIB = libxilprofile.a @@ -54,7 +53,7 @@ RELEASEDIR = ../../../../lib INCLUDEDIR = ../../../../include INCLUDES = -I./. -I${INCLUDEDIR} -OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o +OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o DUMMYOBJ = dummy.o INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h @@ -72,7 +71,7 @@ dummylibs : $(DUMMYOBJ) %.o:%.S $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES) -include: +include: $(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR) clean: diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_clean.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_clean.c similarity index 93% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_clean.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_clean.c index bd6955e86..1d8aada04 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_clean.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_clean.c @@ -1,7 +1,6 @@ -// $Id: _profile_clean.c,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,6 +34,8 @@ #include "_profile_timer_hw.h" #include "xil_exception.h" +void _profile_clean( void ); + /* * This function is the exit routine and is called by the crtinit, when the * program terminates. The name needs to be changed later.. @@ -44,4 +45,3 @@ void _profile_clean( void ) Xil_ExceptionDisable(); disable_timer(); } - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_init.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_init.c similarity index 59% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_init.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_init.c index 809f3468b..0ac51b175 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_init.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_init.c @@ -1,7 +1,6 @@ -// $Id: _profile_init.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -38,57 +37,54 @@ #include "profile.h" -// XMD Initializes the following Global Variables Value during Program -// Download with appropriate values. +/* XMD Initializes the following Global Variables Value during Program + * Download with appropriate values. */ #ifdef PROC_MICROBLAZE -extern int microblaze_init(void); +extern s32 microblaze_init(void); #elif defined PROC_PPC -extern int powerpc405_init(void); +extern s32 powerpc405_init(void); #else -extern int cortexa9_init(void); +extern s32 cortexa9_init(void); #endif +s32 profile_version = 1; /* Version of S/W Intrusive Profiling library */ +u32 binsize = (u32)BINSIZE; /* Histogram Bin Size */ +u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ; /* CPU Clock Frequency */ +u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ; /* Histogram Sampling Frequency */ +u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */ -int profile_version = 1; // Version of S/W Intrusive Profiling library +/* Structure for Storing the Profiling Data */ +struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU); +s32 n_gmon_sections = 1; -int binsize = BINSIZE; // Histogram Bin Size -unsigned int cpu_clk_freq = CPU_FREQ_HZ ; // CPU Clock Frequency -unsigned int sample_freq_hz = SAMPLE_FREQ_HZ ; // Histogram Sampling Frequency -unsigned int timer_clk_ticks = TIMER_CLK_TICKS ;// Timer Clock Ticks for the Timer +/* This is the initialization code, which is called from the crtinit. */ -// Structure for Storing the Profiling Data -struct gmonparam *_gmonparam = (struct gmonparam *)0xffffffff; -int n_gmon_sections = 1; - -// This is the initialization code, which is called from the crtinit. -// void _profile_init( void ) { -/* print("Gmon Init called....\r\n") ; */ -/* putnum(n_gmon_sections) ; print("\r\n") ; */ +/* print("Gmon Init called....\r\n") */ +/* putnum(n_gmon_sections) , print("\r\n") */ /* if( _gmonparam == 0xffffffff ) */ -/* printf("Gmonparam is NULL !!\r\n"); */ -/* for( i = 0; i < n_gmon_sections; i++ ){ */ -/* putnum(_gmonparam[i].lowpc) ; print("\t") ; */ -/* putnum(_gmonparam[i].highpc) ; print("\r\n") ; */ -/* putnum( _gmonparam[i].textsize ); print("\r\n") ; */ -/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short));print("\r\n"); */ -/* } */ +/* printf("Gmonparam is NULL !!\r\n") */ +/* for( i = 0, i < n_gmon_sections, i++ )[ */ +/* putnum( _gmonparam[i].lowpc) , print("\t") */ +/* putnum( _gmonparam[i].highpc) , print("\r\n") */ +/* putnum( _gmonparam[i].textsize ), print("\r\n") */ +/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n") */ +/* ] */ #ifdef PROC_MICROBLAZE - microblaze_init(); + (void)microblaze_init(); #elif defined PROC_PPC powerpc405_init(); #else - cortexa9_init (); + (void)cortexa9_init(); #endif } - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.c new file mode 100644 index 000000000..e85fb5c2d --- /dev/null +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.c @@ -0,0 +1,387 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +****************************************************************************** +* +* _program_timer_hw.c: +* Timer related functions +* +******************************************************************************/ + +#include "profile.h" +#include "_profile_timer_hw.h" + +#include "xil_exception.h" + +#ifdef PROC_PPC +#include "xtime_l.h" +#include "xpseudo_asm.h" +#endif + +#ifdef TIMER_CONNECT_INTC +#include "xintc_l.h" +#include "xintc.h" +#endif /* TIMER_CONNECT_INTC */ + +/* #ifndef PPC_PIT_INTERRUPT */ +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +#include "xtmrctr_l.h" +#endif + +/* extern u32 timer_clk_ticks, */ + +#ifdef PROC_PPC405 +#ifdef PPC_PIT_INTERRUPT +s32 ppc_pit_init( void ); +#endif +s32 powerpc405_init() +#endif /* PROC_CORTEXA9 */ + +#ifdef PROC_PPC440 +#ifdef PPC_PIT_INTERRUPT +s32 ppc_dec_init( void ); +#endif +s32 powerpc405_init(void); +#endif /* PROC_PPC440 */ + +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +s32 opb_timer_init( void ); +#endif + +#ifdef PROC_MICROBLAZE +s32 microblaze_init(void); +#endif /* PROC_MICROBLAZE */ + +#ifdef PROC_CORTEXA9 +s32 scu_timer_init( void ); +s32 cortexa9_init(void); +#endif /* PROC_CORTEXA9 */ + + +/*-------------------------------------------------------------------- + * PowerPC Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_PPC405 + + +/*-------------------------------------------------------------------- +* PowerPC PIT Timer Init. +* Defined only if PIT Timer is used for Profiling +* +*-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +int ppc_pit_init( void ) +{ + /* 1. Register Profile_intr_handler as Interrupt handler */ + /* 2. Set PIT Timer Interrupt and Enable it. */ + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT, + (Xil_ExceptionHandler)profile_intr_handler,NULL); + XTime_PITSetInterval( timer_clk_ticks ) ; + XTime_PITEnableAutoReload() ; + return 0; +} +#endif + + +/* -------------------------------------------------------------------- +* PowerPC Timer Initialization functions. +* For PowerPC, PIT and opb_timer can be used for Profiling. This +* is selected by the user in standalone BSP +* +*-------------------------------------------------------------------- */ +s32 powerpc405_init() +{ + Xil_ExceptionInit() ; + Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ; + + /* Initialize the Timer. + * 1. If PowerPC PIT Timer has to be used, initialize PIT timer. + * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */ +#ifdef PPC_PIT_INTERRUPT + ppc_pit_init(); +#else +#ifdef TIMER_CONNECT_INTC + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, + (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL); + XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, + (XInterruptHandler)profile_intr_handler,NULL); +#else + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, + (Xil_ExceptionHandler)profile_intr_handler,NULL); +#endif + /* Initialize the timer with Timer Ticks */ + opb_timer_init() ; +#endif + + /* Enable Interrupts in the System, if Profile Timer is the only Interrupt + * in the System. */ +#ifdef ENABLE_SYS_INTR +#ifdef PPC_PIT_INTERRUPT + XTime_PITEnableInterrupt() ; +#elif TIMER_CONNECT_INTC + XIntc_MasterEnable( INTC_BASEADDR ); + XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); + XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); +#endif + Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ; +#endif + return 0; +} + +#endif /* PROC_PPC */ + + + +/*-------------------------------------------------------------------- + * PowerPC440 Target - Timer related functions + * -------------------------------------------------------------------- */ +#ifdef PROC_PPC440 + + +/*-------------------------------------------------------------------- + * PowerPC DEC Timer Init. + * Defined only if DEC Timer is used for Profiling + * + *-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +s32 ppc_dec_init( void ) +{ + /* 1. Register Profile_intr_handler as Interrupt handler */ + /* 2. Set DEC Timer Interrupt and Enable it. */ + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT, + (Xil_ExceptionHandler)profile_intr_handler,NULL); + XTime_DECSetInterval( timer_clk_ticks ) ; + XTime_DECEnableAutoReload() ; + return 0; +} +#endif + + +/*-------------------------------------------------------------------- + * PowerPC Timer Initialization functions. + * For PowerPC, DEC and opb_timer can be used for Profiling. This + * is selected by the user in standalone BSP + * + *-------------------------------------------------------------------- */ +s32 powerpc405_init(void) +{ + Xil_ExceptionInit(); + Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ; + + /* Initialize the Timer. + * 1. If PowerPC DEC Timer has to be used, initialize DEC timer. + * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */ +#ifdef PPC_PIT_INTERRUPT + ppc_dec_init(); +#else +#ifdef TIMER_CONNECT_INTC + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT, + (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL); + + XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, + (XInterruptHandler)profile_intr_handler,NULL); +#else + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, + (Xil_ExceptionHandler)profile_intr_handler,NULL); + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, + (Xil_ExceptionHandler)profile_intr_handler,NULL); +#endif + /* Initialize the timer with Timer Ticks */ + opb_timer_init() ; +#endif + + /* Enable Interrupts in the System, if Profile Timer is the only Interrupt + * in the System. */ +#ifdef ENABLE_SYS_INTR +#ifdef PPC_PIT_INTERRUPT + XTime_DECEnableInterrupt() ; +#elif TIMER_CONNECT_INTC + XIntc_MasterEnable( INTC_BASEADDR ); + XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); + XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); +#endif + Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ; +#endif + return 0; +} + +#endif /* PROC_PPC440 */ + +/* -------------------------------------------------------------------- + * opb_timer Initialization for PowerPC and MicroBlaze. This function + * is not needed if DEC timer is used in PowerPC + * + *-------------------------------------------------------------------- */ +/* #ifndef PPC_PIT_INTERRUPT */ +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +s32 opb_timer_init( void ) +{ + /* set the number of cycles the timer counts before interrupting */ + XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks); + + /* reset the timers, and clear interrupts */ + XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, + (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK ); + + /* start the timers */ + XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK + | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK); + return 0; +} +#endif + + +/*-------------------------------------------------------------------- + * MicroBlaze Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_MICROBLAZE + +/* -------------------------------------------------------------------- + * Initialize the Profile Timer for MicroBlaze Target. + * For MicroBlaze, opb_timer is used. The opb_timer can be directly + * connected to MicroBlaze or connected through Interrupt Controller. + * + *-------------------------------------------------------------------- */ +s32 microblaze_init(void) +{ + /* Register profile_intr_handler + * 1. If timer is connected to Interrupt Controller, register the handler + * to Interrupt Controllers vector table. + * 2. If timer is directly connected to MicroBlaze, register the handler + * as Interrupt handler */ + Xil_ExceptionInit(); + +#ifdef TIMER_CONNECT_INTC + XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, + (XInterruptHandler)profile_intr_handler,NULL); +#else + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)profile_intr_handler, + NULL) ; +#endif + + /* Initialize the timer with Timer Ticks */ + (void)opb_timer_init() ; + + /* Enable Interrupts in the System, if Profile Timer is the only Interrupt + * in the System. */ +#ifdef ENABLE_SYS_INTR +#ifdef TIMER_CONNECT_INTC + XIntc_MasterEnable((u32)INTC_BASEADDR ); + XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); + XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL); +#endif + +#endif + + Xil_ExceptionEnable(); + + return 0; + +} + +#endif /* PROC_MICROBLAZE */ + + + +/* -------------------------------------------------------------------- + * Cortex A9 Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_CORTEXA9 + +/* -------------------------------------------------------------------- + * Initialize the Profile Timer for Cortex A9 Target. + * The scu private timer is connected to the Scu GIC controller. + * + *-------------------------------------------------------------------- */ +s32 scu_timer_init( void ) +{ + /* set the number of cycles the timer counts before interrupting + * scu timer runs at half the cpu clock */ + XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U); + + /* clear any pending interrupts */ + XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U); + + /* enable interrupts, auto-reload mode and start the timer */ + XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK | + XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK); + + return 0; +} + +s32 cortexa9_init(void) +{ + + Xil_ExceptionInit(); + + XScuGic_DeviceInitialize(0); + + /* + * Connect the interrupt controller interrupt handler to the hardware + * interrupt handling logic in the processor. + */ + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, + (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler, + NULL); + + /* + * Connect the device driver handler that will be called when an + * interrupt for the device occurs, the handler defined above performs + * the specific interrupt processing for the device. + */ + XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR, + PROFILE_TIMER_INTR_ID, + (Xil_ExceptionHandler)profile_intr_handler, + NULL); + + /* + * Enable the interrupt for scu timer. + */ + XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID); + + /* + * Enable interrupts in the Processor. + */ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ); + + /* + * Initialize the timer with Timer Ticks + */ + (void)scu_timer_init() ; + + Xil_ExceptionEnable(); + + return 0; +} + +#endif /* PROC_CORTEXA9 */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_timer_hw.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.h similarity index 51% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_timer_hw.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.h index ac8968fcf..2cee66b09 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_timer_hw.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.h @@ -1,7 +1,6 @@ -// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -36,8 +35,8 @@ * ******************************************************************************/ -#ifndef _PROFILE_TIMER_HW_H -#define _PROFILE_TIMER_HW_H +#ifndef PROFILE_TIMER_HW_H +#define PROFILE_TIMER_HW_H #include "profile.h" @@ -52,26 +51,26 @@ #endif #ifdef PROC_PPC -#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; +#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; } #define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; } #else #define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); -#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); } +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); } #endif #define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ - ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ - (RegOffset)), (ValueToWrite)) + ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \ + (u32)(RegOffset)), (u32)(ValueToWrite)) #define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ - ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset)) + ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset)) #define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ (RegisterValue)) #define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \ - ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) + ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) @@ -88,7 +87,7 @@ extern "C" { #ifdef TIMER_CONNECT_INTC #include "xintc_l.h" #include "xintc.h" -#endif // TIMER_CONNECT_INTC +#endif /* TIMER_CONNECT_INTC */ #if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) #include "xtmrctr_l.h" @@ -99,15 +98,15 @@ extern "C" { #include "xscugic.h" #endif -extern unsigned int timer_clk_ticks ; +extern u32 timer_clk_ticks ; -//-------------------------------------------------------------------- -// PowerPC Target - Timer related functions -//-------------------------------------------------------------------- +/*-------------------------------------------------------------------- + * PowerPC Target - Timer related functions + *-------------------------------------------------------------------- */ #ifdef PROC_PPC #ifdef PPC_PIT_INTERRUPT -unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG +u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */ #endif #ifdef PROC_PPC440 @@ -117,21 +116,21 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG #define XEXC_ID_PIT_INT XEXC_ID_DEC_INT #endif -//-------------------------------------------------------------------- -// Disable the Timer - During Profiling -// -// For PIT Timer - -// 1. XTime_PITDisableInterrupt() ; -// 2. Store the remaining timer clk tick -// 3. Stop the PIT Timer -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Disable the Timer - During Profiling + * + * For PIT Timer - + * 1. XTime_PITDisableInterrupt() ; + * 2. Store the remaining timer clk tick + * 3. Stop the PIT Timer + *-------------------------------------------------------------------- */ #ifdef PPC_PIT_INTERRUPT #define disable_timer() \ { \ - unsigned long val; \ + u32 val; \ val=mfspr(XREG_SPR_TCR); \ - mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \ + mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \ timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \ mtspr(XREG_SPR_PIT, 0); \ } @@ -140,24 +139,24 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG { \ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \ + tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ } #endif -//-------------------------------------------------------------------- -// Enable the Timer -// -// For PIT Timer - -// 1. Load the remaining timer clk ticks -// 2. XTime_PITEnableInterrupt() ; -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Enable the Timer + * + * For PIT Timer - + * 1. Load the remaining timer clk ticks + * 2. XTime_PITEnableInterrupt() ; + *-------------------------------------------------------------------- */ #ifdef PPC_PIT_INTERRUPT #define enable_timer() \ { \ - unsigned long val; \ + u32 val; \ val=mfspr(XREG_SPR_TCR); \ mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \ mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \ @@ -174,18 +173,18 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -// For PIT Timer - -// 1. Load the timer clk ticks -// 2. Enable AutoReload and Interrupt -// 3. Clear PIT Timer Status bits -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + * For PIT Timer - + * 1. Load the timer clk ticks + * 2. Enable AutoReload and Interrupt + * 3. Clear PIT Timer Status bits + *-------------------------------------------------------------------- */ #ifdef PPC_PIT_INTERRUPT #define timer_ack() \ { \ - unsigned long val; \ + u32 val; \ mtspr(XREG_SPR_PIT, timer_clk_ticks); \ mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \ val=mfspr(XREG_SPR_TCR); \ @@ -194,109 +193,116 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG #else #define timer_ack() \ { \ - unsigned int csr; \ + u32 csr; \ csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ } #endif -//-------------------------------------------------------------------- -#endif // PROC_PPC -//-------------------------------------------------------------------- +/*-------------------------------------------------------------------- */ +#endif /* PROC_PPC */ +/* -------------------------------------------------------------------- */ -//-------------------------------------------------------------------- -// MicroBlaze Target - Timer related functions -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * MicroBlaze Target - Timer related functions + *-------------------------------------------------------------------- */ #ifdef PROC_MICROBLAZE -//-------------------------------------------------------------------- -// Disable the Timer during Call-Graph Data collection -// -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ #define disable_timer() \ { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(Addr); \ + tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \ + u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \ + OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + OutAddr += (u32)XTC_TCSR_OFFSET; \ + ProfIo_Out32(OutAddr, (u32)tmp_v); \ } -//-------------------------------------------------------------------- -// Enable the Timer after Call-Graph Data collection -// -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ #define enable_timer() \ { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = (u32)ProfIo_In32(Addr); \ + tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \ } -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ #define timer_ack() \ { \ - unsigned int csr; \ - csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ - ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ + u32 csr; \ + csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \ + ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \ } -//-------------------------------------------------------------------- -#endif // PROC_MICROBLAZE -//-------------------------------------------------------------------- +/*-------------------------------------------------------------------- */ +#endif /* PROC_MICROBLAZE */ +/*-------------------------------------------------------------------- */ -//-------------------------------------------------------------------- -// Cortex A9 Target - Timer related functions -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Cortex A9 Target - Timer related functions + *-------------------------------------------------------------------- */ #ifdef PROC_CORTEXA9 -//-------------------------------------------------------------------- -// Disable the Timer during Call-Graph Data collection -// -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ #define disable_timer() \ { \ u32 Reg; \ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ - Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\ + Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ -} \ +} -//-------------------------------------------------------------------- -// Enable the Timer after Call-Graph Data collection -// -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ #define enable_timer() \ { \ u32 Reg; \ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ -} \ - - -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -//-------------------------------------------------------------------- -#define timer_ack() \ -{ \ - Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \ - XSCUTIMER_ISR_EVENT_FLAG_MASK);\ } -//-------------------------------------------------------------------- -#endif // PROC_CORTEXA9 -//-------------------------------------------------------------------- + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ +#define timer_ack() \ +{ \ + Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \ + (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\ +} + +/*-------------------------------------------------------------------- */ +#endif /* PROC_CORTEXA9 */ +/*-------------------------------------------------------------------- */ #ifdef __cplusplus diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/dummy.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/dummy.S similarity index 89% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/dummy.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/dummy.S index d0d81532b..d28646d6d 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/dummy.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/dummy.S @@ -1,7 +1,6 @@ -// $Id: dummy.S,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,32 +33,32 @@ .globl dummy_f #ifdef PROC_MICROBLAZE - .text + .text .align 2 .ent dummy_f dummy_f: nop - .end dummy_f + .end dummy_f #endif -#ifdef PROC_PPC +#ifdef PROC_PPC .section .text .align 2 .type dummy_f@function - -dummy_f: + +dummy_f: b dummy_f - + #endif -#ifdef PROC_CORTEXA9 +#ifdef PROC_CORTEXA9 .section .text .align 2 .type dummy_f, %function - -dummy_f: + +dummy_f: b dummy_f - + #endif diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/mblaze_nt_types.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/mblaze_nt_types.h similarity index 93% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/mblaze_nt_types.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/mblaze_nt_types.h index 013a3ba1c..7096a92d8 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/mblaze_nt_types.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/mblaze_nt_types.h @@ -1,7 +1,6 @@ -// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile.h similarity index 78% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile.h index 481798e4a..4cb07a7d3 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile.h @@ -1,7 +1,6 @@ -// $Id: profile.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,10 +30,11 @@ * ******************************************************************************/ -#ifndef _PROFILE_H -#define _PROFILE_H 1 +#ifndef PROFILE_H +#define PROFILE_H 1 #include +#include "xil_types.h" #include "profile_config.h" #ifdef PROC_MICROBLAZE @@ -47,8 +47,9 @@ extern "C" { void _system_init( void ) ; void _system_clean( void ) ; -void mcount(unsigned long frompc, unsigned long selfpc); +void mcount(u32 frompc, u32 selfpc); void profile_intr_handler( void ) ; +void _profile_init( void ); @@ -59,19 +60,19 @@ void profile_intr_handler( void ) ; /* * histogram counters are unsigned shorts (according to the kernel). */ -#define HISTCOUNTER unsigned short +#define HISTCOUNTER u16 struct tostruct { - unsigned long selfpc; - long count; - short link; - unsigned short pad; + u32 selfpc; + s32 count; + s16 link; + u16 pad; }; struct fromstruct { - unsigned long frompc ; - short link ; - unsigned short pad ; + u32 frompc ; + s16 link ; + u16 pad ; } ; /* @@ -84,27 +85,27 @@ struct fromstruct { * The profiling data structures are housed in this structure. */ struct gmonparam { - long int state; + s32 state; - // Histogram Information - unsigned short *kcount; /* No. of bins in histogram */ - unsigned long kcountsize; /* Histogram samples */ + /* Histogram Information */ + u16 *kcount; /* No. of bins in histogram */ + u32 kcountsize; /* Histogram samples */ - // Call-graph Information + /* Call-graph Information */ struct fromstruct *froms; - unsigned long fromssize; + u32 fromssize; struct tostruct *tos; - unsigned long tossize; + u32 tossize; - // Initialization I/Ps - unsigned long lowpc; - unsigned long highpc; - unsigned long textsize; - //unsigned long cg_froms; - //unsigned long cg_tos; + /* Initialization I/Ps */ + u32 lowpc; + u32 highpc; + u32 textsize; + /* u32 cg_froms, */ + /* u32 cg_tos, */ }; extern struct gmonparam *_gmonparam; -extern int n_gmon_sections; +extern s32 n_gmon_sections; /* * Possible states of profiling. @@ -127,16 +128,4 @@ extern int n_gmon_sections; } #endif -#endif /* _PROFILE_H */ - - - - - - - - - - - - +#endif /* PROFILE_H */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_cg.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_cg.c similarity index 66% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_cg.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_cg.c index b871fc1f8..2539ce61a 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_cg.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_cg.c @@ -1,7 +1,6 @@ -// $Id: profile_cg.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -47,58 +46,69 @@ #include #include -extern struct gmonparam *_gmonparam; +#ifdef PROFILE_NO_FUNCPTR +s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc ); +#else +s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc ); +#endif + +/*extern struct gmonparam *_gmonparam, */ #ifdef PROFILE_NO_FUNCPTR -int searchpc( struct fromto_struct *cgtable, int cgtable_size, unsigned long frompc ) +s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc ) { - int index = 0 ; + s32 index = 0 ; while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){ index++ ; } - if( index == cgtable_size ) + if( index == cgtable_size ) { return -1 ; - else + } else { return index ; + } } #else -int searchpc( struct fromstruct *froms, int fromssize, unsigned long frompc ) +s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc ) { - int index = 0 ; + s32 index = 0 ; + s32 Status; while( (index < fromssize) && (froms[index].frompc != frompc) ){ index++ ; } - if( index == fromssize ) - return -1 ; - else - return index ; + if( index == fromssize ) { + Status = -1 ; + } else { + Status = index ; + } + return Status; } #endif /* PROFILE_NO_FUNCPTR */ -void mcount( unsigned long frompc, unsigned long selfpc ) +void mcount( u32 frompc, u32 selfpc ) { register struct gmonparam *p = NULL; - register long toindex, fromindex; - int j; + register s32 toindex, fromindex; + s32 j; disable_timer(); - //print("CG: "); putnum(frompc); print("->"); putnum(selfpc); print("\r\n"); - // check that frompcindex is a reasonable pc value. - // for example: signal catchers get called from the stack, - // not from text space. too bad. - // + /*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") , + * check that frompcindex is a reasonable pc value. + * for example: signal catchers get called from the stack, + * not from text space. too bad. + */ for(j = 0; j < n_gmon_sections; j++ ){ if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) { p = &_gmonparam[j]; break; } } - if( j == n_gmon_sections ) + if( j == n_gmon_sections ) { goto done; + } #ifdef PROFILE_NO_FUNCPTR fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ; @@ -112,51 +122,50 @@ void mcount( unsigned long frompc, unsigned long selfpc ) } p->cgtable[fromindex].count++ ; #else - fromindex = searchpc( p->froms, p->fromssize, frompc ) ; + fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ; if( fromindex == -1 ) { - fromindex = p->fromssize ; + fromindex = (s32)p->fromssize ; p->fromssize++ ; - //if( fromindex >= N_FROMS ) { - //print("Error : From PC table overflow\r\n") ; - //goto overflow ; - //} + /*if( fromindex >= N_FROMS ) { + * print("Error : From PC table overflow\r\n") + * goto overflow + *}*/ p->froms[fromindex].frompc = frompc ; p->froms[fromindex].link = -1 ; }else { - toindex = p->froms[fromindex].link ; + toindex = ((s32)(p->froms[fromindex].link)); while(toindex != -1) { - toindex = (p->tossize - toindex)-1 ; + toindex = (((s32)p->tossize) - toindex)-1 ; if( p->tos[toindex].selfpc == selfpc ) { p->tos[toindex].count++ ; goto done ; } - toindex = p->tos[toindex].link ; + toindex = ((s32)(p->tos[toindex].link)) ; } } - //if( toindex == -1 ) { + /*if( toindex == -1 ) { */ p->tos-- ; p->tossize++ ; - //if( toindex >= N_TOS ) { - //print("Error : To PC table overflow\r\n") ; - //goto overflow ; - //} + /* if( toindex >= N_TOS ) { + * print("Error : To PC table overflow\r\n") + * goto overflow + *} */ p->tos[0].selfpc = selfpc ; p->tos[0].count = 1 ; p->tos[0].link = p->froms[fromindex].link ; - p->froms[fromindex].link = p->tossize-1 ; + p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1); #endif done: p->state = GMON_PROF_ON; - goto enable_timer ; - //overflow: - p->state = GMON_PROF_ERROR; - enable_timer: + goto enable_timer_label ; + /* overflow: */ + /*p->state = GMON_PROF_ERROR */ + enable_timer_label: enable_timer(); return ; } #endif /* PROFILE_NO_GRAPH */ - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_config.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_config.h similarity index 85% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_config.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_config.h index b80334dc0..550c60b44 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_config.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_config.h @@ -1,7 +1,6 @@ -// $Id: profile_config.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,14 +34,14 @@ #ifndef _PROFILE_CONFIG_H #define _PROFILE_CONFIG_H -#define BINSIZE 4 -#define SAMPLE_FREQ_HZ 100000 -#define TIMER_CLK_TICKS 1000 +#define BINSIZE 4U +#define SAMPLE_FREQ_HZ 100000U +#define TIMER_CLK_TICKS 1000U #define PROFILE_NO_FUNCPTR_FLAG 0 -#define PROFILE_TIMER_BASEADDR 0x00608000 -#define PROFILE_TIMER_INTR_ID 0 +#define PROFILE_TIMER_BASEADDR 0x00608000U +#define PROFILE_TIMER_INTR_ID 0U #define TIMER_CONNECT_INTC diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_hist.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_hist.c similarity index 82% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_hist.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_hist.c index 3cd0cbc07..c8ee9cef9 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_hist.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_hist.c @@ -1,7 +1,6 @@ -// $Id: profile_hist.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -45,29 +44,28 @@ #include "xil_types.h" -extern int binsize ; +extern u32 binsize ; u32 prof_pc ; void profile_intr_handler( void ) { - int j; + s32 j; #ifdef PROC_MICROBLAZE asm( "swi r14, r0, prof_pc" ) ; #elif defined PROC_PPC prof_pc = mfspr(SPR_SRR0); #else - // for cortexa9, lr is saved in asm interrupt handler + /* for cortexa9, lr is saved in asm interrupt handler */ #endif - //print("PC: "); putnum(prof_pc); print("\r\n"); + /* print("PC: "), putnum(prof_pc), print("\r\n"), */ for(j = 0; j < n_gmon_sections; j++ ){ - if((prof_pc >= _gmonparam[j].lowpc) && (prof_pc < _gmonparam[j].highpc)) { - _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/(4 * binsize)]++; + if((prof_pc >= ((u32)_gmonparam[j].lowpc)) && (prof_pc < ((u32)_gmonparam[j].highpc))) { + _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/((u32)4 * binsize)]++; break; } } - // Ack the Timer Interrupt + /* Ack the Timer Interrupt */ timer_ack(); } - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_mcount_arm.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_mcount_arm.S similarity index 93% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_mcount_arm.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_mcount_arm.S index 2af103af9..e62cec0bd 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_mcount_arm.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_mcount_arm.S @@ -1,7 +1,6 @@ -// $Id: profile_mcount_arm.S,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_mcount_mb.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_mcount_mb.S similarity index 89% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_mcount_mb.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_mcount_mb.S index 0a5d8c9ec..bea2726b6 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_mcount_mb.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_mcount_mb.S @@ -1,7 +1,6 @@ -// $Id: profile_mcount_mb.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,13 +30,13 @@ * ******************************************************************************/ - .globl _mcount - .text + .globl _mcount + .text .align 2 .ent _mcount #ifndef PROFILE_NO_GRAPH - + _mcount: addi r1, r1, -48 swi r11, r1, 44 @@ -49,12 +48,12 @@ _mcount: swi r9, r1, 20 swi r10, r1, 16 swi r15, r1, 12 - add r6, r0, r15 + add r5, r0, r15 brlid r15, mcount - lwi r5, r1, 48 + add r6, r0, r16 lwi r11, r1, 44 - lwi r12, r1, 40 + lwi r12, r1, 40 lwi r5, r1, 36 lwi r6, r1, 32 lwi r7, r1, 28 @@ -66,5 +65,5 @@ _mcount: addi r1, r1, 48 #endif /* PROFILE_NO_GRAPH */ - - .end _mcount + + .end _mcount diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_mcount_ppc.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_mcount_ppc.S similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_mcount_ppc.S rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_mcount_ppc.S index 6bc83a779..39bb92f77 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/profile_mcount_ppc.S +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/profile_mcount_ppc.S @@ -1,7 +1,6 @@ -// $Id: profile_mcount_ppc.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,9 +31,9 @@ ******************************************************************************/ .globl _mcount - - #define _MCOUNT_STACK_FRAME 48 - .section .text + + #define _MCOUNT_STACK_FRAME 48 + .section .text .align 2 .type _mcount@function @@ -54,7 +53,7 @@ _mcount: mflr 4 stw 4, (_MCOUNT_STACK_FRAME+4)(1) lwz 3, (_MCOUNT_STACK_FRAME)(1) - lwz 3, 4(3) + lwz 3, 4(3) bl mcount lwz 4, (_MCOUNT_STACK_FRAME+4)(1) mtlr 4 @@ -67,7 +66,6 @@ _mcount: lwz 6, 20(1) lwz 5, 16(1) lwz 4, 12(1) - lwz 3, 8(1) + lwz 3, 8(1) addi 1,1, _MCOUNT_STACK_FRAME blr - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/pvr.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/pvr.c similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/pvr.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/pvr.c index da65d0798..ca09703ac 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/pvr.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/pvr.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/pvr.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/pvr.h similarity index 99% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/pvr.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/pvr.h index 28825724a..5e8dc897c 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/pvr.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/pvr.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -274,4 +274,3 @@ int microblaze_get_pvr (pvr_t *pvr); } #endif #endif /* _PVR_H */ - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xbasic_types.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xbasic_types.h similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xbasic_types.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xbasic_types.h index b2dd2cd87..787212ca7 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xbasic_types.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xbasic_types.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -89,15 +89,15 @@ typedef Xuint8 u8; #endif #ifndef TRUE -# define TRUE 1 +# define TRUE 1U #endif #ifndef FALSE -# define FALSE 0 +# define FALSE 0U #endif #ifndef NULL -#define NULL 0 +#define NULL 0U #endif /* diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xdebug.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xdebug.h new file mode 100644 index 000000000..650946bd0 --- /dev/null +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xdebug.h @@ -0,0 +1,32 @@ +#ifndef XDEBUG /* prevent circular inclusions */ +#define XDEBUG /* by using protection macros */ + +#if defined(DEBUG) && !defined(NDEBUG) + +#ifndef XDEBUG_WARNING +#define XDEBUG_WARNING +#warning DEBUG is enabled +#endif + +int printf(const char *format, ...); + +#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */ +#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */ +#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */ + +#define xdbg_current_types (XDBG_DEBUG_GENERAL) + +#define xdbg_stmnt(x) x + +#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) + + +#else /* defined(DEBUG) && !defined(NDEBUG) */ + +#define xdbg_stmnt(x) + +#define xdbg_printf(...) + +#endif /* defined(DEBUG) && !defined(NDEBUG) */ + +#endif /* XDEBUG */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xenv.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xenv.h similarity index 98% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xenv.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xenv.h index eebf8e328..3d97bebd4 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xenv.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xenv.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -185,4 +185,3 @@ extern "C" { #endif #endif /* end of protection macro */ - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xenv_standalone.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xenv_standalone.h similarity index 95% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xenv_standalone.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xenv_standalone.h index 271649c4b..f18601874 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xenv_standalone.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xenv_standalone.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -66,6 +66,8 @@ #ifndef XENV_STANDALONE_H #define XENV_STANDALONE_H +#include "xil_types.h" + #ifdef __cplusplus extern "C" { #endif @@ -149,7 +151,7 @@ extern "C" { *****************************************************************************/ #define XENV_MEM_FILL(DestPtr, Data, Bytes) \ - memset((void *) DestPtr, (int) Data, (size_t) Bytes) + memset((void *) DestPtr, (s32) Data, (size_t) Bytes) @@ -163,7 +165,7 @@ extern "C" { * A structure that contains a time stamp used by other time stamp macros * defined below. This structure is processor dependent. */ -typedef int XENV_TIME_STAMP; +typedef s32 XENV_TIME_STAMP; /*****************************************************************************/ /** @@ -278,16 +280,16 @@ typedef int XENV_TIME_STAMP; # define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache() # define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ - microblaze_invalidate_dcache_range((int)(Addr), (int)(Len)) + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) #if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) # define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache() # define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - microblaze_flush_dcache_range((int)(Addr), (int)(Len)) + microblaze_flush_dcache_range((s32)(Addr), (s32)(Len)) #else # define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache() # define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - microblaze_invalidate_dcache_range((int)(Addr), (int)(Len)) + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) #endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/ #else @@ -307,7 +309,7 @@ typedef int XENV_TIME_STAMP; # define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache() # define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ - microblaze_invalidate_icache_range((int)(Addr), (int)(Len)) + microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len)) #else # define XCACHE_ENABLE_ICACHE() @@ -340,10 +342,10 @@ typedef int XENV_TIME_STAMP; #define XCACHE_DISABLE_ICACHE() XCache_DisableICache() #define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ - XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len)) + XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len)) #define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len)) + XCache_FlushDCacheRange((u32)(Addr), (u32)(Len)) #define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache() @@ -364,4 +366,3 @@ typedef int XENV_TIME_STAMP; #endif #endif /* #ifndef XENV_STANDALONE_H */ - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_assert.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_assert.c similarity index 95% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_assert.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_assert.c index 8eba39371..42db07deb 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_assert.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_assert.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -64,14 +64,14 @@ * sets this variable such that a driver can evaluate this variable * to determine if an assert occurred. */ -unsigned int Xil_AssertStatus; +u32 Xil_AssertStatus; /** * This variable allows the assert functionality to be changed for testing * such that it does not wait infinitely. Use the debugger to disable the * waiting during testing of asserts. */ -int Xil_AssertWait = TRUE; +/*s32 Xil_AssertWait = 1*/ /* The callback function to be invoked when an assert is taken */ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; @@ -93,8 +93,9 @@ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; * @note None. * ******************************************************************************/ -void Xil_Assert(const char *File, int Line) +void Xil_Assert(const char8 *File, s32 Line) { + s32 Xil_AssertWait = 1; /* if the callback has been set then invoke it */ if (Xil_AssertCallbackRoutine != 0) { (*Xil_AssertCallbackRoutine)(File, Line); @@ -103,7 +104,7 @@ void Xil_Assert(const char *File, int Line) /* if specified, wait indefinitely such that the assert will show up * in testing */ - while (Xil_AssertWait) { + while (Xil_AssertWait != 0) { } } @@ -141,6 +142,5 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine) ******************************************************************************/ void XNullHandler(void *NullParameter) { - (void) NullParameter; + (void *) NullParameter; } - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_assert.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_assert.h similarity index 93% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_assert.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_assert.h index 47347ad2b..7034bc9ad 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_assert.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_assert.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -49,6 +49,8 @@ #ifndef XIL_ASSERT_H /* prevent circular inclusions */ #define XIL_ASSERT_H /* by using protection macros */ +#include "xil_types.h" + #ifdef __cplusplus extern "C" { #endif @@ -59,19 +61,19 @@ extern "C" { /************************** Constant Definitions *****************************/ -#define XIL_ASSERT_NONE 0 -#define XIL_ASSERT_OCCURRED 1 +#define XIL_ASSERT_NONE 0U +#define XIL_ASSERT_OCCURRED 1U #define XNULL NULL -extern unsigned int Xil_AssertStatus; -extern void Xil_Assert(const char *, int); +extern u32 Xil_AssertStatus; +extern void Xil_Assert(const char8 *File, s32 Line); void XNullHandler(void *NullParameter); /** * This data type defines a callback to be invoked when an * assert occurs. The callback is invoked only when asserts are enabled */ -typedef void (*Xil_AssertCallback) (const char *File, int Line); +typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); /***************** Macros (Inline Functions) Definitions *********************/ @@ -83,7 +85,7 @@ typedef void (*Xil_AssertCallback) (const char *File, int Line); * (void). This in conjunction with the Xil_AssertWait boolean can be used to * accomodate tests so that asserts which fail allow execution to continue. * -* @param expression is the expression to evaluate. If it evaluates to +* @param Expression is the expression to evaluate. If it evaluates to * false, the assert occurs. * * @return Returns void unless the Xil_AssertWait variable is true, in which @@ -109,7 +111,7 @@ typedef void (*Xil_AssertCallback) (const char *File, int Line); * conjunction with the Xil_AssertWait boolean can be used to accomodate tests * so that asserts which fail allow execution to continue. * -* @param expression is the expression to evaluate. If it evaluates to false, +* @param Expression is the expression to evaluate. If it evaluates to false, * the assert occurs. * * @return Returns 0 unless the Xil_AssertWait variable is true, in which diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_cache.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_cache.c similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_cache.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_cache.c index 4a306c88a..8024b7fdc 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_cache.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_cache.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -92,5 +92,3 @@ void Xil_ICacheDisable(void) Xil_ICacheInvalidate(); Xil_L1ICacheDisable(); } - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_cache.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_cache.h similarity index 95% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_cache.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_cache.h index fb182730e..aa4f79650 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_cache.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_cache.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -133,7 +133,7 @@ extern "C" { * Processor must be in real mode. ****************************************************************************/ #define Xil_L1DCacheInvalidateRange(Addr, Len) \ - microblaze_invalidate_dcache_range(Addr, Len) + microblaze_invalidate_dcache_range((Addr), (Len)) /****************************************************************************/ /** @@ -153,7 +153,7 @@ extern "C" { * Processor must be in real mode. ****************************************************************************/ #define Xil_L2CacheInvalidateRange(Addr, Len) \ - microblaze_invalidate_cache_ext_range(Addr, Len) + microblaze_invalidate_cache_ext_range((Addr), (Len)) /****************************************************************************/ /** @@ -170,10 +170,10 @@ extern "C" { ****************************************************************************/ #if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) # define Xil_L1DCacheFlushRange(Addr, Len) \ - microblaze_flush_dcache_range(Addr, Len) + microblaze_flush_dcache_range((Addr), (Len)) #else # define Xil_L1DCacheFlushRange(Addr, Len) \ - microblaze_invalidate_dcache_range(Addr, Len) + microblaze_invalidate_dcache_range((Addr), (Len)) #endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */ /****************************************************************************/ @@ -190,7 +190,7 @@ extern "C" { * ****************************************************************************/ #define Xil_L2CacheFlushRange(Addr, Len) \ - microblaze_flush_cache_ext_range(Addr, Len) + microblaze_flush_cache_ext_range((Addr), (Len)) /****************************************************************************/ /** @@ -232,7 +232,7 @@ extern "C" { * ****************************************************************************/ #define Xil_L1ICacheInvalidateRange(Addr, Len) \ - microblaze_invalidate_icache_range(Addr, Len) + microblaze_invalidate_icache_range((Addr), (Len)) /****************************************************************************/ /** @@ -360,8 +360,8 @@ extern "C" { * ****************************************************************************/ #define Xil_DCacheInvalidateRange(Addr, Len) \ - Xil_L2CacheInvalidateRange(Addr, Len); \ - Xil_L1DCacheInvalidateRange(Addr, Len); + Xil_L2CacheInvalidateRange((Addr), (Len)); \ + Xil_L1DCacheInvalidateRange((Addr), (Len)); /**************************************************************************** @@ -395,8 +395,8 @@ extern "C" { * ****************************************************************************/ #define Xil_DCacheFlushRange(Addr, Len) \ - Xil_L2CacheFlushRange(Addr, Len); \ - Xil_L1DCacheFlushRange(Addr, Len); + Xil_L2CacheFlushRange((Addr), (Len)); \ + Xil_L1DCacheFlushRange((Addr), (Len)); /**************************************************************************** @@ -432,8 +432,8 @@ extern "C" { * ****************************************************************************/ #define Xil_ICacheInvalidateRange(Addr, Len) \ - Xil_L2CacheInvalidateRange(Addr, Len); \ - Xil_L1ICacheInvalidateRange(Addr, Len); + Xil_L2CacheInvalidateRange((Addr), (Len)); \ + Xil_L1ICacheInvalidateRange((Addr), (Len)); void Xil_DCacheDisable(void); void Xil_ICacheDisable(void); diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_cache_vxworks.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_cache_vxworks.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h index 788883878..6e8cfa75f 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_cache_vxworks.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -91,4 +91,3 @@ extern "C" { #endif #endif - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_exception.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_exception.c similarity index 95% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_exception.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_exception.c index 7fa90d4bc..2c1c47342 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_exception.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_exception.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -55,6 +55,7 @@ #include "xil_exception.h" #include "microblaze_exceptions_g.h" +#include "microblaze_interrupts_i.h" #ifdef __cplusplus extern "C" { @@ -75,10 +76,10 @@ typedef struct { void *CallBackRef; } MB_ExceptionVectorTableEntry; -typedef struct { - Xil_ExceptionHandler Handler; - void *CallBackRef; -} MB_InterruptVectorTableEntry; +/*typedef struct { + Xil_ExceptionHandler Handler, + void *CallBackRef, +} MB_InterruptVectorTableEntry, */ #ifdef __cplusplus } @@ -86,7 +87,7 @@ typedef struct { /************************** Variable Definitions *****************************/ -extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[]; +extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[XIL_EXCEPTION_ID_INT]; extern MB_InterruptVectorTableEntry MB_InterruptVectorTable; /** @@ -109,7 +110,7 @@ extern MB_InterruptVectorTableEntry MB_InterruptVectorTable; *****************************************************************************/ static void Xil_ExceptionNullHandler(void *Data) { - (void) Data; + (void *) Data; } /****************************************************************************/ @@ -241,4 +242,3 @@ void Xil_ExceptionRemoveHandler(u32 Id) #endif } } - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_exception.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_exception.h similarity index 83% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_exception.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_exception.h index 877d4163d..79418dd01 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_exception.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_exception.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -68,24 +68,24 @@ extern "C" { * These constants are specific to Microblaze processor. */ -#define XIL_EXCEPTION_ID_FIRST 0 -#define XIL_EXCEPTION_ID_FSL 0 -#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1 -#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2 -#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3 -#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3 -#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4 -#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4 -#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5 -#define XIL_EXCEPTION_ID_FPU 6 -#define XIL_EXCEPTION_ID_STACK_VIOLATION 7 -#define XIL_EXCEPTION_ID_MMU 7 +#define XIL_EXCEPTION_ID_FIRST 0U +#define XIL_EXCEPTION_ID_FSL 0U +#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1U +#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2U +#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3U +#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3U +#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4U +#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4U +#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5U +#define XIL_EXCEPTION_ID_FPU 6U +#define XIL_EXCEPTION_ID_STACK_VIOLATION 7U +#define XIL_EXCEPTION_ID_MMU 7U #define XIL_EXCEPTION_ID_LAST XIL_EXCEPTION_ID_MMU /* * XIL_EXCEPTION_ID_INT is defined for all processors, but with different value. */ -#define XIL_EXCEPTION_ID_INT 16 /** +#define XIL_EXCEPTION_ID_INT 16U /** * exception ID for interrupt */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_hal.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_hal.h similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_hal.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_hal.h index 90626a350..d4434d07f 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_hal.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -59,4 +59,3 @@ #include "xil_types.h" #endif - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_io.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_io.c similarity index 88% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_io.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_io.c index e7951019d..a6fd5496e 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_io.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_io.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -44,6 +44,8 @@ * ----- ---- -------- ------------------------------------------------------- * 3.00a hbm 07/28/09 Initial release * 3.00a hbm 07/21/10 Added Xil_EndianSwap32/16, Xil_Htonl/s, Xil_Ntohl/s +* 5.4 sk 01/14/16 Changed xil_io() and xil_out() functions to static inline +* functions. * * * @@ -70,6 +72,7 @@ /************************** Function Prototypes ******************************/ +/***************** Macros (Inline Functions) and Functions Definitions *******/ /*****************************************************************************/ /** @@ -85,7 +88,7 @@ ******************************************************************************/ u16 Xil_EndianSwap16(u16 Data) { - return (u16) (((Data & 0xFF00) >> 8) | ((Data & 0x00FF) << 8)); + return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); } /*****************************************************************************/ @@ -107,17 +110,17 @@ u32 Xil_EndianSwap32(u32 Data) /* get each of the half words from the 32 bit word */ - LoWord = (u16) (Data & 0x0000FFFF); - HiWord = (u16) ((Data & 0xFFFF0000) >> 16); + LoWord = (u16) (Data & 0x0000FFFFU); + HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); /* byte swap each of the 16 bit half words */ - LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8)); - HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8)); + LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); + HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); /* swap the half words before returning the value */ - return (u32) ((LoWord << 16) | HiWord); + return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); } /*****************************************************************************/ @@ -140,9 +143,9 @@ u32 Xil_EndianSwap32(u32 Data) * ******************************************************************************/ #ifndef __LITTLE_ENDIAN__ -u16 Xil_In16LE(u32 Addr) +u16 Xil_In16LE(UINTPTR Addr) #else -u16 Xil_In16BE(u32 Addr) +u16 Xil_In16BE(UINTPTR Addr) #endif { u16 Value; @@ -172,9 +175,9 @@ u16 Xil_In16BE(u32 Addr) * ******************************************************************************/ #ifndef __LITTLE_ENDIAN__ -u32 Xil_In32LE(u32 Addr) +u32 Xil_In32LE(UINTPTR Addr) #else -u32 Xil_In32BE(u32 Addr) +u32 Xil_In32BE(UINTPTR Addr) #endif { u32 InValue; @@ -203,9 +206,9 @@ u32 Xil_In32BE(u32 Addr) * ******************************************************************************/ #ifndef __LITTLE_ENDIAN__ -void Xil_Out16LE(u32 Addr, u16 Value) +void Xil_Out16LE(UINTPTR Addr, u16 Value) #else -void Xil_Out16BE(u32 Addr, u16 Value) +void Xil_Out16BE(UINTPTR Addr, u16 Value) #endif { u16 OutValue; @@ -235,9 +238,9 @@ void Xil_Out16BE(u32 Addr, u16 Value) * ******************************************************************************/ #ifndef __LITTLE_ENDIAN__ -void Xil_Out32LE(u32 Addr, u32 Value) +void Xil_Out32LE(UINTPTR Addr, u32 Value) #else -void Xil_Out32BE(u32 Addr, u32 Value) +void Xil_Out32BE(UINTPTR Addr, u32 Value) #endif { u32 OutValue; diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_io.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_io.h similarity index 82% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_io.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_io.h index bc3020741..fa872b9b7 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_io.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_io.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -47,6 +47,8 @@ * 3.00a hbm 07/21/10 Added Xil_EndianSwap32/16, Xil_Htonl/s, Xil_Ntohl/s * 3.03a sdm 08/18/11 Added INST_SYNC and DATA_SYNC macros. * 3.07a asa 08/31/12 Added xil_printf.h include +* 5.4 sk 01/14/16 Changed xil_io() and xil_out() functions to static inline +* functions. * * * @@ -71,24 +73,18 @@ extern "C" { /************************** Constant Definitions *****************************/ -/**************************** Type Definitions *******************************/ +/**************************** Function Prototypes ****************************/ + +static inline u8 Xil_In8(UINTPTR Addr); +static inline u16 Xil_In16(UINTPTR Addr); +static inline u32 Xil_In32(UINTPTR Addr); + +static inline void Xil_Out8(UINTPTR Addr, u8 Value); +static inline void Xil_Out16(UINTPTR Addr, u16 Value); +static inline void Xil_Out32(UINTPTR Addr, u32 Value); /***************** Macros (Inline Functions) Definitions *********************/ -#if defined __GNUC__ -# define INST_SYNC mbar(0) -# define DATA_SYNC mbar(1) -#else -# define INST_SYNC -# define DATA_SYNC -#endif /* __GNUC__ */ - -/* - * The following macros allow optimized I/O operations for memory mapped I/O. - * It should be noted that macros cannot be used if synchronization of the I/O - * operation is needed as it will likely break some code. - */ - /*****************************************************************************/ /** * @@ -102,7 +98,9 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_In8(Addr) (*(volatile u8 *)(Addr)) +static inline u8 Xil_In8(UINTPTR Addr) { + return *(volatile u8 *)Addr; +} /*****************************************************************************/ /** @@ -117,13 +115,15 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_In16(Addr) (*(volatile u16 *)(Addr)) +static inline u16 Xil_In16(UINTPTR Addr) { + return *(volatile u16 *)Addr; +} /*****************************************************************************/ /** * -* Perform an input operation for a 32-bit memory location by reading from the -* specified address and returning the value read from that address. +* Performs an input operation for a 32-bit memory location by reading from the +* specified address and returning the Value read from that address. * * @param Addr contains the address to perform the input operation at. * @@ -132,7 +132,9 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_In32(Addr) (*(volatile u32 *)(Addr)) +static inline u32 Xil_In32(UINTPTR Addr) { + return *(volatile u32 *)Addr; +} /*****************************************************************************/ @@ -149,8 +151,10 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_Out8(Addr, Value) \ - (*(volatile u8 *)((Addr)) = (Value)) +static inline void Xil_Out8(UINTPTR Addr, u8 Value) { + volatile u8 *LocalAddr = (u8 *)Addr; + *LocalAddr = Value; +} /*****************************************************************************/ /** @@ -166,8 +170,10 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_Out16(Addr, Value) \ - (*(volatile u16 *)((Addr)) = (Value)) +static inline void Xil_Out16(UINTPTR Addr, u16 Value) { + volatile u16 *LocalAddr = (u16 *)Addr; + *LocalAddr = Value; +} /*****************************************************************************/ /** @@ -183,18 +189,35 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_Out32(Addr, Value) \ - (*(volatile u32 *)((Addr)) = (Value)) +static inline void Xil_Out32(UINTPTR Addr, u32 Value) { + volatile u32 *LocalAddr = (u32 *)Addr; + *LocalAddr = Value; +} + +#if defined __GNUC__ +# define INST_SYNC mbar(0) +# define DATA_SYNC mbar(1) +#else +# define INST_SYNC +# define DATA_SYNC +#endif /* __GNUC__ */ + +/* + * The following macros allow optimized I/O operations for memory mapped I/O. + * It should be noted that macros cannot be used if synchronization of the I/O + * operation is needed as it will likely break some code. + */ + extern u16 Xil_EndianSwap16(u16 Data); extern u32 Xil_EndianSwap32(u32 Data); #ifndef __LITTLE_ENDIAN__ -extern u16 Xil_In16LE(u32 Addr); -extern u32 Xil_In32LE(u32 Addr); -extern void Xil_Out16LE(u32 Addr, u16 Value); -extern void Xil_Out32LE(u32 Addr, u32 Value); +extern u16 Xil_In16LE(UINTPTR Addr); +extern u32 Xil_In32LE(UINTPTR Addr); +extern void Xil_Out16LE(UINTPTR Addr, u16 Value); +extern void Xil_Out32LE(UINTPTR Addr, u32 Value); /** * @@ -213,7 +236,7 @@ extern void Xil_Out32LE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_In16BE(Addr) Xil_In16(Addr) +#define Xil_In16BE(Addr) Xil_In16((Addr)) /** * @@ -233,7 +256,7 @@ extern void Xil_Out32LE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_In32BE(Addr) Xil_In32(Addr) +#define Xil_In32BE(Addr) Xil_In32((Addr)) /*****************************************************************************/ /** @@ -253,7 +276,7 @@ extern void Xil_Out32LE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Out16BE(Addr, Value) Xil_Out16(Addr, Value) +#define Xil_Out16BE(Addr, Value) Xil_Out16((Addr), (Value)) /*****************************************************************************/ /** @@ -272,7 +295,7 @@ extern void Xil_Out32LE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Out32BE(Addr, Value) Xil_Out32(Addr, Value) +#define Xil_Out32BE(Addr, Value) Xil_Out32((Addr), (Value)) #define Xil_Htonl(Data) (Data) #define Xil_Htons(Data) (Data) @@ -281,15 +304,15 @@ extern void Xil_Out32LE(u32 Addr, u32 Value); #else -extern u16 Xil_In16BE(u32 Addr); -extern u32 Xil_In32BE(u32 Addr); -extern void Xil_Out16BE(u32 Addr, u16 Value); -extern void Xil_Out32BE(u32 Addr, u32 Value); +extern u16 Xil_In16BE(UINTPTR Addr); +extern u32 Xil_In32BE(UINTPTR Addr); +extern void Xil_Out16BE(UINTPTR Addr, u16 Value); +extern void Xil_Out32BE(UINTPTR Addr, u32 Value); -#define Xil_In16LE(Addr) Xil_In16(Addr) -#define Xil_In32LE(Addr) Xil_In32(Addr) -#define Xil_Out16LE(Addr, Value) Xil_Out16(Addr, Value) -#define Xil_Out32LE(Addr, Value) Xil_Out32(Addr, Value) +#define Xil_In16LE(Addr) Xil_In16((Addr)) +#define Xil_In32LE(Addr) Xil_In32((Addr)) +#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value)) +#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value)) /*****************************************************************************/ @@ -304,7 +327,7 @@ extern void Xil_Out32BE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Htonl(Data) Xil_EndianSwap32(Data) +#define Xil_Htonl(Data) Xil_EndianSwap32((Data)) /*****************************************************************************/ /** @@ -318,7 +341,7 @@ extern void Xil_Out32BE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Htons(Data) Xil_EndianSwap16(Data) +#define Xil_Htons(Data) Xil_EndianSwap16((Data)) /*****************************************************************************/ /** @@ -332,7 +355,7 @@ extern void Xil_Out32BE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Ntohl(Data) Xil_EndianSwap32(Data) +#define Xil_Ntohl(Data) Xil_EndianSwap32((Data)) /*****************************************************************************/ /** @@ -346,7 +369,7 @@ extern void Xil_Out32BE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Ntohs(Data) Xil_EndianSwap16(Data) +#define Xil_Ntohs(Data) Xil_EndianSwap16((Data)) #endif diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_macroback.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_macroback.h similarity index 99% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_macroback.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_macroback.h index c3c468296..ebafde87d 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_macroback.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_macroback.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_misc_psreset_api.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_misc_psreset_api.c similarity index 88% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_misc_psreset_api.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_misc_psreset_api.c index 8f742ec5c..ee76cac06 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_misc_psreset_api.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_misc_psreset_api.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -45,6 +45,7 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.00b kpc 03/07/13 First release +* 5.4 pkp 16/11/15 Change the description for XOcm_Remap function * * ******************************************************************************/ @@ -76,15 +77,15 @@ * @note None. * ******************************************************************************/ -void XDdr_ResetHw() +void XDdr_ResetHw(void) { u32 RegVal; - /* Unlock the slcr register access lock */ + /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert and deassert the ddr softreset bit */ RegVal = Xil_In32(XDDRC_CTRL_BASEADDR); - RegVal &= ~XDDRPS_CTRL_RESET_MASK; + RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK); Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); RegVal |= XDDRPS_CTRL_RESET_MASK; Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); @@ -94,6 +95,7 @@ void XDdr_ResetHw() /*****************************************************************************/ /** * This function contains the implementation for remapping the ocm memory region +* to postbootrom state. * * @param N/A. * @@ -102,7 +104,7 @@ void XDdr_ResetHw() * @note None. * ******************************************************************************/ -void XOcm_Remap() +void XOcm_Remap(void) { u32 RegVal; @@ -110,7 +112,7 @@ void XOcm_Remap() Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Map the ocm region to postbootrom state */ RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR); - RegVal = (RegVal & ~XSLCR_OCM_CFG_HIADDR_MASK) | XSLCR_OCM_CFG_RESETVAL; + RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL; Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal); } @@ -131,11 +133,11 @@ void XSmc_ResetHw(u32 BaseAddress) /* Clear the interuupts */ RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET); - RegVal = RegVal | XSMC_MEMC_CLR_CONFIG_MASK; + RegVal |= XSMC_MEMC_CLR_CONFIG_MASK; Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal); /* Clear the idle counter registers */ - Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0); - Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0); + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U); + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U); /* Update the ecc registers with reset values */ Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET, XSMC_ECC_MEMCFG1_RESET_VAL); @@ -157,26 +159,26 @@ void XSmc_ResetHw(u32 BaseAddress) * @note None. * ******************************************************************************/ -void XSlcr_MioWriteResetValues() +void XSlcr_MioWriteResetValues(void) { u32 i; /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Update all the MIO registers with reset values */ - for (i=0; i<=1;i++); + for (i=0U; i<=1U;i++) { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_00_RESET_VAL); } - for (; i<=8;i++); + for (; i<=8U;i++) { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_02_RESET_VAL); } - for (; i<=53 ;i++); + for (; i<=53U ;i++) { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_00_RESET_VAL); } @@ -194,7 +196,7 @@ void XSlcr_MioWriteResetValues() * @note None. * ******************************************************************************/ -void XSlcr_PllWriteResetValues() +void XSlcr_PllWriteResetValues(void) { /* Unlock the slcr register access lock */ @@ -224,14 +226,14 @@ void XSlcr_PllWriteResetValues() * @note None. * ******************************************************************************/ -void XSlcr_DisableLevelShifters() +void XSlcr_DisableLevelShifters(void) { u32 RegVal; /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Disable the level shifters */ RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR); - RegVal = RegVal & ~XSLCR_LVL_SHFTR_EN_MASK; + RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK); Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal); } @@ -254,11 +256,11 @@ void XSlcr_OcmReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_OCM_RST_CTRL_VAL; + RegVal |= XSLCR_OCM_RST_CTRL_VAL; Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_OCM_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL); Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); } @@ -280,11 +282,11 @@ void XSlcr_EmacPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_GEM_RST_CTRL_VAL; + RegVal |= XSLCR_GEM_RST_CTRL_VAL; Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_GEM_RST_CTRL_VAL; + RegVal &= (u32)(~XSLCR_GEM_RST_CTRL_VAL); Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); } @@ -307,11 +309,11 @@ void XSlcr_UsbPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_USB_RST_CTRL_VAL; + RegVal |= XSLCR_USB_RST_CTRL_VAL; Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_USB_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL); Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -333,11 +335,11 @@ void XSlcr_QspiPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_QSPI_RST_CTRL_VAL; + RegVal |= XSLCR_QSPI_RST_CTRL_VAL; Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_QSPI_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL); Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -359,11 +361,11 @@ void XSlcr_SpiPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_SPI_RST_CTRL_VAL; + RegVal |= XSLCR_SPI_RST_CTRL_VAL; Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_SPI_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL); Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -384,11 +386,11 @@ void XSlcr_I2cPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_I2C_RST_CTRL_VAL; + RegVal |= XSLCR_I2C_RST_CTRL_VAL; Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_I2C_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL); Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -410,11 +412,11 @@ void XSlcr_UartPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_UART_RST_CTRL_VAL; + RegVal |= XSLCR_UART_RST_CTRL_VAL; Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_UART_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL); Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -436,11 +438,11 @@ void XSlcr_CanPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_CAN_RST_CTRL_VAL; + RegVal |= XSLCR_CAN_RST_CTRL_VAL; Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_CAN_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL); Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -461,11 +463,11 @@ void XSlcr_SmcPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_SMC_RST_CTRL_VAL; + RegVal |= XSLCR_SMC_RST_CTRL_VAL; Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_SMC_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL); Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -487,11 +489,11 @@ void XSlcr_DmaPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_DMAC_RST_CTRL_VAL; + RegVal |= XSLCR_DMAC_RST_CTRL_VAL; Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_DMAC_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL); Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -513,10 +515,10 @@ void XSlcr_GpioPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_GPIO_RST_CTRL_VAL; + RegVal |= XSLCR_GPIO_RST_CTRL_VAL; Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_GPIO_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL); Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); -} \ No newline at end of file +} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_misc_psreset_api.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_misc_psreset_api.h similarity index 59% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_misc_psreset_api.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_misc_psreset_api.h index 073ed3279..234d9bebf 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_misc_psreset_api.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_misc_psreset_api.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -58,137 +58,137 @@ extern "C" { #include "xil_io.h" /************************** Constant Definitions *****************************/ -#define XDDRC_CTRL_BASEADDR 0xF8006000 -#define XSLCR_BASEADDR 0xF8000000 +#define XDDRC_CTRL_BASEADDR 0xF8006000U +#define XSLCR_BASEADDR 0xF8000000U /**< OCM configuration register */ -#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x910) +#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U) /**< SLCR unlock register */ -#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x8) +#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U) /**< SLCR GEM0 rx clock control register */ -#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x138) +#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U) /**< SLCR GEM1 rx clock control register */ -#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x13C) +#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU) /**< SLCR GEM0 clock control register */ -#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x140) +#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U) /**< SLCR GEM1 clock control register */ -#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x144) +#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U) /**< SLCR SMC clock control register */ -#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x148) +#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U) /**< SLCR GEM reset control register */ -#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) +#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U) /**< SLCR USB0 clock control register */ -#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x130) +#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U) /**< SLCR USB1 clock control register */ -#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x134) +#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U) /**< SLCR USB1 reset control register */ -#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) +#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U) /**< SLCR SMC reset control register */ -#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) +#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U) /**< SLCR Level shifter enable register */ -#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x900) +#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U) /**< SLCR ARM pll control register */ -#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x100) +#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U) /**< SLCR DDR pll control register */ -#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x104) +#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U) /**< SLCR IO pll control register */ -#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x108) +#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U) /**< SLCR ARM pll configuration register */ -#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x110) +#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U) /**< SLCR DDR pll configuration register */ -#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x114) +#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U) /**< SLCR IO pll configuration register */ -#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x118) +#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U) /**< SLCR ARM clock control register */ -#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x120) +#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U) /**< SLCR DDR clock control register */ -#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x124) +#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U) /**< SLCR MIO pin address register */ -#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x700) +#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U) /**< SLCR DMAC reset control address register */ -#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x20C) +#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU) /**< SLCR USB reset control address register */ -#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) +/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/ /**< SLCR GEM reset control address register */ -#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) +/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/ /**< SLCR SDIO reset control address register */ -#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x218) +#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U) /**< SLCR SPI reset control address register */ -#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x21C) +#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU) /**< SLCR CAN reset control address register */ -#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x220) +#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U) /**< SLCR I2C reset control address register */ -#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x224) +#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U) /**< SLCR UART reset control address register */ -#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x228) +#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U) /**< SLCR GPIO reset control address register */ -#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x22C) +#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU) /**< SLCR LQSPI reset control address register */ -#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x230) +#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U) /**< SLCR SMC reset control address register */ -#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) +/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/ /**< SLCR OCM reset control address register */ -#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x238) +#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U) /**< SMC mem controller clear config register */ -#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0C +#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU /**< SMC idlecount configuration register */ -#define XSMC_REFRESH_PERIOD_0_OFFSET 0x20 -#define XSMC_REFRESH_PERIOD_1_OFFSET 0x24 +#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U +#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U /**< SMC ECC configuration register */ -#define XSMC_ECC_MEMCFG1_OFFSET 0x404 +#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U /**< SMC ECC command 1 register */ -#define XSMC_ECC_MEMCMD1_OFFSET 0x404 +#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U /**< SMC ECC command 2 register */ -#define XSMC_ECC_MEMCMD2_OFFSET 0x404 +#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U /**< SLCR unlock code */ -#define XSLCR_UNLOCK_CODE 0x0000DF0D +#define XSLCR_UNLOCK_CODE 0x0000DF0DU /**< SMC mem clear configuration mask */ -#define XSMC_MEMC_CLR_CONFIG_MASK 0x5F +#define XSMC_MEMC_CLR_CONFIG_MASK 0x0000005FU /**< SMC ECC memconfig 1 reset value */ -#define XSMC_ECC_MEMCFG1_RESET_VAL 0x43 +#define XSMC_ECC_MEMCFG1_RESET_VAL 0x00000043U /**< SMC ECC memcommand 1 reset value */ -#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080 +#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U /**< SMC ECC memcommand 2 reset value */ -#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585 +#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U /**< DDR controller reset bit mask */ -#define XDDRPS_CTRL_RESET_MASK 0x1 +#define XDDRPS_CTRL_RESET_MASK 0x00000001U /**< SLCR OCM configuration reset value*/ -#define XSLCR_OCM_CFG_RESETVAL 0x8 +#define XSLCR_OCM_CFG_RESETVAL 0x00000008U /**< SLCR OCM bank selection mask*/ -#define XSLCR_OCM_CFG_HIADDR_MASK 0xF +#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU /**< SLCR level shifter enable mask*/ -#define XSLCR_LVL_SHFTR_EN_MASK 0xF +#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU /**< SLCR PLL register reset values */ -#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400 -#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003 +#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U +#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U /**< SLCR MIO register default values */ -#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601 -#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601 +#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U +#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U /**< SLCR Reset control registers default values */ -#define XSLCR_DMAC_RST_CTRL_VAL 0x1 -#define XSLCR_GEM_RST_CTRL_VAL 0xF3 -#define XSLCR_USB_RST_CTRL_VAL 0x3 -#define XSLCR_I2C_RST_CTRL_VAL 0x3 -#define XSLCR_SPI_RST_CTRL_VAL 0xF -#define XSLCR_UART_RST_CTRL_VAL 0xF -#define XSLCR_QSPI_RST_CTRL_VAL 0x3 -#define XSLCR_GPIO_RST_CTRL_VAL 0x1 -#define XSLCR_SMC_RST_CTRL_VAL 0x3 -#define XSLCR_OCM_RST_CTRL_VAL 0x1 -#define XSLCR_SDIO_RST_CTRL_VAL 0x33 -#define XSLCR_CAN_RST_CTRL_VAL 0x3 +#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U +#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U +#define XSLCR_USB_RST_CTRL_VAL 0x00000003U +#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U +#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU +#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU +#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U +#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U +#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U +#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U +#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U +#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U /**************************** Type Definitions *******************************/ /* the following data type is used to hold a null terminated version string @@ -203,11 +203,11 @@ extern "C" { /* * Performs reset operation to the ddr interface */ -void XDdr_ResetHw(); +void XDdr_ResetHw(void); /* * Map the ocm region to post bootrom state */ -void XOcm_Remap(); +void XOcm_Remap(void); /* * Performs the smc interface reset */ @@ -215,15 +215,15 @@ void XSmc_ResetHw(u32 BaseAddress); /* * updates the MIO registers with reset values */ -void XSlcr_MioWriteResetValues(); +void XSlcr_MioWriteResetValues(void); /* * updates the PLL and clock registers with reset values */ -void XSlcr_PllWriteResetValues(); +void XSlcr_PllWriteResetValues(void); /* * Disables the level shifters */ -void XSlcr_DisableLevelShifters(); +void XSlcr_DisableLevelShifters(void); /* * provides softreset to the GPIO interface */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_printf.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_printf.c new file mode 100644 index 000000000..0f0db4fc9 --- /dev/null +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_printf.c @@ -0,0 +1,360 @@ +/*---------------------------------------------------*/ +/* Modified from : */ +/* Public Domain version of printf */ +/* Rud Merriam, Compsult, Inc. Houston, Tx. */ +/* For Embedded Systems Programming, 1991 */ +/* */ +/*---------------------------------------------------*/ +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include +#include +#include + +static void padding( const s32 l_flag,const struct params_s *par); +static void outs(const charptr lp, struct params_s *par); +static s32 getnum( charptr* linep); + +typedef struct params_s { + s32 len; + s32 num1; + s32 num2; + char8 pad_character; + s32 do_padding; + s32 left_flag; + s32 unsigned_flag; +} params_t; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + + +/*---------------------------------------------------*/ +/* */ +/* This routine puts pad characters into the output */ +/* buffer. */ +/* */ +static void padding( const s32 l_flag, const struct params_s *par) +{ + s32 i; + + if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { + i=(par->len); + for (; i<(par->num1); i++) { +#ifdef STDOUT_BASEADDRESS + outbyte( par->pad_character); +#endif + } + } +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a string to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ +static void outs(const charptr lp, struct params_s *par) +{ + charptr LocalPtr; + LocalPtr = lp; + /* pad on left if needed */ + if(LocalPtr != NULL) { + par->len = (s32)strlen( LocalPtr); + } + padding( !(par->left_flag), par); + + /* Move string to the buffer */ + while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) { + (par->num2)--; +#ifdef STDOUT_BASEADDRESS + outbyte(*LocalPtr); + LocalPtr += 1; +#endif +} + + /* Pad on right if needed */ + /* CR 439175 - elided next stmt. Seemed bogus. */ + /* par->len = strlen( lp) */ + padding( par->left_flag, par); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a number to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ + +static void outnum( const s32 n, const s32 base, struct params_s *par) +{ + charptr cp; + s32 negative; + s32 i; + char8 outbuf[32]; + const char8 digits[] = "0123456789ABCDEF"; + u32 num; + for(i = 0; i<32; i++) { + outbuf[i] = '0'; + } + + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = n; + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % base)]; + i++; + num /= base; + } while (num > 0); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = 0; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { +#ifdef STDOUT_BASEADDRESS + outbyte( outbuf[i] ); + i--; +#endif +} + padding( par->left_flag, par); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine gets a number from the format */ +/* string. */ +/* */ +static s32 getnum( charptr* linep) +{ + s32 n; + s32 ResultIsDigit = 0; + charptr cptr; + n = 0; + cptr = *linep; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + while (ResultIsDigit != 0) { + if(cptr != NULL){ + n = ((n*10) + (((s32)*cptr) - (s32)'0')); + cptr += 1; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + } + ResultIsDigit = isdigit(((s32)*cptr)); + } + *linep = ((charptr )(cptr)); + return(n); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine operates just like a printf/sprintf */ +/* routine. It outputs a set of data under the */ +/* control of a formatting string. Not all of the */ +/* standard C format control are supported. The ones */ +/* provided are primarily those needed for embedded */ +/* systems work. Primarily the floating point */ +/* routines are omitted. Other formats could be */ +/* added easily by following the examples shown for */ +/* the supported formats. */ +/* */ + +/* void esp_printf( const func_ptr f_ptr, + const charptr ctrl1, ...) */ +void xil_printf( const char8 *ctrl1, ...) +{ + s32 Check; + s32 long_flag; + s32 dot_flag; + + params_t par; + + char8 ch; + va_list argp; + char8 *ctrl = (char8 *)ctrl1; + + va_start( argp, ctrl1); + + while ((ctrl != NULL) && (*ctrl != (char8)0)) { + + /* move format string chars to buffer until a */ + /* format control is found. */ + if (*ctrl != '%') { +#ifdef STDOUT_BASEADDRESS + outbyte(*ctrl); + ctrl += 1; +#endif + continue; + } + + /* initialize all the flags for this format. */ + dot_flag = 0; + long_flag = 0; + par.unsigned_flag = 0; + par.left_flag = 0; + par.do_padding = 0; + par.pad_character = ' '; + par.num2=32767; + par.num1=0; + par.len=0; + + try_next: + if(ctrl != NULL) { + ctrl += 1; + } + if(ctrl != NULL) { + ch = *ctrl; + } + else { + ch = *ctrl; + } + + if (isdigit((s32)ch) != 0) { + if (dot_flag != 0) { + par.num2 = getnum(&ctrl); + } + else { + if (ch == '0') { + par.pad_character = '0'; + } + if(ctrl != NULL) { + par.num1 = getnum(&ctrl); + } + par.do_padding = 1; + } + if(ctrl != NULL) { + ctrl -= 1; + } + goto try_next; + } + + switch (tolower((s32)ch)) { + case '%': +#ifdef STDOUT_BASEADDRESS + outbyte( '%'); +#endif + Check = 1; + break; + + case '-': + par.left_flag = 1; + Check = 0; + break; + + case '.': + dot_flag = 1; + Check = 0; + break; + + case 'l': + long_flag = 1; + Check = 0; + break; + + case 'u': + par.unsigned_flag = 1; + /* fall through */ + case 'i': + case 'd': + if ((long_flag != 0) || (ch == 'D')) { + outnum( va_arg(argp, s32), 10L, &par); + } + else { + outnum( va_arg(argp, s32), 10L, &par); + } + Check = 1; + break; + case 'p': + case 'X': + case 'x': + par.unsigned_flag = 1; + outnum((s32)va_arg(argp, s32), 16L, &par); + Check = 1; + break; + + case 's': + outs( va_arg( argp, char *), &par); + Check = 1; + break; + + case 'c': +#ifdef STDOUT_BASEADDRESS + outbyte( va_arg( argp, s32)); +#endif + Check = 1; + break; + + case '\\': + switch (*ctrl) { + case 'a': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x07)); +#endif + break; + case 'h': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x08)); +#endif + break; + case 'r': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x0D)); +#endif + break; + case 'n': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x0D)); + outbyte( ((char8)0x0A)); +#endif + break; + default: +#ifdef STDOUT_BASEADDRESS + outbyte( *ctrl); +#endif + break; + } + ctrl += 1; + Check = 0; + break; + + default: + Check = 1; + break; + } + if(Check == 1) { + if(ctrl != NULL) { + ctrl += 1; + } + continue; + } + goto try_next; + } + va_end( argp); +} + +/*---------------------------------------------------*/ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_printf.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_printf.h similarity index 62% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_printf.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_printf.h index d928da4e7..ee307bca8 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_printf.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_printf.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -36,8 +36,36 @@ extern "C" { #endif -void xil_printf(const char *ctrl1, ...); -void print(char *ptr); +#include +#include +#include +#include "xil_types.h" +#include "xparameters.h" + +/*----------------------------------------------------*/ +/* Use the following parameter passing structure to */ +/* make xil_printf re-entrant. */ +/*----------------------------------------------------*/ + +struct params_s; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + +typedef char8* charptr; +typedef s32 (*func_ptr)(int c); + +/* */ + +void xil_printf( const char8 *ctrl1, ...); +void print(const char8 *ptr); +void outbyte(char c); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testcache.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testcache.c similarity index 53% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testcache.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testcache.c index 6e313dbef..a2c4b0bbf 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testcache.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testcache.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -51,19 +51,27 @@ * This file contain functions that all operate on HAL. * ******************************************************************************/ +#ifdef __ARM__ #include "xil_cache.h" #include "xil_testcache.h" +#include "xil_types.h" +#include "xpseudo_asm.h" +#ifdef __aarch64__ +#include "xreg_cortexa53.h" +#else +#include "xreg_cortexr5.h" +#endif -extern void xil_printf(const char *ctrl1, ...); +#include "xil_types.h" + +extern void xil_printf(const char8 *ctrl1, ...); #define DATA_LENGTH 128 -#ifdef __GNUC__ -static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32))); -#elif defined (__ICCARM__) -static u32 Data[DATA_LENGTH]; +#ifdef __aarch64__ +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64))); #else -static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32))); +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32))); #endif /** @@ -77,30 +85,35 @@ static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32))); * - 0 is returned for a pass * - -1 is returned for a failure */ -int Xil_TestDCacheRange(void) +s32 Xil_TestDCacheRange(void) { - int Index; - int Status; - - u32 Value; + s32 Index; + s32 Status = 0; + u32 CtrlReg; + INTPTR Value; xil_printf("-- Cache Range Test --\n\r"); - for (Index = 0; Index < DATA_LENGTH; Index++) Data[Index] = 0xA0A00505; xil_printf(" initialize Data done:\r\n"); - Xil_DCacheFlushRange((u32)Data, DATA_LENGTH * sizeof(u32)); + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); xil_printf(" flush range done\r\n"); - for (Index = 0; Index < DATA_LENGTH; Index++) - Data[Index] = Index + 3; - Xil_DCacheInvalidateRange((u32)Data, DATA_LENGTH * sizeof(u32)); - - xil_printf(" invalidate dcache range done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); Status = 0; @@ -113,15 +126,80 @@ int Xil_TestDCacheRange(void) } } + if (!Status) { + xil_printf(" Flush worked\r\n"); + } + else { + xil_printf("Error: flush dcache range not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0C505; + + + + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = Index + 3; + + Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + xil_printf(" invalidate dcache range done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0A05; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0xA0A0A05) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { xil_printf(" Invalidate worked\r\n"); } else { xil_printf("Error: Invalidate dcache range not working\r\n"); } - xil_printf("-- Cache Range Test Complete --\r\n"); - return Status; } @@ -136,23 +214,66 @@ int Xil_TestDCacheRange(void) * - 0 is returned for a pass * - -1 is returned for a failure */ -int Xil_TestDCacheAll(void) +s32 Xil_TestDCacheAll(void) { - int Index; - int Status; - u32 Value; + s32 Index; + s32 Status; + INTPTR Value; + u32 CtrlReg; xil_printf("-- Cache All Test --\n\r"); - for (Index = 0; Index < DATA_LENGTH; Index++) Data[Index] = 0x50500A0A; - xil_printf(" initialize Data done:\r\n"); Xil_DCacheFlush(); - xil_printf(" flush all done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + + if (Value != 0x50500A0A) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Flush all worked\r\n"); + } + else { + xil_printf("Error: Flush dcache all not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x505FFA0A; + + Xil_DCacheFlush(); + for (Index = 0; Index < DATA_LENGTH; Index++) Data[Index] = Index + 3; @@ -160,12 +281,35 @@ int Xil_TestDCacheAll(void) Xil_DCacheInvalidate(); xil_printf(" invalidate all done\r\n"); - + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x50CFA0A; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); Status = 0; for (Index = 0; Index < DATA_LENGTH; Index++) { Value = Data[Index]; - if (Value != 0x50500A0A) { + if (Value != 0x50CFA0A) { Status = -1; xil_printf("Data[%d] = %x\r\n", Index, Value); break; @@ -176,13 +320,12 @@ int Xil_TestDCacheAll(void) xil_printf(" Invalidate all worked\r\n"); } else { - xil_printf("Error: Invalidate dcache all not working\r\n"); + xil_printf("Error: Invalidate dcache all not working\r\n"); } xil_printf("-- DCache all Test Complete --\n\r"); return Status; - } @@ -194,12 +337,12 @@ int Xil_TestDCacheAll(void) * - 0 is returned for a pass * The function will hang if it fails. */ -int Xil_TestICacheRange(void) +s32 Xil_TestICacheRange(void) { - Xil_ICacheInvalidateRange((u32)Xil_TestICacheRange, 1024); - Xil_ICacheInvalidateRange((u32)Xil_TestDCacheRange, 1024); - Xil_ICacheInvalidateRange((u32)Xil_TestDCacheAll, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024); xil_printf("-- Invalidate icache range done --\r\n"); @@ -214,9 +357,10 @@ int Xil_TestICacheRange(void) * - 0 is returned for a pass * The function will hang if it fails. */ -int Xil_TestICacheAll(void) +s32 Xil_TestICacheAll(void) { Xil_ICacheInvalidate(); xil_printf("-- Invalidate icache all done --\r\n"); return 0; } +#endif diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testcache.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testcache.h similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testcache.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testcache.h index 501cbba5a..b3c416cd0 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testcache.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testcache.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -45,14 +45,16 @@ #ifndef XIL_TESTCACHE_H /* prevent circular inclusions */ #define XIL_TESTCACHE_H /* by using protection macros */ +#include "xil_types.h" + #ifdef __cplusplus extern "C" { #endif -extern int Xil_TestDCacheRange(void); -extern int Xil_TestDCacheAll(void); -extern int Xil_TestICacheRange(void); -extern int Xil_TestICacheAll(void); +extern s32 Xil_TestDCacheRange(void); +extern s32 Xil_TestDCacheAll(void); +extern s32 Xil_TestICacheRange(void); +extern s32 Xil_TestICacheAll(void); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testio.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testio.c similarity index 75% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testio.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testio.c index 78ec83fde..a68d7652f 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testio.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testio.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -60,19 +60,19 @@ * * Endian swap a 16-bit word. * @param Data is the 16-bit word to be swapped. - * @return The endian swapped valud. + * @return The endian swapped value. * */ static u16 Swap16(u16 Data) { - return ((Data >> 8) & 0x00FF) | ((Data << 8) & 0xFF00); + return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U); } /** * * Endian swap a 32-bit word. * @param Data is the 32-bit word to be swapped. - * @return The endian swapped valud. + * @return The endian swapped value. * */ static u32 Swap32(u32 Data) @@ -83,13 +83,13 @@ static u32 Swap32(u32 Data) u16 Swap16Lo; u16 Swap16Hi; - Hi16 = (u16)((Data >> 16) & 0x0000FFFF); - Lo16 = (u16)(Data & 0x0000FFFF); + Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU); + Lo16 = (u16)(Data & 0x0000FFFFU); Swap16Lo = Swap16(Lo16); Swap16Hi = Swap16(Hi16); - return (((u32)(Swap16Lo)) << 16) | ((u32)Swap16Hi); + return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi); } /*****************************************************************************/ @@ -100,7 +100,7 @@ static u32 Swap32(u32 Data) * values. * * @param Addr is a pointer to the region of memory to be tested. -* @param Len is the length of the block. +* @param Length is the Length of the block. * @param Value is the constant used for writting the memory. * * @return @@ -110,22 +110,23 @@ static u32 Swap32(u32 Data) * *****************************************************************************/ -int Xil_TestIO8(u8 *Addr, int Len, u8 Value) +s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value) { u8 ValueIn; - int Index; + s32 Index; + s32 Status = 0; - for (Index = 0; Index < Len; Index++) { - Xil_Out8((u32)Addr, Value); + for (Index = 0; Index < Length; Index++) { + Xil_Out8((INTPTR)Addr, Value); - ValueIn = Xil_In8((u32)Addr); + ValueIn = Xil_In8((INTPTR)Addr); - if (Value != ValueIn) { - return -1; + if ((Value != ValueIn) && (Status == 0)) { + Status = -1; + break; } } - - return 0; + return Status; } @@ -142,7 +143,7 @@ int Xil_TestIO8(u8 *Addr, int Len, u8 Value) * read-in value before comparing is controlled by the 5th argument. * * @param Addr is a pointer to the region of memory to be tested. -* @param Len is the length of the block. +* @param Length is the Length of the block. * @param Value is the constant used for writting the memory. * @param Kind is the test kind. Acceptable values are: * XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. @@ -155,60 +156,63 @@ int Xil_TestIO8(u8 *Addr, int Len, u8 Value) * *****************************************************************************/ -int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap) +s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) { - u16 ValueIn; - int Index; + u16 *TempAddr16; + u16 ValueIn = 0U; + s32 Index; + TempAddr16 = Addr; + Xil_AssertNonvoid(TempAddr16 != NULL); - for (Index = 0; Index < Len; Index++) { + for (Index = 0; Index < Length; Index++) { switch (Kind) { case XIL_TESTIO_LE: - Xil_Out16LE((u32)Addr, Value); + Xil_Out16LE((INTPTR)TempAddr16, Value); break; case XIL_TESTIO_BE: - Xil_Out16BE((u32)Addr, Value); + Xil_Out16BE((INTPTR)TempAddr16, Value); break; default: - Xil_Out16((u32)Addr, Value); + Xil_Out16((INTPTR)TempAddr16, Value); break; } - ValueIn = Xil_In16((u32)Addr); + ValueIn = Xil_In16((INTPTR)TempAddr16); - if (Kind && Swap) + if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap16(ValueIn); + } if (Value != ValueIn) { return -1; } /* second round */ - Xil_Out16((u32)Addr, Value); + Xil_Out16((INTPTR)TempAddr16, Value); switch (Kind) { case XIL_TESTIO_LE: - ValueIn = Xil_In16LE((u32)Addr); + ValueIn = Xil_In16LE((INTPTR)TempAddr16); break; case XIL_TESTIO_BE: - ValueIn = Xil_In16BE((u32)Addr); + ValueIn = Xil_In16BE((INTPTR)TempAddr16); break; default: - ValueIn = Xil_In16((u32)Addr); + ValueIn = Xil_In16((INTPTR)TempAddr16); break; } - if (Kind && Swap) + if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap16(ValueIn); + } if (Value != ValueIn) { return -1; } - Addr++; + TempAddr16 += sizeof(u16); } - return 0; - } @@ -225,7 +229,7 @@ int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap) * before comparing is controlled by the 5th argument. * * @param Addr is a pointer to the region of memory to be tested. -* @param Len is the length of the block. +* @param Length is the Length of the block. * @param Value is the constant used for writting the memory. * @param Kind is the test kind. Acceptable values are: * XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. @@ -237,57 +241,61 @@ int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap) * - 0 is returned for a pass * *****************************************************************************/ -int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap) +s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) { - u32 ValueIn; - int Index; + u32 *TempAddr; + u32 ValueIn = 0U; + s32 Index; + TempAddr = Addr; + Xil_AssertNonvoid(TempAddr != NULL); - for (Index = 0; Index < Len; Index++) { + for (Index = 0; Index < Length; Index++) { switch (Kind) { case XIL_TESTIO_LE: - Xil_Out32LE((u32)Addr, Value); + Xil_Out32LE((INTPTR)TempAddr, Value); break; case XIL_TESTIO_BE: - Xil_Out32BE((u32)Addr, Value); + Xil_Out32BE((INTPTR)TempAddr, Value); break; default: - Xil_Out32((u32)Addr, Value); + Xil_Out32((INTPTR)TempAddr, Value); break; } - ValueIn = Xil_In32((u32)Addr); + ValueIn = Xil_In32((INTPTR)TempAddr); - if (Kind && Swap) + if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap32(ValueIn); + } if (Value != ValueIn) { return -1; } /* second round */ - Xil_Out32((u32)Addr, Value); + Xil_Out32((INTPTR)TempAddr, Value); switch (Kind) { case XIL_TESTIO_LE: - ValueIn = Xil_In32LE((u32)Addr); + ValueIn = Xil_In32LE((INTPTR)TempAddr); break; case XIL_TESTIO_BE: - ValueIn = Xil_In32BE((u32)Addr); + ValueIn = Xil_In32BE((INTPTR)TempAddr); break; default: - ValueIn = Xil_In32((u32)Addr); + ValueIn = Xil_In32((INTPTR)TempAddr); break; } - if (Kind && Swap) + if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap32(ValueIn); + } if (Value != ValueIn) { return -1; } - Addr++; + TempAddr += sizeof(u32); } return 0; } - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testio.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testio.h similarity index 91% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testio.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testio.h index bb0520824..fba0c1060 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testio.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testio.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -80,9 +80,9 @@ extern "C" { /************************** Function Prototypes ******************************/ -extern int Xil_TestIO8(u8 *Addr, int Len, u8 Value); -extern int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap); -extern int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap); +extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value); +extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap); +extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testmem.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testmem.c similarity index 66% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testmem.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testmem.c index 492bf0878..19a3b6608 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testmem.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testmem.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -92,16 +92,18 @@ static u32 RotateRight(u32 Input, u8 Width); * patterns used not to repeat over the region tested. * *****************************************************************************/ -int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) +s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) { u32 I; - u32 J; + u32 j; u32 Val; u32 FirtVal; - u32 Word; + u32 WordMem32; + s32 Status = 0; - Xil_AssertNonvoid(Words != 0); - Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); /* * variable initialization @@ -109,25 +111,14 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) Val = XIL_TESTMEM_INIT_VALUE; FirtVal = XIL_TESTMEM_INIT_VALUE; - /* - * Select the proper Subtest - */ - switch (Subtest) { - - case XIL_TESTMEM_ALLMEMTESTS: - - /* this case executes all of the Subtests */ - - /* fall through case statement */ - - case XIL_TESTMEM_INCREMENT: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' */ - for (I = 0L; I < Words; I++) { - Addr[I] = Val; + for (I = 0U; I < Words; I++) { + *(Addr+I) = Val; Val++; } @@ -144,104 +135,90 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * Val */ - for (I = 0L; I < Words; I++) { - Word = Addr[I]; + for (I = 0U; I < Words; I++) { + WordMem32 = *(Addr+I); - if (Word != Val) { - return -1; + if (WordMem32 != Val) { + Status = -1; + goto End_Label; } Val++; } + } - - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - - /* end of case 1 */ - - /* fall through case statement */ - - case XIL_TESTMEM_WALKONES: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test */ - for (J = 0L; J < 32; J++) { + for (j = 0U; j < (u32)32; j++) { /* * Generate an initial value for walking ones test * to test for bad data bits */ - Val = 1 << J; + Val = (1U << j); /* * START walking ones test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 32; I++) { + for (I = 0U; I < (u32)32; I++) { /* write memory location */ - Addr[I] = Val; - Val = (u32) RotateLeft(Val, 32); + *(Addr+I) = Val; + Val = (u32) RotateLeft(Val, 32U); } /* * Restore the reference 'val' to the * initial value */ - Val = 1 << J; + Val = 1U << j; /* Read the values from each location that was * written */ - for (I = 0L; I < 32; I++) { + for (I = 0U; I < (u32)32; I++) { /* read memory location */ - Word = Addr[I]; + WordMem32 = *(Addr+I); - if (Word != Val) { - return -1; + if (WordMem32 != Val) { + Status = -1; + goto End_Label; } - Val = (u32)RotateLeft(Val, 32); + Val = (u32)RotateLeft(Val, 32U); } - } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - /* end of case 2 */ - /* fall through case statement */ - - case XIL_TESTMEM_WALKZEROS: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible * initial test Patterns for walking zeros test */ - for (J = 0L; J < 32; J++) { + for (j = 0U; j < (u32)32; j++) { /* * Generate an initial value for walking ones test * to test for bad data bits */ - Val = ~(1 << J); + Val = ~(1U << j); /* * START walking zeros test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 32; I++) { + for (I = 0U; I < (u32)32; I++) { /* write memory location */ - Addr[I] = Val; - Val = ~((u32)RotateLeft(~Val, 32)); + *(Addr+I) = Val; + Val = ~((u32)RotateLeft(~Val, 32U)); } /* @@ -249,35 +226,29 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * initial value */ - Val = ~(1 << J); + Val = ~(1U << j); /* Read the values from each location that was * written */ - for (I = 0L; I < 32; I++) { + for (I = 0U; I < (u32)32; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem32 = *(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; } - Val = ~((u32)RotateLeft(~Val, 32)); + Val = ~((u32)RotateLeft(~Val, 32U)); } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - /* end of case 3 */ - - /* fall through case statement */ - - case XIL_TESTMEM_INVERSEADDR: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Val = (u32) (~((u32) (&Addr[I]))); - Addr[I] = Val; + Val = (u32) (~((INTPTR) (&Addr[I]))); + *(Addr+I) = Val; } /* @@ -285,31 +256,26 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * of tested memory */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* Read the location */ - Word = Addr[I]; - Val = (u32) (~((u32) (&Addr[I]))); + WordMem32 = *(Addr+I); + Val = (u32) (~((INTPTR) (&Addr[I]))); - if ((Word ^ Val) != 0x00000000) { - return -1; + if ((WordMem32 ^ Val) != 0x00000000U) { + Status = -1; + goto End_Label; } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 4 */ - - /* fall through case statement */ - - case XIL_TESTMEM_FIXEDPATTERN: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing */ - if (Pattern == 0) { - Val = 0xDEADBEEF; + if (Pattern == (u32)0) { + Val = 0xDEADBEEFU; } else { Val = Pattern; @@ -319,9 +285,9 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * Fill the memory with fixed Pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Addr[I] = Val; + *(Addr+I) = Val; } /* @@ -330,33 +296,20 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * with the fixed Pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem32 = *(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 5 */ - - /* this break is for the prior fall through case statements */ - - break; - - default: - return -1; - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return 0; +End_Label: + return Status; } /*****************************************************************************/ @@ -388,16 +341,18 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * patterns used not to repeat over the region tested. * *****************************************************************************/ -int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) +s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) { u32 I; - u32 J; + u32 j; u16 Val; u16 FirtVal; - u16 Word; + u16 WordMem16; + s32 Status = 0; - Xil_AssertNonvoid(Words != 0); + Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); /* * variable initialization @@ -409,22 +364,14 @@ int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * selectthe proper Subtest(s) */ - switch (Subtest) { - - case XIL_TESTMEM_ALLMEMTESTS: - - /* this case executes all of the Subtests */ - - /* fall through case statement */ - - case XIL_TESTMEM_INCREMENT: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Addr[I] = Val; + *(Addr+I) = Val; Val++; } /* @@ -439,145 +386,131 @@ int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * with the incrementing reference val */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; } Val++; } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } + } - /* end of case 1 */ - /* fall through case statement */ - - case XIL_TESTMEM_WALKONES: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial test * Patterns for walking ones test */ - for (J = 0L; J < 16; J++) { + for (j = 0U; j < (u32)16; j++) { /* * Generate an initial value for walking ones test * to test for bad data bits */ - Val = 1 << J; + Val = (u16)((u32)1 << j); /* * START walking ones test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 16; I++) { + for (I = 0U; I < (u32)16; I++) { /* write memory location */ - Addr[I] = Val; - Val = (u16)RotateLeft(Val, 16); + *(Addr+I) = Val; + Val = (u16)RotateLeft(Val, 16U); } /* * Restore the reference 'Val' to the * initial value */ - Val = 1 << J; + Val = (u16)((u32)1 << j); /* Read the values from each location that was written */ - for (I = 0L; I < 16; I++) { + for (I = 0U; I < (u32)16; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; } - Val = (u16)RotateLeft(Val, 16); + Val = (u16)RotateLeft(Val, 16U); } - } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 2 */ - /* fall through case statement */ + } - case XIL_TESTMEM_WALKZEROS: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial * test Patterns for walking zeros test */ - for (J = 0L; J < 16; J++) { + for (j = 0U; j < (u32)16; j++) { /* * Generate an initial value for walking ones * test to test for bad * data bits */ - Val = ~(1 << J); + Val = ~(1U << j); /* * START walking zeros test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 16; I++) { + for (I = 0U; I < (u32)16; I++) { /* write memory location */ - Addr[I] = Val; - Val = ~((u16)RotateLeft(~Val, 16)); + *(Addr+I) = Val; + Val = ~((u16)RotateLeft(~Val, 16U)); } /* * Restore the reference 'Val' to the * initial value */ - Val = ~(1 << J); + Val = ~(1U << j); /* Read the values from each location that was written */ - for (I = 0L; I < 16; I++) { + for (I = 0U; I < (u32)16; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; } - Val = ~((u16)RotateLeft(~Val, 16)); + Val = ~((u16)RotateLeft(~Val, 16U)); } } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 3 */ - /* fall through case statement */ + } - case XIL_TESTMEM_INVERSEADDR: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Val = (u16) (~((u32) (&Addr[I]))); - Addr[I] = Val; + Val = (u16) (~((INTPTR)(&Addr[I]))); + *(Addr+I) = Val; } /* * Check every word within the words * of tested memory */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - Val = (u16) (~((u32) (&Addr[I]))); - if ((Word ^ Val) != 0x0000) { - return -1; + WordMem16 = *(Addr+I); + Val = (u16) (~((INTPTR) (&Addr[I]))); + if ((WordMem16 ^ Val) != 0x0000U) { + Status = -1; + goto End_Label; } } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 4 */ - /* fall through case statement */ + } - case XIL_TESTMEM_FIXEDPATTERN: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing */ - if (Pattern == 0) { - Val = 0xDEAD; + if (Pattern == (u16)0) { + Val = 0xDEADU; } else { Val = Pattern; @@ -587,9 +520,9 @@ int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * Fill the memory with fixed pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Addr[I] = Val; + *(Addr+I) = Val; } /* @@ -598,29 +531,18 @@ int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * with the fixed pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; } } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 5 */ - /* this break is for the prior fall through case statements */ + } - break; - - default: - return -1; - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return 0; +End_Label: + return Status; } @@ -653,16 +575,18 @@ int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * patterns used not to repeat over the region tested. * *****************************************************************************/ -int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) +s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) { u32 I; - u32 J; + u32 j; u8 Val; u8 FirtVal; - u8 Word; + u8 WordMem8; + s32 Status = 0; - Xil_AssertNonvoid(Words != 0); + Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); /* * variable initialization @@ -674,20 +598,14 @@ int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) * select the proper Subtest(s) */ - switch (Subtest) { - - case XIL_TESTMEM_ALLMEMTESTS: - /* this case executes all of the Subtests */ - /* fall through case statement */ - - case XIL_TESTMEM_INCREMENT: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Addr[I] = Val; + *(Addr+I) = Val; Val++; } /* @@ -702,115 +620,102 @@ int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) * Val */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; } Val++; } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 1 */ - - /* fall through case statement */ - - case XIL_TESTMEM_WALKONES: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test */ - for (J = 0L; J < 8; J++) { + for (j = 0U; j < (u32)8; j++) { /* * Generate an initial value for walking ones test * to test for bad data bits */ - Val = 1 << J; + Val = (u8)((u32)1 << j); /* * START walking ones test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 8; I++) { + for (I = 0U; I < (u32)8; I++) { /* write memory location */ - Addr[I] = Val; - Val = (u8)RotateLeft(Val, 8); + *(Addr+I) = Val; + Val = (u8)RotateLeft(Val, 8U); } /* * Restore the reference 'Val' to the * initial value */ - Val = 1 << J; + Val = (u8)((u32)1 << j); /* Read the values from each location that was written */ - for (I = 0L; I < 8; I++) { + for (I = 0U; I < (u32)8; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; } - Val = (u8)RotateLeft(Val, 8); + Val = (u8)RotateLeft(Val, 8U); } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 2 */ - /* fall through case statement */ - - case XIL_TESTMEM_WALKZEROS: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial test * Patterns for walking zeros test */ - for (J = 0L; J < 8; J++) { + for (j = 0U; j < (u32)8; j++) { /* * Generate an initial value for walking ones test to test * for bad data bits */ - Val = ~(1 << J); + Val = ~(1U << j); /* * START walking zeros test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 8; I++) { + for (I = 0U; I < (u32)8; I++) { /* write memory location */ - Addr[I] = Val; - Val = ~((u8)RotateLeft(~Val, 8)); + *(Addr+I) = Val; + Val = ~((u8)RotateLeft(~Val, 8U)); } /* * Restore the reference 'Val' to the * initial value */ - Val = ~(1 << J); + Val = ~(1U << j); /* Read the values from each location that was written */ - for (I = 0L; I < 8; I++) { + for (I = 0U; I < (u32)8; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; } - Val = ~((u8)RotateLeft(~Val, 8)); + Val = ~((u8)RotateLeft(~Val, 8U)); } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 3 */ - /* fall through case statement */ - - case XIL_TESTMEM_INVERSEADDR: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Val = (u8) (~((u32) (&Addr[I]))); - Addr[I] = Val; + Val = (u8) (~((INTPTR) (&Addr[I]))); + *(Addr+I) = Val; } /* @@ -818,28 +723,25 @@ int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) * of tested memory */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - Val = (u8) (~((u32) (&Addr[I]))); - if ((Word ^ Val) != 0x00) { - return -1; + WordMem8 = *(Addr+I); + Val = (u8) (~((INTPTR) (&Addr[I]))); + if ((WordMem8 ^ Val) != 0x00U) { + Status = -1; + goto End_Label; } } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 4 */ - /* fall through case statement */ + } - case XIL_TESTMEM_FIXEDPATTERN: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing */ - if (Pattern == 0) { - Val = 0xA5; + if (Pattern == (u8)0) { + Val = 0xA5U; } else { Val = Pattern; @@ -847,9 +749,9 @@ int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) /* * Fill the memory with fixed Pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Addr[I] = Val; + *(Addr+I) = Val; } /* * Check every word within the words @@ -857,32 +759,18 @@ int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) * with the fixed Pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - /* end of case 5 */ - - /* this break is for the prior fall through case statements */ - - break; - - default: - return -1; - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return 0; +End_Label: + return Status; } @@ -909,27 +797,28 @@ static u32 RotateLeft(u32 Input, u8 Width) u32 ReturnVal; u32 WidthMask; u32 MsbMask; + u32 LocalInput = Input; /* * set up the WidthMask and the MsbMask */ - MsbMask = 1 << (Width - 1); + MsbMask = 1U << (Width - 1U); - WidthMask = (MsbMask << 1) - 1; + WidthMask = (MsbMask << (u32)1) - (u32)1; /* * set the Width of the Input to the correct width */ - Input = Input & WidthMask; + LocalInput = LocalInput & WidthMask; - Msb = Input & MsbMask; + Msb = LocalInput & MsbMask; - ReturnVal = Input << 1; + ReturnVal = LocalInput << 1U; - if (Msb != 0x00000000) { - ReturnVal = ReturnVal | 0x00000001; + if (Msb != 0x00000000U) { + ReturnVal = ReturnVal | (u32)0x00000001; } ReturnVal = ReturnVal & WidthMask; @@ -962,26 +851,26 @@ static u32 RotateRight(u32 Input, u8 Width) u32 ReturnVal; u32 WidthMask; u32 MsbMask; - + u32 LocalInput = Input; /* * set up the WidthMask and the MsbMask */ - MsbMask = 1 << (Width - 1); + MsbMask = 1U << (Width - 1U); - WidthMask = (MsbMask << 1) - 1; + WidthMask = (MsbMask << 1U) - 1U; /* * set the width of the input to the correct width */ - Input = Input & WidthMask; + LocalInput = LocalInput & WidthMask; - ReturnVal = Input >> 1; + ReturnVal = LocalInput >> 1U; - Lsb = Input & 0x00000001; + Lsb = LocalInput & 0x00000001U; - if (Lsb != 0x00000000) { + if (Lsb != 0x00000000U) { ReturnVal = ReturnVal | MsbMask; } @@ -991,4 +880,3 @@ static u32 RotateRight(u32 Input, u8 Width) } #endif /* ROTATE_RIGHT */ - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testmem.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testmem.h similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testmem.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testmem.h index 3b161f220..4cbfd878b 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_testmem.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_testmem.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -127,7 +127,7 @@ extern "C" { /* xutil_memtest defines */ -#define XIL_TESTMEM_INIT_VALUE 1 +#define XIL_TESTMEM_INIT_VALUE 1U /** @name Memory subtests * @{ @@ -135,12 +135,12 @@ extern "C" { /** * See the detailed description of the subtests in the file description. */ -#define XIL_TESTMEM_ALLMEMTESTS 0 -#define XIL_TESTMEM_INCREMENT 1 -#define XIL_TESTMEM_WALKONES 2 -#define XIL_TESTMEM_WALKZEROS 3 -#define XIL_TESTMEM_INVERSEADDR 4 -#define XIL_TESTMEM_FIXEDPATTERN 5 +#define XIL_TESTMEM_ALLMEMTESTS 0x00U +#define XIL_TESTMEM_INCREMENT 0x01U +#define XIL_TESTMEM_WALKONES 0x02U +#define XIL_TESTMEM_WALKZEROS 0x03U +#define XIL_TESTMEM_INVERSEADDR 0x04U +#define XIL_TESTMEM_FIXEDPATTERN 0x05U #define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN /* @} */ @@ -151,9 +151,9 @@ extern "C" { /* xutil_testmem prototypes */ -extern int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); -extern int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); -extern int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); +extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); +extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); +extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_types.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_types.h similarity index 80% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_types.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_types.h index c9c173018..e8b78b7c6 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xil_types.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xil_types.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -44,7 +44,9 @@ * ----- ---- -------- ------------------------------------------------------- * 1.00a hbm 07/14/09 First release * 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros -* 4.2 srt 07/03/14 Use standard definitions from stdint.h +* 5.00 pkp 05/29/14 Made changes for 64 bit architecture +* srt 07/14/14 Use standard definitions from stdint.h and stddef.h +* Define LONG and ULONG datatypes and mask values * * ******************************************************************************/ @@ -58,19 +60,19 @@ /************************** Constant Definitions *****************************/ #ifndef TRUE -# define TRUE 1 +# define TRUE 1U #endif #ifndef FALSE -# define FALSE 0 +# define FALSE 0U #endif #ifndef NULL -#define NULL 0 +#define NULL 0U #endif -#define XIL_COMPONENT_IS_READY 0x11111111 /**< component has been initialized */ -#define XIL_COMPONENT_IS_STARTED 0x22222222 /**< component has been started */ +#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */ /** @name New types * New simple types. @@ -124,25 +126,27 @@ typedef struct /** * xbasic_types.h does not typedef s* or u64 */ -typedef uint64_t u64; +typedef char char8; typedef int8_t s8; typedef int16_t s16; typedef int32_t s32; typedef int64_t s64; +typedef uint64_t u64; +typedef int sint32; + typedef intptr_t INTPTR; typedef uintptr_t UINTPTR; -typedef ptrdiff_t PTRDIFF; +typedef ptrdiff_t PTRDIFF; #if !defined(LONG) || !defined(ULONG) typedef long LONG; typedef unsigned long ULONG; #endif -#define ULONG64_HI_MASK 0xFFFFFFFF00000000 +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U #define ULONG64_LO_MASK ~ULONG64_HI_MASK - #else #include #endif @@ -160,21 +164,37 @@ typedef void (*XInterruptHandler) (void *InstancePtr); */ typedef void (*XExceptionHandler) (void *InstancePtr); +/** + * UPPER_32_BITS - return bits 32-63 of a number + * @n: the number we're accessing + * + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress + * the "right shift count >= width of type" warning when that quantity is + * 32-bits. + */ +#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16)) + +/** + * LOWER_32_BITS - return bits 0-31 of a number + * @n: the number we're accessing + */ +#define LOWER_32_BITS(n) ((u32)(n)) + /*@}*/ /************************** Constant Definitions *****************************/ #ifndef TRUE -#define TRUE 1 +#define TRUE 1U #endif #ifndef FALSE -#define FALSE 0 +#define FALSE 0U #endif #ifndef NULL -#define NULL 0 +#define NULL 0U #endif #endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_stats.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xplatform_info.c similarity index 61% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_stats.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xplatform_info.c index fbf55ce6a..fea992e40 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_stats.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xplatform_info.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,81 +32,102 @@ /*****************************************************************************/ /** * -* @file xtmrctr_stats.c +* @file xplatform_info.c * -* Contains function to get and clear statistics for the XTmrCtr component. +* This file contains information about hardware for which the code is built * * 
 * MODIFICATION HISTORY:
 *
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl  02/06/02 First release.
-* 1.10b mta  03/21/07 Updated for new coding style.
-* 2.00a ktn  10/30/09 Updated to use HAL API's.
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00  pkp  12/15/14 Initial release
+* 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
+*					  mode
 *
* ******************************************************************************/ /***************************** Include Files *********************************/ -#include "xtmrctr.h" +#include "xil_types.h" +#include "xplatform_info.h" /************************** Constant Definitions *****************************/ - /**************************** Type Definitions *******************************/ - /***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - - /************************** Variable Definitions *****************************/ +/************************** Function Prototypes ******************************/ + /*****************************************************************************/ /** * -* Get a copy of the XTmrCtrStats structure, which contains the current -* statistics for this driver. +* This API is used to provide information about platform * -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param StatsPtr is a pointer to a XTmrCtrStats structure which will get -* a copy of current statistics. +* @param None. * -* @return None. +* @return The information about platform defined in xplatform_info.h * -* @note None. +* @note None. * ******************************************************************************/ -void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr) +u32 XGetPlatform_Info() { - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(StatsPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - StatsPtr->Interrupts = InstancePtr->Stats.Interrupts; + u32 reg; +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) + return XPLAT_ZYNQ_ULTRA_MP; +#elif (__microblaze__) + return XPLAT_MICROBLAZE; +#else + return XPLAT_ZYNQ; +#endif } /*****************************************************************************/ /** * -* Clear the XTmrCtrStats structure for this driver. +* This API is used to provide information about zynq ultrascale MP platform * -* @param InstancePtr is a pointer to the XTmrCtr instance. +* @param None. * -* @return None. +* @return The information about zynq ultrascale MP platform defined in +* xplatform_info.h * -* @note None. +* @note None. * ******************************************************************************/ -void XTmrCtr_ClearStats(XTmrCtr * InstancePtr) +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +u32 XGet_Zynq_UltraMp_Platform_info() { - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - InstancePtr->Stats.Interrupts = 0; + u32 reg; + reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK); + return reg; } +#endif + +/*****************************************************************************/ +/** +* +* This API is used to provide information about PS Silicon version +* +* @param None. +* +* @return The information about PS Silicon version. +* +* @note None. +* +******************************************************************************/ +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +u32 XGetPSVersion_Info() +{ + u32 reg; + reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) + & XPS_VERSION_INFO_MASK); + return reg; +} +#endif diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_i.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xplatform_info.h similarity index 69% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_i.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xplatform_info.h index 362eeeff6..7028a83af 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_i.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xplatform_info.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,28 +32,14 @@ /*****************************************************************************/ /** * -* @file xintc_i.h +* @file xplatform_info.h * -* This file contains data which is shared between files and internal to the -* XIntc component. It is intended for internal use only. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b jhl  02/06/02 First release
-* 1.00b jhl  04/24/02 Moved register definitions to xintc_l.h
-* 1.00c rpm  10/17/03 New release. Removed extern of global, single instance
-*                     pointer.
-* 1.10c mta  03/21/07 Updated to new coding style
-* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs.
-*
+* This file contains definitions for various platforms available * ******************************************************************************/ -#ifndef XINTC_I_H /* prevent circular inclusions */ -#define XINTC_I_H /* by using protection macros */ +#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */ +#define XPLATFORM_INFO_H /* by using protection macros */ #ifdef __cplusplus extern "C" { @@ -62,29 +48,44 @@ extern "C" { /***************************** Include Files *********************************/ #include "xil_types.h" -#include "xil_assert.h" -#include "xintc.h" /************************** Constant Definitions *****************************/ +#define XPAR_CSU_BASEADDR 0xFFCA0000U +#define XPAR_CSU_VER_OFFSET 0x00000044U + +#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0 +#define XPLAT_ZYNQ_ULTRA_MP 0x1 +#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2 +#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3 +#define XPLAT_ZYNQ 0x4 +#define XPLAT_MICROBLAZE 0x5 + +#define XPS_VERSION_1 0x0 +#define XPS_VERSION_2 0x1 + +#define XPLAT_INFO_MASK (0xF) +#define XPS_VERSION_INFO_MASK (0xF) /**************************** Type Definitions *******************************/ - /***************** Macros (Inline Functions) Definitions *********************/ +u32 XGetPlatform_Info(); + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +u32 XGetPSVersion_Info(); +#endif + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +u32 XGet_Zynq_UltraMp_Platform_info(); +#endif /************************** Function Prototypes ******************************/ -/************************** Variable Definitions *****************************/ - -extern u32 XIntc_BitPosMask[]; - -extern XIntc_Config XIntc_ConfigTable[]; - #ifdef __cplusplus } #endif -#endif +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xstatus.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xstatus.h similarity index 99% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xstatus.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xstatus.h index 4452bb833..3c8670cb3 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xstatus.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/xstatus.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -416,7 +416,7 @@ extern "C" { /**************************** Type Definitions *******************************/ -typedef int XStatus; +typedef s32 XStatus; /***************** Macros (Inline Functions) Definitions *********************/ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/Makefile b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/Makefile deleted file mode 100644 index 20fb57c34..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES=*.c -INCLUDEFILES=*.h - -libs: - echo "Compiling tmrctr" - $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} - make clean - -include: - ${CP} $(INCLUDEFILES) $(INCLUDEDIR) - -clean: - rm -rf ${OUTS} - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr.c deleted file mode 100644 index 90e8c5bb1..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr.c +++ /dev/null @@ -1,522 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr.c -* -* Contains required functions for the XTmrCtr driver. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm  08/16/01 First release
-* 1.00b jhl  02/21/02 Repartitioned the driver for smaller files
-* 1.10b mta  03/21/07 Updated to new coding style
-* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
-*		      definitions.
-* 2.05a adk  15/05/13 Fixed the CR:693066
-*		      Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
-*		      XTmrCtr instance structure.
-*		      The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
-*		      the XTmrCtr_Start function.
-*		      The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
-*		      There will be no Initialization done in the
-*		      XTmrCtr_Initialize if both the timers have already started and
-*		      the XST_DEVICE_IS_STARTED Status is returned.
-*		      Removed the logic in the XTmrCtr_Initialize function
-*		      which was checking the Register Value to know whether
-*		      a timer has started or not.
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xparameters.h" -#include "xtmrctr.h" -#include "xtmrctr_i.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Initializes a specific timer/counter instance/driver. Initialize fields of -* the XTmrCtr structure, then reset the timer/counter.If a timer is already -* running then it is not initialized. -* -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param DeviceId is the unique id of the device controlled by this -* XTmrCtr component. Passing in a device id associates the -* generic XTmrCtr component to a specific device, as chosen by -* the caller or application developer. -* -* @return -* - XST_SUCCESS if initialization was successful -* - XST_DEVICE_IS_STARTED if the device has already been started -* - XST_DEVICE_NOT_FOUND if the device doesn't exist -* -* @note None. -* -******************************************************************************/ -int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId) -{ - XTmrCtr_Config *TmrCtrConfigPtr; - int TmrCtrNumber; - int TmrCtrLowIndex = 0; - int TmrCtrHighIndex = XTC_DEVICE_TIMER_COUNT; - - Xil_AssertNonvoid(InstancePtr != NULL); - - - /* - * If both the timers have already started, disallow the initialize and - * return a status indicating it is started. This allows the user to stop - * the device and reinitialize, but prevents a user from inadvertently - * initializing. - * In case one of the timers has not started then that particular timer - * will be initialized - */ - if ((InstancePtr->IsStartedTmrCtr0 == XIL_COMPONENT_IS_STARTED) && - (InstancePtr->IsStartedTmrCtr1 == XIL_COMPONENT_IS_STARTED)) { - return XST_DEVICE_IS_STARTED; - } - - - /* - * Ensure that only the timer which is NOT started can be initialized - */ - if ((InstancePtr->IsStartedTmrCtr0 == XIL_COMPONENT_IS_STARTED)) { - TmrCtrLowIndex = 1; - } else if ((InstancePtr->IsStartedTmrCtr1 == XIL_COMPONENT_IS_STARTED)) { - TmrCtrHighIndex = 1; - } else { - InstancePtr->IsStartedTmrCtr0 = 0; - InstancePtr->IsStartedTmrCtr1 = 0; - } - - - - /* - * Lookup the device configuration in the temporary CROM table. Use this - * configuration info down below when initializing this component. - */ - TmrCtrConfigPtr = XTmrCtr_LookupConfig(DeviceId); - - if (TmrCtrConfigPtr == (XTmrCtr_Config *) NULL) { - return XST_DEVICE_NOT_FOUND; - } - - /* - * Set some default values, including setting the callback - * handlers to stubs. - */ - InstancePtr->BaseAddress = TmrCtrConfigPtr->BaseAddress; - InstancePtr->Handler = NULL; - InstancePtr->CallBackRef = NULL; - - /* - * Clear the statistics for this driver - */ - InstancePtr->Stats.Interrupts = 0; - - /* Initialize the registers of each timer/counter in the device */ - - for (TmrCtrNumber = TmrCtrLowIndex; TmrCtrNumber < TmrCtrHighIndex; - TmrCtrNumber++) { - - /* - * Set the Compare register to 0 - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TLR_OFFSET, 0); - /* - * Reset the timer and the interrupt, the reset bit will need to - * be cleared after this - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK); - /* - * Set the control/status register to complete initialization by - * clearing the reset bit which was just set - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, 0); - } - - /* - * Indicate the instance is ready to use, successfully initialized - */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Starts the specified timer counter of the device such that it starts running. -* The timer counter is reset before it is started and the reset value is -* loaded into the timer counter. -* -* If interrupt mode is specified in the options, it is necessary for the caller -* to connect the interrupt handler of the timer/counter to the interrupt source, -* typically an interrupt controller, and enable the interrupt within the -* interrupt controller. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - u32 ControlStatusReg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the current register contents such that only the necessary bits - * of the register are modified in the following operations - */ - ControlStatusReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCSR_OFFSET); - /* - * Reset the timer counter such that it reloads from the compare - * register and the interrupt is cleared simultaneously, the interrupt - * can only be cleared after reset such that the interrupt condition is - * cleared - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - XTC_CSR_LOAD_MASK); - - - - /* - * Indicate that the timer is started before enabling it - */ - if (TmrCtrNumber == 0) { - InstancePtr->IsStartedTmrCtr0 = XIL_COMPONENT_IS_STARTED; - } else { - InstancePtr->IsStartedTmrCtr1 = XIL_COMPONENT_IS_STARTED; - } - - - /* - * Remove the reset condition such that the timer counter starts running - * with the value loaded from the compare register - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - ControlStatusReg | XTC_CSR_ENABLE_TMR_MASK); -} - -/*****************************************************************************/ -/** -* -* Stops the timer counter by disabling it. -* -* It is the callers' responsibility to disconnect the interrupt handler of the -* timer_counter from the interrupt source, typically an interrupt controller, -* and disable the interrupt within the interrupt controller. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - u32 ControlStatusReg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the current register contents - */ - ControlStatusReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCSR_OFFSET); - /* - * Disable the timer counter such that it's not running - */ - ControlStatusReg &= ~(XTC_CSR_ENABLE_TMR_MASK); - - /* - * Write out the updated value to the actual register. - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, ControlStatusReg); - - /* - * Indicate that the timer is stopped - */ - if (TmrCtrNumber == 0) { - InstancePtr->IsStartedTmrCtr0 = 0; - } else { - InstancePtr->IsStartedTmrCtr1 = 0; - } -} - -/*****************************************************************************/ -/** -* -* Get the current value of the specified timer counter. The timer counter -* may be either incrementing or decrementing based upon the current mode of -* operation. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The current value for the timer counter. -* -* @note None. -* -******************************************************************************/ -u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - return XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCR_OFFSET); -} - -/*****************************************************************************/ -/** -* -* Set the reset value for the specified timer counter. This is the value -* that is loaded into the timer counter when it is reset. This value is also -* loaded when the timer counter is started. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param ResetValue contains the value to be used to reset the timer -* counter. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber, - u32 ResetValue) -{ - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TLR_OFFSET, ResetValue); -} - -/*****************************************************************************/ -/** -* -* Returns the timer counter value that was captured the last time the external -* capture input was asserted. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The current capture value for the indicated timer counter. -* -* @note None. -* -*******************************************************************************/ -u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - return XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TLR_OFFSET); -} - -/*****************************************************************************/ -/** -* -* Resets the specified timer counter of the device. A reset causes the timer -* counter to set it's value to the reset value. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - u32 CounterControlReg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read current contents of the register so it won't be destroyed - */ - CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCSR_OFFSET); - /* - * Reset the timer by toggling the reset bit in the register - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - CounterControlReg | XTC_CSR_LOAD_MASK); - - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, CounterControlReg); -} - -/*****************************************************************************/ -/** -* -* Checks if the specified timer counter of the device has expired. In capture -* mode, expired is defined as a capture occurred. In compare mode, expired is -* defined as the timer counter rolled over/under for up/down counting. -* -* When interrupts are enabled, the expiration causes an interrupt. This function -* is typically used to poll a timer counter to determine when it has expired. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return TRUE if the timer has expired, and FALSE otherwise. -* -* @note None. -* -******************************************************************************/ -int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - u32 CounterControlReg; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Check if timer is expired - */ - CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCSR_OFFSET); - - return ((CounterControlReg & XTC_CSR_INT_OCCURED_MASK) == - XTC_CSR_INT_OCCURED_MASK); -} - -/***************************************************************************** -* -* Looks up the device configuration based on the unique device ID. The table -* TmrCtrConfigTable contains the configuration info for each device in the -* system. -* -* @param DeviceId is the unique device ID to search for in the config -* table. -* -* @return A pointer to the configuration that matches the given device ID, -* or NULL if no match is found. -* -* @note None. -* -******************************************************************************/ -XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId) -{ - XTmrCtr_Config *CfgPtr = NULL; - int Index; - - for (Index = 0; Index < XPAR_XTMRCTR_NUM_INSTANCES; Index++) { - if (XTmrCtr_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XTmrCtr_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr.h deleted file mode 100644 index 1f6726570..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr.h +++ /dev/null @@ -1,301 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr.h -* -* The Xilinx timer/counter component. This component supports the Xilinx -* timer/counter. More detailed description of the driver operation can -* be found in the xtmrctr.c file. -* -* The Xilinx timer/counter supports the following features: -* - Polled mode. -* - Interrupt driven mode -* - enabling and disabling specific timers -* - PWM operation -* - Cascade Operation (This is to be used for getting a 64 bit timer and this -* feature is present in the latest versions of the axi_timer IP) -* -* The driver does not currently support the PWM operation of the device. -* -* The timer counter operates in 2 primary modes, compare and capture. In -* either mode, the timer counter may count up or down, with up being the -* default. -* -* Compare mode is typically used for creating a single time period or multiple -* repeating time periods in the auto reload mode, such as a periodic interrupt. -* When started, the timer counter loads an initial value, referred to as the -* compare value, into the timer counter and starts counting down or up. The -* timer counter expires when it rolls over/under depending upon the mode of -* counting. An external compare output signal may be configured such that a -* pulse is generated with this signal when it hits the compare value. -* -* Capture mode is typically used for measuring the time period between -* external events. This mode uses an external capture input signal to cause -* the value of the timer counter to be captured. When started, the timer -* counter loads an initial value, referred to as the compare value, - -* The timer can be configured to either cause an interrupt when the count -* reaches the compare value in compare mode or latch the current count -* value in the capture register when an external input is asserted -* in capture mode. The external capture input can be enabled/disabled using the -* XTmrCtr_SetOptions function. While in compare mode, it is also possible to -* drive an external output when the compare value is reached in the count -* register The external compare output can be enabled/disabled using the -* XTmrCtr_SetOptions function. -* -* Interrupts -* -* It is the responsibility of the application to connect the interrupt -* handler of the timer/counter to the interrupt source. The interrupt -* handler function, XTmrCtr_InterruptHandler, is visible such that the user -* can connect it to the interrupt source. Note that this interrupt handler -* does not provide interrupt context save and restore processing, the user -* must perform this processing. -* -* The driver services interrupts and passes timeouts to the upper layer -* software through callback functions. The upper layer software must register -* its callback functions during initialization. The driver requires callback -* functions for timers. -* -* @note -* The default settings for the timers are: -* - Interrupt generation disabled -* - Count up mode -* - Compare mode -* - Hold counter (will not reload the timer) -* - External compare output disabled -* - External capture input disabled -* - Pulse width modulation disabled -* - Timer disabled, waits for Start function to be called -*

-* A timer counter device may contain multiple timer counters. The symbol -* XTC_DEVICE_TIMER_COUNT defines the number of timer counters in the device. -* The device currently contains 2 timer counters. -*

-* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads -* or thread mutual exclusion, virtual memory, or cache control must be -* satisfied by the layer above this driver. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm  08/16/01 First release
-* 1.00b jhl  02/21/02 Repartitioned the driver for smaller files
-* 1.10b mta  03/21/07 Updated to new coding style.
-* 1.11a sdm  08/22/08 Removed support for static interrupt handlers from the MDD
-*		      file
-* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
-*		      definitions.
-* 2.01a ktn  07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
-*		      for naming consistency (CR 559142).
-* 2.02a sdm  09/28/10 Updated the driver tcl to generate the xparameters
-*		      for the timer clock frequency (CR 572679).
-* 2.03a rvo  11/30/10 Added check to see if interrupt is enabled before further
-*		      processing for CR 584557.
-* 2.04a sdm  07/12/11 Added support for cascade mode operation.
-* 		      The cascade mode of operation is present in the latest
-*		      versions of the axi_timer IP. Please check the HW
-*		      Datasheet to see whether this feature is present in the
-*		      version of the IP that you are using.
-* 2.05a adk  15/05/13 Fixed the CR:693066
-*		      Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
-*		      XTmrCtr instance structure.
-*		      The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
-*		      the XTmrCtr_Start function.
-*		      The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
-*		      There will be no Initialization done in the
-*		      XTmrCtr_Initialize if both the timers have already started and
-*		      the XST_DEVICE_IS_STARTED Status is returned.
-*		      Removed the logic in the XTmrCtr_Initialize function
-*		      which was checking the Register Value to know whether
-*		      a timer has started or not.
-* 3.0   adk  19/12/13 Updated as per the New Tcl API's
-*
-* -******************************************************************************/ - -#ifndef XTMRCTR_H /* prevent circular inclusions */ -#define XTMRCTR_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xtmrctr_l.h" - -/************************** Constant Definitions *****************************/ - -/** - * @name Configuration options - * These options are used in XTmrCtr_SetOptions() and XTmrCtr_GetOptions() - * @{ - */ -/** - * Used to configure the timer counter device. - * 
- * XTC_CASCADE_MODE_OPTION	Enables the Cascade Mode only valid for TCSRO.
- * XTC_ENABLE_ALL_OPTION	Enables all timer counters at once.
- * XTC_DOWN_COUNT_OPTION	Configures the timer counter to count down from
- *				start value, the default is to count up.
- * XTC_CAPTURE_MODE_OPTION	Configures the timer to capture the timer
- *				counter value when the external capture line is
- *				asserted. The default mode is compare mode.
- * XTC_INT_MODE_OPTION		Enables the timer counter interrupt output.
- * XTC_AUTO_RELOAD_OPTION	In compare mode, configures the timer counter to
- *				reload from the compare value. The default mode
- *				causes the timer counter to hold when the
- *				compare value is hit.
- *				In capture mode, configures the timer counter to
- *				not hold the previous capture value if a new
- *				event occurs. The default mode cause the timer
- *				counter to hold the capture value until
- *				recognized.
- * XTC_EXT_COMPARE_OPTION	Enables the external compare output signal.
- *
- */ -#define XTC_CASCADE_MODE_OPTION 0x00000080UL -#define XTC_ENABLE_ALL_OPTION 0x00000040UL -#define XTC_DOWN_COUNT_OPTION 0x00000020UL -#define XTC_CAPTURE_MODE_OPTION 0x00000010UL -#define XTC_INT_MODE_OPTION 0x00000008UL -#define XTC_AUTO_RELOAD_OPTION 0x00000004UL -#define XTC_EXT_COMPARE_OPTION 0x00000002UL -/*@}*/ - -/**************************** Type Definitions *******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress;/**< Register base address */ -} XTmrCtr_Config; - -/** - * Signature for the callback function. - * - * @param CallBackRef is a callback reference passed in by the upper layer - * when setting the callback functions, and passed back to the - * upper layer when the callback is invoked. Its type is - * unimportant to the driver, so it is a void pointer. - * @param TmrCtrNumber is the number of the timer/counter within the - * device. The device typically contains at least two - * timer/counters. The timer number is a zero based number with a - * range of 0 to (XTC_DEVICE_TIMER_COUNT - 1). - */ -typedef void (*XTmrCtr_Handler) (void *CallBackRef, u8 TmrCtrNumber); - - -/** - * Timer/Counter statistics - */ -typedef struct { - u32 Interrupts; /**< The number of interrupts that have occurred */ -} XTmrCtrStats; - -/** - * The XTmrCtr driver instance data. The user is required to allocate a - * variable of this type for every timer/counter device in the system. A - * pointer to a variable of this type is then passed to the driver API - * functions. - */ -typedef struct { - XTmrCtrStats Stats; /**< Component Statistics */ - u32 BaseAddress; /**< Base address of registers */ - u32 IsReady; /**< Device is initialized and ready */ - u32 IsStartedTmrCtr0; /**< Is Timer Counter 0 started */ - u32 IsStartedTmrCtr1; /**< Is Timer Counter 1 started */ - - XTmrCtr_Handler Handler; /**< Callback function */ - void *CallBackRef; /**< Callback reference for handler */ -} XTmrCtr; - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -/* - * Required functions, in file xtmrctr.c - */ -int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId); -void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber, - u32 ResetValue); -u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId); - -/* - * Functions for options, in file xtmrctr_options.c - */ -void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options); -u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber); - -/* - * Functions for statistics, in file xtmrctr_stats.c - */ -void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr); -void XTmrCtr_ClearStats(XTmrCtr * InstancePtr); - -/* - * Functions for self-test, in file xtmrctr_selftest.c - */ -int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber); - -/* - * Functions for interrupts, in file xtmrctr_intr.c - */ -void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr, - void *CallBackRef); -void XTmrCtr_InterruptHandler(void *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_g.c deleted file mode 100644 index 002eff4d7..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_g.c +++ /dev/null @@ -1,55 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by HSI. -* Version: -* DO NOT EDIT. -* -* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* -*Permission is hereby granted, free of charge, to any person obtaining a copy -*of this software and associated documentation files (the Software), to deal -*in the Software without restriction, including without limitation the rights -*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -*copies of the Software, and to permit persons to whom the Software is -*furnished to do so, subject to the following conditions: -* -*The above copyright notice and this permission notice shall be included in -*all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -*(a) running on a Xilinx device, or -*(b) that interact with a Xilinx device through a bus or interconnect. -* -*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*Except as contained in this notice, the name of the Xilinx shall not be used -*in advertising or otherwise to promote the sale, use or other dealings in -*this Software without prior written authorization from Xilinx. -* - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xtmrctr.h" - -/* -* The configuration table for devices -*/ - -XTmrCtr_Config XTmrCtr_ConfigTable[] = -{ - { - XPAR_AXI_TIMER_0_DEVICE_ID, - XPAR_AXI_TIMER_0_BASEADDR - } -}; - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_intr.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_intr.c deleted file mode 100644 index f36fb0bd3..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_intr.c +++ /dev/null @@ -1,230 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_intr.c -* -* Contains interrupt-related functions for the XTmrCtr component. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl  02/06/02 First release
-* 1.10b mta  03/21/07 Updated to new coding style
-* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
-*		      definitions.
-* 2.03a rvo  11/30/10 Added check to see if interrupt is enabled before further
-*		      processing for CR 584557.
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xtmrctr.h" - - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Sets the timer callback function, which the driver calls when the specified -* timer times out. -* -* @param InstancePtr is a pointer to the XTmrCtr instance . -* @param CallBackRef is the upper layer callback reference passed back -* when the callback function is invoked. -* @param FuncPtr is the pointer to the callback function. -* -* @return None. -* -* @note -* -* The handler is called within interrupt context so the function that is -* called should either be short or pass the more extensive processing off -* to another task to allow the interrupt to return and normal processing -* to continue. -* -******************************************************************************/ -void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr, - void *CallBackRef) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(FuncPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - InstancePtr->Handler = FuncPtr; - InstancePtr->CallBackRef = CallBackRef; -} - -/*****************************************************************************/ -/** -* -* Interrupt Service Routine (ISR) for the driver. This function only performs -* processing for the device and does not save and restore the interrupt context. -* -* @param InstancePtr contains a pointer to the timer/counter instance for -* the interrupt. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_InterruptHandler(void *InstancePtr) -{ - XTmrCtr *TmrCtrPtr = NULL; - u8 TmrCtrNumber; - u32 ControlStatusReg; - - /* - * Verify that each of the inputs are valid. - */ - Xil_AssertVoid(InstancePtr != NULL); - - /* - * Convert the non-typed pointer to an timer/counter instance pointer - * such that there is access to the timer/counter - */ - TmrCtrPtr = (XTmrCtr *) InstancePtr; - - /* - * Loop thru each timer counter in the device and call the callback - * function for each timer which has caused an interrupt - */ - for (TmrCtrNumber = 0; - TmrCtrNumber < XTC_DEVICE_TIMER_COUNT; TmrCtrNumber++) { - - ControlStatusReg = XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress, - TmrCtrNumber, - XTC_TCSR_OFFSET); - /* - * Check if interrupt is enabled - */ - if (ControlStatusReg & XTC_CSR_ENABLE_INT_MASK) { - - /* - * Check if timer expired and interrupt occured - */ - if (ControlStatusReg & XTC_CSR_INT_OCCURED_MASK) { - /* - * Increment statistics for the number of - * interrupts and call the callback to handle - * any application specific processing - */ - TmrCtrPtr->Stats.Interrupts++; - TmrCtrPtr->Handler(TmrCtrPtr->CallBackRef, - TmrCtrNumber); - /* - * Read the new Control/Status Register content. - */ - ControlStatusReg = - XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress, - TmrCtrNumber, - XTC_TCSR_OFFSET); - /* - * If in compare mode and a single shot rather - * than auto reload mode then disable the timer - * and reset it such so that the interrupt can - * be acknowledged, this should be only temporary - * till the hardware is fixed - */ - if (((ControlStatusReg & - XTC_CSR_AUTO_RELOAD_MASK) == 0) && - ((ControlStatusReg & - XTC_CSR_CAPTURE_MODE_MASK)== 0)) { - /* - * Disable the timer counter and - * reset it such that the timer - * counter is loaded with the - * reset value allowing the - * interrupt to be acknowledged - */ - ControlStatusReg &= - ~XTC_CSR_ENABLE_TMR_MASK; - - XTmrCtr_WriteReg( - TmrCtrPtr->BaseAddress, - TmrCtrNumber, - XTC_TCSR_OFFSET, - ControlStatusReg | - XTC_CSR_LOAD_MASK); - - /* - * Clear the reset condition, - * the reset bit must be - * manually cleared by a 2nd write - * to the register - */ - XTmrCtr_WriteReg( - TmrCtrPtr->BaseAddress, - TmrCtrNumber, - XTC_TCSR_OFFSET, - ControlStatusReg); - } - - /* - * Acknowledge the interrupt by clearing the - * interrupt bit in the timer control status - * register, this is done after calling the - * handler so the application could call - * IsExpired, the interrupt is cleared by - * writing a 1 to the interrupt bit of the - * register without changing any of the other - * bits - */ - XTmrCtr_WriteReg(TmrCtrPtr->BaseAddress, - TmrCtrNumber, - XTC_TCSR_OFFSET, - ControlStatusReg | - XTC_CSR_INT_OCCURED_MASK); - } - } - } -} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_l.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_l.c deleted file mode 100644 index acdb5d511..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_l.c +++ /dev/null @@ -1,76 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_l.c -* -* This file contains low-level driver functions that can be used to access the -* device. The user should refer to the hardware device specification for more -* details of the device operation. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl  04/24/02 First release
-* 1.10b mta  03/21/07 Updated to new coding style
-* 2.00a ktn  10/30/09 Updated to use HAL API's
-*
-* -******************************************************************************/ - - -/***************************** Include Files *********************************/ - -#include "xtmrctr_l.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - -/* The following table contains the offset from the base address of a timer - * counter device for each timer counter. A single device may contain multiple - * timer counters and the functions specify which one to operate on. - */ -u8 XTmrCtr_Offsets[] = { 0, XTC_TIMER_COUNTER_OFFSET }; diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_l.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_l.h deleted file mode 100644 index 8d1a65f68..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_l.h +++ /dev/null @@ -1,426 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_l.h -* -* This header file contains identifiers and low-level driver functions (or -* macros) that can be used to access the device. The user should refer to the -* hardware device specification for more details of the device operation. -* High-level driver functions are defined in xtmrctr.h. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl  04/24/02 First release
-* 1.10b mta  03/21/07 Updated to new coding style
-* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
-*		      definitions.
-* 2.01a ktn  07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
-*		      for naming consistency (CR 559142).
-* 2.04a sdm  07/12/11 Added the CASC mode bit in the TCSRO register for the
-*		      cascade mode operation.
-*		      The cascade mode of operation is present in the latest
-*		      versions of the axi_timer IP. Please check the HW
-*		      Datasheet to see whether this feature is present in the
-*		      version of the IP that you are using.
-*
-* -******************************************************************************/ - -#ifndef XTMRCTR_L_H /* prevent circular inclusions */ -#define XTMRCTR_L_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** - * Defines the number of timer counters within a single hardware device. This - * number is not currently parameterized in the hardware but may be in the - * future. - */ -#define XTC_DEVICE_TIMER_COUNT 2 - -/* Each timer counter consumes 16 bytes of address space */ - -#define XTC_TIMER_COUNTER_OFFSET 16 - -/** @name Register Offset Definitions - * Register offsets within a timer counter, there are multiple - * timer counters within a single device - * @{ - */ - -#define XTC_TCSR_OFFSET 0 /**< Control/Status register */ -#define XTC_TLR_OFFSET 4 /**< Load register */ -#define XTC_TCR_OFFSET 8 /**< Timer counter register */ - -/* @} */ - -/** @name Control Status Register Bit Definitions - * Control Status Register bit masks - * Used to configure the timer counter device. - * @{ - */ - -#define XTC_CSR_CASC_MASK 0x00000800 /**< Cascade Mode */ -#define XTC_CSR_ENABLE_ALL_MASK 0x00000400 /**< Enables all timer - counters */ -#define XTC_CSR_ENABLE_PWM_MASK 0x00000200 /**< Enables the Pulse Width - Modulation */ -#define XTC_CSR_INT_OCCURED_MASK 0x00000100 /**< If bit is set, an - interrupt has occured. - If set and '1' is - written to this bit - position, bit is - cleared. */ -#define XTC_CSR_ENABLE_TMR_MASK 0x00000080 /**< Enables only the - specific timer */ -#define XTC_CSR_ENABLE_INT_MASK 0x00000040 /**< Enables the interrupt - output. */ -#define XTC_CSR_LOAD_MASK 0x00000020 /**< Loads the timer using - the load value provided - earlier in the Load - Register, - XTC_TLR_OFFSET. */ -#define XTC_CSR_AUTO_RELOAD_MASK 0x00000010 /**< In compare mode, - configures - the timer counter to - reload from the - Load Register. The - default mode - causes the timer counter - to hold when the compare - value is hit. In capture - mode, configures the - timer counter to not - hold the previous - capture value if a new - event occurs. The - default mode cause the - timer counter to hold - the capture value until - recognized. */ -#define XTC_CSR_EXT_CAPTURE_MASK 0x00000008 /**< Enables the - external input - to the timer counter. */ -#define XTC_CSR_EXT_GENERATE_MASK 0x00000004 /**< Enables the - external generate output - for the timer. */ -#define XTC_CSR_DOWN_COUNT_MASK 0x00000002 /**< Configures the timer - counter to count down - from start value, the - default is to count - up.*/ -#define XTC_CSR_CAPTURE_MODE_MASK 0x00000001 /**< Enables the timer to - capture the timer - counter value when the - external capture line is - asserted. The default - mode is compare mode.*/ -/* @} */ - -/**************************** Type Definitions *******************************/ - -extern u8 XTmrCtr_Offsets[]; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** -* Read one of the timer counter registers. -* -* @param BaseAddress contains the base address of the timer counter -* device. -* @param TmrCtrNumber contains the specific timer counter within the -* device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegOffset contains the offset from the 1st register of the timer -* counter to select the specific register of the timer counter. -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber, - unsigned RegOffset); -******************************************************************************/ -#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ - Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ - (RegOffset)) - -#ifndef XTimerCtr_ReadReg -#define XTimerCtr_ReadReg XTmrCtr_ReadReg -#endif - -/*****************************************************************************/ -/** -* Write a specified value to a register of a timer counter. -* -* @param BaseAddress is the base address of the timer counter device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegOffset contain the offset from the 1st register of the timer -* counter to select the specific register of the timer counter. -* @param ValueToWrite is the 32 bit value to be written to the register. -* -* @note C-Style signature: -* void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber, -* unsigned RegOffset, u32 ValueToWrite); -******************************************************************************/ -#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ - Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ - (RegOffset)), (ValueToWrite)) - -/****************************************************************************/ -/** -* -* Set the Control Status Register of a timer counter to the specified value. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegisterValue is the 32 bit value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_SetControlStatusReg(u32 BaseAddress, -* u8 TmrCtrNumber,u32 RegisterValue); -*****************************************************************************/ -#define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the Control Status Register of a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, -* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress, -* u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber) \ - XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) - -/****************************************************************************/ -/** -* -* Get the Timer Counter Register of a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, -* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress, -* u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber) \ - XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \ - -/****************************************************************************/ -/** -* -* Set the Load Register of a timer counter to the specified value. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegisterValue is the 32 bit value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber, -* u32 RegisterValue); -*****************************************************************************/ -#define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \ - (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the Load Register of a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber) \ -XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET) - -/****************************************************************************/ -/** -* -* Enable a timer counter such that it starts running. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_Enable(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \ - XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK)) - -/****************************************************************************/ -/** -* -* Disable a timer counter such that it stops running. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, -* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_Disable(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\ - XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK)) - -/****************************************************************************/ -/** -* -* Enable the interrupt for a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \ - XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK)) - -/****************************************************************************/ -/** -* -* Disable the interrupt for a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \ - XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_INT_MASK)) - -/****************************************************************************/ -/** -* -* Cause the timer counter to load it's Timer Counter Register with the value -* in the Load Register. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress, - u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\ - XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK)) - -/****************************************************************************/ -/** -* -* Determine if a timer counter event has occurred. Events are defined to be -* when a capture has occurred or the counter has roller over. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @note C-Style signature: -* int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber) \ - ((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \ - XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) == \ - XTC_CSR_INT_OCCURED_MASK) - -/************************** Function Prototypes ******************************/ -/************************** Variable Definitions *****************************/ -#ifdef __cplusplus -} -#endif -#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_options.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_options.c deleted file mode 100644 index cc20dd007..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_options.c +++ /dev/null @@ -1,214 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_options.c -* -* Contains configuration options functions for the XTmrCtr component. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl  02/06/02 First release
-* 1.10b mta  03/21/07 Updated to new coding style
-* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
-*		      definitions.
-* 2.04a sdm  07/12/11 Added support for the cascade mode operation.
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xtmrctr.h" -#include "xtmrctr_i.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - -/* - * The following data type maps an option to a register mask such that getting - * and setting the options may be table driven. - */ -typedef struct { - u32 Option; - u32 Mask; -} Mapping; - -/* - * Create the table which contains options which are to be processed to get/set - * the options. These options are table driven to allow easy maintenance and - * expansion of the options. - */ -static Mapping OptionsTable[] = { - {XTC_CASCADE_MODE_OPTION, XTC_CSR_CASC_MASK}, - {XTC_ENABLE_ALL_OPTION, XTC_CSR_ENABLE_ALL_MASK}, - {XTC_DOWN_COUNT_OPTION, XTC_CSR_DOWN_COUNT_MASK}, - {XTC_CAPTURE_MODE_OPTION, XTC_CSR_CAPTURE_MODE_MASK | - XTC_CSR_EXT_CAPTURE_MASK}, - {XTC_INT_MODE_OPTION, XTC_CSR_ENABLE_INT_MASK}, - {XTC_AUTO_RELOAD_OPTION, XTC_CSR_AUTO_RELOAD_MASK}, - {XTC_EXT_COMPARE_OPTION, XTC_CSR_EXT_GENERATE_MASK} -}; - -/* Create a constant for the number of entries in the table */ - -#define XTC_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping)) - -/*****************************************************************************/ -/** -* -* Enables the specified options for the specified timer counter. This function -* sets the options without regard to the current options of the driver. To -* prevent a loss of the current options, the user should call -* XTmrCtr_GetOptions() prior to this function and modify the retrieved options -* to pass into this function to prevent loss of the current options. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param Options contains the desired options to be set or cleared. -* Setting the option to '1' enables the option, clearing the to -* '0' disables the option. The options are bit masks such that -* multiple options may be set or cleared. The options are -* described in xtmrctr.h. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options) -{ - u32 CounterControlReg = 0; - u32 Index; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Loop through the Options table, turning the enable on or off - * depending on whether the bit is set in the incoming Options flag. - */ - - for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) { - if (Options & OptionsTable[Index].Option) { - - /* - * Turn the option on - */ - CounterControlReg |= OptionsTable[Index].Mask; - } - else { - /* - * Turn the option off - */ - CounterControlReg &= ~OptionsTable[Index].Mask; - } - } - - /* - * Write out the updated value to the actual register - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, CounterControlReg); -} - -/*****************************************************************************/ -/** -* -* Get the options for the specified timer counter. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return -* -* The currently set options. An option which is set to a '1' is enabled and -* set to a '0' is disabled. The options are bit masks such that multiple -* options may be set or cleared. The options are described in xtmrctr.h. -* -* @note None. -* -******************************************************************************/ -u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - - u32 Options = 0; - u32 CounterControlReg; - u32 Index; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the current contents of the control status register to allow - * the current options to be determined - */ - CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCSR_OFFSET); - /* - * Loop through the Options table, turning the enable on or off - * depending on whether the bit is set in the current register settings. - */ - for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) { - if (CounterControlReg & OptionsTable[Index].Mask) { - Options |= OptionsTable[Index].Option; /* turn it on */ - } - else { - Options &= ~OptionsTable[Index].Option; /* turn it off */ - } - } - - return Options; -} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_selftest.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_selftest.c deleted file mode 100644 index 4b2a6a861..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_selftest.c +++ /dev/null @@ -1,163 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_selftest.c -* -* Contains diagnostic/self-test functions for the XTmrCtr component. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl  02/06/02 First release
-* 1.10b mta  03/21/07 Updated to new coding style
-* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
-*		      definitions.
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_io.h" -#include "xtmrctr.h" -#include "xtmrctr_i.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Runs a self-test on the driver/device. This test verifies that the specified -* timer counter of the device can be enabled and increments. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return -* - XST_SUCCESS if self-test was successful -* - XST_FAILURE if the timer is not incrementing. -* -* @note -* -* This is a destructive test using the provided timer. The current settings -* of the timer are returned to the initialized values and all settings at the -* time this function is called are overwritten. -* -******************************************************************************/ -int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - u32 TimerCount1 = 0; - u32 TimerCount2 = 0; - u16 Count = 0; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Set the Capture register to 0 - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TLR_OFFSET, 0); - - /* - * Reset the timer and the interrupt - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK); - - /* - * Set the control/status register to enable timer - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, XTC_CSR_ENABLE_TMR_MASK); - - /* - * Read the timer - */ - TimerCount1 = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCR_OFFSET); - /* - * Make sure timer is incrementing if the Count rolls over to zero - * and the timer still has not incremented an error is returned - */ - - do { - TimerCount2 = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCR_OFFSET); - Count++; - } - while ((TimerCount1 == TimerCount2) && (Count != 0)); - - /* - * Reset the timer and the interrupt - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK); - - /* - * Set the control/status register to 0 to complete initialization - * this disables the timer completely and allows it to be used again - */ - - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, 0); - - if (TimerCount1 == TimerCount2) { - return XST_FAILURE; - } - else { - return XST_SUCCESS; - } -} diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/Makefile b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/Makefile similarity index 100% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/Makefile rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/Makefile diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite.c similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite.c index da0e781c2..4be03cdbf 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,8 @@ /** * * @file xuartlite.c +* @addtogroup uartlite_v3_1 +* @{ * * Contains required functions for the XUartLite driver. See the xuartlite.h * header file for more details on this driver. @@ -67,6 +69,12 @@ * 2.01a adk 18/04/13 Updated the code to avoid unused variable * warnings when compiling with the -Wextra -Wall flags * In the file xuartlite.c. CR:704999. +* 3.1 nsk 21/07/15 Updated XUartLite_ReceiveBuffer function to update the +* receive data into user buffer in critical region. +* CR#865787. +* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototype of XUartLite_CfgInitialize API. +* * * *****************************************************************************/ @@ -126,7 +134,7 @@ static void StubHandler(void *CallBackRef, unsigned int ByteCount); * *****************************************************************************/ int XUartLite_CfgInitialize(XUartLite *InstancePtr, XUartLite_Config *Config, - u32 EffectiveAddr) + UINTPTR EffectiveAddr) { (void) Config; /* @@ -574,8 +582,16 @@ unsigned int XUartLite_SendBuffer(XUartLite *InstancePtr) unsigned int XUartLite_ReceiveBuffer(XUartLite *InstancePtr) { u8 StatusRegister; + u8 StatusRegisterVal; unsigned int ReceivedCount = 0; + /* + * Enter a critical region by disabling all the UART interrupts to allow + * this call to stop a previous operation that may be interrupt driven + */ + StatusRegisterVal = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress); + XUartLite_WriteReg(InstancePtr->RegBaseAddress, + XUL_CONTROL_REG_OFFSET, 0); /* * Loop until there is not more data buffered by the UART or the * specified number of bytes is received @@ -611,14 +627,6 @@ unsigned int XUartLite_ReceiveBuffer(XUartLite *InstancePtr) } } - /* - * Enter a critical region by disabling all the UART interrupts to allow - * this call to stop a previous operation that may be interrupt driven - */ - StatusRegister = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress); - XUartLite_WriteReg(InstancePtr->RegBaseAddress, - XUL_CONTROL_REG_OFFSET, 0); - /* * Update the receive buffer to reflect the number of bytes that was * received @@ -635,12 +643,13 @@ unsigned int XUartLite_ReceiveBuffer(XUartLite *InstancePtr) * Restore the interrupt enable register to it's previous value such * that the critical region is exited */ - StatusRegister &= XUL_CR_ENABLE_INTR; + StatusRegisterVal &= XUL_CR_ENABLE_INTR; XUartLite_WriteReg(InstancePtr->RegBaseAddress, - XUL_CONTROL_REG_OFFSET, StatusRegister); + XUL_CONTROL_REG_OFFSET, StatusRegisterVal); return ReceivedCount; } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite.h similarity index 95% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite.h index bb382541a..dd18b9872 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,9 @@ /** * * @file xuartlite.h +* @addtogroup uartlite_v3_1 +* @{ +* @details * * This component contains the implementation of the XUartLite component which is * the driver for the Xilinx UART Lite device. This UART is a minimal hardware @@ -131,6 +134,11 @@ * 3.0 adk 17/12/13 Fixed CR:741186,761863 Changes are made in the file * xuartlite_selftest.c * 3.0 adk 19/12/13 Update the driver as per new TCL API's +* 3.1 nsk 21/07/15 Updated XUartLite_ReceiveBuffer function in xuartlite.c +* to update the receive data into user buffer in critical +* region.CR#865787. +* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototype of XUartLite_CfgInitialize API. * * * @@ -191,7 +199,7 @@ typedef struct { */ typedef struct { u16 DeviceId; /**< Unique ID of device */ - u32 RegBaseAddr; /**< Register base address */ + UINTPTR RegBaseAddr; /**< Register base address */ u32 BaudRate; /**< Fixed baud rate */ u8 UseParity; /**< Parity generator enabled when TRUE */ u8 ParityOdd; /**< Parity generated is odd when TRUE, even @@ -206,7 +214,7 @@ typedef struct { */ typedef struct { XUartLite_Stats Stats; /* Component Statistics */ - u32 RegBaseAddress; /* Base address of registers */ + UINTPTR RegBaseAddress; /* Base address of registers */ u32 IsReady; /* Device is initialized and ready */ XUartLite_Buffer SendBuffer; @@ -235,7 +243,7 @@ XUartLite_Config *XUartLite_LookupConfig(u16 DeviceId); */ int XUartLite_CfgInitialize(XUartLite *InstancePtr, XUartLite_Config *Config, - u32 EffectiveAddr); + UINTPTR EffectiveAddr); void XUartLite_ResetFifos(XUartLite *InstancePtr); @@ -276,3 +284,4 @@ void XUartLite_InterruptHandler(XUartLite *InstancePtr); #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_g.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c index a282809b1..1edd414e3 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_g.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -22,8 +22,8 @@ * *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_i.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_i.h similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_i.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_i.h index 8ae56bbe3..c28b830d0 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_i.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_i.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,8 @@ /** * * @file xuartlite_i.h +* @addtogroup uartlite_v3_1 +* @{ * * Contains data which is shared between the files of the XUartLite component. * It is intended for internal use only. @@ -120,3 +122,4 @@ unsigned int XUartLite_ReceiveBuffer(XUartLite *InstancePtr); #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_intr.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_intr.c similarity index 99% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_intr.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_intr.c index cd7c5da29..373ca5417 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_intr.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_intr.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,8 @@ /** * * @file xuartlite_intr.c +* @addtogroup uartlite_v3_1 +* @{ * * This file contains interrupt-related functions for the UART Lite component * (XUartLite). @@ -330,3 +332,4 @@ void XUartLite_EnableInterrupt(XUartLite *InstancePtr) XUL_CONTROL_REG_OFFSET, XUL_CR_ENABLE_INTR); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_l.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_l.c similarity index 90% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_l.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_l.c index eed69b774..bbb3922dc 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_l.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_l.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,8 @@ /** * * @file xuartlite_l.c +* @addtogroup uartlite_v3_1 +* @{ * * This file contains low-level driver functions that can be used to access the * device. The user should refer to the hardware device specification for more @@ -46,6 +48,9 @@ * 1.00b rpm 04/25/02 First release * 1.12a rpm 07/16/07 Fixed arg type for RecvByte * 2.00a ktn 10/20/09 The macros have been renamed to remove _m from the name. +* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototypes of XUartLite_SendByte, +* XUartLite_RecvByte APIs. * * ******************************************************************************/ @@ -84,7 +89,7 @@ * @note None. * ******************************************************************************/ -void XUartLite_SendByte(u32 BaseAddress, u8 Data) +void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data) { while (XUartLite_IsTransmitFull(BaseAddress)); @@ -106,10 +111,11 @@ void XUartLite_SendByte(u32 BaseAddress, u8 Data) * @note None. * ******************************************************************************/ -u8 XUartLite_RecvByte(u32 BaseAddress) +u8 XUartLite_RecvByte(UINTPTR BaseAddress) { while (XUartLite_IsReceiveEmpty(BaseAddress)); return (u8)XUartLite_ReadReg(BaseAddress, XUL_RX_FIFO_OFFSET); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_l.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_l.h similarity index 96% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_l.h rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_l.h index 9c4b34c6e..6a5307c4b 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_l.h +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_l.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,8 @@ /** * * @file xuartlite_l.h +* @addtogroup uartlite_v3_1 +* @{ * * This header file contains identifiers and low-level driver functions (or * macros) that can be used to access the device. High-level driver functions @@ -50,6 +52,9 @@ * 1.13a sv 01/21/08 Updated driver to support access through DCR bus * 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been * renamed to remove _m from the name. +* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototypes of XUartLite_SendByte, +* XUartLite_RecvByte APIs. * * *****************************************************************************/ @@ -318,8 +323,8 @@ extern "C" { /************************** Function Prototypes *****************************/ -void XUartLite_SendByte(u32 BaseAddress, u8 Data); -u8 XUartLite_RecvByte(u32 BaseAddress); +void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data); +u8 XUartLite_RecvByte(UINTPTR BaseAddress); #ifdef __cplusplus } @@ -328,3 +333,4 @@ u8 XUartLite_RecvByte(u32 BaseAddress); #endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_selftest.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_selftest.c similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_selftest.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_selftest.c index 4c39a2d33..7a53fc78f 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_selftest.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_selftest.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,8 @@ /** * * @file xuartlite_selftest.c +* @addtogroup uartlite_v3_1 +* @{ * * This file contains the self-test functions for the UART Lite component * (XUartLite). @@ -135,3 +137,4 @@ int XUartLite_SelfTest(XUartLite *InstancePtr) } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_sinit.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_sinit.c similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_sinit.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_sinit.c index 97611dada..39688a3fb 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_sinit.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_sinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2005 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,8 @@ /** * * @file xuartlite_sinit.c +* @addtogroup uartlite_v3_1 +* @{ * * The implementation of the XUartLite component's static initialzation * functionality. @@ -143,3 +145,4 @@ int XUartLite_Initialize(XUartLite *InstancePtr, u16 DeviceId) ConfigPtr->RegBaseAddr); } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_stats.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_stats.c similarity index 97% rename from FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_stats.c rename to FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_stats.c index 305d37f9c..b3231832a 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_0/src/xuartlite_stats.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_stats.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,8 @@ /** * * @file xuartlite_stats.c +* @addtogroup uartlite_v3_1 +* @{ * * This file contains the statistics functions for the UART Lite component * (XUartLite). @@ -139,3 +141,4 @@ void XUartLite_ClearStats(XUartLite *InstancePtr) } +/** @} */ diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/system.mss b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/system.mss index b0bccf959..2304f57ad 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/system.mss +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/system.mss @@ -1,62 +1,51 @@ - PARAMETER NAME = C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\MicroBlaze_Kintex7_EthernetLite\BSP\system.mss - PARAMETER VERSION = 2.2.0 BEGIN OS PARAMETER OS_NAME = standalone - PARAMETER OS_VER = 4.2 + PARAMETER OS_VER = 5.4 PARAMETER PROC_INSTANCE = microblaze_0 + PARAMETER microblaze_exceptions = true + PARAMETER stdin = axi_uartlite_0 + PARAMETER stdout = axi_uartlite_0 END BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu - PARAMETER DRIVER_VER = 2.2 + PARAMETER DRIVER_VER = 2.4 PARAMETER HW_INSTANCE = microblaze_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = emaclite - PARAMETER DRIVER_VER = 4.0 + PARAMETER DRIVER_VER = 4.2 PARAMETER HW_INSTANCE = axi_ethernetlite_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = gpio - PARAMETER DRIVER_VER = 4.0 + PARAMETER DRIVER_VER = 4.1 PARAMETER HW_INSTANCE = axi_gpio_0 END -BEGIN DRIVER - PARAMETER DRIVER_NAME = intc - PARAMETER DRIVER_VER = 3.2 - PARAMETER HW_INSTANCE = axi_intc_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = tmrctr - PARAMETER DRIVER_VER = 3.0 - PARAMETER HW_INSTANCE = axi_timer_0 -END - BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite - PARAMETER DRIVER_VER = 3.0 + PARAMETER DRIVER_VER = 3.2 PARAMETER HW_INSTANCE = axi_uartlite_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = bram - PARAMETER DRIVER_VER = 4.0 + PARAMETER DRIVER_VER = 4.1 PARAMETER HW_INSTANCE = microblaze_0_local_memory_dlmb_bram_if_cntlr END BEGIN DRIVER PARAMETER DRIVER_NAME = bram - PARAMETER DRIVER_VER = 4.0 + PARAMETER DRIVER_VER = 4.1 PARAMETER HW_INSTANCE = microblaze_0_local_memory_ilmb_bram_if_cntlr END diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/.project b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/.project index f860e24f1..ab1ca784d 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/.project +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/.project @@ -1,7 +1,7 @@ Hardware - Created by SDK v2014.4 + Created by SDK v2016.1 @@ -11,7 +11,7 @@ - 1421760060412 + 1462808401190 6 @@ -20,7 +20,7 @@ - 1421760060422 + 1462808401200 6 @@ -29,7 +29,7 @@ - 1421760060432 + 1462808401200 6 @@ -37,32 +37,5 @@ 1.0-name-matches-false-false-*.hwh - - 1421760060432 - - 6 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-*.bit - - - - 1421760060442 - - 6 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-*.bmm - - - - 1421760060442 - - 6 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-*.mmi - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design.hwh b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design.hwh deleted file mode 100644 index bf43cd8a5..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design.hwh +++ /dev/null @@ -1,6575 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_bd.tcl b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_bd.tcl deleted file mode 100644 index ef538a029..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_bd.tcl +++ /dev/null @@ -1,360 +0,0 @@ - -################################################################ -# This is a generated script based on design: base_microblaze_design -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2014.4 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source base_microblaze_design_script.tcl - -# If you do not already have a project created, -# you can create a project using the following command: -# create_project project_1 myproj -part xc7k325tffg900-2 -# set_property BOARD_PART xilinx.com:kc705:part0:1.1 [current_project] - - -# CHANGE DESIGN NAME HERE -set design_name base_microblaze_design - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# CHECKING IF PROJECT EXISTS -if { [get_projects -quiet] eq "" } { - puts "ERROR: Please open or create a project!" - return 1 -} - - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "ERROR: Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - puts "INFO: Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - puts "INFO: Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - puts "INFO: Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - puts "INFO: Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -puts "INFO: Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - puts $errMsg - return $nRet -} - -################################################################## -# DESIGN PROCs -################################################################## - - -# Hierarchical cell: microblaze_0_local_memory -proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } { - - if { $parentCell eq "" || $nameHier eq "" } { - puts "ERROR: create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!" - return - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - puts "ERROR: Unable to find parent cell <$parentCell>!" - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - # Create cell and set as current instance - set hier_obj [create_bd_cell -type hier $nameHier] - current_bd_instance $hier_obj - - # Create interface pins - create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB - create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB - - # Create pins - create_bd_pin -dir I -type clk LMB_Clk - create_bd_pin -dir I -from 0 -to 0 -type rst LMB_Rst - - # Create instance: dlmb_bram_if_cntlr, and set properties - set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ] - set_property -dict [ list CONFIG.C_ECC {0} ] $dlmb_bram_if_cntlr - - # Create instance: dlmb_v10, and set properties - set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ] - - # Create instance: ilmb_bram_if_cntlr, and set properties - set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ] - set_property -dict [ list CONFIG.C_ECC {0} ] $ilmb_bram_if_cntlr - - # Create instance: ilmb_v10, and set properties - set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ] - - # Create instance: lmb_bram, and set properties - set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 lmb_bram ] - set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller} ] $lmb_bram - - # Create interface connections - connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M] - connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0] - connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA] - connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M] - connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0] - connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB] - - # Create port connections - connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk] - connect_bd_net -net microblaze_0_LMB_Rst [get_bd_pins LMB_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst] - - # Restore current instance - current_bd_instance $oldCurInst -} - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - puts "ERROR: Unable to find parent cell <$parentCell>!" - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ] - set led_8bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 led_8bits ] - set mdio_mdc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio_mdc ] - set mii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mii_rtl:1.0 mii ] - set rs232_uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 rs232_uart ] - set sys_diff_clock [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_diff_clock ] - - # Create ports - set reset [ create_bd_port -dir I -type rst reset ] - set_property -dict [ list CONFIG.POLARITY {ACTIVE_HIGH} ] $reset - - # Create instance: axi_ethernetlite_0, and set properties - set axi_ethernetlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernetlite:3.0 axi_ethernetlite_0 ] - set_property -dict [ list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} CONFIG.MII_BOARD_INTERFACE {mii} CONFIG.USE_BOARD_FLOW {true} ] $axi_ethernetlite_0 - - # Create instance: axi_gpio_0, and set properties - set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] - set_property -dict [ list CONFIG.GPIO_BOARD_INTERFACE {led_8bits} CONFIG.USE_BOARD_FLOW {true} ] $axi_gpio_0 - - # Create instance: axi_intc_0, and set properties - set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ] - - # Create instance: axi_mem_intercon, and set properties - set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ] - set_property -dict [ list CONFIG.NUM_MI {1} CONFIG.NUM_SI {2} ] $axi_mem_intercon - - # Create instance: axi_timer_0, and set properties - set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] - - # Create instance: axi_uartlite_0, and set properties - set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ] - set_property -dict [ list CONFIG.C_BAUDRATE {115200} CONFIG.UARTLITE_BOARD_INTERFACE {rs232_uart} CONFIG.USE_BOARD_FLOW {true} ] $axi_uartlite_0 - - # Create instance: mdm_1, and set properties - set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ] - - # Create instance: microblaze_0, and set properties - set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.4 microblaze_0 ] - set_property -dict [ list CONFIG.C_CACHE_BYTE_SIZE {32768} \ -CONFIG.C_DCACHE_BYTE_SIZE {32768} CONFIG.C_DCACHE_LINE_LEN {8} \ -CONFIG.C_DCACHE_USE_WRITEBACK {1} CONFIG.C_DCACHE_VICTIMS {8} \ -CONFIG.C_DEBUG_ENABLED {1} CONFIG.C_DIV_ZERO_EXCEPTION {1} \ -CONFIG.C_D_AXI {1} CONFIG.C_D_LMB {1} \ -CONFIG.C_FPU_EXCEPTION {1} CONFIG.C_ICACHE_LINE_LEN {8} \ -CONFIG.C_ICACHE_STREAMS {1} CONFIG.C_ICACHE_VICTIMS {8} \ -CONFIG.C_ILL_OPCODE_EXCEPTION {1} CONFIG.C_I_LMB {1} \ -CONFIG.C_M_AXI_D_BUS_EXCEPTION {1} CONFIG.C_M_AXI_I_BUS_EXCEPTION {1} \ -CONFIG.C_NUMBER_OF_PC_BRK {8} CONFIG.C_NUMBER_OF_RD_ADDR_BRK {2} \ -CONFIG.C_NUMBER_OF_WR_ADDR_BRK {2} CONFIG.C_OPCODE_0x0_ILLEGAL {1} \ -CONFIG.C_TRACE {1} CONFIG.C_UNALIGNED_EXCEPTIONS {1} \ -CONFIG.C_USE_BARREL {1} CONFIG.C_USE_BRANCH_TARGET_CACHE {1} \ -CONFIG.C_USE_DCACHE {1} CONFIG.C_USE_DIV {1} \ -CONFIG.C_USE_FPU {2} CONFIG.C_USE_HW_MUL {2} \ -CONFIG.C_USE_ICACHE {1} CONFIG.C_USE_MSR_INSTR {1} \ -CONFIG.C_USE_PCMP_INSTR {1} CONFIG.C_USE_REORDER_INSTR {1} \ -CONFIG.C_USE_STACK_PROTECTION {1} CONFIG.G_TEMPLATE_LIST {2} \ -CONFIG.G_USE_EXCEPTIONS {1} ] $microblaze_0 - - # Create instance: microblaze_0_axi_periph, and set properties - set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ] - set_property -dict [ list CONFIG.NUM_MI {5} CONFIG.NUM_SI {1} ] $microblaze_0_axi_periph - - # Create instance: microblaze_0_local_memory - create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory - - # Create instance: mig_7series_0, and set properties - set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 mig_7series_0 ] - set_property -dict [ list CONFIG.BOARD_MIG_PARAM {ddr3_sdram} CONFIG.RESET_BOARD_INTERFACE {reset} ] $mig_7series_0 - - # Create instance: rst_clk_wiz_1_100M, and set properties - set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ] - set_property -dict [ list CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.USE_BOARD_FLOW {true} ] $rst_clk_wiz_1_100M - - # Create instance: xlconcat_0, and set properties - set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] - set_property -dict [ list CONFIG.NUM_PORTS {3} ] $xlconcat_0 - - # Create interface connections - connect_bd_intf_net -intf_net SYS_CLK_1 [get_bd_intf_ports sys_diff_clock] [get_bd_intf_pins mig_7series_0/SYS_CLK] - connect_bd_intf_net -intf_net axi_ethernetlite_0_MDIO [get_bd_intf_ports mdio_mdc] [get_bd_intf_pins axi_ethernetlite_0/MDIO] - connect_bd_intf_net -intf_net axi_ethernetlite_0_MII [get_bd_intf_ports mii] [get_bd_intf_pins axi_ethernetlite_0/MII] - connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports led_8bits] [get_bd_intf_pins axi_gpio_0/GPIO] - connect_bd_intf_net -intf_net axi_intc_0_interrupt [get_bd_intf_pins axi_intc_0/interrupt] [get_bd_intf_pins microblaze_0/INTERRUPT] - connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins mig_7series_0/S_AXI] - connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports rs232_uart] [get_bd_intf_pins axi_uartlite_0/UART] - connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC] - connect_bd_intf_net -intf_net microblaze_0_M_AXI_DP [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI] - connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_mem_intercon/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC] - connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI] - connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI] - connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins axi_ethernetlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI] - connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG] - connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB] - connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB] - connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0/DDR3] - - # Create port connections - connect_bd_net -net axi_ethernetlite_0_ip2intc_irpt [get_bd_pins axi_ethernetlite_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In2] - connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins xlconcat_0/In0] - connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In1] - connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst] - connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_ethernetlite_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon/S01_ACLK] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk] - connect_bd_net -net mig_7series_0_mmcm_locked [get_bd_pins mig_7series_0/mmcm_locked] [get_bd_pins rst_clk_wiz_1_100M/dcm_locked] - connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in] - connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins mig_7series_0/sys_rst] - connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/LMB_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset] - connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn] - connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins rst_clk_wiz_1_100M/mb_reset] - connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins axi_ethernetlite_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon/S01_ARESETN] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins mig_7series_0/aresetn] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn] - connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat_0/dout] - - # Create address segments - create_bd_addr_seg -range 0x10000 -offset 0x40E00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_ethernetlite_0/S_AXI/Reg] SEG_axi_ethernetlite_0_Reg - create_bd_addr_seg -range 0x10000 -offset 0x40000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg - create_bd_addr_seg -range 0x10000 -offset 0x41200000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_intc_0/s_axi/Reg] SEG_axi_intc_0_Reg - create_bd_addr_seg -range 0x10000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg - create_bd_addr_seg -range 0x10000 -offset 0x40600000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg - create_bd_addr_seg -range 0x40000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem - create_bd_addr_seg -range 0x40000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem - create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr - create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr - - - # Restore current instance - current_bd_instance $oldCurInst - - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.mmi b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.mmi deleted file mode 100644 index 40c93ef57..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.mmi +++ /dev/null @@ -1,334 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/sysdef.xml b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/sysdef.xml deleted file mode 100644 index 6e97db55c..000000000 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/sysdef.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/system.hdf b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/system.hdf index d508b5e65..f0e38f475 100644 Binary files a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/system.hdf and b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/system.hdf differ