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Update the Microblaze hardware design and BSP to the latest IP and tool versions.

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This commit is contained in:
Richard Barry 2016-05-09 15:55:51 +00:00
parent 324127837c
commit 501be60574
165 changed files with 3287 additions and 15005 deletions
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4
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.cproject
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@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.1741365255">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1741365255" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<cconfiguration id="org.eclipse.cdt.core.default.config.1709418136">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1709418136" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>

2
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.project
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@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>BSP</name>
<comment>Created by SDK v2014.4</comment>
<comment>Created by SDK v2016.1</comment>
<projects>
</projects>
<buildSpec>

4
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/Makefile
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@ -21,11 +21,11 @@ $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
@echo "Running Make include in $(subst /make.include,,$@)"
$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.4 -mhard-float -mlittle-endian -mno-xl-soft-div -mno-xl-soft-mul -mxl-barrel-shift -mxl-float-convert -mxl-float-sqrt -mxl-multiply-high -mxl-pattern-compare" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections"
$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.6 -mlittle-endian -mno-xl-soft-div -mxl-barrel-shift -mxl-pattern-compare -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-g"
%/make.libs: include
@echo "Running Make libs in $(subst /make.libs,,$@)"
$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.4 -mhard-float -mlittle-endian -mno-xl-soft-div -mno-xl-soft-mul -mxl-barrel-shift -mxl-float-convert -mxl-float-sqrt -mxl-multiply-high -mxl-pattern-compare" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections"
$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.6 -mlittle-endian -mno-xl-soft-div -mxl-barrel-shift -mxl-pattern-compare -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-g"
clean:
rm -f ${PROCESSOR}/lib/libxil.a

219
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include/xparameters.h
View file

@ -15,59 +15,72 @@
/* Definitions for peripheral MICROBLAZE_0 */
#define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 15
#define XPAR_MICROBLAZE_0_ADDR_SIZE 32
#define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 16
#define XPAR_MICROBLAZE_0_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_0_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_0_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_0_ASYNC_INTERRUPT 1
#define XPAR_MICROBLAZE_0_ASYNC_WAKEUP 3
#define XPAR_MICROBLAZE_0_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_0_BASE_VECTORS 0x00000000
#define XPAR_MICROBLAZE_0_BASE_VECTORS 0x0000000000000000
#define XPAR_MICROBLAZE_0_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_0_DADDR_SIZE 32
#define XPAR_MICROBLAZE_0_DATA_SIZE 32
#define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 15
#define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 16
#define XPAR_MICROBLAZE_0_DCACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_0_DCACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_0_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_0_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0xBFFFFFFF
#define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_0_DCACHE_LINE_LEN 8
#define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 1
#define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 8
#define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 0
#define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 0
#define XPAR_MICROBLAZE_0_DC_AXI_MON 0
#define XPAR_MICROBLAZE_0_DEBUG_COUNTER_WIDTH 32
#define XPAR_MICROBLAZE_0_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_0_DEBUG_ENABLED 2
#define XPAR_MICROBLAZE_0_DEBUG_EVENT_COUNTERS 5
#define XPAR_MICROBLAZE_0_DEBUG_EXTERNAL_TRACE 0
#define XPAR_MICROBLAZE_0_DEBUG_LATENCY_COUNTERS 1
#define XPAR_MICROBLAZE_0_DEBUG_PROFILE_SIZE 0
#define XPAR_MICROBLAZE_0_DEBUG_TRACE_SIZE 8192
#define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 1
#define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 0
#define XPAR_MICROBLAZE_0_DP_AXI_MON 0
#define XPAR_MICROBLAZE_0_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_0_D_AXI 1
#define XPAR_MICROBLAZE_0_D_LMB 1
#define XPAR_MICROBLAZE_0_D_LMB_MON 0
#define XPAR_MICROBLAZE_0_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_0_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_0_ENABLE_DISCRETE_PORTS 0
#define XPAR_MICROBLAZE_0_ENDIANNESS 1
#define XPAR_MICROBLAZE_0_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_0_FPU_EXCEPTION 1
#define XPAR_MICROBLAZE_0_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_0_FREQ 100000000
#define XPAR_MICROBLAZE_0_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_0_FSL_LINKS 0
#define XPAR_MICROBLAZE_0_IADDR_SIZE 32
#define XPAR_MICROBLAZE_0_ICACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_0_ICACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_0_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_0_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0xBFFFFFFF
#define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_0_ICACHE_LINE_LEN 8
#define XPAR_MICROBLAZE_0_ICACHE_STREAMS 1
#define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 8
#define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 1
#define XPAR_MICROBLAZE_0_ICACHE_STREAMS 0
#define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 0
#define XPAR_MICROBLAZE_0_IC_AXI_MON 0
#define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 0
#define XPAR_MICROBLAZE_0_IMPRECISE_EXCEPTIONS 0
#define XPAR_MICROBLAZE_0_INSTR_SIZE 32
#define XPAR_MICROBLAZE_0_INTERCONNECT 2
#define XPAR_MICROBLAZE_0_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_0_INTERRUPT_MON 0
#define XPAR_MICROBLAZE_0_IP_AXI_MON 0
#define XPAR_MICROBLAZE_0_I_AXI 0
#define XPAR_MICROBLAZE_0_I_LMB 1
#define XPAR_MICROBLAZE_0_I_LMB_MON 0
#define XPAR_MICROBLAZE_0_LOCKSTEP_SELECT 0
#define XPAR_MICROBLAZE_0_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_0_M0_AXIS_DATA_WIDTH 32
@ -106,7 +119,7 @@
#define XPAR_MICROBLAZE_0_MMU_ITLB_SIZE 2
#define XPAR_MICROBLAZE_0_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_0_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_0_MMU_ZONES 2
#define XPAR_MICROBLAZE_0_MMU_ZONES 16
#define XPAR_MICROBLAZE_0_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_DC_AWUSER_WIDTH 5
@ -122,7 +135,7 @@
#define XPAR_MICROBLAZE_0_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_0_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_0_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_IC_AWUSER_WIDTH 5
@ -136,7 +149,7 @@
#define XPAR_MICROBLAZE_0_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_0_NUMBER_OF_PC_BRK 8
#define XPAR_MICROBLAZE_0_NUMBER_OF_RD_ADDR_BRK 2
#define XPAR_MICROBLAZE_0_NUMBER_OF_WR_ADDR_BRK 2
@ -144,7 +157,7 @@
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_DEBUG 2
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_IRQ 1
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_DBG_CLK 1
#define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 1
#define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 0
#define XPAR_MICROBLAZE_0_OPTIMIZATION 0
#define XPAR_MICROBLAZE_0_PC_WIDTH 32
#define XPAR_MICROBLAZE_0_PVR 0
@ -184,8 +197,8 @@
#define XPAR_MICROBLAZE_0_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_SCO 0
#define XPAR_MICROBLAZE_0_TRACE 1
#define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 1
#define XPAR_MICROBLAZE_0_TRACE 0
#define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 0
#define XPAR_MICROBLAZE_0_USE_BARREL 1
#define XPAR_MICROBLAZE_0_USE_BRANCH_TARGET_CACHE 1
#define XPAR_MICROBLAZE_0_USE_CONFIG_RESET 0
@ -194,78 +207,92 @@
#define XPAR_MICROBLAZE_0_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_0_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_0_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_0_USE_FPU 2
#define XPAR_MICROBLAZE_0_USE_HW_MUL 2
#define XPAR_MICROBLAZE_0_USE_FPU 0
#define XPAR_MICROBLAZE_0_USE_HW_MUL 0
#define XPAR_MICROBLAZE_0_USE_ICACHE 1
#define XPAR_MICROBLAZE_0_USE_INTERRUPT 1
#define XPAR_MICROBLAZE_0_USE_INTERRUPT 0
#define XPAR_MICROBLAZE_0_USE_MMU 0
#define XPAR_MICROBLAZE_0_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_0_USE_NON_SECURE 0
#define XPAR_MICROBLAZE_0_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_0_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 1
#define XPAR_MICROBLAZE_0_COMPONENT_NAME base_microblaze_design_microblaze_0_0
#define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 0
#define XPAR_MICROBLAZE_0_COMPONENT_NAME mb_subsystem_microblaze_0_0
#define XPAR_MICROBLAZE_0_EDK_IPTYPE PROCESSOR
#define XPAR_MICROBLAZE_0_EDK_SPECIAL microblaze
#define XPAR_MICROBLAZE_0_G_TEMPLATE_LIST 2
#define XPAR_MICROBLAZE_0_G_USE_EXCEPTIONS 1
#define XPAR_MICROBLAZE_0_G_TEMPLATE_LIST 0
#define XPAR_MICROBLAZE_0_G_USE_EXCEPTIONS 0
/******************************************************************/
#define XPAR_CPU_ID 0
#define XPAR_MICROBLAZE_ID 0
#define XPAR_MICROBLAZE_ADDR_TAG_BITS 15
#define XPAR_MICROBLAZE_ADDR_SIZE 32
#define XPAR_MICROBLAZE_ADDR_TAG_BITS 16
#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1
#define XPAR_MICROBLAZE_ASYNC_WAKEUP 3
#define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_BASE_VECTORS 0x00000000
#define XPAR_MICROBLAZE_BASE_VECTORS 0x0000000000000000
#define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_DADDR_SIZE 32
#define XPAR_MICROBLAZE_DATA_SIZE 32
#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 15
#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 16
#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xBFFFFFFF
#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 8
#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 1
#define XPAR_MICROBLAZE_DCACHE_VICTIMS 8
#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 0
#define XPAR_MICROBLAZE_DCACHE_VICTIMS 0
#define XPAR_MICROBLAZE_DC_AXI_MON 0
#define XPAR_MICROBLAZE_DEBUG_COUNTER_WIDTH 32
#define XPAR_MICROBLAZE_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_DEBUG_ENABLED 2
#define XPAR_MICROBLAZE_DEBUG_EVENT_COUNTERS 5
#define XPAR_MICROBLAZE_DEBUG_EXTERNAL_TRACE 0
#define XPAR_MICROBLAZE_DEBUG_LATENCY_COUNTERS 1
#define XPAR_MICROBLAZE_DEBUG_PROFILE_SIZE 0
#define XPAR_MICROBLAZE_DEBUG_TRACE_SIZE 8192
#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 1
#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 0
#define XPAR_MICROBLAZE_DP_AXI_MON 0
#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_D_AXI 1
#define XPAR_MICROBLAZE_D_LMB 1
#define XPAR_MICROBLAZE_D_LMB_MON 0
#define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 0
#define XPAR_MICROBLAZE_ENDIANNESS 1
#define XPAR_MICROBLAZE_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_FPU_EXCEPTION 1
#define XPAR_MICROBLAZE_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_FREQ 100000000
#define XPAR_MICROBLAZE_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_FSL_LINKS 0
#define XPAR_MICROBLAZE_IADDR_SIZE 32
#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xBFFFFFFF
#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 8
#define XPAR_MICROBLAZE_ICACHE_STREAMS 1
#define XPAR_MICROBLAZE_ICACHE_VICTIMS 8
#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1
#define XPAR_MICROBLAZE_ICACHE_STREAMS 0
#define XPAR_MICROBLAZE_ICACHE_VICTIMS 0
#define XPAR_MICROBLAZE_IC_AXI_MON 0
#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 0
#define XPAR_MICROBLAZE_IMPRECISE_EXCEPTIONS 0
#define XPAR_MICROBLAZE_INSTR_SIZE 32
#define XPAR_MICROBLAZE_INTERCONNECT 2
#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_INTERRUPT_MON 0
#define XPAR_MICROBLAZE_IP_AXI_MON 0
#define XPAR_MICROBLAZE_I_AXI 0
#define XPAR_MICROBLAZE_I_LMB 1
#define XPAR_MICROBLAZE_I_LMB_MON 0
#define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0
#define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32
@ -304,7 +331,7 @@
#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 2
#define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_MMU_ZONES 2
#define XPAR_MICROBLAZE_MMU_ZONES 16
#define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5
@ -320,7 +347,7 @@
#define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5
@ -334,7 +361,7 @@
#define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 8
#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 2
#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 2
@ -342,7 +369,7 @@
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_DEBUG 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_IRQ 1
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_CLK 1
#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1
#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 0
#define XPAR_MICROBLAZE_OPTIMIZATION 0
#define XPAR_MICROBLAZE_PC_WIDTH 32
#define XPAR_MICROBLAZE_PVR 0
@ -382,8 +409,8 @@
#define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_SCO 0
#define XPAR_MICROBLAZE_TRACE 1
#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1
#define XPAR_MICROBLAZE_TRACE 0
#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 0
#define XPAR_MICROBLAZE_USE_BARREL 1
#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 1
#define XPAR_MICROBLAZE_USE_CONFIG_RESET 0
@ -392,23 +419,26 @@
#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_USE_FPU 2
#define XPAR_MICROBLAZE_USE_HW_MUL 2
#define XPAR_MICROBLAZE_USE_FPU 0
#define XPAR_MICROBLAZE_USE_HW_MUL 0
#define XPAR_MICROBLAZE_USE_ICACHE 1
#define XPAR_MICROBLAZE_USE_INTERRUPT 1
#define XPAR_MICROBLAZE_USE_INTERRUPT 0
#define XPAR_MICROBLAZE_USE_MMU 0
#define XPAR_MICROBLAZE_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_USE_NON_SECURE 0
#define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 1
#define XPAR_MICROBLAZE_COMPONENT_NAME base_microblaze_design_microblaze_0_0
#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 0
#define XPAR_MICROBLAZE_COMPONENT_NAME mb_subsystem_microblaze_0_0
#define XPAR_MICROBLAZE_EDK_IPTYPE PROCESSOR
#define XPAR_MICROBLAZE_EDK_SPECIAL microblaze
#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 2
#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1
#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 0
#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 0
/******************************************************************/
#define STDIN_BASEADDRESS 0x40600000
#define STDOUT_BASEADDRESS 0x40600000
/******************************************************************/
@ -428,7 +458,7 @@
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS 2
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0000FFFF
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
@ -446,7 +476,7 @@
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS 2
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0000FFFF
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
@ -466,7 +496,7 @@
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 1
#define XPAR_BRAM_0_WRITE_ACCESS 2
#define XPAR_BRAM_0_BASEADDR 0x00000000
#define XPAR_BRAM_0_HIGHADDR 0x0003FFFF
#define XPAR_BRAM_0_HIGHADDR 0x0000FFFF
/* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
#define XPAR_BRAM_1_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID
@ -481,7 +511,7 @@
#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 1
#define XPAR_BRAM_1_WRITE_ACCESS 2
#define XPAR_BRAM_1_BASEADDR 0x00000000
#define XPAR_BRAM_1_HIGHADDR 0x0003FFFF
#define XPAR_BRAM_1_HIGHADDR 0x0000FFFF
/******************************************************************/
@ -534,55 +564,6 @@
#define XPAR_GPIO_0_IS_DUAL 0
/******************************************************************/
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_HAS_SIE 1
#define XPAR_XINTC_HAS_CIE 1
#define XPAR_XINTC_HAS_IVR 1
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1
/* Definitions for peripheral AXI_INTC_0 */
#define XPAR_AXI_INTC_0_DEVICE_ID 0
#define XPAR_AXI_INTC_0_BASEADDR 0x41200000
#define XPAR_AXI_INTC_0_HIGHADDR 0x4120FFFF
#define XPAR_AXI_INTC_0_KIND_OF_INTR 0xFFFFFFFE
#define XPAR_AXI_INTC_0_HAS_FAST 0
#define XPAR_AXI_INTC_0_IVAR_RESET_VALUE 0x00000010
#define XPAR_AXI_INTC_0_NUM_INTR_INPUTS 3
/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
#define XPAR_AXI_INTC_0_TYPE 0
#define XPAR_AXI_TIMER_0_INTERRUPT_MASK 0X000001
#define XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR 0
#define XPAR_AXI_UARTLITE_0_INTERRUPT_MASK 0X000002
#define XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR 1
#define XPAR_AXI_ETHERNETLITE_0_IP2INTC_IRPT_MASK 0X000004
#define XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR 2
/******************************************************************/
/* Canonical definitions for peripheral AXI_INTC_0 */
#define XPAR_INTC_0_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
#define XPAR_INTC_0_BASEADDR 0x41200000
#define XPAR_INTC_0_HIGHADDR 0x4120FFFF
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFFE
#define XPAR_INTC_0_HAS_FAST 0
#define XPAR_INTC_0_IVAR_RESET_VALUE 0x00000010
#define XPAR_INTC_0_NUM_INTR_INPUTS 3
#define XPAR_INTC_0_INTC_TYPE 0
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR
#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR
#define XPAR_INTC_0_EMACLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR
/******************************************************************/
/* Definitions for driver MIG_7SERIES */
@ -601,7 +582,7 @@
/* Definitions for peripheral MIG_7SERIES_0 */
#define XPAR_MIG_7SERIES_0_BASEADDR 0x80000000
#define XPAR_MIG_7SERIES_0_HIGHADDR 0xBFFFFFFF
#define XPAR_MIG_7SERIES_0_HIGHADDR 0x9FFFFFFF
/******************************************************************/
@ -613,29 +594,9 @@
#define XPAR_MIG7SERIES_0_DDR_BANK_WIDTH 3
#define XPAR_MIG7SERIES_0_DDR_DQ_WIDTH 64
#define XPAR_MIG7SERIES_0_BASEADDR 0x80000000
#define XPAR_MIG7SERIES_0_HIGHADDR 0xBFFFFFFF
#define XPAR_MIG7SERIES_0_HIGHADDR 0x9FFFFFFF
/******************************************************************/
/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1
/* Definitions for peripheral AXI_TIMER_0 */
#define XPAR_AXI_TIMER_0_DEVICE_ID 0
#define XPAR_AXI_TIMER_0_BASEADDR 0x41C00000
#define XPAR_AXI_TIMER_0_HIGHADDR 0x41C0FFFF
#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000
/******************************************************************/
/* Canonical definitions for peripheral AXI_TIMER_0 */
#define XPAR_TMRCTR_0_DEVICE_ID 0
#define XPAR_TMRCTR_0_BASEADDR 0x41C00000
#define XPAR_TMRCTR_0_HIGHADDR 0x41C0FFFF
#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ
/******************************************************************/
/* Definitions for driver UARTLITE */
@ -645,7 +606,7 @@
#define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000
#define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060FFFF
#define XPAR_AXI_UARTLITE_0_DEVICE_ID 0
#define XPAR_AXI_UARTLITE_0_BAUDRATE 115200
#define XPAR_AXI_UARTLITE_0_BAUDRATE 9600
#define XPAR_AXI_UARTLITE_0_USE_PARITY 0
#define XPAR_AXI_UARTLITE_0_ODD_PARITY 0
#define XPAR_AXI_UARTLITE_0_DATA_BITS 8
@ -657,7 +618,7 @@
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0x40600000
#define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF
#define XPAR_UARTLITE_0_BAUDRATE 115200
#define XPAR_UARTLITE_0_BAUDRATE 9600
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 8

0
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/Makefile → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/Makefile
View file

9
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -32,6 +32,8 @@
/**
* @file xbram.c
* @addtogroup bram_v4_0
* @{
*
* The implementation of the XBram driver's basic functionality.
* See xbram.h for more information about the driver.
@ -49,6 +51,8 @@
* 3.01a sa 13/01/12 Added CorrectableFailingDataRegs and
* UncorrectableFailingDataRegs in
* XBram_CfgInitialize API.
* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototype of XBram_CfgInitialize API.
*</pre>
*
*****************************************************************************/
@ -104,7 +108,7 @@
*****************************************************************************/
int XBram_CfgInitialize(XBram *InstancePtr,
XBram_Config *Config,
u32 EffectiveAddr)
UINTPTR EffectiveAddr)
{
/*
* Assert arguments
@ -142,3 +146,4 @@ int XBram_CfgInitialize(XBram *InstancePtr,
return (XST_SUCCESS);
}
/** @} */

14
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -32,6 +32,9 @@
/*****************************************************************************/
/**
* @file xbram.h
* @addtogroup bram_v4_0
* @{
* @details
*
* If ECC is not enabled, this driver exists only to allow the tools to
* create a memory test application and to populate xparameters.h with memory
@ -108,6 +111,8 @@
* flush the Cache after writing to BRAM in InjectErrors
* API(CR #719011)
* 4.0 adk 19/12/13 Updated as per the New Tcl API's
* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototype of XBram_CfgInitialize API.
* </pre>
*****************************************************************************/
#ifndef XBRAM_H /* prevent circular inclusions */
@ -158,8 +163,8 @@ typedef struct {
* h/w */
u32 MemBaseAddress; /**< Device memory base address */
u32 MemHighAddress; /**< Device memory high address */
u32 CtrlBaseAddress; /**< Device register base address.*/
u32 CtrlHighAddress; /**< Device register base address.*/
UINTPTR CtrlBaseAddress; /**< Device register base address.*/
UINTPTR CtrlHighAddress; /**< Device register base address.*/
} XBram_Config;
/**
@ -187,7 +192,7 @@ XBram_Config *XBram_LookupConfig(u16 DeviceId);
* Functions implemented in xbram.c
*/
int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
u32 EffectiveAddr);
UINTPTR EffectiveAddr);
/*
* Functions implemented in xbram_selftest.c
@ -208,3 +213,4 @@ u32 XBram_InterruptGetStatus(XBram *InstancePtr);
#endif
#endif /* end of protection macro */
/** @} */

6
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_g.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -22,8 +22,8 @@
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*

5
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_hw.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_hw.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -33,6 +33,8 @@
/**
*
* @file xbram_hw.h
* @addtogroup bram_v4_0
* @{
*
* This header file contains identifiers and driver functions (or
* macros) that can be used to access the device. The user should refer to the
@ -404,3 +406,4 @@ extern "C" {
#endif
#endif /* end of protection macro */
/** @} */

5
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_intr.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_intr.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -33,6 +33,8 @@
/*****************************************************************************/
/**
* @file xbram_intr.c
* @addtogroup bram_v4_0
* @{
*
* Implements BRAM interrupt processing functions for the
* XBram driver. See xbram.h for more information
@ -233,3 +235,4 @@ u32 XBram_InterruptGetStatus(XBram * InstancePtr)
return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
}
/** @} */

5
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_selftest.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_selftest.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -32,6 +32,8 @@
/*****************************************************************************/
/**
* @file xbram_selftest.c
* @addtogroup bram_v4_0
* @{
*
* The implementation of the XBram driver's self test function. This SelfTest
* is only applicable if ECC is enabled.
@ -554,3 +556,4 @@ int XBram_SelfTest(XBram *InstancePtr, u8 IntMask)
return (XST_SUCCESS);
}
/** @} */

5
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_0/src/xbram_sinit.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_sinit.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -32,6 +32,8 @@
/*****************************************************************************/
/**
* @file xbram_sinit.c
* @addtogroup bram_v4_0
* @{
*
* The implementation of the XBram driver's static initialzation
* functionality.
@ -99,3 +101,4 @@ XBram_Config *XBram_LookupConfig(u16 DeviceId)
return CfgPtr;
}
/** @} */

4
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/Makefile → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/Makefile
View file

@ -17,10 +17,10 @@ INCLUDEFILES=xio.h
libs:
echo "Compiling cpu"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:

4
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/fsl.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/fsl.h
View file

@ -32,6 +32,8 @@
/*****************************************************************************/
/**
* @file fsl.h
* @addtogroup cpu_v2_3
* @{
*
* This file contains macros for interfacing to the Fast Simplex Link (FSL)
* interface..
@ -167,4 +169,4 @@ extern "C" {
}
#endif
#endif /* _FSL_H */
/** @} */

3
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/xio.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/xio.c
View file

@ -33,6 +33,8 @@
/**
*
* @file xio.c
* @addtogroup cpu_v2_3
* @{
*
* Contains I/O functions for memory-mapped or non-memory-mapped I/O
* architectures. These functions encapsulate generic CPU I/O requirements.
@ -225,3 +227,4 @@ void XIo_OutSwap32(XIo_Address OutAddress, u32 Value)
XIo_EndianSwap32(Value, &OutData);
XIo_Out32(OutAddress, OutData);
}
/** @} */

10
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_2/src/xio.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/cpu_v2_4/src/xio.h
View file

@ -33,6 +33,9 @@
/**
*
* @file xio.h
* @addtogroup cpu_v2_3
* @{
* @details
*
* This file contains the interface for the XIo component, which encapsulates
* the Input/Output functions for processors that do not require any special
@ -59,6 +62,12 @@
* CR#794205
* 2.2 bss 08/04/14 Updated driver tcl to add protection macros for
* xparameters.h (CR#802257).
* 2.3 sk 12/15/14 Updated mdd file to delete <EFBFBD>ffunction-sections &
* -fdata-sections flags from extra compiler flags CR#838648
* Changed default os to latest version in mdd file.
* 2.4 nsk 11/05/15 Updated generate and post_generate procs in driver tcl
* not to generate cpu macros, when microblaze is connected
* as one of the streaming slaves to itself. CR#876604
*
* </pre>
*
@ -261,3 +270,4 @@ void XIo_OutSwap32(XIo_Address OutAddress, u32 Value);
#endif
#endif /* end of protection macro */
/** @} */

7
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/Makefile → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/Makefile
View file

@ -11,17 +11,16 @@ INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
OUTS = *.o
libs:
echo "Compiling emaclite"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

36
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite.c
View file

@ -33,6 +33,8 @@
/**
*
* @file xemaclite.c
* @addtogroup emaclite_v4_1
* @{
*
* Functions in this file are the minimum required functions for the EmacLite
* driver. See xemaclite.h for a detailed description of the driver.
@ -62,6 +64,9 @@
* 3.02a sdm 07/22/11 Removed redundant code in XEmacLite_Recv functions for
* CR617290
* 3.04a srt 04/13/13 Removed warnings (CR 705000).
* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototypes of XEmacLite_GetReceiveDataLength,
* XEmacLite_CfgInitialize API's.
*
* </pre>
******************************************************************************/
@ -82,7 +87,7 @@
/************************** Function Prototypes ******************************/
static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress);
static u16 XEmacLite_GetReceiveDataLength(UINTPTR BaseAddress);
/************************** Variable Definitions *****************************/
@ -113,7 +118,7 @@ static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress);
******************************************************************************/
int XEmacLite_CfgInitialize(XEmacLite *InstancePtr,
XEmacLite_Config *EmacLiteConfigPtr,
u32 EffectiveAddr)
UINTPTR EffectiveAddr)
{
/*
@ -185,8 +190,8 @@ int XEmacLite_CfgInitialize(XEmacLite *InstancePtr,
int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount)
{
u32 Register;
u32 BaseAddress;
u32 EmacBaseAddress;
UINTPTR BaseAddress;
UINTPTR EmacBaseAddress;
u32 IntrEnableStatus;
/*
@ -232,7 +237,7 @@ int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount)
/*
* Write the frame to the buffer.
*/
XEmacLite_AlignedWrite(FramePtr, (u32 *) BaseAddress,
XEmacLite_AlignedWrite(FramePtr, (UINTPTR *) BaseAddress,
ByteCount);
@ -241,7 +246,7 @@ int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount)
*/
XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET,
(ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
XEL_TPLR_LENGTH_MASK_LO)));
XEL_TPLR_LENGTH_MASK_LO)));
/*
* Update the Tx Status Register to indicate that there is a
@ -285,7 +290,7 @@ int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount)
/*
* Write the frame to the buffer.
*/
XEmacLite_AlignedWrite(FramePtr, (u32 *) BaseAddress,
XEmacLite_AlignedWrite(FramePtr, (UINTPTR *) BaseAddress,
ByteCount);
/*
@ -361,7 +366,7 @@ u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr)
u16 LengthType;
u16 Length;
u32 Register;
u32 BaseAddress;
UINTPTR BaseAddress;
/*
* Verify that each of the inputs are valid.
@ -460,7 +465,7 @@ u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr)
/*
* Field contains type other than IP or ARP, use max
* frame size and let user parse it.
*/
*/
Length = XEL_MAX_FRAME_SIZE;
}
@ -475,7 +480,7 @@ u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr)
/*
* Read from the EmacLite.
*/
XEmacLite_AlignedRead(((u32 *) (BaseAddress + XEL_RXBUFF_OFFSET)),
XEmacLite_AlignedRead(((UINTPTR *) (BaseAddress + XEL_RXBUFF_OFFSET)),
FramePtr, Length);
/*
@ -512,7 +517,7 @@ u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr)
******************************************************************************/
void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr)
{
u32 BaseAddress;
UINTPTR BaseAddress;
/*
* Verify that each of the inputs are valid.
@ -528,7 +533,7 @@ void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr)
* Copy the MAC address to the Transmit buffer.
*/
XEmacLite_AlignedWrite(AddressPtr,
(u32 *) BaseAddress,
(UINTPTR *) BaseAddress,
XEL_MAC_ADDR_SIZE);
/*
@ -610,8 +615,8 @@ int XEmacLite_TxBufferAvailable(XEmacLite *InstancePtr)
/*
* Read the Tx Status of the second buffer register and determine if the
* buffer is available.
* Read the Tx Status of the second buffer register and determine if the
* buffer is available.
*/
if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
Register = XEmacLite_GetTxStatus(InstancePtr->EmacLiteConfig.
@ -946,7 +951,7 @@ void XEmacLite_DisableLoopBack(XEmacLite *InstancePtr)
* @note None.
*
******************************************************************************/
static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress)
static u16 XEmacLite_GetReceiveDataLength(UINTPTR BaseAddress)
{
u16 Length;
@ -965,3 +970,4 @@ static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress)
return Length;
}
/** @} */

17
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite.h
View file

@ -33,6 +33,9 @@
/**
*
* @file xemaclite.h
* @addtogroup emaclite_v4_1
* @{
* @details
*
* The Xilinx Ethernet Lite (EmacLite) driver. This driver supports the Xilinx
* Ethernet Lite 10/100 MAC (EmacLite).
@ -190,6 +193,15 @@
* driver is compiled with ARM toolchain.
* 3.04a srt 04/13/13 Removed warnings (CR 705000).
* 4.0 adk 19/12/13 Updated as per the New Tcl API's
* 4.1 nsk 07/13/15 Added Length check in XEmacLite_AlignedWrite function
* in xemaclite_l.c file to avoid extra write operation
* (CR 843707).
* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototype of XEmacLite_CfgInitialize API.
* 4.2 adk 11/18/15 Fix compilation errors due to conflicting data types
* CR#917930
* 4.2 adk 29/02/16 Updated interrupt example to support Zynq and ZynqMP
* CR#938244.
*
* </pre>
*
@ -229,7 +241,7 @@ extern "C" {
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Device base address */
UINTPTR BaseAddress; /**< Device base address */
u8 TxPingPong; /**< 1 if TX Pong buffer configured, 0 otherwise */
u8 RxPingPong; /**< 1 if RX Pong buffer configured, 0 otherwise */
u8 MdioInclude; /**< 1 if MDIO is enabled, 0 otherwise */
@ -355,7 +367,7 @@ typedef struct {
*/
int XEmacLite_CfgInitialize(XEmacLite *InstancePtr,
XEmacLite_Config *EmacLiteConfigPtr,
u32 EffectiveAddr);
UINTPTR EffectiveAddr);
void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr);
int XEmacLite_TxBufferAvailable(XEmacLite *InstancePtr);
void XEmacLite_FlushReceive(XEmacLite *InstancePtr);
@ -402,3 +414,4 @@ int XEmacLite_SelfTest(XEmacLite *InstancePtr);
#endif /* end of protection macro */
/** @} */

6
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_g.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -22,8 +22,8 @@
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*

7
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_i.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_i.h
View file

@ -32,6 +32,8 @@
/******************************************************************************/
/**
* @file xemaclite_i.h
* @addtogroup emaclite_v4_1
* @{
*
* This header file contains internal identifiers, which are those shared
* between the files of the driver. It is intended for internal use only.
@ -123,8 +125,8 @@ extern XEmacLite_Config XEmacLite_ConfigTable[];
/************************** Function Prototypes ******************************/
void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount);
void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount);
void XEmacLite_AlignedWrite(void *SrcPtr, UINTPTR *DestPtr, unsigned ByteCount);
void XEmacLite_AlignedRead(UINTPTR *SrcPtr, void *DestPtr, unsigned ByteCount);
void StubHandler(void *CallBackRef);
@ -134,3 +136,4 @@ void StubHandler(void *CallBackRef);
#endif
#endif /* end of protection macro */
/** @} */

10
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_intr.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_intr.c
View file

@ -33,6 +33,8 @@
/**
*
* @file xemaclite_intr.c
* @addtogroup emaclite_v4_1
* @{
*
* Functions in this file are for the interrupt driven processing functionality.
* See xemaclite.h for a detailed description of the driver.
@ -52,6 +54,7 @@
* the HW.
* 3.00a ktn 10/22/09 Updated file to use the HAL Processor APIs/macros.
* The macros have been renamed to remove _m from the name.
* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
*
* </pre>
******************************************************************************/
@ -94,7 +97,7 @@
int XEmacLite_EnableInterrupts(XEmacLite *InstancePtr)
{
u32 Register;
u32 BaseAddress;
UINTPTR BaseAddress;
/*
* Verify that each of the inputs are valid.
@ -156,7 +159,7 @@ int XEmacLite_EnableInterrupts(XEmacLite *InstancePtr)
void XEmacLite_DisableInterrupts(XEmacLite *InstancePtr)
{
u32 Register;
u32 BaseAddress;
UINTPTR BaseAddress;
/*
* Verify that each of the inputs are valid.
@ -216,7 +219,7 @@ void XEmacLite_InterruptHandler(void *InstancePtr)
XEmacLite *EmacLitePtr;
int TxCompleteIntr = FALSE;
u32 BaseAddress;
UINTPTR BaseAddress;
u32 TxStatus;
/*
@ -357,3 +360,4 @@ void XEmacLite_SetSendHandler(XEmacLite *InstancePtr, void *CallBackRef,
InstancePtr->SendHandler = FuncPtr;
InstancePtr->SendRef = CallBackRef;
}
/** @} */

33
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_l.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_l.c
View file

@ -33,6 +33,8 @@
/**
*
* @file xemaclite_l.c
* @addtogroup emaclite_v4_1
* @{
*
* This file contains the minimal, polled functions to send and receive Ethernet
* frames.
@ -52,6 +54,12 @@
* XEmacLite_AlignedRead functions to use volatile
* variables so that they are not optimized.
* 3.00a ktn 10/22/09 The macros have been renamed to remove _m from the name.
* 4.1 nsk 07/13/15 Added Length check in XEmacLite_AlignedWrite function
* to avoid extra write operation (CR 843707).
* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototypes of XEmacLite_SendFrame,
* XEmacLite_RecvFrame, XEmacLite_AlignedWrite,
* XEmacLite_AlignedRead APIs.
*
* </pre>
*
@ -71,8 +79,8 @@
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount);
void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount);
void XEmacLite_AlignedWrite(void *SrcPtr, UINTPTR *DestPtr, unsigned ByteCount);
void XEmacLite_AlignedRead(UINTPTR *SrcPtr, void *DestPtr, unsigned ByteCount);
/************************** Variable Definitions *****************************/
@ -101,20 +109,20 @@ void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount);
* The function does not take the different buffers into consideration.
*
******************************************************************************/
void XEmacLite_SendFrame(u32 BaseAddress, u8 *FramePtr, unsigned ByteCount)
void XEmacLite_SendFrame(UINTPTR BaseAddress, u8 *FramePtr, unsigned ByteCount)
{
u32 Register;
/*
* Write data to the EmacLite
*/
XEmacLite_AlignedWrite(FramePtr, (u32 *) (BaseAddress), ByteCount);
XEmacLite_AlignedWrite(FramePtr, (UINTPTR *) (BaseAddress), ByteCount);
/*
* The frame is in the buffer, now send it
*/
XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET,
(ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
(ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
XEL_TPLR_LENGTH_MASK_LO)));
@ -156,7 +164,7 @@ void XEmacLite_SendFrame(u32 BaseAddress, u8 *FramePtr, unsigned ByteCount)
* The function does not take the different buffers into consideration.
*
******************************************************************************/
u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr)
u16 XEmacLite_RecvFrame(UINTPTR BaseAddress, u8 *FramePtr)
{
u16 LengthType;
u16 Length;
@ -196,7 +204,7 @@ u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr)
/*
* Read each byte from the EmacLite
*/
XEmacLite_AlignedRead((u32 *) (BaseAddress + XEL_RXBUFF_OFFSET),
XEmacLite_AlignedRead((UINTPTR *) (BaseAddress + XEL_RXBUFF_OFFSET),
FramePtr, Length);
/*
@ -224,7 +232,7 @@ u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr)
* @note None.
*
******************************************************************************/
void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount)
void XEmacLite_AlignedWrite(void *SrcPtr, UINTPTR *DestPtr, unsigned ByteCount)
{
unsigned Index;
unsigned Length = ByteCount;
@ -364,9 +372,9 @@ void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount)
for (Index = 0; Index < Length; Index++) {
*To8Ptr++ = *From8Ptr++;
}
*To32Ptr++ = AlignBuffer;
if (Length) {
*To32Ptr++ = AlignBuffer;
}
}
/******************************************************************************/
@ -384,7 +392,7 @@ void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount)
* @note None.
*
******************************************************************************/
void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount)
void XEmacLite_AlignedRead(UINTPTR *SrcPtr, void *DestPtr, unsigned ByteCount)
{
unsigned Index;
unsigned Length = ByteCount;
@ -501,3 +509,4 @@ void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount)
*To8Ptr++ = *From8Ptr++;
}
}
/** @} */

10
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_l.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_l.h
View file

@ -33,6 +33,8 @@
/**
*
* @file xemaclite_l.h
* @addtogroup emaclite_v4_1
* @{
*
* This header file contains identifiers and basic driver functions and macros
* that can be used to access the Xilinx Ethernet Lite 10/100 MAC (EmacLite).
@ -71,6 +73,9 @@
* XEmacLite_mSetRxStatus changed to XEmacLite_SetRxStatus,
* XEmacLite_mIsTxDone changed to XEmacLite_IsTxDone and
* XEmacLite_mIsRxEmpty changed to XEmacLite_IsRxEmpty.
* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* Changed the prototypes of XEmacLite_SendFrame,
* XEmacLite_RecvFrame APIs.
* </pre>
*
******************************************************************************/
@ -361,11 +366,12 @@ extern "C" {
/************************** Function Prototypes ******************************/
void XEmacLite_SendFrame(u32 BaseAddress, u8 *FramePtr, unsigned ByteCount);
u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr);
void XEmacLite_SendFrame(UINTPTR BaseAddress, u8 *FramePtr, unsigned ByteCount);
u16 XEmacLite_RecvFrame(UINTPTR BaseAddress, u8 *FramePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

22
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_selftest.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_selftest.c
View file

@ -33,6 +33,8 @@
/**
*
* @file xemaclite_selftest.c
* @addtogroup emaclite_v4_1
* @{
*
* Function(s) in this file are the required functions for the EMAC Lite
* driver sefftest for the hardware.
@ -46,6 +48,7 @@
* 1.01a ecm 01/31/04 First release
* 1.11a mta 03/21/07 Updated to new coding style
* 3.00a ktn 10/22/09 Updated driver to use the HAL Processor APIs/macros.
* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
* </pre>
******************************************************************************/
@ -86,7 +89,7 @@
******************************************************************************/
int XEmacLite_SelfTest(XEmacLite * InstancePtr)
{
u32 BaseAddress;
UINTPTR BaseAddress;
u8 Index;
u8 TestString[4] = { 0xDE, 0xAD, 0xBE, 0xEF };
u8 ReturnString[4] = { 0x0, 0x0, 0x0, 0x0 };
@ -106,9 +109,9 @@ int XEmacLite_SelfTest(XEmacLite * InstancePtr)
* Write the TestString to the TX buffer in EMAC Lite then
* back from the EMAC Lite and verify
*/
XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress,
XEmacLite_AlignedWrite(TestString, (UINTPTR *) BaseAddress,
sizeof(TestString));
XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString,
XEmacLite_AlignedRead((UINTPTR *) BaseAddress, ReturnString,
sizeof(ReturnString));
for (Index = 0; Index < 4; Index++) {
@ -132,9 +135,9 @@ int XEmacLite_SelfTest(XEmacLite * InstancePtr)
* Write the TestString to the optional TX buffer in EMAC Lite
* then back from the EMAC Lite and verify
*/
XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress,
XEmacLite_AlignedWrite(TestString, (UINTPTR *) BaseAddress,
sizeof(TestString));
XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString,
XEmacLite_AlignedRead((UINTPTR *) BaseAddress, ReturnString,
sizeof(ReturnString));
for (Index = 0; Index < 4; Index++) {
@ -160,9 +163,9 @@ int XEmacLite_SelfTest(XEmacLite * InstancePtr)
* Write the TestString to the RX buffer in EMAC Lite then
* back from the EMAC Lite and verify
*/
XEmacLite_AlignedWrite(TestString, (u32 *) (BaseAddress),
XEmacLite_AlignedWrite(TestString, (UINTPTR *) (BaseAddress),
sizeof(TestString));
XEmacLite_AlignedRead((u32 *) (BaseAddress), ReturnString,
XEmacLite_AlignedRead((UINTPTR *) (BaseAddress), ReturnString,
sizeof(ReturnString));
for (Index = 0; Index < 4; Index++) {
@ -186,9 +189,9 @@ int XEmacLite_SelfTest(XEmacLite * InstancePtr)
* Write the TestString to the optional RX buffer in EMAC Lite
* then back from the EMAC Lite and verify
*/
XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress,
XEmacLite_AlignedWrite(TestString, (UINTPTR *) BaseAddress,
sizeof(TestString));
XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString,
XEmacLite_AlignedRead((UINTPTR *) BaseAddress, ReturnString,
sizeof(ReturnString));
for (Index = 0; Index < 4; Index++) {
@ -206,3 +209,4 @@ int XEmacLite_SelfTest(XEmacLite * InstancePtr)
return XST_SUCCESS;
}
/** @} */

3
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_0/src/xemaclite_sinit.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_sinit.c
View file

@ -33,6 +33,8 @@
/**
*
* @file xemaclite_sinit.c
* @addtogroup emaclite_v4_1
* @{
*
* This file contains the implementation of the XEmacLite driver's static
* initialization functionality.
@ -151,3 +153,4 @@ int XEmacLite_Initialize(XEmacLite *InstancePtr, u16 DeviceId)
}
/** @} */

0
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/Makefile → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/Makefile
View file

23
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -32,6 +32,8 @@
/*****************************************************************************/
/**
* @file xgpio.c
* @addtogroup gpio_v4_1
* @{
*
* The implementation of the XGpio driver's basic functionality. See xgpio.h
* for more information about the driver.
@ -58,6 +60,8 @@
* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the
* macros to remove _m from the name.
* 4.1 lks 11/18/15 Clean up of the comments in the code and
* removed support for DCR bridge
* </pre>
*
*****************************************************************************/
@ -106,7 +110,7 @@
* address instead.
*
* @return
* - XST_SUCCESS Initialization was successfull.
* - XST_SUCCESS if the initialization is successfull.
*
* @note None.
*
@ -114,19 +118,11 @@
int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config,
u32 EffectiveAddr)
{
/*
* Assert arguments
*/
/* Assert arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Set some default values.
*/
#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
InstancePtr->BaseAddress = ((EffectiveAddr >> 2)) & 0xFFF;
#else
/* Set some default values. */
InstancePtr->BaseAddress = EffectiveAddr;
#endif
InstancePtr->InterruptPresent = Config->InterruptPresent;
InstancePtr->IsDual = Config->IsDual;
@ -157,7 +153,7 @@ int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config,
* function will assert.
*
*****************************************************************************/
void XGpio_SetDataDirection(XGpio * InstancePtr, unsigned Channel,
void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
u32 DirectionMask)
{
Xil_AssertVoid(InstancePtr != NULL);
@ -253,3 +249,4 @@ void XGpio_DiscreteWrite(XGpio * InstancePtr, unsigned Channel, u32 Data)
((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,
Data);
}
/** @} */

10
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -32,6 +32,9 @@
/*****************************************************************************/
/**
* @file xgpio.h
* @addtogroup gpio_v4_1
* @{
* @details
*
* This file contains the software API definition of the Xilinx General Purpose
* I/O (XGpio) device driver.
@ -100,6 +103,10 @@
* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
* xparameters.h. CR#698589
* 4.0 adk 19/12/13 Updated as per the New Tcl API's
* 4.1 lks 11/18/15 Updated to use cannonical xparameters in examples and
* clean up of the comments, removed support for DCR bridge
* and removed xgpio_intr_example for CR 900381
*
* </pre>
*****************************************************************************/
@ -193,3 +200,4 @@ u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
#endif
#endif /* end of protection macro */
/** @} */

13
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_extra.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_extra.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -32,6 +32,8 @@
/*****************************************************************************/
/**
* @file xgpio_extra.c
* @addtogroup gpio_v4_1
* @{
*
* The implementation of the XGpio driver's advanced discrete functions.
* See xgpio.h for more information about the driver.
@ -104,9 +106,7 @@ void XGpio_DiscreteSet(XGpio * InstancePtr, unsigned Channel, u32 Mask)
Xil_AssertVoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
/*
* Calculate the offset to the data register of the GPIO once
*/
/* Calculate the offset to the data register of the GPIO */
DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
/*
@ -150,9 +150,7 @@ void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask)
Xil_AssertVoid((Channel == 1) ||
((Channel == 2) && (InstancePtr->IsDual == TRUE)));
/*
* Calculate the offset to the data register of the GPIO once
*/
/* Calculate the offset to the data register of the GPIO */
DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
/*
@ -163,3 +161,4 @@ void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask)
Current &= ~Mask;
XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
}
/** @} */

6
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_g.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -22,8 +22,8 @@
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*

5
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_i.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_i.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -32,6 +32,8 @@
/******************************************************************************/
/**
* @file xgpio_i.h
* @addtogroup gpio_v4_1
* @{
*
* This header file contains internal identifiers, which are those shared
* between the files of the driver. It is intended for internal use only.
@ -82,3 +84,4 @@ extern XGpio_Config XGpio_ConfigTable[];
#endif
#endif /* end of protection macro */
/** @} */

11
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_intr.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_intr.c
View file

@ -32,6 +32,8 @@
/*****************************************************************************/
/**
* @file xgpio_intr.c
* @addtogroup gpio_v4_1
* @{
*
* Implements GPIO interrupt processing functions for the XGpio driver.
* See xgpio.h for more information about the driver.
@ -88,7 +90,7 @@
* @note None.
*
*****************************************************************************/
void XGpio_InterruptGlobalEnable(XGpio * InstancePtr)
void XGpio_InterruptGlobalEnable(XGpio *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -115,7 +117,7 @@ void XGpio_InterruptGlobalEnable(XGpio * InstancePtr)
* @note None.
*
*****************************************************************************/
void XGpio_InterruptGlobalDisable(XGpio * InstancePtr)
void XGpio_InterruptGlobalDisable(XGpio *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -143,7 +145,7 @@ void XGpio_InterruptGlobalDisable(XGpio * InstancePtr)
* @note None.
*
*****************************************************************************/
void XGpio_InterruptEnable(XGpio * InstancePtr, u32 Mask)
void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask)
{
u32 Register;
@ -179,7 +181,7 @@ void XGpio_InterruptEnable(XGpio * InstancePtr, u32 Mask)
* @note None.
*
*****************************************************************************/
void XGpio_InterruptDisable(XGpio * InstancePtr, u32 Mask)
void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask)
{
u32 Register;
@ -289,3 +291,4 @@ u32 XGpio_InterruptGetStatus(XGpio * InstancePtr)
return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
}
/** @} */

41
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_l.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_l.h
View file

@ -33,6 +33,8 @@
/**
*
* @file xgpio_l.h
* @addtogroup gpio_v4_1
* @{
*
* This header file contains identifiers and driver functions (or
* macros) that can be used to access the device. The user should refer to the
@ -66,6 +68,7 @@
* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
* same functionality.
* 4.1 lks 11/18/15 Removed support for DCR bridge
* </pre>
*
******************************************************************************/
@ -83,16 +86,6 @@ extern "C" {
#include "xil_assert.h"
#include "xil_io.h"
/*
* XPAR_XGPIO_USE_DCR_BRIDGE has to be set to 1 if the GPIO device is
* accessed through a DCR bus connected to a bridge
*/
#define XPAR_XGPIO_USE_DCR_BRIDGE 0
#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
#include "xio_dcr.h"
#endif
/************************** Constant Definitions *****************************/
@ -101,19 +94,6 @@ extern "C" {
* Register offsets for this device.
* @{
*/
#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
#define XGPIO_TRI_OFFSET 0x1 /**< I/O direction reg for 1st channel */
#define XGPIO_DATA2_OFFSET 0x2 /**< Data register for 2nd channel */
#define XGPIO_TRI2_OFFSET 0x3 /**< I/O direction reg for 2nd channel */
#define XGPIO_GIE_OFFSET 0x47 /**< Global interrupt enable register */
#define XGPIO_ISR_OFFSET 0x48 /**< Interrupt status register */
#define XGPIO_IER_OFFSET 0x4A /**< Interrupt enable register */
#else
#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
@ -123,8 +103,6 @@ extern "C" {
#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
#endif
/* @} */
/* The following constant describes the offset of each channels data and
@ -159,21 +137,9 @@ extern "C" {
/***************** Macros (Inline Functions) Definitions *********************/
/*
* Define the appropriate I/O access method to memory mapped I/O or DCR.
*/
#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
#define XGpio_In32 XIo_DcrIn
#define XGpio_Out32 XIo_DcrOut
#else
#define XGpio_In32 Xil_In32
#define XGpio_Out32 Xil_Out32
#endif
/****************************************************************************/
/**
@ -224,3 +190,4 @@ extern "C" {
#endif
#endif /* end of protection macro */
/** @} */

3
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_selftest.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_selftest.c
View file

@ -32,6 +32,8 @@
/*****************************************************************************/
/**
* @file xgpio_selftest.c
* @addtogroup gpio_v4_1
* @{
*
* The implementation of the XGpio driver's self test function.
* See xgpio.h for more information about the driver.
@ -105,3 +107,4 @@ int XGpio_SelfTest(XGpio * InstancePtr)
return (XST_SUCCESS);
}
/** @} */

9
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_0/src/xgpio_sinit.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_sinit.c
View file

@ -32,6 +32,8 @@
/*****************************************************************************/
/**
* @file xgpio_sinit.c
* @addtogroup gpio_v4_1
* @{
*
* The implementation of the XGpio driver's static initialzation
* functionality.
@ -47,6 +49,8 @@
* ----- ---- -------- -----------------------------------------------
* 2.01a jvb 10/13/05 First release
* 2.11a mta 03/21/07 Updated to new coding style
* 4.0 sha 07/15/15 Defined macro XPAR_XGPIO_NUM_INSTANCES if not
* defined in xparameters.h
* </pre>
*
*****************************************************************************/
@ -59,6 +63,10 @@
/************************** Constant Definitions ****************************/
#ifndef XPAR_XGPIO_NUM_INSTANCES
#define XPAR_XGPIO_NUM_INSTANCES 0
#endif
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
@ -148,3 +156,4 @@ int XGpio_Initialize(XGpio * InstancePtr, u16 DeviceId)
return XGpio_CfgInitialize(InstancePtr, ConfigPtr,
ConfigPtr->BaseAddress);
}
/** @} */

30
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/Makefile
View file

@ -1,30 +0,0 @@
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
LEVEL=0
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling intc"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

1078
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc.c
View file

File diff suppressed because it is too large Load diff

363
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc.h
View file

@ -1,363 +0,0 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc.h
*
* The Xilinx interrupt controller driver component. This component supports the
* Xilinx interrupt controller.
*
* The interrupt controller driver uses the idea of priority for the various
* handlers. Priority is an integer within the range of 0 and 31 inclusive with
* 0 being the highest priority interrupt source.
*
* The Xilinx interrupt controller supports the following features:
*
* - specific individual interrupt enabling/disabling
* - specific individual interrupt acknowledging
* - attaching specific callback function to handle interrupt source
* - master enable/disable
* - single callback per interrupt or all pending interrupts handled for
* each interrupt of the processor
*
* The acknowledgement of the interrupt within the interrupt controller is
* selectable, either prior to the device's handler being called or after
* the handler is called. This is necessary to support interrupt signal inputs
* which are either edge or level signals. Edge driven interrupt signals
* require that the interrupt is acknowledged prior to the interrupt being
* serviced in order to prevent the loss of interrupts which are occurring
* extremely close together. A level driven interrupt input signal requires
* the interrupt to acknowledged after servicing the interrupt to ensure that
* the interrupt only generates a single interrupt condition.
*
* Details about connecting the interrupt handler of the driver are contained
* in the source file specific to interrupt processing, xintc_intr.c.
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads
* or thread mutual exclusion, virtual memory, or cache control must be
* satisfied by the layer above this driver.
*
* <b>Interrupt Vector Tables</b>
*
* The interrupt vector table for each interrupt controller device is declared
* statically in xintc_g.c within the configuration data for each instance.
* The device ID of the interrupt controller device is used by the driver as a
* direct index into the configuration data table - to retrieve the vector table
* for an instance of the interrupt controller. The user should populate the
* vector table with handlers and callbacks at run-time using the XIntc_Connect()
* and XIntc_Disconnect() functions.
*
* Each vector table entry corresponds to a device that can generate an
* interrupt. Each entry contains an interrupt handler function and an argument
* to be passed to the handler when an interrupt occurs. The tools default this
* argument to the base address of the interrupting device. Note that the
* device driver interrupt handlers given in this file do not take a base
* address as an argument, but instead take a pointer to the driver instance.
* This means that although the table is created statically, the user must still
* use XIntc_Connect() when the interrupt handler takes an argument other than
* the base address. This is only to say that the existence of the static vector
* tables should not mislead the user into thinking they no longer need to
* register/connect interrupt handlers with this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 08/16/01 First release
* 1.00a rpm 01/09/02 Removed the AckLocation argument from XIntc_Connect().
* This information is now internal in xintc_g.c.
* 1.00b jhl 02/13/02 Repartitioned the driver for smaller files
* 1.00b jhl 04/24/02 Made LookupConfig function global and relocated config
* data type
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table. Moved vector
* table and options out of instance structure and into
* the configuration table.
* 1.10c mta 03/21/07 Updated to new coding style
* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed from
* all the macro names/definitions.
* 2.01a sdm 04/27/10 Updated the tcl so that the defintions are generated in
* the xparameters.h to know whether the optional registers
* SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
* This driver doesnot make use of these definitions and does
* not use the optional registers.
* 2.03a hvm 05/24/11 Updated the tcl to generate vector Ids for external
* interrupts. CR565336
* 2.04a bss 01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
* and XIntc_SetNormalIntrMode for setting to normal
* interrupt mode.
* 2.04a asa 03/19/12 Changed the XIntc_Config struct. The order of entries
* declared in the structure now matches with the
* XIntc_ConfigTable generated by the driver tcl.
* 2.05a bss 08/16/12 Updated to support relocatable vectors in Microblaze,
* added IntVectorAddr to XIntc_Config for this.
* Added XIntc_RegisterFastHandler API to register fast
* interrupt handlers using base address.
* 2.06a bss 01/28/13 To support Cascade mode:
* Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
* XIN_INTC_SECONDARY,XIN_INTC_LAST and
* XIN_CONTROLLER_MAX_INTRS macros
* Added NumberofIntrs and IntcType fields in XIntc_Config
* structure.
* Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
* XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
* XIntc_Acknowledge,XIntc_ConnectFastHandler and
* XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
* API in xintc.c
* Modified XIntc_DeviceInterruptHandler,
* XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
* XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
* API in xintc_l.c.
* Modified XIntc_SetOptions API in xintc_options.c.
* Modified XIntc_SimulateIntr API in xintc_selftest.c.
* Modified driver tcl:
* to check for Cascade mode and generate XPAR_INTC_TYPE
* for each controller.
* Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
* interrupt sources of all Controllers in Cascade mode.
* 2.07a bss 10/18/13 To support Nested interrupts:
* Modified XIntc_DeviceInterruptHandler API.
* Added XIN_ILR_OFFSET macro in xintc_l.h.
* Modified driver tcl to generate HAS_ILR parameter in
* xparameters.h
* 3.0 bss 01/28/13 Modified xintc.c to initialize IVAR register with
* XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
* CR#765931.
* Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
* correctly(CR#764865).
*
* @note
* For Cascade mode, Interrupt IDs are generated in xparameters.h
* as shown below:
*
* Master/Primary INTC
* ______
* | |-0 Secondary INTC
* | |-. ______
* | |-. | |-32 Last INTC
* | |-. | |-. ______
* |______|<-31------| |-. | |-64
* | |-. | |-.
* |______|<-63-------| |-.
* | |-.
* |______|-95
*
* All driver functions has to be called using DeviceId/
* InstancePtr/BaseAddress of Primary/Master Controller and
* Interrupts IDs generated in xparameters.h only.
* Driver functions takes care of Slave Controllers based on
* Interrupt ID passed. User must not use Interrupt source/ID
* 31 of Primary and Secondary controllers to call driver
* functions.
*
* For nested interrupts, XIntc_DeviceInterruptHandler saves
* microblaze r14 register on entry and restores on exit. This is
* required since compiler does not support nesting. It enables
* Microblaze interrupts after blocking further interrupts from
* the current interrupt number and interrupts below current
* interrupt proirity by writing to Interrupt Level Register of
* INTC on entry. On exit, it disables microblaze interrupts and
* restores ILR register default value(0xFFFFFFFF)back. It is
* recommended to increase STACK_SIZE in linker script for nested
* interrupts.
* 3.0 adk 12/10/13 Updated as per the New Tcl API's
* 3.0 adk 17/02/14 Fixed the CR:771287 Changes are made in the intc
* driver tcl.
* 3.1 adk 8/4/14 Fixed the CR:783248 Changes are made in
* the test-app tcl
* 3.2 bss 4/8/14 Fixed driver tcl to handle external interrupt pins
* correctly (CR#799609).
*
* </pre>
*
******************************************************************************/
#ifndef XINTC_H /* prevent circular inclusions */
#define XINTC_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xstatus.h"
#include "xintc_l.h"
/************************** Constant Definitions *****************************/
/**
* @name Configuration options
* These options are used in XIntc_SetOptions() to configure the device.
* @{
*/
/**
* <pre>
* XIN_SVC_SGL_ISR_OPTION Service the highest priority pending interrupt
* and then return.
* XIN_SVC_ALL_ISRS_OPTION Service all of the pending interrupts and then
* return.
* </pre>
*/
#define XIN_SVC_SGL_ISR_OPTION 1UL
#define XIN_SVC_ALL_ISRS_OPTION 2UL
/*@}*/
/**
* @name Start modes
* One of these values is passed to XIntc_Start() to start the device.
* @{
*/
/** Simulation only mode, no hardware interrupts recognized */
#define XIN_SIMULATION_MODE 0
/** Real mode, no simulation allowed, hardware interrupts recognized */
#define XIN_REAL_MODE 1
/*@}*/
/**
* @name Masks to specify Interrupt Controller Mode
* @{
*/
#define XIN_INTC_NOCASCADE 0 /* Normal - No Cascade Mode */
#define XIN_INTC_PRIMARY 1 /* Master/Primary controller */
#define XIN_INTC_SECONDARY 2 /* Secondary Slave Controllers */
#define XIN_INTC_LAST 3 /* Last Slave Controller */
/*@}*/
/**
* @name Mask to specify maximum number of interrupt sources per controller
* @{
*/
#define XIN_CONTROLLER_MAX_INTRS 32 /* Each Controller has 32
interrupt pins */
/*@}*/
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Register base address */
u32 AckBeforeService; /**< Ack location per interrupt */
int FastIntr; /**< Fast Interrupt enabled */
u32 IntVectorAddr; /**< Interrupt Vector Address */
int NumberofIntrs; /**< Number of Interrupt sources */
u32 Options; /**< Device options */
int IntcType; /**< Intc type 0 - No Cascade Mode
1 - primary instance
2 - secondary instance
3 - last instance */
/** Static vector table of interrupt handlers */
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
XIntc_VectorTableEntry HandlerTable[XIN_CONTROLLER_MAX_INTRS];
#else
XIntc_VectorTableEntry HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS];
#endif
} XIntc_Config;
/**
* The XIntc driver instance data. The user is required to allocate a
* variable of this type for every intc device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
u32 BaseAddress; /**< Base address of registers */
u32 IsReady; /**< Device is initialized and ready */
u32 IsStarted; /**< Device has been started */
u32 UnhandledInterrupts; /**< Intc Statistics */
XIntc_Config *CfgPtr; /**< Pointer to instance config entry */
} XIntc;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Required functions in xintc.c
*/
int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId);
int XIntc_Start(XIntc * InstancePtr, u8 Mode);
void XIntc_Stop(XIntc * InstancePtr);
int XIntc_Connect(XIntc * InstancePtr, u8 Id,
XInterruptHandler Handler, void *CallBackRef);
void XIntc_Disconnect(XIntc * InstancePtr, u8 Id);
void XIntc_Enable(XIntc * InstancePtr, u8 Id);
void XIntc_Disable(XIntc * InstancePtr, u8 Id);
void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id);
XIntc_Config *XIntc_LookupConfig(u16 DeviceId);
int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
XFastInterruptHandler Handler);
void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id);
/*
* Interrupt functions in xintr_intr.c
*/
void XIntc_VoidInterruptHandler(void);
void XIntc_InterruptHandler(XIntc * InstancePtr);
/*
* Options functions in xintc_options.c
*/
int XIntc_SetOptions(XIntc * InstancePtr, u32 Options);
u32 XIntc_GetOptions(XIntc * InstancePtr);
/*
* Self-test functions in xintc_selftest.c
*/
int XIntc_SelfTest(XIntc * InstancePtr);
int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

78
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_2/src/xintc_g.c
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@ -1,78 +0,0 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xintc.h"
extern void XNullHandler (void *);
/*
* The configuration table for devices
*/
XIntc_Config XIntc_ConfigTable[] =
{
{
XPAR_AXI_INTC_0_DEVICE_ID,
XPAR_AXI_INTC_0_BASEADDR,
XPAR_AXI_INTC_0_KIND_OF_INTR,
XPAR_AXI_INTC_0_HAS_FAST,
XPAR_AXI_INTC_0_IVAR_RESET_VALUE,
XPAR_AXI_INTC_0_NUM_INTR_INPUTS,
XIN_SVC_SGL_ISR_OPTION,
XPAR_AXI_INTC_0_TYPE,
{
{
XNullHandler,
(void *) XNULL
},
{
XNullHandler,
(void *) XNULL
},
{
XNullHandler,
(void *) XNULL
}
}
}
};

173
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View file

@ -1,173 +0,0 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_intr.c
*
* This file contains the interrupt processing for the XIntc component which
* is the driver for the Xilinx Interrupt Controller. The interrupt
* processing is partitioned seperately such that users are not required to
* use the provided interrupt processing. This file requires other files of
* the driver to be linked in also.
*
* Two different interrupt handlers are provided for this driver such that the
* user must select the appropriate handler for the application. The first
* interrupt handler, XIntc_VoidInterruptHandler, is provided for systems
* which use only a single interrupt controller or for systems that cannot
* otherwise provide an argument to the XIntc interrupt handler (e.g., the RTOS
* interrupt vector handler may not provide such a facility). The constant
* XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in
* the driver. The second interrupt handler, XIntc_InterruptHandler, uses an
* input argument which is an instance pointer to an interrupt controller driver
* such that multiple interrupt controllers can be supported. This handler
* requires the calling function to pass it the appropriate argument, so another
* level of indirection may be required.
*
* Note that both of these handlers are now only provided for backward
* compatibility. The handler defined in xintc_l.c is the recommended handler.
*
* The interrupt processing may be used by connecting one of the interrupt
* handlers to the interrupt system. These handlers do not save and restore
* the processor context but only handle the processing of the Interrupt
* Controller. The two handlers are provided as working examples. The user is
* encouraged to supply their own interrupt handler when performance tuning is
* deemed necessary.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.00b jhl 02/13/02 First release
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table. Collapse handlers
* to use the XIntc_DeviceInterruptHandler() in xintc_l.c.
* 1.00c rpm 04/09/04 Added conditional compilation around the old handler
* XIntc_VoidInterruptHandler(). This handler will only be
* include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is defined.
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
*
* </pre>
*
* @internal
*
* This driver assumes that the context of the processor has been saved prior to
* the calling of the Interrupt Controller interrupt handler and then restored
* after the handler returns. This requires either the running RTOS to save the
* state of the machine or that a wrapper be used as the destination of the
* interrupt vector to save the state of the processor and restore the state
* after the interrupt handler returns.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xintc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Interrupt handler for the driver used when there can be no argument passed
* to the handler. This function is provided mostly for backward compatibility.
* The user should use XIntc_DeviceInterruptHandler(), defined in xintc_l.c,
* if possible.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @return None.
*
* @note
*
* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler
* to be included in the driver compilation.
*
******************************************************************************/
#ifdef XPAR_INTC_SINGLE_DEVICE_ID
void XIntc_VoidInterruptHandler(void)
{
/* Use the single instance to call the main interrupt handler */
XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID);
}
#endif
/*****************************************************************************/
/**
*
* The interrupt handler for the driver. This function is provided mostly for
* backward compatibility. The user should use XIntc_DeviceInterruptHandler(),
* defined in xintc_l.c when possible and pass the device ID of the interrupt
* controller device as its argument.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIntc_InterruptHandler(XIntc * InstancePtr)
{
/* Assert that the pointer to the instance is valid
*/
Xil_AssertVoid(InstancePtr != NULL);
/* Use the instance's device ID to call the main interrupt handler.
* (the casts are to avoid a compiler warning)
*/
XIntc_DeviceInterruptHandler((void *)
((u32) (InstancePtr->CfgPtr->DeviceId)));
}

662
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View file

@ -1,662 +0,0 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_l.c
*
* This file contains low-level driver functions that can be used to access the
* device. The user should refer to the hardware device specification for more
* details of the device operation.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b jhl 04/24/02 First release
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table.
* 1.00c rpm 04/09/04 Added conditional compilation around the old handler
* XIntc_LowLevelInterruptHandler(). This handler will only
* be include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is
* defined.
* 1.10c mta 03/21/07 Updated to new coding style
* 1.10c ecm 07/09/07 Read the ISR after the Acknowledge in the interrupt
* handler to support architectures with posted write bus
* access issues.
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed
* from all the macro definitions.
* 2.04a bss 01/13/12 Removed the unused Register variable for warnings.
* 2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
* interrupt handlers using base address.
* 2.06a bss 01/28/13 To support Cascade mode:
* Modified XIntc_DeviceInterruptHandler,
* XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
* XIntc_RegisterFastHandler APIs.
* Added XIntc_CascadeHandler API.
* 2.07a bss 10/18/13 Modified XIntc_DeviceInterruptHandler to support
* nested interrupts.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
#include "xintc_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress);
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
static void XIntc_CascadeHandler(void *DeviceId);
#endif
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* This is the interrupt handler for the driver interface provided in this file
* when there can be no argument passed to the handler. In this case, we just
* use the globally defined device ID for the interrupt controller. This function
* is provided mostly for backward compatibility. The user should use
* XIntc_DeviceInterruptHandler() if possible.
*
* This function does not support multiple interrupt controller instances to be
* handled.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @return None.
*
* @note
*
* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler
* to be included in the driver compilation.
*
******************************************************************************/
#ifdef XPAR_INTC_SINGLE_DEVICE_ID
void XIntc_LowLevelInterruptHandler(void)
{
/*
* A level of indirection here because the interrupt handler used with
* the driver interface given in this file needs to remain void - no
* arguments. So we need the globally defined device ID of THE
* interrupt controller.
*/
XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID);
}
#endif
/*****************************************************************************/
/**
*
* This function is the primary interrupt handler for the driver. It must be
* connected to the interrupt source such that is called when an interrupt of
* the interrupt controller is active. It will resolve which interrupts are
* active and enabled and call the appropriate interrupt handler. It uses
* the AckBeforeService flag in the configuration data to determine when to
* acknowledge the interrupt. Highest priority interrupts are serviced first.
* This function assumes that an interrupt vector table has been previously
* initialized.It does not verify that entries in the table are valid before
* calling an interrupt handler. In Cascade mode this function calls
* XIntc_CascadeHandler to handle interrupts of Master and Slave controllers.
* This functions also handles interrupts nesting by saving and restoring link
* register of Microblaze and Interrupt Level register of interrupt controller
* properly.
* @param DeviceId is the zero-based device ID defined in xparameters.h
* of the interrupting interrupt controller. It is used as a direct
* index into the configuration data, which contains the vector
* table for the interrupt controller. Note that even though the
* argument is a void pointer, the value is not a pointer but the
* actual device ID. The void pointer type is necessary to meet
* the XInterruptHandler typedef for interrupt handlers.
*
* @return None.
*
* @note For nested interrupts, this function saves microblaze r14
* register on entry and restores on exit. This is required since
* compiler does not support nesting. This function enables
* Microblaze interrupts after blocking further interrupts
* from the current interrupt number and interrupts below current
* interrupt proirity by writing to Interrupt Level Register of
* INTC on entry. On exit, it disables microblaze interrupts and
* restores ILR register default value(0xFFFFFFFF)back. It is
* recommended to increase STACK_SIZE in linker script for nested
* interrupts.
*
******************************************************************************/
void XIntc_DeviceInterruptHandler(void *DeviceId)
{
u32 IntrStatus;
u32 IntrMask = 1;
int IntrNumber;
XIntc_Config *CfgPtr;
u32 Imr;
/* Get the configuration data using the device ID */
CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
XIntc_CascadeHandler(DeviceId);
}
else
#endif
{ /* This extra brace is required for compilation in Cascade Mode */
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
volatile u32 R14_register;
/* Save r14 register */
R14_register = mfgpr(r14);
#endif
volatile u32 ILR_reg;
/* Save ILR register */
ILR_reg = Xil_In32(CfgPtr->BaseAddress + XIN_ILR_OFFSET);
#endif
/* Get the interrupts that are waiting to be serviced */
IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/* Mask the Fast Interrupts */
if (CfgPtr->FastIntr == TRUE) {
Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
IntrStatus &= ~Imr;
}
/* Service each interrupt that is active and enabled by
* checking each bit in the register from LSB to MSB which
* corresponds to an interrupt input signal
*/
for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs;
IntrNumber++) {
if (IntrStatus & 1) {
XIntc_VectorTableEntry *TablePtr;
#if XPAR_XINTC_HAS_ILR == TRUE
/* Write to ILR the current interrupt
* number
*/
Xil_Out32(CfgPtr->BaseAddress +
XIN_ILR_OFFSET, IntrNumber);
/* Read back ILR to ensure the value
* has been updated and it is safe to
* enable interrupts
*/
Xil_In32(CfgPtr->BaseAddress +
XIN_ILR_OFFSET);
/* Enable interrupts */
Xil_ExceptionEnable();
#endif
/* If the interrupt has been setup to
* acknowledge it before servicing the
* interrupt, then ack it */
if (CfgPtr->AckBeforeService & IntrMask) {
XIntc_AckIntr(CfgPtr->BaseAddress,
IntrMask);
}
/* The interrupt is active and enabled, call
* the interrupt handler that was setup with
* the specified parameter
*/
TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
TablePtr->Handler(TablePtr->CallBackRef);
/* If the interrupt has been setup to
* acknowledge it after it has been serviced
* then ack it
*/
if ((CfgPtr->AckBeforeService &
IntrMask) == 0) {
XIntc_AckIntr(CfgPtr->BaseAddress,
IntrMask);
}
#if XPAR_XINTC_HAS_ILR == TRUE
/* Disable interrupts */
Xil_ExceptionDisable();
/* Restore ILR */
Xil_Out32(CfgPtr->BaseAddress + XIN_ILR_OFFSET,
ILR_reg);
#endif
/*
* Read the ISR again to handle architectures
* with posted write bus access issues.
*/
XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/*
* If only the highest priority interrupt is to
* be serviced, exit loop and return after
* servicing
* the interrupt
*/
if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
/* Restore r14 */
mtgpr(r14, R14_register);
#endif
#endif
return;
}
}
/* Move to the next interrupt to check */
IntrMask <<= 1;
IntrStatus >>= 1;
/* If there are no other bits set indicating that all
* interrupts have been serviced, then exit the loop
*/
if (IntrStatus == 0) {
break;
}
}
#if XPAR_XINTC_HAS_ILR == TRUE
#ifdef __MICROBLAZE__
/* Restore r14 */
mtgpr(r14, R14_register);
#endif
#endif
}
}
/*****************************************************************************/
/**
*
* Set the interrupt service option, which can configure the driver so that it
* services only a single interrupt at a time when an interrupt occurs, or
* services all pending interrupts when an interrupt occurs. The default
* behavior when using the driver interface given in xintc.h file is to service
* only a single interrupt, whereas the default behavior when using the driver
* interface given in this file is to service all outstanding interrupts when an
* interrupt occurs. In Cascade mode same Option is set to Slave controllers.
*
* @param BaseAddress is the unique identifier for a device.
* @param Option is XIN_SVC_SGL_ISR_OPTION if you want only a single
* interrupt serviced when an interrupt occurs, or
* XIN_SVC_ALL_ISRS_OPTION if you want all pending interrupts
* serviced when an interrupt occurs.
*
* @return None.
*
* @note
*
* Note that this function has no effect if the input base address is invalid.
*
******************************************************************************/
void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option)
{
XIntc_Config *CfgPtr;
CfgPtr = LookupConfigByBaseAddress(BaseAddress);
if (CfgPtr != NULL) {
CfgPtr->Options = Option;
/* If Cascade mode set the option for all Slaves */
if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
int Index;
for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1;
Index++) {
CfgPtr = XIntc_LookupConfig(Index);
CfgPtr->Options = Option;
}
}
}
}
/*****************************************************************************/
/**
*
* Register a handler function for a specific interrupt ID. The vector table
* of the interrupt controller is updated, overwriting any previous handler.
* The handler function will be called when an interrupt occurs for the given
* interrupt ID.
*
* This function can also be used to remove a handler from the vector table
* by passing in the XIntc_DefaultHandler() as the handler and NULL as the
* callback reference.
* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
* Controller
*
* @param BaseAddress is the base address of the interrupt controller
* whose vector table will be modified.
* @param InterruptId is the interrupt ID to be associated with the input
* handler.
* @param Handler is the function pointer that will be added to
* the vector table for the given interrupt ID.
* @param CallBackRef is the argument that will be passed to the new
* handler function when it is called. This is user-specific.
*
* @return None.
*
* @note
*
* Note that this function has no effect if the input base address is invalid.
*
******************************************************************************/
void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId,
XInterruptHandler Handler, void *CallBackRef)
{
XIntc_Config *CfgPtr;
CfgPtr = LookupConfigByBaseAddress(BaseAddress);
if (CfgPtr != NULL) {
if (InterruptId > 31) {
CfgPtr = XIntc_LookupConfig(InterruptId/32);
CfgPtr->HandlerTable[InterruptId%32].Handler = Handler;
CfgPtr->HandlerTable[InterruptId%32].CallBackRef =
CallBackRef;
}
else {
CfgPtr->HandlerTable[InterruptId].Handler = Handler;
CfgPtr->HandlerTable[InterruptId].CallBackRef =
CallBackRef;
}
}
}
/*****************************************************************************/
/**
*
* Looks up the device configuration based on the base address of the device.
* A table contains the configuration info for each device in the system.
*
* @param BaseAddress is the unique identifier for a device.
*
* @return
*
* A pointer to the configuration structure for the specified device, or
* NULL if the device was not found.
*
* @note None.
*
******************************************************************************/
static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress)
{
XIntc_Config *CfgPtr = NULL;
int Index;
for (Index = 0; Index < XPAR_XINTC_NUM_INSTANCES; Index++) {
if (XIntc_ConfigTable[Index].BaseAddress == BaseAddress) {
CfgPtr = &XIntc_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/*****************************************************************************/
/**
*
* Register a fast handler function for a specific interrupt ID. The handler
* function will be called when an interrupt occurs for the given interrupt ID.
* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
* Controller
*
* @param BaseAddress is the base address of the interrupt controller
* whose vector table will be modified.
* @param InterruptId is the interrupt ID to be associated with the input
* handler.
* @param FastHandler is the function pointer that will be called when
* interrupt occurs
*
* @return None.
*
* @note
*
* Note that this function has no effect if the input base address is invalid.
*
******************************************************************************/
void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id,
XFastInterruptHandler FastHandler)
{
u32 CurrentIER;
u32 Mask;
u32 Imr;
XIntc_Config *CfgPtr;
if (Id > 31) {
/* Enable user required Id in Slave controller */
CfgPtr = XIntc_LookupConfig(Id/32);
/* Get the Enabled Interrupts */
CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
/* Convert from integer id to bit mask */
Mask = XIntc_BitPosMask[(Id%32)];
/* Disable the Interrupt if it was enabled before calling
* this function
*/
if (CurrentIER & Mask) {
XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
(CurrentIER & ~Mask));
}
XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET +
((Id%32) * 4), (u32) FastHandler);
/* Slave controllers in Cascade Mode should have all as Fast
* interrupts or Normal interrupts, mixed interrupts are not
* supported
*/
XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF);
/* Enable the Interrupt if it was enabled before calling this
* function
*/
if (CurrentIER & Mask) {
XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
(CurrentIER | Mask));
}
}
else {
CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
/* Convert from integer id to bit mask */
Mask = XIntc_BitPosMask[Id];
if (CurrentIER & Mask) {
/* Disable Interrupt if it was enabled */
CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
(CurrentIER & ~Mask));
}
XIntc_Out32(BaseAddress + XIN_IVAR_OFFSET + (Id * 4),
(u32) FastHandler);
Imr = XIntc_In32(BaseAddress + XIN_IMR_OFFSET);
XIntc_Out32(BaseAddress + XIN_IMR_OFFSET, Imr | Mask);
/* Enable Interrupt if it was enabled before calling
* this function
*/
if (CurrentIER & Mask) {
CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
(CurrentIER | Mask));
}
}
}
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
/*****************************************************************************/
/**
*
* This function is called by primary interrupt handler for the driver to handle
* all Controllers in Cascade mode.It will resolve which interrupts are active
* and enabled and call the appropriate interrupt handler. It uses the
* AckBeforeService flag in the configuration data to determine when to
* acknowledge the interrupt. Highest priority interrupts are serviced first.
* This function assumes that an interrupt vector table has been previously
* initialized. It does not verify that entries in the table are valid before
* calling an interrupt handler.This function calls itself recursively to handle
* all interrupt controllers.
*
* @param DeviceId is the zero-based device ID defined in xparameters.h
* of the interrupting interrupt controller. It is used as a direct
* index into the configuration data, which contains the vector
* table for the interrupt controller.
*
* @return None.
*
* @note
*
******************************************************************************/
static void XIntc_CascadeHandler(void *DeviceId)
{
u32 IntrStatus;
u32 IntrMask = 1;
int IntrNumber;
u32 Imr;
XIntc_Config *CfgPtr;
static int Id = 0;
/* Get the configuration data using the device ID */
CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
/* Get the interrupts that are waiting to be serviced */
IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/* Mask the Fast Interrupts */
if (CfgPtr->FastIntr == TRUE) {
Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
IntrStatus &= ~Imr;
}
/* Service each interrupt that is active and enabled by
* checking each bit in the register from LSB to MSB which
* corresponds to an interrupt input signal
*/
for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs; IntrNumber++) {
if (IntrStatus & 1) {
XIntc_VectorTableEntry *TablePtr;
/* In Cascade mode call this function recursively
* for interrupt id 31 and until interrupts of last
* instance/controller are handled
*/
if ((IntrNumber == 31) &&
(CfgPtr->IntcType != XIN_INTC_LAST) &&
(CfgPtr->IntcType != XIN_INTC_NOCASCADE)) {
XIntc_CascadeHandler((void *)++Id);
Id--;
}
/* If the interrupt has been setup to
* acknowledge it before servicing the
* interrupt, then ack it */
if (CfgPtr->AckBeforeService & IntrMask) {
XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
}
/* Handler of 31 interrupt Id has to be called only
* for Last controller in cascade Mode
*/
if (!((IntrNumber == 31) &&
(CfgPtr->IntcType != XIN_INTC_LAST) &&
(CfgPtr->IntcType != XIN_INTC_NOCASCADE))) {
/* The interrupt is active and enabled, call
* the interrupt handler that was setup with
* the specified parameter
*/
TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
TablePtr->Handler(TablePtr->CallBackRef);
}
/* If the interrupt has been setup to acknowledge it
* after it has been serviced then ack it
*/
if ((CfgPtr->AckBeforeService & IntrMask) == 0) {
XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
}
/*
* Read the ISR again to handle architectures with
* posted write bus access issues.
*/
XIntc_GetIntrStatus(CfgPtr->BaseAddress);
/*
* If only the highest priority interrupt is to be
* serviced, exit loop and return after servicing
* the interrupt
*/
if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
return;
}
}
/* Move to the next interrupt to check */
IntrMask <<= 1;
IntrStatus >>= 1;
/* If there are no other bits set indicating that all interrupts
* have been serviced, then exit the loop
*/
if (IntrStatus == 0) {
break;
}
}
}
#endif

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@ -1,327 +0,0 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_l.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
*
* Note that users of the driver interface given in this file can register
* an interrupt handler dynamically (at run-time) using the
* XIntc_RegisterHandler() function.
* User of the driver interface given in xintc.h should still use
* XIntc_Connect(), as always.
* Also see the discussion of the interrupt vector tables in xintc.h.
*
* There are currently two interrupt handlers specified in this interface.
*
* - XIntc_LowLevelInterruptHandler() is a handler without any arguments that
* is used in cases where there is a single interrupt controller device in
* the system and the handler cannot be passed an argument. This function is
* provided mostly for backward compatibility.
*
* - XIntc_DeviceInterruptHandler() is a handler that takes a device ID as an
* argument, indicating which interrupt controller device in the system is
* causing the interrupt - thereby supporting multiple interrupt controllers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00b jhl 04/24/02 First release
* 1.00c rpm 10/17/03 New release. Support the static vector table created
* in the xintc_g.c configuration table.
* 1.10c mta 03/21/07 Updated to new coding style
* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. _m is removed from all
* the macro definitions.
* 2.04a bss 01/13/12 Updated for adding defines for IMR and IVAR for
* the FAST Interrupt
* 2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
* interrupt handlers using base address.
* 2.07a bss 10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.
*
* </pre>
*
******************************************************************************/
#ifndef XINTC_L_H /* prevent circular inclusions */
#define XINTC_L_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xil_io.h"
/*
* XPAR_XINTC_USE_DCR_BRIDGE has to be set to 1 if the Intc device will be
* accessed through a DCR bus connected to a bridge.
*/
#define XPAR_XINTC_USE_DCR_BRIDGE 0
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#include "xio_dcr.h"
#endif
/************************** Constant Definitions *****************************/
/* define the offsets from the base address for all the registers of the
* interrupt controller, some registers may be optional in the hardware device
*/
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
#define XIN_IPR_OFFSET 1 /* Interrupt Pending Register */
#define XIN_IER_OFFSET 2 /* Interrupt Enable Register */
#define XIN_IAR_OFFSET 3 /* Interrupt Acknowledge Register */
#define XIN_SIE_OFFSET 4 /* Set Interrupt Enable Register */
#define XIN_CIE_OFFSET 5 /* Clear Interrupt Enable Register */
#define XIN_IVR_OFFSET 6 /* Interrupt Vector Register */
#define XIN_MER_OFFSET 7 /* Master Enable Register */
#define XIN_IMR_OFFSET 8 /* Interrupt Mode Register , this is present
* only for Fast Interrupt */
#define XIN_IVAR_OFFSET 64 /* Interrupt Vector Address Register
* Interrupt 0 Offest, this is present
* only for Fast Interrupt */
#else /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
#define XIN_IPR_OFFSET 4 /* Interrupt Pending Register */
#define XIN_IER_OFFSET 8 /* Interrupt Enable Register */
#define XIN_IAR_OFFSET 12 /* Interrupt Acknowledge Register */
#define XIN_SIE_OFFSET 16 /* Set Interrupt Enable Register */
#define XIN_CIE_OFFSET 20 /* Clear Interrupt Enable Register */
#define XIN_IVR_OFFSET 24 /* Interrupt Vector Register */
#define XIN_MER_OFFSET 28 /* Master Enable Register */
#define XIN_IMR_OFFSET 32 /* Interrupt Mode Register , this is present
* only for Fast Interrupt */
#define XIN_ILR_OFFSET 36 /* Interrupt level register */
#define XIN_IVAR_OFFSET 0x100 /* Interrupt Vector Address Register
* Interrupt 0 Offest, this is present
* only for Fast Interrupt */
#endif /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
/* Bit definitions for the bits of the MER register */
#define XIN_INT_MASTER_ENABLE_MASK 0x1UL
#define XIN_INT_HARDWARE_ENABLE_MASK 0x2UL /* once set cannot be cleared */
/**************************** Type Definitions *******************************/
/* The following data type defines each entry in an interrupt vector table.
* The callback reference is the base address of the interrupting device
* for the driver interface given in this file and an instance pointer for the
* driver interface given in xintc.h file.
*/
typedef struct {
XInterruptHandler Handler;
void *CallBackRef;
} XIntc_VectorTableEntry;
typedef void (*XFastInterruptHandler) (void);
/***************** Macros (Inline Functions) Definitions *********************/
/*
* Define the appropriate I/O access method to memory mapped I/O or DCR.
*/
#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
#define XIntc_In32 XIo_DcrIn
#define XIntc_Out32 XIo_DcrOut
#else
#define XIntc_In32 Xil_In32
#define XIntc_Out32 Xil_Out32
#endif
/****************************************************************************/
/**
*
* Enable all interrupts in the Master Enable register of the interrupt
* controller. The interrupt controller defaults to all interrupts disabled
* from reset such that this macro must be used to enable interrupts.
*
* @param BaseAddress is the base address of the device.
*
* @return None.
*
* @note C-style signature:
* void XIntc_MasterEnable(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_MasterEnable(BaseAddress) \
XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, \
XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK)
/****************************************************************************/
/**
*
* Disable all interrupts in the Master Enable register of the interrupt
* controller.
*
* @param BaseAddress is the base address of the device.
*
* @return None.
*
* @note C-style signature:
* void XIntc_MasterDisable(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_MasterDisable(BaseAddress) \
XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)
/****************************************************************************/
/**
*
* Enable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param EnableMask is the 32-bit value to write to the enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only the bits which are set in the mask will enable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask);
*
*****************************************************************************/
#define XIntc_EnableIntr(BaseAddress, EnableMask) \
XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
/****************************************************************************/
/**
*
* Disable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param DisableMask is the 32-bit value to write to the enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only the bits which are set in the mask will disable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask);
*
*****************************************************************************/
#define XIntc_DisableIntr(BaseAddress, DisableMask) \
XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
/****************************************************************************/
/**
*
* Acknowledge specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param AckMask is the 32-bit value to write to the acknowledge
* register. Each bit of the mask corresponds to an interrupt input
* signal that is connected to the interrupt controller (INT0 =
* LSB). Only the bits which are set in the mask will acknowledge
* interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIntc_AckIntr(u32 BaseAddress, u32 AckMask);
*
*****************************************************************************/
#define XIntc_AckIntr(BaseAddress, AckMask) \
XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
/****************************************************************************/
/**
*
* Get the interrupt status from the interrupt controller which indicates
* which interrupts are active and enabled.
*
* @param BaseAddress is the base address of the device
*
* @return The 32-bit contents of the interrupt status register. Each bit
* corresponds to an interrupt input signal that is connected to
* the interrupt controller (INT0 = LSB). Bits which are set
* indicate an active interrupt which is also enabled.
*
* @note C-style signature:
* u32 XIntc_GetIntrStatus(u32 BaseAddress);
*
*****************************************************************************/
#define XIntc_GetIntrStatus(BaseAddress) \
(XIntc_In32((BaseAddress) + XIN_ISR_OFFSET) & \
XIntc_In32((BaseAddress) + XIN_IER_OFFSET))
/************************** Function Prototypes ******************************/
/*
* Interrupt controller handlers, to be connected to processor exception
* handling code.
*/
void XIntc_LowLevelInterruptHandler(void);
void XIntc_DeviceInterruptHandler(void *DeviceId);
/* Various configuration functions */
void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option);
void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId,
XInterruptHandler Handler, void *CallBackRef);
void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id,
XFastInterruptHandler FastHandler);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

146
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@ -1,146 +0,0 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_options.c
*
* Contains option functions for the XIntc driver. These functions allow the
* user to configure an instance of the XIntc driver. This file requires other
* files of the component to be linked in also.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00b jhl 02/21/02 First release
* 1.00c rpm 10/17/03 New release. Support the relocation of the options flag
* from the instance structure to the xintc_g.c
* configuration table.
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs
* 2.06a bss 01/28/13 To support Cascade mode:
* Modified XIntc_SetOptions API.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Set the options for the interrupt controller driver. In Cascade mode same
* Option is set to Slave controllers.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
* @param Options to be set. The available options are described in
* xintc.h.
*
* @return
* - XST_SUCCESS if the options were set successfully
* - XST_INVALID_PARAM if the specified option was not valid
*
* @note None.
*
****************************************************************************/
int XIntc_SetOptions(XIntc * InstancePtr, u32 Options)
{
XIntc_Config *CfgPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Make sure option request is valid
*/
if ((Options == XIN_SVC_SGL_ISR_OPTION) ||
(Options == XIN_SVC_ALL_ISRS_OPTION)) {
InstancePtr->CfgPtr->Options = Options;
/* If Cascade mode set the option for all Slaves */
if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
int Index;
for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1;
Index++) {
CfgPtr = XIntc_LookupConfig(Index);
CfgPtr->Options = Options;
}
}
return XST_SUCCESS;
}
else {
return XST_INVALID_PARAM;
}
}
/*****************************************************************************/
/**
*
* Return the currently set options.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
*
* @return The currently set options. The options are described in xintc.h.
*
* @note None.
*
****************************************************************************/
u32 XIntc_GetOptions(XIntc * InstancePtr)
{
/*
* Assert the arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return InstancePtr->CfgPtr->Options;
}

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@ -1,252 +0,0 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xintc_selftest.c
*
* Contains diagnostic self-test functions for the XIntc component. This file
* requires other files of the component to be linked in also.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b jhl 02/21/02 First release
* 1.10c mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs
* 2.04a bss 01/16/12 Removed CurrentMIE variable and reading of the
* MER register to remove warnings
* 2.06a bss 01/28/13 To support Cascade mode:
* Modified XIntc_SimulateIntr API.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xintc.h"
#include "xintc_i.h"
/************************** Constant Definitions *****************************/
#define XIN_TEST_MASK 1
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Run a self-test on the driver/device. This is a destructive test.
*
* This involves forcing interrupts into the controller and verifying that they
* are recognized and can be acknowledged. This test will not succeed if the
* interrupt controller has been started in real mode such that interrupts
* cannot be forced.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
*
* @return
* - XST_SUCCESS if self-test is successful.
* - XST_INTC_FAIL_SELFTEST if the Interrupt controller fails the
* self-test. It will fail the self test if the device has
* previously been started in real mode.
*
* @note None.
*
******************************************************************************/
int XIntc_SelfTest(XIntc * InstancePtr)
{
u32 CurrentISR;
u32 Temp;
/*
* Assert the arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Acknowledge all pending interrupts by reading the interrupt status
* register and writing the value to the acknowledge register
*/
Temp = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Temp);
/*
* Verify that there are no interrupts by reading the interrupt status
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
/*
* ISR should be zero after all interrupts are acknowledged
*/
if (CurrentISR != 0) {
return XST_INTC_FAIL_SELFTEST;
}
/*
* Set a bit in the ISR which simulates an interrupt
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, XIN_TEST_MASK);
/*
* Verify that it was set
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
if (CurrentISR != XIN_TEST_MASK) {
return XST_INTC_FAIL_SELFTEST;
}
/*
* Acknowledge the interrupt
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, XIN_TEST_MASK);
/*
* Read back the ISR to verify that the interrupt is gone
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
if (CurrentISR != 0) {
return XST_INTC_FAIL_SELFTEST;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Allows software to simulate an interrupt in the interrupt controller. This
* function will only be successful when the interrupt controller has been
* started in simulation mode. Once it has been started in real mode,
* interrupts cannot be simulated. A simulated interrupt allows the interrupt
* controller to be tested without any device to drive an interrupt input
* signal into it. In Cascade mode writes to ISR of appropraite Slave
* controller depending on Id.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
* @param Id is the interrupt ID for which to simulate an interrupt.
*
* @return
* - XST_SUCCESS if successful
* - XST_FAILURE if the interrupt could not be
* simulated because the interrupt controller is or
* has previously been in real mode.
*
* @note None.
*
******************************************************************************/
int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id)
{
u32 Mask;
u32 MasterEnable;
XIntc_Config *CfgPtr;
int Index;
int DeviceId;
/*
* Assert the arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
/* Get the contents of the master enable register and determine if
* hardware interrupts have already been enabled, if so, this is a write
* once bit such that simulation can't be done at this point because
* the ISR register is no longer writable by software
*/
MasterEnable = XIntc_In32(InstancePtr->BaseAddress + XIN_MER_OFFSET);
if (MasterEnable & XIN_INT_HARDWARE_ENABLE_MASK) {
return XST_FAILURE;
}
if (Id > 31) {
DeviceId = Id/32;
CfgPtr = XIntc_LookupConfig(Id/32);
Mask = XIntc_BitPosMask[Id%32];
XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET, Mask);
/* Generate interrupt for 31 by writing to Interrupt Status
* register of parent controllers. Primary controller ISR
* will be written last in the loop
*/
Mask = XIntc_BitPosMask[31];
for (Index = DeviceId - 1; Index >= 0; Index--)
{
CfgPtr = XIntc_LookupConfig(Index);
XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET,
Mask);
}
}
else {
/*
* The Id is used to create the appropriate mask for the
* desired bit position.
*/
Mask = XIntc_BitPosMask[Id];
/*
* Enable the selected interrupt source by reading the interrupt
* enable register and then modifying only the specified
* interrupt id enable
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, Mask);
}
/* indicate the interrupt was successfully simulated */
return XST_SUCCESS;
}

4
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/mig_7series_v2_0/src/xmig_7series.h
View file

@ -33,6 +33,9 @@
/**
*
* @file xmig_7series.h
* @addtogroup mig_7series_v2_0
* @{
* @details
* This driver exists only to allow the SDK tools to create a memory test
* application and to populate xparameters.h with memory range constants.
* There is no source code.
@ -40,3 +43,4 @@
* 2.0 adk 19/12/13 Updated as per the New Tcl API's
*
******************************************************************************/
/** @} */

68
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_dcache.S
View file

@ -1,68 +0,0 @@
/******************************************************************************
* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* File : microblaze_disable_dcache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Disable the L1 dcache on the microblaze.
*
*******************************************************************************/
#include "xparameters.h"
.text
.globl microblaze_disable_dcache
.ent microblaze_disable_dcache
.align 2
microblaze_disable_dcache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
addik r1, r1, -4
swi r15, r1, 0
brlid r15, microblaze_flush_dcache /* microblaze_flush_dcache does not use r1*/
nop
lwi r15, r1, 0
addi r1, r1, 4
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
rtsd r15, 8
msrclr r0, 0x80
#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 1 */
addik r1, r1, -4
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
swi r15, r1, 0
brlid r15, microblaze_flush_dcache
nop
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
mfs r11, rmsr
andi r11, r11, ~(0x80)
mts rmsr, r11
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
lwi r15, r1, 0
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
rtsd r15, 8
addi r1, r1, 4
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_disable_dcache

360
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_timer_hw.c
View file

@ -1,360 +0,0 @@
// $Id: _profile_timer_hw.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************
*
* _program_timer_hw.c:
* Timer related functions
*
******************************************************************************/
#include "profile.h"
#include "_profile_timer_hw.h"
#include "xil_exception.h"
#ifdef PROC_PPC
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif // TIMER_CONNECT_INTC
//#ifndef PPC_PIT_INTERRUPT
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
#endif
extern unsigned int timer_clk_ticks ;
//--------------------------------------------------------------------
// PowerPC Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_PPC405
//--------------------------------------------------------------------
// PowerPC PIT Timer Init.
// Defined only if PIT Timer is used for Profiling
//
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
int ppc_pit_init( void )
{
// 1. Register Profile_intr_handler as Interrupt handler
// 2. Set PIT Timer Interrupt and Enable it.
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
XTime_PITSetInterval( timer_clk_ticks ) ;
XTime_PITEnableAutoReload() ;
return 0;
}
#endif
//--------------------------------------------------------------------
// PowerPC Timer Initialization functions.
// For PowerPC, PIT and opb_timer can be used for Profiling. This
// is selected by the user in standalone BSP
//
//--------------------------------------------------------------------
int powerpc405_init()
{
Xil_ExceptionInit() ;
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
// Initialize the Timer.
// 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
#ifdef PPC_PIT_INTERRUPT
ppc_pit_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
#endif
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_PITEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
#endif
return 0;
}
#endif // PROC_PPC
//--------------------------------------------------------------------
// PowerPC440 Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_PPC440
//--------------------------------------------------------------------
// PowerPC DEC Timer Init.
// Defined only if DEC Timer is used for Profiling
//
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
int ppc_dec_init( void )
{
// 1. Register Profile_intr_handler as Interrupt handler
// 2. Set DEC Timer Interrupt and Enable it.
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
XTime_DECSetInterval( timer_clk_ticks ) ;
XTime_DECEnableAutoReload() ;
return 0;
}
#endif
//--------------------------------------------------------------------
// PowerPC Timer Initialization functions.
// For PowerPC, DEC and opb_timer can be used for Profiling. This
// is selected by the user in standalone BSP
//
//--------------------------------------------------------------------
int powerpc405_init(void)
{
Xil_ExceptionInit();
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
// Initialize the Timer.
// 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
#ifdef PPC_PIT_INTERRUPT
ppc_dec_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
#endif
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_DECEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
#endif
return 0;
}
#endif // PROC_PPC440
//--------------------------------------------------------------------
// opb_timer Initialization for PowerPC and MicroBlaze. This function
// is not needed if DEC timer is used in PowerPC
//
//--------------------------------------------------------------------
//#ifndef PPC_PIT_INTERRUPT
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
int opb_timer_init( void )
{
// set the number of cycles the timer counts before interrupting
XTmrCtr_SetLoadReg(PROFILE_TIMER_BASEADDR, 0, timer_clk_ticks);
// reset the timers, and clear interrupts
XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0,
XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
// start the timers
XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK
| XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
return 0;
}
#endif
//--------------------------------------------------------------------
// MicroBlaze Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_MICROBLAZE
//--------------------------------------------------------------------
// Initialize the Profile Timer for MicroBlaze Target.
// For MicroBlaze, opb_timer is used. The opb_timer can be directly
// connected to MicroBlaze or connected through Interrupt Controller.
//
//--------------------------------------------------------------------
int microblaze_init(void)
{
// Register profile_intr_handler
// 1. If timer is connected to Interrupt Controller, register the handler
// to Interrupt Controllers vector table.
// 2. If timer is directly connected to MicroBlaze, register the handler
// as Interrupt handler
Xil_ExceptionInit();
#ifdef TIMER_CONNECT_INTC
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)profile_intr_handler,
(void *)0) ;
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
#endif
#endif
Xil_ExceptionEnable();
return 0;
}
#endif // PROC_MICROBLAZE
//--------------------------------------------------------------------
// Cortex A9 Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_CORTEXA9
//--------------------------------------------------------------------
// Initialize the Profile Timer for Cortex A9 Target.
// The scu private timer is connected to the Scu GIC controller.
//
//--------------------------------------------------------------------
int scu_timer_init( void )
{
// set the number of cycles the timer counts before interrupting
// scu timer runs at half the cpu clock
XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2);
// clear any pending interrupts
XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1);
// enable interrupts, auto-reload mode and start the timer
XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
return 0;
}
int cortexa9_init(void)
{
Xil_ExceptionInit();
XScuGic_DeviceInitialize(0);
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
(void *)0);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
PROFILE_TIMER_INTR_ID,
(Xil_ExceptionHandler)profile_intr_handler,
(void *)0);
/*
* Enable the interrupt for scu timer.
*/
XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
/*
* Initialize the timer with Timer Ticks
*/
scu_timer_init() ;
Xil_ExceptionEnable();
return 0;
}
#endif // PROC_CORTEXA9

59
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/xdebug.h
View file

@ -1,59 +0,0 @@
#ifndef XDEBUG
#define XDEBUG
#if defined(DEBUG) && !defined(NDEBUG)
#ifndef XDEBUG_WARNING
#define XDEBUG_WARNING
#warning DEBUG is enabled
#endif
int printf(const char *format, ...);
#define XDBG_DEBUG_ERROR 0x00000001 /* error condition messages */
#define XDBG_DEBUG_GENERAL 0x00000002 /* general debug messages */
#define XDBG_DEBUG_ALL 0xFFFFFFFF /* all debugging data */
#define XDBG_DEBUG_FIFO_REG 0x00000100 /* display register reads/writes */
#define XDBG_DEBUG_FIFO_RX 0x00000101 /* receive debug messages */
#define XDBG_DEBUG_FIFO_TX 0x00000102 /* transmit debug messages */
#define XDBG_DEBUG_FIFO_ALL 0x0000010F /* all fifo debug messages */
#define XDBG_DEBUG_TEMAC_REG 0x00000400 /* display register reads/writes */
#define XDBG_DEBUG_TEMAC_RX 0x00000401 /* receive debug messages */
#define XDBG_DEBUG_TEMAC_TX 0x00000402 /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ALL 0x0000040F /* all temac debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800 /* receive debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801 /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802 /* ioctl debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803 /* debug msg for other routines */
#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080F /* all temac adapter debug messages */
#define xdbg_current_types (XDBG_DEBUG_ERROR)
#define xdbg_stmnt(x) x
/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
* macros that accept variable number of arguments
*/
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
#else /* ANSI Syntax */
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
#endif
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x)
/* See VxWorks comments above */
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...)
#else /* ANSI Syntax */
#define xdbg_printf(...)
#endif
#endif /* defined(DEBUG) && !defined(NDEBUG) */
#endif /* XDEBUG */

11
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/Makefile → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/Makefile
View file

@ -1,6 +1,6 @@
###############################################################################
#
# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
@ -27,11 +27,12 @@
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
######################################################################
#
###############################################################################
# The following are defined in config.make
# LIBSOURCES - Based on if MicroBlaze support Exceptions
# LIBS - Do Build Profile Libraries
# LIBS - Do Build Profile Libraries
include config.make
AS=mb-as
@ -49,7 +50,7 @@ RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
OUTS = *.o
INCLUDEFILES=*.h
@ -58,7 +59,7 @@ libs: $(LIBS)
standalone_libs: $(LIBSOURCES)
echo "Compiling standalone";
$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
$(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
$(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
profile_libs:
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" libs

11
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/_exit.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/_exit.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -31,11 +31,16 @@
******************************************************************************/
#include <unistd.h>
#include "xil_types.h"
void _exit (sint32 status);
/* _exit - Simple implementation. Does not return.
*/
void _exit (int status)
void _exit (sint32 status)
{
(void) status;
while (1);
while (1)
{
;
}
}

6
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/bspconfig.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -22,8 +22,8 @@
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*

170
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/changelog.txt → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/changelog.txt
View file

@ -3,7 +3,7 @@
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
* 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
* cacheable regions
@ -94,13 +94,13 @@
* Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
* fixes the CR #692094.
* 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
* 3.10a srt 04/18/13 Implemented ARM Erratas.
* 3.10a srt 04/18/13 Implemented ARM Erratas.
* Cortex A9 Errata - 742230, 743622, 775420, 794073
* L2Cache PL310 Errata - 588369, 727915, 759370
* Please refer to file 'xil_errata.h' for errata
* description.
* 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
* cache APIs were corresponding to only Layer 1 cache
* cache APIs were corresponding to only Layer 1 cache
* memories. New APIs were now added and the existing cache
* related APIs were changed to provide a uniform interface
* to flush/invalidate/enable/disable the complete cache
@ -115,13 +115,13 @@
* microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
* microblaze_invalidate_cache_ext_range -> Invalidates a
* range of memory in L2 cache.
* These changes are done to implement PR #697214.
* These changes are done to implement PR #697214.
* 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
* fix the CR #706464. L2 cache disabling happens independent
* of L1 data cache disable operation. Changes are done in the
* same file in cache handling APIs to do a L2 cache sync
* (poll reg7_?cache_?sync). This fixes CR #700542.
* 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
* same file in cache handling APIs to do a L2 cache sync
* (poll reg7_?cache_?sync). This fixes CR #700542.
* 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
* interrupts for ARM. These are done to fix the CR#699680.
* 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
* sync operation. This fixes the CR# 716781.
@ -131,11 +131,11 @@
* fix issues related to NEON context saving. The assembly
* routines for IRQ and FIQ handling are modified.
* Deprecated the older BSP (3.10a).
* 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
* 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
* various potential issues. Made changes in the function
* Xil_SetAttributes in file xil_mmu.c.
* 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
* in src\cortexa9 and src\microblaze folders.
* in src\cortexa9 and src\microblaze folders.
* 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
* L2 cache sync operation and to fix issues around complete
* L2 cache flush/invalidation by ways.
@ -143,23 +143,23 @@
* to fix linking issues with armcc/DS-5. Modified the armcc
* makefile to fix issues.
* 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
* 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
* 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
* 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
* and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
* and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
* src\cortexa9\armcc\) to fix CR#767251
* 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
* 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
* Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
* Few cache lines were missed to invalidate when unaligned address
* invalidation was accommodated in Xil_DCacheInvalidateRange.
* invalidation was accommodated in Xil_DCacheInvalidateRange.
* In Xil_L1DCacheInvalidate, while invalidating all L1D cache
* stack memory (which contains return address) was invalidated. So
* stack memory is flushed first and then L1D cache is invalidated.
* This is done to fix CR #763829
* 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
* mblaze_nt_types.h file and replace uint32_t with u32 in the
* profile_hist.c to fix the above CR.
* 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
* mblaze_nt_types.h file and replace uint32_t with u32 in the
* profile_hist.c to fix the above CR.
* 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
* instead of libxil.a and added prototypes for
* instead of libxil.a and added prototypes for
* microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
* mb_interface.h
* 4.1 hk 04/18/14 Add sleep function.
@ -173,28 +173,28 @@
* Fix for CR#764881.
* 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
* output the DEBUG logs when -DDEBUG flag is enabled in BSP.
* 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
* 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
* Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
* 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
* cortexa9/armcc/boot.s. Added default exception handlers for data
* cortexa9/armcc/boot.s. Added default exception handlers for data
* abort and prefetch abort using handlers called
* DataAbortHandler and PrefetchAbortHandler respectively in
* DataAbortHandler and PrefetchAbortHandler respectively in
* cortexa9/xil_exception.c to fix CR#802862.
* 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
* issue of improper linking of translation_table.s
* 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
* issue of improper linking of translation_table.s
* 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
* in tool chain to avoid conflicts into some special cases
* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
* Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
* 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
* containing type def u32 defined in xil_types.g to resolve issue of
* 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
* containing type def u32 defined in xil_types.g to resolve issue of
* CR#805869
* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
* it is not possible to generate timer in nanosecond due to limited
* cpu frequency
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
* uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
* and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
* and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
* removed function definition of XSmc_NorInit and XSmc_NorInit from
* cortexa9/smc.h
* 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
@ -209,4 +209,116 @@
* 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
* and cortexa9/armcc/translation_table.s to resolve compilation
* error for solving CR#822897
******************************************************************************************/
* 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for
* MISRA-C:2012 compliance.
* 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by
* adding src/common/xplatform_info.*s
* 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and
* removed incorrect initialization of TLB lockdown register to fix
* CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
* and iccarm/boot.s
* 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
* for iccarm and armcc compiler of cortexA9
* 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
* and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
* caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
* of L2Cache is done later.
* 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
* Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
* taking long time to fix CR#853097. L2CacheSync is added into
* Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
* Xil_L2CacheInvalidate APIs are modified to flush the complete stack
* instead of just System Stack
* 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
* to update ECC_FLAGS and also take the compiler and archiver as specified
* in settings instead of hardcoding it.
* 5.2 pkp 06/08/15 Modified cortexa9/gcc/translation_table.S to put a check for
* XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
* accordingly generate the translation table
* 5.2 pkp 23/07/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
* to update ECC_FLAGS to fix a bug introduced during new version creation
* of BSP.
* 5.3 pkp 10/07/15 Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
* functionalities are avoided for the OpenAMP slave application(when
* USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
* cache for its operation. Also file operations such as read, write,
* close, open are also avoided for OpenAMP support(when USE_AMP flag is
* defined for BSP) because XilOpenAMP library contains own file operation.
* The xil-crt0.S file is modified for not initializing global timer for
* OpenAMP application as it might be already in use by master CPU
* 5.3 pkp 10/09/15 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
* definition for dsb, isb and dmb to fix the compilation error when used
* kvn 16/10/15 Encapsulated assembly code into macros for R5 xil_cache file.
* 5.4 pkp 09/11/15 Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
* R5 deadlock for errata 780125
* 5.4 pkp 09/11/15 Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
* 32 bit BSP in the initialization
* 5.4 pkp 09/11/15 Modified cortexa9/xil_misc_psreset_api.c file to change the description
* for XOcm_Remap function
* 5.4 pkp 16/11/15 Modified microblaze/xil_misc_psreset_api.c file to change the description
* for XOcm_Remap function
* kvn 21/11/15 Added volatile keyword for ADDR varibles in Xil_Out API
* kvn 21/11/15 Changed ADDR variable type from u32 to UINTPTR. This is
* required for MISRA-C:2012 Compliance.
* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
* in cortexa9/xil_mmu.h
* 5.4 pkp 23/11/15 Added default undefined exception handler for Cortex-A9
* 5.4 pkp 11/12/15 Modified common/xplatform_info.h to add #defines for silicon for
* checking the current executing platform
* 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
* to initialize global constructor for C++ applications
* 5.4 pkp 18/12/15 Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
* C++ applications
* 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
* translation_table.S to update the translation table according to proper
* address map
* 5.4 pkp 18/12/15 Modified cortexar5/mpu.c to initialize the MPU according to proper
* address map
* 5.4 pkp 05/01/16 Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
* equivalent to vector table base address
* 5.4 pkp 08/01/16 Modified cortexa9/gcc/Makefile to update the extra compiler flag
* as per the toolchain update
* 5.4 pkp 12/01/16 Changed common/xplatform_info.* to add platform information support
* for Cortex-A53 32bit mode
* 5.4 pkp 28/01/16 Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
* and usleep.c to correct routines to avoid hardcoding the timer frequency,
* instead take it from xparameters.h to properly configure the timestamp
* clock frequency
* 5.4 asa 29/01/16 Modified microblaze/mb_interface.h to add macros that support the
* new instructions for MB address extension feature
* 5.4 kvn 30/01/16 Modified xparameters_ps.h file to add interrupt ID number for
* system monitor.
* 5.4 pkp 04/02/16 Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
* 5.4 pkp 19/02/16 Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
* cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
* cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
* use set of assembly instructions to provide required delay to fix
* CR#913249.
* 5.4 asa 25/02/16 Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
* _exit with exit. We should not be directly calling _exit and should
* always use the library exit. This fixes the CR#937036.
* 5.4 pkp 25/02/16 Made change to cortexr5/gcc/boot.S to initialize the floating point
* registers, banked registers for various modes and enabled
* the cache ECC check before enabling the fault log for lock step mode
* Also modified the cortexr5/gcc/Makefile to support floating point
* registers initialization in boot code.
* 5.4 pkp 03/01/16 Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
* logic in case of lock-step mode when fault log is enabled to fix
* CR#938281
* 5.4 pkp 03/02/16 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
* header file instrinsics.h which contains assembly instructions
* definitions which can be used by C
* 5.4 asa 03/02/16 Added print.c in MB BSP. Made other cosmetic changes to have uniform
* proto for all print.c across the BSPs. This patch fixes CR#938738.
* 5.4 pkp 03/09/16 Modified cortexr5/sleep.c and usleep.c to avoid disabling the
* interrupts when sleep/usleep is being executed using assembly
* instructions to fix CR#913249.
* 5.4 pkp 03/11/16 Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
* instead modified cortexr5/sleep.c and usleep.c to poll the counter
* value and compare it with previous value to detect the overflow
* to fix CR#940209.
* 5.4 pkp 03/24/16 Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
* the fault log to avoid intervention for lock-step mode and cortexr5/
* _exit.c to enable the dbg_lpd_reset once the fault log is disabled
* to fix CR#947335
*****************************************************************************************/

0
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/config.make → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/config.make
View file

6
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/errno.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/errno.c
View file

@ -4,9 +4,11 @@
#include <errno.h>
#include <reent.h>
#include "xil_types.h"
sint32 * __errno (void);
int *
__errno ()
sint32 *
__errno (void)
{
return &_REENT->_errno;
}

4
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/fcntl.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/fcntl.c
View file

@ -1,10 +1,12 @@
#include <stdio.h>
#include "xil_types.h"
sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg);
/*
* fcntl -- Manipulate a file descriptor.
* We don't have a filesystem, so we do nothing.
*/
int fcntl (int fd, int cmd, long arg)
sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg)
{
(void) fd;
(void) cmd;

9
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/fsl.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/fsl.h
View file

@ -1,5 +1,5 @@
#ifndef _FSL_H
#define _FSL_H
#ifndef FSL_H
#define FSL_H
#include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */
@ -8,7 +8,7 @@ extern "C" {
#endif
/* Extended FSL macros. These now replace all of the previous FSL macros */
#define FSL_DEFAULT
#define FSL_DEFAULT
#define FSL_NONBLOCKING n
#define FSL_EXCEPTION e
#define FSL_CONTROL c
@ -44,5 +44,4 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#endif /* _FSL_H */
#endif /* FSL_H */

503
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/hw_exception_handler.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/hw_exception_handler.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -29,7 +29,7 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
/******************************************************************************
* Microblaze HW Exception Handler
* - Non self-modifying exception handler for the following exception conditions
* - Unalignment
@ -38,7 +38,7 @@
* - Illegal instruction opcode
* - Divide-by-zero
* - Stack protection violation
*/
*******************************************************************************/
#include "microblaze_exceptions_g.h"
#include "xparameters.h"
@ -46,129 +46,129 @@
/* Helpful Macros */
#define EX_HANDLER_STACK_SIZ (4*21)
#define RMSR_OFFSET (20 * 4)
#define R17_OFFSET (0)
#define R17_OFFSET (0)
#define REG_OFFSET(regnum) (4 * (regnum + 1))
#define NUM_TO_REG(num) r ## num
#define R3_TO_STACK(regnum) swi r3, r1, REG_OFFSET(regnum)
#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum)
#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum)
#define PUSH_REG(regnum) swi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
#define POP_REG(regnum) lwi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
/* Uses r5 */
#define PUSH_MSR \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET;
#define PUSH_MSR_AND_ENABLE_EXC \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET; \
ori r5, r5, 0x100; /* Turn ON the EE bit*/ \
mts rmsr, r5;
/* Uses r5 */
#define POP_MSR \
lwi r5, r1, RMSR_OFFSET; \
mts rmsr, r5;
mts rmsr, r5;
/* Push r17 */
/* Push r17 */
#define PUSH_R17 swi r17, r1, R17_OFFSET
/* Pop r17 */
/* Pop r17 */
#define POP_R17 lwi r17, r1, R17_OFFSET
#define LWREG_NOP \
bri ex_handler_unhandled; \
nop;
#define SWREG_NOP \
bri ex_handler_unhandled; \
nop;
nop;
/* r3 is the source */
#define R3_TO_LWREG_V(regnum) \
R3_TO_STACK (regnum); \
bri ex_handler_done;
bri ex_handler_done;
/* r3 is the source */
#define R3_TO_LWREG(regnum) \
or NUM_TO_REG (regnum), r0, r3; \
bri ex_handler_done;
bri ex_handler_done;
/* r3 is the target */
/* r3 is the target */
#define SWREG_TO_R3_V(regnum) \
R3_FROM_STACK (regnum); \
bri ex_sw_tail;
/* r3 is the target */
bri ex_sw_tail;
/* r3 is the target */
#define SWREG_TO_R3(regnum) \
or r3, r0, NUM_TO_REG (regnum); \
bri ex_sw_tail;
bri ex_sw_tail;
/* regnum is the source */
/* regnum is the source */
#define FP_EX_OPB_SAVE(regnum) \
swi NUM_TO_REG (regnum), r0, mb_fpex_op_b; \
nop; \
bri handle_fp_ex_opa;
bri handle_fp_ex_opa;
/* regnum is the source */
/* regnum is the source */
#define FP_EX_OPB_SAVE_V(regnum) \
R3_FROM_STACK (regnum); \
swi r3, r0, mb_fpex_op_b; \
bri handle_fp_ex_opa;
/* regnum is the source */
bri handle_fp_ex_opa;
/* regnum is the source */
#define FP_EX_OPA_SAVE(regnum) \
swi NUM_TO_REG (regnum), r0, mb_fpex_op_a; \
nop; \
bri handle_fp_ex_done;
/* regnum is the source */
bri handle_fp_ex_done;
/* regnum is the source */
#define FP_EX_OPA_SAVE_V(regnum) \
R3_FROM_STACK (regnum); \
swi r3, r0, mb_fpex_op_a; \
bri handle_fp_ex_done;
bri handle_fp_ex_done;
#define FP_EX_UNHANDLED \
bri fp_ex_unhandled; \
nop; \
nop;
/* ESR masks */
/* ESR masks */
#define ESR_EXC_MASK 0x0000001F
#define ESR_REG_MASK 0x000003E0
#define ESR_LW_SW_MASK 0x00000400
#define ESR_WORD_MASK 0x00000800
#define ESR_DS_MASK 0x00001000
/* Extern declarations */
.extern XNullHandler
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
/*
/*
* hw_exception_handler - Handler for unaligned exceptions
* Exception handler notes:
* Exception handler notes:
* - Does not handle exceptions other than unaligned exceptions
* - Does not handle exceptions during load into r17, r1, r0.
* - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case)
*
* Relevant register structures
*
* EAR - |----|----|----|----|----|----|----|----|
* - < ## 32 bit faulting address ## >
*
* ESR - |----|----|----|----|----| - | - |-----|-----|
*
* EAR - |----|----|----|----|----|----|----|----|
* - < ## 32 bit faulting address ## >
*
* ESR - |----|----|----|----|----| - | - |-----|-----|
* - W S REG EXC
*
*
*
* STACK FRAME STRUCTURE
* ---------------------
*
* +-------------+ + 0
* | r17 |
* +-------------+ + 4
* +-------------+ + 4
* | Args for |
* | next func |
* +-------------+ + 8
@ -179,19 +179,19 @@
* | . |
* | r18 |
* +-------------+ + 80
* | MSR |
* +-------------+ + 84
* | . |
* | . |
*/
* | MSR |
* +-------------+ + 84
* | . |
* | . |
*/
.global _hw_exception_handler
.section .text
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
.type _hw_exception_handler, @function
_hw_exception_handler:
.type _hw_exception_handler, @function
_hw_exception_handler:
#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
/* Immediately halt for stack protection violation exception without using any stack */
@ -207,33 +207,33 @@ ex_handler_not_sp_violation:
#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
PUSH_REG(3);
PUSH_REG(4);
PUSH_REG(5);
PUSH_REG(3);
PUSH_REG(4);
PUSH_REG(5);
PUSH_REG(6);
#ifdef MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
mfs r6, resr;
andi r6, r6, ESR_DS_MASK;
beqi r6, ex_handler_no_ds;
mfs r17, rbtr;
ex_handler_no_ds:
ex_handler_no_ds:
#endif
PUSH_R17;
PUSH_R17;
PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */
mfs r3, resr;
mfs r3, resr;
andi r5, r3, ESR_EXC_MASK; /* Extract ESR[EXC] */
#ifndef NO_UNALIGNED_EXCEPTIONS
xori r6, r5, 1; /* 00001 = Unaligned Exception */
bnei r6, handle_ex_regular;
xori r6, r5, 1; /* 00001 = Unaligned Exception */
bnei r6, handle_ex_regular;
la r4, r0, MB_ExceptionVectorTable; /* Check if user has registered an unaligned exception handler */
lwi r4, r4, 8;
lwi r4, r4, 8;
la r6, r0, XNullHandler; /* If exceptionvectortable entry is still XNullHandler, use */
xor r6, r4, r6; /* the default exception handler */
beqi r6, handle_unaligned_ex ;
handle_ex_regular:
beqi r6, handle_unaligned_ex ;
handle_ex_regular:
#endif /* ! NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
@ -241,29 +241,29 @@ handle_ex_regular:
beqi r6, handle_fp_ex; /* Go and decode the FP exception */
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
handle_other_ex: /* Handle Other exceptions here */
ori r6, r0, 20;
handle_other_ex: /* Handle Other exceptions here */
ori r6, r0, 20;
cmp r6, r5, r6; /* >= 20 are exceptions we do not handle. */
blei r6, ex_handler_unhandled;
ori r6, r0, 7;
cmp r6, r5, r6; /* Convert MMU exception indices into an ordinal of 7 */
bgti r6, handle_other_ex_tail;
ori r5, r0, 0x7;
handle_other_ex_tail:
ori r5, r0, 0x7;
handle_other_ex_tail:
PUSH_REG(7); /* Save other volatiles before we make procedure calls below */
PUSH_REG(8);
PUSH_REG(9);
PUSH_REG(10);
PUSH_REG(11);
PUSH_REG(8);
PUSH_REG(9);
PUSH_REG(10);
PUSH_REG(11);
PUSH_REG(12);
PUSH_REG(15);
PUSH_REG(18);
PUSH_REG(18);
la r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */
addk r7, r5, r5; /* Calculate exception vector offset = r5 * 8 */
addk r7, r7, r7;
addk r7, r7, r7;
addk r7, r7, r7;
addk r7, r7, r4; /* Get pointer to exception vector */
lwi r5, r7, 4; /* Load argument to exception handler from table */
@ -271,20 +271,20 @@ handle_other_ex_tail:
brald r15, r7; /* Branch to handler */
nop;
POP_REG(7); /* Restore other volatiles */
POP_REG(8);
POP_REG(9);
POP_REG(10);
POP_REG(11);
POP_REG(8);
POP_REG(9);
POP_REG(10);
POP_REG(11);
POP_REG(12);
POP_REG(15);
POP_REG(18);
POP_REG(18);
bri ex_handler_done; /* Complete exception handling */
bri ex_handler_done; /* Complete exception handling */
#ifndef NO_UNALIGNED_EXCEPTIONS
handle_unaligned_ex:
handle_unaligned_ex:
andi r6, r3, ESR_REG_MASK; /* Mask and extract the register operand */
srl r6, r6; /* r6 >> 5 */
srl r6, r6;
@ -292,14 +292,14 @@ handle_unaligned_ex:
srl r6, r6;
srl r6, r6;
sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */
mfs r4, rear;
mfs r4, rear;
andi r6, r3, ESR_LW_SW_MASK; /* Extract ESR[S] */
bnei r6, ex_sw;
ex_lw:
ex_lw:
andi r6, r3, ESR_WORD_MASK; /* Extract ESR[W] */
beqi r6, ex_lhw;
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lbui r5, r4, 2;
@ -307,32 +307,32 @@ ex_lw:
lbui r5, r4, 3;
sbi r5, r0, ex_tmp_data_loc_3;
lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
bri ex_lw_tail;
ex_lhw:
bri ex_lw_tail;
ex_lhw:
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
ex_lw_tail:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
la r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */
addk r5, r5, r5;
addk r5, r5, r5;
addk r5, r5, r5;
addk r5, r5, r5;
addk r5, r5, r6;
bra r5;
ex_lw_end: /* Exception handling of load word, ends */
ex_sw:
ex_sw:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
la r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */
add r5, r5, r5;
add r5, r5, r5;
add r5, r5, r5;
add r5, r5, r5;
add r5, r5, r6;
bra r5;
ex_sw_tail:
mfs r6, resr;
ex_sw_tail:
mfs r6, resr;
andi r6, r6, ESR_WORD_MASK; /* Extract ESR[W] */
beqi r6, ex_shw;
swi r3, r0, ex_tmp_data_loc_0;
@ -341,13 +341,13 @@ ex_sw_tail:
lbui r3, r0, ex_tmp_data_loc_1;
sbi r3, r4, 1;
lbui r3, r0, ex_tmp_data_loc_2;
sbi r3, r4, 2;
sbi r3, r4, 2;
lbui r3, r0, ex_tmp_data_loc_3;
sbi r3, r4, 3;
sbi r3, r4, 3;
bri ex_handler_done;
ex_shw:
ex_shw:
swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */
#ifdef __LITTLE_ENDIAN__
lbui r3, r0, ex_tmp_data_loc_0;
#else
@ -361,7 +361,7 @@ ex_shw:
#endif
sbi r3, r4, 1;
ex_sw_end: /* Exception handling of store word, ends. */
bri ex_handler_done;
bri ex_handler_done;
#endif /* !NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
@ -371,76 +371,76 @@ handle_fp_ex:
handle_fp_ex_opb:
la r6, r0, fp_table_opb; /* Decode opB and store its value in mb_fpex_op_b */
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
andi r3, r4, 0x1F;
add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
add r3, r3, r3;
add r5, r3, r3;
add r5, r5, r3;
add r5, r5, r6;
bra r5;
bra r5;
handle_fp_ex_opa:
la r6, r0, fp_table_opa; /* Decode opA and store its value in mb_fpex_op_a */
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
andi r3, r4, 0x1F;
add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
add r3, r3, r3;
add r5, r3, r3;
add r5, r5, r3;
add r5, r5, r6;
bra r5;
bra r5;
handle_fp_ex_done:
ori r5, r0, 6; /* Set exception number back to 6 */
bri handle_other_ex_tail;
fp_ex_unhandled:
bri 0;
bri handle_other_ex_tail;
fp_ex_unhandled:
bri 0;
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
ex_handler_done:
POP_R17;
POP_MSR;
POP_REG(3);
POP_REG(4);
POP_REG(5);
POP_REG(6);
POP_REG(3);
POP_REG(4);
POP_REG(5);
POP_REG(6);
rted r17, 0
addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
ex_handler_unhandled:
bri 0 /* UNHANDLED. TRAP HERE */
.end _hw_exception_handler
addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
ex_handler_unhandled:
bri 0 /* UNHANDLED. TRAP HERE */
.end _hw_exception_handler
#ifndef NO_UNALIGNED_EXCEPTIONS
#ifndef NO_UNALIGNED_EXCEPTIONS
/*
/*
* hw_exception_handler Jump Table
* - Contains code snippets for each register that caused the unaligned exception.
* - Hence exception handler is NOT self-modifying
* - Separate table for load exceptions and store exceptions.
* - Each table is of size: (8 * 32) = 256 bytes
*/
.section .text
.align 4
lw_table:
lw_r0: R3_TO_LWREG (0);
lw_r0: R3_TO_LWREG (0);
lw_r1: LWREG_NOP;
lw_r2: R3_TO_LWREG (2);
lw_r3: R3_TO_LWREG_V (3);
@ -451,30 +451,30 @@ lw_r7: R3_TO_LWREG (7);
lw_r8: R3_TO_LWREG (8);
lw_r9: R3_TO_LWREG (9);
lw_r10: R3_TO_LWREG (10);
lw_r11: R3_TO_LWREG (11);
lw_r11: R3_TO_LWREG (11);
lw_r12: R3_TO_LWREG (12);
lw_r13: R3_TO_LWREG (13);
lw_r14: R3_TO_LWREG (14);
lw_r15: R3_TO_LWREG (15);
lw_r16: R3_TO_LWREG (16);
lw_r14: R3_TO_LWREG (14);
lw_r15: R3_TO_LWREG (15);
lw_r16: R3_TO_LWREG (16);
lw_r17: LWREG_NOP;
lw_r18: R3_TO_LWREG (18);
lw_r19: R3_TO_LWREG (19);
lw_r20: R3_TO_LWREG (20);
lw_r18: R3_TO_LWREG (18);
lw_r19: R3_TO_LWREG (19);
lw_r20: R3_TO_LWREG (20);
lw_r21: R3_TO_LWREG (21);
lw_r22: R3_TO_LWREG (22);
lw_r23: R3_TO_LWREG (23);
lw_r24: R3_TO_LWREG (24);
lw_r25: R3_TO_LWREG (25);
lw_r26: R3_TO_LWREG (26);
lw_r27: R3_TO_LWREG (27);
lw_r28: R3_TO_LWREG (28);
lw_r29: R3_TO_LWREG (29);
lw_r23: R3_TO_LWREG (23);
lw_r24: R3_TO_LWREG (24);
lw_r25: R3_TO_LWREG (25);
lw_r26: R3_TO_LWREG (26);
lw_r27: R3_TO_LWREG (27);
lw_r28: R3_TO_LWREG (28);
lw_r29: R3_TO_LWREG (29);
lw_r30: R3_TO_LWREG (30);
lw_r31: R3_TO_LWREG (31);
sw_table:
sw_r0: SWREG_TO_R3 (0);
sw_r0: SWREG_TO_R3 (0);
sw_r1: SWREG_NOP;
sw_r2: SWREG_TO_R3 (2);
sw_r3: SWREG_TO_R3_V (3);
@ -485,128 +485,128 @@ sw_r7: SWREG_TO_R3 (7);
sw_r8: SWREG_TO_R3 (8);
sw_r9: SWREG_TO_R3 (9);
sw_r10: SWREG_TO_R3 (10);
sw_r11: SWREG_TO_R3 (11);
sw_r11: SWREG_TO_R3 (11);
sw_r12: SWREG_TO_R3 (12);
sw_r13: SWREG_TO_R3 (13);
sw_r14: SWREG_TO_R3 (14);
sw_r15: SWREG_TO_R3 (15);
sw_r16: SWREG_TO_R3 (16);
sw_r17: SWREG_NOP;
sw_r18: SWREG_TO_R3 (18);
sw_r19: SWREG_TO_R3 (19);
sw_r20: SWREG_TO_R3 (20);
sw_r14: SWREG_TO_R3 (14);
sw_r15: SWREG_TO_R3 (15);
sw_r16: SWREG_TO_R3 (16);
sw_r17: SWREG_NOP;
sw_r18: SWREG_TO_R3 (18);
sw_r19: SWREG_TO_R3 (19);
sw_r20: SWREG_TO_R3 (20);
sw_r21: SWREG_TO_R3 (21);
sw_r22: SWREG_TO_R3 (22);
sw_r23: SWREG_TO_R3 (23);
sw_r24: SWREG_TO_R3 (24);
sw_r25: SWREG_TO_R3 (25);
sw_r26: SWREG_TO_R3 (26);
sw_r27: SWREG_TO_R3 (27);
sw_r28: SWREG_TO_R3 (28);
sw_r29: SWREG_TO_R3 (29);
sw_r23: SWREG_TO_R3 (23);
sw_r24: SWREG_TO_R3 (24);
sw_r25: SWREG_TO_R3 (25);
sw_r26: SWREG_TO_R3 (26);
sw_r27: SWREG_TO_R3 (27);
sw_r28: SWREG_TO_R3 (28);
sw_r29: SWREG_TO_R3 (29);
sw_r30: SWREG_TO_R3 (30);
sw_r31: SWREG_TO_R3 (31);
/* Temporary data structures used in the handler */
.section .data
.align 2
ex_tmp_data_loc_0:
ex_tmp_data_loc_0:
.byte 0
ex_tmp_data_loc_1:
ex_tmp_data_loc_1:
.byte 0
ex_tmp_data_loc_2:
ex_tmp_data_loc_2:
.byte 0
ex_tmp_data_loc_3:
.byte 0
ex_tmp_data_loc_3:
.byte 0
ex_reg_op:
.byte 0
#endif /* ! NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
/*
/*
* FP exception decode jump table.
* - Contains code snippets for each register that could have been a source operand for an excepting FP instruction
* - Hence exception handler is NOT self-modifying
* - Separate table for opA and opB
* - Each table is of size: (12 * 32) = 384 bytes
*/
.section .text
.align 4
fp_table_opa:
opa_r0: FP_EX_OPA_SAVE (0);
opa_r1: FP_EX_UNHANDLED;
opa_r2: FP_EX_OPA_SAVE (2);
opa_r3: FP_EX_OPA_SAVE_V (3);
opa_r4: FP_EX_OPA_SAVE_V (4);
opa_r5: FP_EX_OPA_SAVE_V (5);
opa_r6: FP_EX_OPA_SAVE_V (6);
opa_r7: FP_EX_OPA_SAVE (7);
opa_r8: FP_EX_OPA_SAVE (8);
opa_r9: FP_EX_OPA_SAVE (9);
opa_r10: FP_EX_OPA_SAVE (10);
opa_r11: FP_EX_OPA_SAVE (11);
opa_r12: FP_EX_OPA_SAVE (12);
opa_r13: FP_EX_OPA_SAVE (13);
opa_r14: FP_EX_UNHANDLED;
opa_r15: FP_EX_UNHANDLED;
opa_r16: FP_EX_UNHANDLED;
opa_r17: FP_EX_UNHANDLED;
opa_r18: FP_EX_OPA_SAVE (18);
opa_r19: FP_EX_OPA_SAVE (19);
opa_r20: FP_EX_OPA_SAVE (20);
opa_r21: FP_EX_OPA_SAVE (21);
opa_r22: FP_EX_OPA_SAVE (22);
opa_r23: FP_EX_OPA_SAVE (23);
opa_r24: FP_EX_OPA_SAVE (24);
opa_r25: FP_EX_OPA_SAVE (25);
opa_r26: FP_EX_OPA_SAVE (26);
opa_r27: FP_EX_OPA_SAVE (27);
opa_r28: FP_EX_OPA_SAVE (28);
opa_r29: FP_EX_OPA_SAVE (29);
opa_r30: FP_EX_OPA_SAVE (30);
opa_r31: FP_EX_OPA_SAVE (31);
opa_r0: FP_EX_OPA_SAVE (0);
opa_r1: FP_EX_UNHANDLED;
opa_r2: FP_EX_OPA_SAVE (2);
opa_r3: FP_EX_OPA_SAVE_V (3);
opa_r4: FP_EX_OPA_SAVE_V (4);
opa_r5: FP_EX_OPA_SAVE_V (5);
opa_r6: FP_EX_OPA_SAVE_V (6);
opa_r7: FP_EX_OPA_SAVE (7);
opa_r8: FP_EX_OPA_SAVE (8);
opa_r9: FP_EX_OPA_SAVE (9);
opa_r10: FP_EX_OPA_SAVE (10);
opa_r11: FP_EX_OPA_SAVE (11);
opa_r12: FP_EX_OPA_SAVE (12);
opa_r13: FP_EX_OPA_SAVE (13);
opa_r14: FP_EX_UNHANDLED;
opa_r15: FP_EX_UNHANDLED;
opa_r16: FP_EX_UNHANDLED;
opa_r17: FP_EX_UNHANDLED;
opa_r18: FP_EX_OPA_SAVE (18);
opa_r19: FP_EX_OPA_SAVE (19);
opa_r20: FP_EX_OPA_SAVE (20);
opa_r21: FP_EX_OPA_SAVE (21);
opa_r22: FP_EX_OPA_SAVE (22);
opa_r23: FP_EX_OPA_SAVE (23);
opa_r24: FP_EX_OPA_SAVE (24);
opa_r25: FP_EX_OPA_SAVE (25);
opa_r26: FP_EX_OPA_SAVE (26);
opa_r27: FP_EX_OPA_SAVE (27);
opa_r28: FP_EX_OPA_SAVE (28);
opa_r29: FP_EX_OPA_SAVE (29);
opa_r30: FP_EX_OPA_SAVE (30);
opa_r31: FP_EX_OPA_SAVE (31);
fp_table_opb:
opb_r0: FP_EX_OPB_SAVE (0);
opb_r1: FP_EX_UNHANDLED;
opb_r2: FP_EX_OPB_SAVE (2);
opb_r3: FP_EX_OPB_SAVE_V (3);
opb_r4: FP_EX_OPB_SAVE_V (4);
opb_r5: FP_EX_OPB_SAVE_V (5);
opb_r6: FP_EX_OPB_SAVE_V (6);
opb_r7: FP_EX_OPB_SAVE (7);
opb_r8: FP_EX_OPB_SAVE (8);
opb_r9: FP_EX_OPB_SAVE (9);
opb_r10: FP_EX_OPB_SAVE (10);
opb_r11: FP_EX_OPB_SAVE (11);
opb_r12: FP_EX_OPB_SAVE (12);
opb_r13: FP_EX_OPB_SAVE (13);
opb_r14: FP_EX_UNHANDLED;
opb_r15: FP_EX_UNHANDLED;
opb_r16: FP_EX_UNHANDLED;
opb_r17: FP_EX_UNHANDLED;
opb_r18: FP_EX_OPB_SAVE (18);
opb_r19: FP_EX_OPB_SAVE (19);
opb_r20: FP_EX_OPB_SAVE (20);
opb_r21: FP_EX_OPB_SAVE (21);
opb_r22: FP_EX_OPB_SAVE (22);
opb_r23: FP_EX_OPB_SAVE (23);
opb_r24: FP_EX_OPB_SAVE (24);
opb_r25: FP_EX_OPB_SAVE (25);
opb_r26: FP_EX_OPB_SAVE (26);
opb_r27: FP_EX_OPB_SAVE (27);
opb_r28: FP_EX_OPB_SAVE (28);
opb_r29: FP_EX_OPB_SAVE (29);
opb_r30: FP_EX_OPB_SAVE (30);
opb_r31: FP_EX_OPB_SAVE (31);
fp_table_opb:
opb_r0: FP_EX_OPB_SAVE (0);
opb_r1: FP_EX_UNHANDLED;
opb_r2: FP_EX_OPB_SAVE (2);
opb_r3: FP_EX_OPB_SAVE_V (3);
opb_r4: FP_EX_OPB_SAVE_V (4);
opb_r5: FP_EX_OPB_SAVE_V (5);
opb_r6: FP_EX_OPB_SAVE_V (6);
opb_r7: FP_EX_OPB_SAVE (7);
opb_r8: FP_EX_OPB_SAVE (8);
opb_r9: FP_EX_OPB_SAVE (9);
opb_r10: FP_EX_OPB_SAVE (10);
opb_r11: FP_EX_OPB_SAVE (11);
opb_r12: FP_EX_OPB_SAVE (12);
opb_r13: FP_EX_OPB_SAVE (13);
opb_r14: FP_EX_UNHANDLED;
opb_r15: FP_EX_UNHANDLED;
opb_r16: FP_EX_UNHANDLED;
opb_r17: FP_EX_UNHANDLED;
opb_r18: FP_EX_OPB_SAVE (18);
opb_r19: FP_EX_OPB_SAVE (19);
opb_r20: FP_EX_OPB_SAVE (20);
opb_r21: FP_EX_OPB_SAVE (21);
opb_r22: FP_EX_OPB_SAVE (22);
opb_r23: FP_EX_OPB_SAVE (23);
opb_r24: FP_EX_OPB_SAVE (24);
opb_r25: FP_EX_OPB_SAVE (25);
opb_r26: FP_EX_OPB_SAVE (26);
opb_r27: FP_EX_OPB_SAVE (27);
opb_r28: FP_EX_OPB_SAVE (28);
opb_r29: FP_EX_OPB_SAVE (29);
opb_r30: FP_EX_OPB_SAVE (30);
opb_r31: FP_EX_OPB_SAVE (31);
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
#if defined(MICROBLAZE_FP_EXCEPTION_ENABLED) && defined(MICROBLAZE_FP_EXCEPTION_DECODE)
/* This is where we store the opA and opB of the last excepting FP instruction */
.section .data
.section .data
.align 2
.global mb_fpex_op_a
.global mb_fpex_op_b
@ -644,19 +644,16 @@ MB_ExceptionVectorTable:
.long XNullHandler
.long 6 /* -- FPU Exception -- */
.long XNullHandler
.long 7 /* -- MMU Exceptions -- */
.long 7 /* -- MMU Exceptions -- */
#else /* Dummy exception handler, in case exceptions are not present in the processor */
.global _hw_exception_handler
.section .text
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
_hw_exception_handler:
bri 0;
.end _hw_exception_handler
bri 0;
.end _hw_exception_handler
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */

14
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/inbyte.c Normal file
View file

@ -0,0 +1,14 @@
#include "xparameters.h"
#include "xuartlite_l.h"
#ifdef __cplusplus
extern "C" {
#endif
char inbyte(void);
#ifdef __cplusplus
}
#endif
char inbyte(void) {
return XUartLite_RecvByte(STDIN_BASEADDRESS);
}

123
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/mb_interface.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/mb_interface.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -54,22 +54,22 @@ extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_Exception
extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
extern void microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the icache */
extern void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the dcache */
extern void microblaze_flush_dcache_range(unsigned int cacheaddr, unsigned int len); /* Flush a part of the dcache */
extern void microblaze_invalidate_icache_range(u32 cacheaddr, u32 len); /* Invalidate a part of the icache */
extern void microblaze_invalidate_dcache_range(u32 cacheaddr, u32 len); /* Invalidate a part of the dcache */
extern void microblaze_flush_dcache_range(u32 cacheaddr, u32 len); /* Flush a part of the dcache */
extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */
extern void microblaze_flush_cache_ext(void); /* Flush cache ext */
extern void microblaze_flush_cache_ext_range(unsigned int cacheaddr,
unsigned int len); /* Flush cache ext range */
extern void microblaze_invalidate_cache_ext_range(unsigned int cacheaddr,
unsigned int len); /* Invalidate cache ext range */
extern void microblaze_flush_cache_ext_range(u32 cacheaddr,
u32 len); /* Flush cache ext range */
extern void microblaze_invalidate_cache_ext_range(u32 cacheaddr,
u32 len); /* Invalidate cache ext range */
/* Deprecated */
extern void microblaze_update_icache (int , int , int ) __attribute__((deprecated));
extern void microblaze_init_icache_range (int , int ) __attribute__((deprecated));
extern void microblaze_update_dcache (int , int , int ) __attribute__((deprecated));
extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated));
extern void microblaze_update_icache (s32 , s32 , s32 ) __attribute__((deprecated));
extern void microblaze_init_icache_range (s32 , s32 ) __attribute__((deprecated));
extern void microblaze_update_dcache (s32 , s32 , s32 ) __attribute__((deprecated));
extern void microblaze_init_dcache_range (s32 , s32 ) __attribute__((deprecated));
/* necessary for pre-processor */
#define stringify(s) tostring(s)
@ -119,7 +119,7 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated
"andi\t%0,%0,0x10" : "=d" (error))
/* Pseudo assembler instructions */
#define clz(v) ({ unsigned int _rval; \
#define clz(v) ({ u32 _rval; \
__asm__ __volatile__ ( \
"clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
); \
@ -129,119 +129,133 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated
#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
#define mb_swapb(v) ({ unsigned int _rval; \
#define mb_swapb(v) ({ u32 _rval; \
__asm__ __volatile__ ( \
"swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
#define mb_swaph(v) ({ unsigned int _rval; \
#define mb_swaph(v) ({ u32 _rval; \
__asm__ __volatile__ ( \
"swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
#define mfgpr(rn) ({ unsigned int _rval; \
#define mfgpr(rn) ({ u32 _rval; \
__asm__ __volatile__ ( \
"or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfmsr() ({ unsigned int _rval; \
#define mfmsr() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rmsr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfear() ({ unsigned int _rval; \
#define mfear() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rear\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfesr() ({ unsigned int _rval; \
#define mfeare() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfse\t%0,rear\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfesr() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,resr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mffsr() ({ unsigned int _rval; \
#define mffsr() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rfsr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpvr(rn) ({ unsigned int _rval; \
#define mfpvr(rn) ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfbtr() ({ unsigned int _rval; \
#define mfpvre(rn) ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfse\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfbtr() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rbtr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfedr() ({ unsigned int _rval; \
#define mfedr() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,redr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpid() ({ unsigned int _rval; \
#define mfpid() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpid\n" : "=d"(_rval)\
); \
_rval; \
})
#define mfzpr() ({ unsigned int _rval; \
#define mfzpr() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rzpr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbx() ({ unsigned int _rval; \
#define mftlbx() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbx\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlblo() ({ unsigned int _rval; \
#define mftlblo() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlblo\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbhi() ({ unsigned int _rval; \
#define mftlbhi() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbhi\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfslr() ({ unsigned int _rval; \
#define mfslr() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rslr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfshr() ({ unsigned int _rval; \
#define mfshr() ({ u32 _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rshr\n" : "=d"(_rval) \
); \
@ -304,34 +318,56 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated
); \
})
#define lwx(address) ({ unsigned int _rval; \
#define lwx(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lwr(address) ({ unsigned int _rval; \
#define lwr(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lhur(address) ({ unsigned int _rval; \
#define lwea(lladdr) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lwea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define lhur(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lbur(address) ({ unsigned int _rval; \
#define lhuea(lladdr) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lhuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define lbur(address) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lbuea(lladdr) ({ u32 _rval; \
__asm__ __volatile__ ( \
"lbuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define swx(address, data) ({ __asm__ __volatile__ ( \
"swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
@ -342,23 +378,38 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated
); \
})
#define swea(lladdr, data) ({ __asm__ __volatile__ ( \
"swea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define shr(address, data) ({ __asm__ __volatile__ ( \
"shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define shea(lladdr, data) ({ __asm__ __volatile__ ( \
"shea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define sbr(address, data) ({ __asm__ __volatile__ ( \
"sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define sbea(lladdr, data) ({ __asm__ __volatile__ ( \
"sbea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define microblaze_getfpex_operand_a() ({ \
extern unsigned int mb_fpex_op_a; \
extern u32 mb_fpex_op_a; \
mb_fpex_op_a; \
})
#define microblaze_getfpex_operand_b() ({ \
extern unsigned int mb_fpex_op_b; \
extern u32 mb_fpex_op_b; \
mb_fpex_op_b; \
})

81
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v3_0/src/xtmrctr_i.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_dcache.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -29,51 +29,56 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
/******************************************************************************
* File : microblaze_disable_dcache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* @file xtmrctr_i.h
* Summary:
* Disable the L1 dcache on the microblaze.
*
* This file contains data which is shared between files internal to the
* XTmrCtr component. It is intended for internal use only.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b jhl 02/06/02 First release
* 1.10b mta 03/21/07 Updated to new coding style
* 2.00a ktn 10/30/09 _m is removed from all the macro definitions.
* </pre>
*
******************************************************************************/
*******************************************************************************/
#ifndef XTMRCTR_I_H /* prevent circular inclusions */
#define XTMRCTR_I_H /* by using protection macros */
#include "xparameters.h"
#ifdef __cplusplus
extern "C" {
#endif
.text
.globl microblaze_disable_dcache
.ent microblaze_disable_dcache
.align 2
microblaze_disable_dcache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
/***************************** Include Files *********************************/
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
addik r1, r1, -4
swi r15, r1, 0
brlid r15, microblaze_flush_dcache /* microblaze_flush_dcache does not use r1*/
nop
lwi r15, r1, 0
addi r1, r1, 4
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
rtsd r15, 8
msrclr r0, 0x80
#include "xil_types.h"
#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 1 */
/************************** Constant Definitions *****************************/
addik r1, r1, -4
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
swi r15, r1, 0
brlid r15, microblaze_flush_dcache
nop
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
mfs r11, rmsr
andi r11, r11, ~(0x80)
mts rmsr, r11
/************************** Function Prototypes ******************************/
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
lwi r15, r1, 0
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
rtsd r15, 8
addi r1, r1, 4
/************************** Variable Definitions *****************************/
extern XTmrCtr_Config XTmrCtr_ConfigTable[];
extern u8 XTmrCtr_Offsets[];
#ifdef __cplusplus
}
#endif
#endif
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_disable_dcache

20
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_exceptions.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_exceptions.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -29,11 +29,12 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# Disable exceptions on microblaze.
#
#
####################################################################
/******************************************************************************
*
* Disable exceptions on microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
@ -45,14 +46,11 @@ microblaze_disable_exceptions:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrclr r0, 0x100
#else
#else
mfs r4, rmsr;
andi r4, r4, ~(0x100); /* Turn OFF the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
nop;
#endif
.end microblaze_disable_exceptions

30
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_icache.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_icache.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -29,17 +29,18 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# File : microblaze_disable_icache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable L1 icache on the microblaze.
#
#
####################################################################
/******************************************************************************
*
* File : microblaze_disable_icache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Disable L1 icache on the microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
@ -47,7 +48,7 @@
.globl microblaze_disable_icache
.ent microblaze_disable_icache
.align 2
microblaze_disable_icache:
microblaze_disable_icache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrclr r0, 0x20
@ -63,6 +64,3 @@ microblaze_disable_icache:
nop
#endif
.end microblaze_disable_icache

30
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_disable_interrupts.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_disable_interrupts.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -29,17 +29,18 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# File : microblaze_disable_interrupts.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable interrupts on the microblaze.
#
#
####################################################################
/******************************************************************************
*
* File : microblaze_disable_interrupts.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Disable interrupts on the microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
@ -47,7 +48,7 @@
.globl microblaze_disable_interrupts
.ent microblaze_disable_interrupts
.align 2
microblaze_disable_interrupts:
microblaze_disable_interrupts:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrclr r0, 0x2
@ -63,6 +64,3 @@ microblaze_disable_interrupts:
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_disable_interrupts

32
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_dcache.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_dcache.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -29,25 +29,26 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# File : microblaze_enable_dcache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable L1 dcache on the microblaze.
#
#
####################################################################
/******************************************************************************
*
* File : microblaze_enable_dcache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Enable L1 dcache on the microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
#include "xparameters.h"
.text
.globl microblaze_enable_dcache
.ent microblaze_enable_dcache
.align 2
microblaze_enable_dcache:
microblaze_enable_dcache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
@ -64,6 +65,3 @@ microblaze_enable_dcache:
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_dcache

18
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_exceptions.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_exceptions.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -29,11 +29,12 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# Enable exceptions on microblaze.
#
#
####################################################################
/******************************************************************************
*
* Enable exceptions on microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
@ -50,9 +51,6 @@ microblaze_enable_exceptions:
ori r4, r4, 0x100; /* Turn ON the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
nop;
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_exceptions

29
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_icache.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_icache.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -29,18 +29,18 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# File : microblaze_enable_icache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable icache on the microblaze.
#
#
####################################################################
/******************************************************************************
*
* File : microblaze_enable_icache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Enable icache on the microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
.text
@ -63,6 +63,3 @@ microblaze_enable_icache:
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_icache

32
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_enable_interrupts.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_enable_interrupts.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -29,25 +29,26 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#
# File : microblaze_enable_interrupts.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable interrupts on the microblaze.
#
#
####################################################################
/******************************************************************************
*
* File : microblaze_enable_interrupts.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Enable interrupts on the microblaze.
*
*
******************************************************************************/
#include "xparameters.h"
#include "xparameters.h"
.text
.globl microblaze_enable_interrupts
.ent microblaze_enable_interrupts
.align 2
microblaze_enable_interrupts:
microblaze_enable_interrupts:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
rtsd r15, 8
msrset r0, 0x2
@ -63,6 +64,3 @@ microblaze_enable_interrupts:
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_enable_interrupts

2
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exception_handler.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exception_handler.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal

11
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exceptions_g.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -22,8 +22,8 @@
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
@ -37,8 +37,3 @@
*
*******************************************************************/
#define MICROBLAZE_EXCEPTIONS_ENABLED 1
#define MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
#define MICROBLAZE_FP_EXCEPTION_ENABLED 1

24
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_exceptions_i.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_i.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -67,17 +67,17 @@ typedef struct
} MB_ExceptionVectorTableEntry;
/* Exception IDs */
#define XEXC_ID_FSL 0
#define XEXC_ID_UNALIGNED_ACCESS 1
#define XEXC_ID_ILLEGAL_OPCODE 2
#define XEXC_ID_M_AXI_I_EXCEPTION 3
#define XEXC_ID_IPLB_EXCEPTION 3
#define XEXC_ID_M_AXI_D_EXCEPTION 4
#define XEXC_ID_DPLB_EXCEPTION 4
#define XEXC_ID_DIV_BY_ZERO 5
#define XEXC_ID_FPU 6
#define XEXC_ID_STACK_VIOLATION 7
#define XEXC_ID_MMU 7
#define XEXC_ID_FSL 0U
#define XEXC_ID_UNALIGNED_ACCESS 1U
#define XEXC_ID_ILLEGAL_OPCODE 2U
#define XEXC_ID_M_AXI_I_EXCEPTION 3U
#define XEXC_ID_IPLB_EXCEPTION 3U
#define XEXC_ID_M_AXI_D_EXCEPTION 4U
#define XEXC_ID_DPLB_EXCEPTION 4U
#define XEXC_ID_DIV_BY_ZERO 5U
#define XEXC_ID_FPU 6U
#define XEXC_ID_STACK_VIOLATION 7U
#define XEXC_ID_MMU 7U
void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr);

12
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_cache_ext.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_cache_ext.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,9 +28,12 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_flush_cache_ext()
*
* Flush the entire L2 Cache
* Flush the entire L2 Cache
*
*
*******************************************************************************/
@ -48,7 +51,7 @@ microblaze_flush_cache_ext:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
@ -60,6 +63,3 @@ Loop_start:
rtsd r15, 8
nop
.end microblaze_flush_cache_ext

12
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_cache_ext_range.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_cache_ext_range.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,11 +28,14 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len)
*
*Flush a L2 Cache range
*
*Parameters:
*Parameters:
* 'cacheaddr' - address in the L2 cache where the flush begins
* 'len ' - length (in bytes) worth of L2 cache to be flushed
*
@ -63,12 +66,9 @@ Loop_start:
bneid r6, Loop_start
addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_done:
Loop_done:
#endif
rtsd r15, 8
nop
.end microblaze_flush_cache_ext_range

31
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_dcache.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_dcache.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,9 +28,13 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
*
* microblaze_flush_dcache()
*
* Flush the L1 DCache
*
* Flush the L1 DCache
*
*******************************************************************************/
@ -38,11 +42,11 @@
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
.text
.globl microblaze_flush_dcache
.ent microblaze_flush_dcache
@ -50,21 +54,18 @@
microblaze_flush_dcache:
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Align to cache line */
addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
L_start:
wdc.flush r5, r0 /* Flush the Cache */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
L_done:
rtsd r15, 8 /* Return */
nop
.end microblaze_flush_dcache

46
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_flush_dcache_range.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_flush_dcache_range.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,11 +28,14 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_flush_dcache_range (unsigned int cacheaddr, unsigned int len)
*
*
* Flush a L1 DCache range
*
* Parameters:
*
* Parameters:
* 'cacheaddr' - address in the Dcache where the flush begins
* 'len ' - length (in bytes) worth of Dcache to be flushed
*
@ -42,7 +45,7 @@
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
@ -61,32 +64,32 @@
microblaze_flush_dcache_range:
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
beqi r6, L_done /* Skip loop if size is zero */
add r6, r5, r6 /* Compute end address */
addik r6, r6, -1
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
L_start:
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
wdc r5, r0 /* Invalidate the cache line */
brid L_start /* Branch to the beginning of the loop */
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#else
rsubk r6, r5, r6
rsubk r6, r5, r6
/* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
L_start:
wdc.flush r5, r6 /* Flush the cache line */
@ -94,15 +97,12 @@ L_start:
addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
#endif
L_done:
rtsd r15, 8
L_done:
rtsd r15, 8
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_flush_dcache_range

32
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_init_dcache_range.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_init_dcache_range.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,11 +28,14 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_init_dcache_range (unsigned int cache_start, unsigned int cache_len)
*
*
* Invalidate dcache on the microblaze
*
* Parameters:
*
* Parameters:
* 'cache_start' - address in the Dcache where invalidation begins
* 'cache_len' - length (in bytes) worth of Dcache to be invalidated
*
@ -43,11 +46,11 @@
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
.text
.globl microblaze_init_dcache_range
.ent microblaze_init_dcache_range
@ -61,22 +64,19 @@ microblaze_init_dcache_range:
andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
add r6, r5, r6 /* Compute end */
add r6, r5, r6 /* Compute end */
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
L_start:
wdc r5, r0 /* Invalidate the Cache (delay slot) */
cmpu r18, r5, r6 /* Are we at the end ? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
cmpu r18, r5, r6 /* Are we at the end ? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
L_done:
rtsd r15, 8 /* Return */
mts rmsr, r9
.end microblaze_init_dcache_range

32
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_init_icache_range.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_init_icache_range.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,12 +28,15 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
*
* microblaze_init_icache_range (unsigned int cache_start, unsigned int cache_len)
*
*
* Invalidate icache on the microblaze
*
* Parameters:
*
* Parameters:
* 'cache_start' - address in the Icache where invalidation begins
* 'cache_len' - length (in bytes) worth of Icache to be invalidated
*
@ -44,11 +47,11 @@
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
.text
.globl microblaze_init_icache_range
.ent microblaze_init_icache_range
@ -62,22 +65,19 @@ microblaze_init_icache_range:
andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
add r6, r5, r6 /* Compute end */
add r6, r5, r6 /* Compute end */
andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
L_start:
wic r5, r0 /* Invalidate the Cache (delay slot) */
cmpu r18, r5, r6 /* Are we at the end ? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
cmpu r18, r5, r6 /* Are we at the end ? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
L_done:
rtsd r15, 8 /* Return */
mts rmsr, r9
.end microblaze_init_icache_range

6
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupt_handler.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupt_handler.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -64,6 +64,7 @@
/************************** Function Prototypes ******************************/
void __interrupt_handler (void) __attribute__ ((interrupt_handler));
void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr);
/************************** Variable Definitions *****************************/
@ -91,7 +92,7 @@ extern MB_InterruptVectorTableEntry MB_InterruptVectorTable;
void __interrupt_handler(void)
{
/* The compiler saves all volatiles and the MSR */
MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef);
(void)MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef);
/* The compiler restores all volatiles and MSR, and returns from interrupt */
}
@ -119,4 +120,3 @@ void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr)
MB_InterruptVectorTable.Handler = Handler;
MB_InterruptVectorTable.CallBackRef = DataPtr;
}

12
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupts_g.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c
View file

@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
@ -22,8 +22,8 @@
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
@ -41,7 +41,7 @@
#include "xparameters.h"
extern void XIntc_DeviceInterruptHandler (void *);
extern void XNullHandler (void *);
/*
* The interrupt handler table for microblaze processor
@ -49,7 +49,7 @@ extern void XIntc_DeviceInterruptHandler (void *);
MB_InterruptVectorTableEntry MB_InterruptVectorTable[] =
{
{ XIntc_DeviceInterruptHandler,
(void*) XPAR_AXI_INTC_0_DEVICE_ID}
{ XNullHandler,
(void*) XNULL}
};

2
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_interrupts_i.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_i.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal

16
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_cache_ext.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_cache_ext.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,9 +28,12 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_invalidate_cache_ext()
*
*Invalidate the entire L2 Cache
*Invalidate the entire L2 Cache
*
*
*******************************************************************************/
@ -48,19 +51,16 @@ microblaze_invalidate_cache_ext:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN))
addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_start:
wdc.ext.clear r5, r6
bgtid r6,Loop_start
addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
#endif
#endif
rtsd r15, 8
nop
.end microblaze_invalidate_cache_ext

10
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_cache_ext_range.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_cache_ext_range.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,6 +28,9 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_invalidate_cache_ext_range (unsigned int cacheaddr, unsigned int len)
*
*Invalidate an L2 cache range
@ -64,12 +67,9 @@ Loop_start:
bneid r6, Loop_start
addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_done:
Loop_done:
#endif
rtsd r15, 8
nop
.end microblaze_invalidate_cache_ext_range

36
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_dcache.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_dcache.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,9 +28,12 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_invalidate_dcache()
*
* Invalidate the entire L1 DCache
*
* Invalidate the entire L1 DCache
*
*
*******************************************************************************/
@ -39,7 +42,7 @@
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
@ -47,7 +50,7 @@
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_dcache
.ent microblaze_invalidate_dcache
@ -55,24 +58,24 @@
microblaze_invalidate_dcache:
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
L_start:
wdc r5, r0 /* Invalidate the Cache */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
@ -81,6 +84,3 @@ L_done:
#endif
.end microblaze_invalidate_dcache

54
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_dcache_range.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_dcache_range.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,12 +28,15 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
*
* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
*
*
* Invalidate a Dcache range
*
* Parameters:
*
* Parameters:
* 'cacheaddr' - address in the Dcache where invalidation begins
* 'len ' - length (in bytes) worth of Dcache to be invalidated
*
@ -44,7 +47,7 @@
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
@ -55,7 +58,7 @@
#else
#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#endif
.text
.globl microblaze_invalidate_dcache_range
.ent microblaze_invalidate_dcache_range
@ -63,34 +66,34 @@
microblaze_invalidate_dcache_range:
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
beqi r6, L_done /* Skip loop if size is zero */
add r6, r5, r6 /* Compute end address */
addik r6, r6, -1
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
L_start:
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
wdc r5, r0
brid L_start /* Branch to the beginning of the loop */
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
wdc r5, r0
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#else
rsubk r6, r5, r6
rsubk r6, r5, r6
/* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
L_start:
wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */
@ -98,15 +101,12 @@ L_start:
addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
#endif
L_done:
rtsd r15, 8
L_done:
rtsd r15, 8
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_invalidate_dcache_range

30
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_icache.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_icache.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,9 +28,12 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
*
* microblaze_invalidate_icache()
*
*
* Invalidate the entire ICache
*
*
@ -40,7 +43,7 @@
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
@ -48,7 +51,7 @@
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_icache
.ent microblaze_invalidate_icache
@ -56,23 +59,23 @@
microblaze_invalidate_icache:
#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
addik r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */
addik r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */
addik r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */
addik r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */
L_start:
wic r5, r0 /* Invalidate the Cache */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
@ -81,6 +84,3 @@ L_done:
nop
#endif
.end microblaze_invalidate_icache

36
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_invalidate_icache_range.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_invalidate_icache_range.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,12 +28,15 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
*
* microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len)
*
*
* Invalidate an ICache range
*
* Parameters:
*
* Parameters:
* 'cacheaddr' - address in the Icache where invalidation begins
* 'len' - length (in bytes) worth of Icache to be invalidated
*
@ -44,7 +47,7 @@
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
@ -52,7 +55,7 @@
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_icache_range
.ent microblaze_invalidate_icache_range
@ -60,27 +63,27 @@
microblaze_invalidate_icache_range:
#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
mfs r9, rmsr
#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
beqi r6, L_done /* Skip loop if size is zero */
add r6, r5, r6 /* Compute end address */
addik r6, r6, -1
andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */
andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */
andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align start down to cache line */
L_start:
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
wic r5, r0 /* Invalidate the cache line */
brid L_start /* Branch to the beginning of the loop */
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
@ -91,6 +94,3 @@ L_done:
nop
#endif
.end microblaze_invalidate_icache_range

5
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_scrub.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_scrub.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,6 +28,9 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* microblaze_scrub ()
*
* Scrub LMB memory and all internal BRAMs (data cache, instruction cache,

6
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_sleep.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_sleep.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -80,9 +80,9 @@
* @note Instruction cache should be enabled for this to work.
*
******************************************************************************/
void MB_Sleep(unsigned int MilliSeconds)
void MB_Sleep(u32 MilliSeconds)
{
if (((mfmsr() & 0x20) == 0)) {
if (((mfmsr() & 0x20U) == 0U)) {
/*
* Instruction cache not enabled.
* Delay will be much higher than expected.

4
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_sleep.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_sleep.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -74,7 +74,7 @@ extern "C" {
/************************** Function Prototypes ******************************/
void MB_Sleep(unsigned int MilliSeconds);
void MB_Sleep(u32 MilliSeconds);
#ifdef __cplusplus
}

13
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_update_dcache.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_update_dcache.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,7 +28,10 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
*
******************************************************************************/
/******************************************************************************
*
*
* File : microblaze_update_dcache.s
* Date : 2003, September 24
* Company: Xilinx
@ -49,14 +52,14 @@
* | 0 | 0 | Invalidate Cache
* | 0 | 1 | Valid, but unlocked cacheline
* | 1 | 0 | Invalidate Cache, No effect of lock
* | 1 | 1 | Valid cache. Locked to a
* | 1 | 1 | Valid cache. Locked to a
* | | | particular addrees
* --------------------------------------------------------------
*
*
**********************************************************************************/
#include "xparameters.h"
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
@ -97,7 +100,7 @@ microblaze_update_dcache:
addik r6, r0, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
/* We don't have a return instruction here. This is tail call optimization :) */
#endif /* XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1 */
.end microblaze_update_dcache

16
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/microblaze_update_icache.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_update_icache.S
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -28,6 +28,9 @@
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/******************************************************************************
*
* File : microblaze_update_icache.s
* Date : 2003, September 24
* Company: Xilinx
@ -48,14 +51,14 @@
* | 0 | 0 | Invalidate Cache
* | 0 | 1 | Valid, but unlocked cacheline
* | 1 | 0 | Invalidate Cache, No effect of lock
* | 1 | 1 | Valid cache. Locked to a
* | 1 | 1 | Valid cache. Locked to a
* | | | particular addrees
* --------------------------------------------------------------
*
*
**********************************************************************************/
#include "xparameters.h"
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
@ -67,7 +70,7 @@
microblaze_update_icache:
#if XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1
/* Read the MSR register into a temp register */
mfs r18, rmsr
@ -96,8 +99,7 @@ microblaze_update_icache:
addik r6, r0, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
/* We don't have a return instruction here. This is tail call optimization :) */
#endif /* XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 */
.end microblaze_update_icache
.end microblaze_update_icache

15
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/outbyte.c Normal file
View file

@ -0,0 +1,15 @@
#include "xparameters.h"
#include "xuartlite_l.h"
#ifdef __cplusplus
extern "C" {
#endif
void outbyte(char c);
#ifdef __cplusplus
}
#endif
void outbyte(char c) {
XUartLite_SendByte(STDOUT_BASEADDRESS, c);
}

32
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/print.c Normal file
View file

@ -0,0 +1,32 @@
/* print.c -- print a string on the output device.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*
*/
/*
* print -- do a raw print of a string
*/
#include "xil_printf.h"
void print(const char8 *ptr)
{
#ifdef STDOUT_BASEADDRESS
while (*ptr != (char8)0) {
outbyte (*ptr);
*ptr++;
}
#else
(void)ptr;
#endif
}

13
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/Makefile → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/Makefile
View file

@ -1,7 +1,6 @@
#$Id: Makefile,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $
###############################################################################
#
# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
@ -32,17 +31,17 @@
###############################################################################
#
# Makefile for profiler
#
#
#######################################################################
# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
include ../config.make
AS=mb-as
COMPILER = mb-gcc
COMPILER = mb-gcc
ARCHIVER = mb-ar
CP = cp
COMPILER_FLAGS=-O2
COMPILER_FLAGS=-O2
EXTRA_COMPILER_FLAGS=
LIB = libxil.a
DUMMYLIB = libxilprofile.a
@ -54,7 +53,7 @@ RELEASEDIR = ../../../../lib
INCLUDEDIR = ../../../../include
INCLUDES = -I./. -I${INCLUDEDIR}
OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
DUMMYOBJ = dummy.o
INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
@ -72,7 +71,7 @@ dummylibs : $(DUMMYOBJ)
%.o:%.S
$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
include:
include:
$(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
clean:

6
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_clean.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_clean.c
View file

@ -1,7 +1,6 @@
// $Id: _profile_clean.c,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -35,6 +34,8 @@
#include "_profile_timer_hw.h"
#include "xil_exception.h"
void _profile_clean( void );
/*
* This function is the exit routine and is called by the crtinit, when the
* program terminates. The name needs to be changed later..
@ -44,4 +45,3 @@ void _profile_clean( void )
Xil_ExceptionDisable();
disable_timer();
}

56
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_init.c → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_init.c
View file

@ -1,7 +1,6 @@
// $Id: _profile_init.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -38,57 +37,54 @@
#include "profile.h"
// XMD Initializes the following Global Variables Value during Program
// Download with appropriate values.
/* XMD Initializes the following Global Variables Value during Program
* Download with appropriate values. */
#ifdef PROC_MICROBLAZE
extern int microblaze_init(void);
extern s32 microblaze_init(void);
#elif defined PROC_PPC
extern int powerpc405_init(void);
extern s32 powerpc405_init(void);
#else
extern int cortexa9_init(void);
extern s32 cortexa9_init(void);
#endif
s32 profile_version = 1; /* Version of S/W Intrusive Profiling library */
u32 binsize = (u32)BINSIZE; /* Histogram Bin Size */
u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ; /* CPU Clock Frequency */
u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ; /* Histogram Sampling Frequency */
u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */
int profile_version = 1; // Version of S/W Intrusive Profiling library
/* Structure for Storing the Profiling Data */
struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU);
s32 n_gmon_sections = 1;
int binsize = BINSIZE; // Histogram Bin Size
unsigned int cpu_clk_freq = CPU_FREQ_HZ ; // CPU Clock Frequency
unsigned int sample_freq_hz = SAMPLE_FREQ_HZ ; // Histogram Sampling Frequency
unsigned int timer_clk_ticks = TIMER_CLK_TICKS ;// Timer Clock Ticks for the Timer
/* This is the initialization code, which is called from the crtinit. */
// Structure for Storing the Profiling Data
struct gmonparam *_gmonparam = (struct gmonparam *)0xffffffff;
int n_gmon_sections = 1;
// This is the initialization code, which is called from the crtinit.
//
void _profile_init( void )
{
/* print("Gmon Init called....\r\n") ; */
/* putnum(n_gmon_sections) ; print("\r\n") ; */
/* print("Gmon Init called....\r\n") */
/* putnum(n_gmon_sections) , print("\r\n") */
/* if( _gmonparam == 0xffffffff ) */
/* printf("Gmonparam is NULL !!\r\n"); */
/* for( i = 0; i < n_gmon_sections; i++ ){ */
/* putnum(_gmonparam[i].lowpc) ; print("\t") ; */
/* putnum(_gmonparam[i].highpc) ; print("\r\n") ; */
/* putnum( _gmonparam[i].textsize ); print("\r\n") ; */
/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short));print("\r\n"); */
/* } */
/* printf("Gmonparam is NULL !!\r\n") */
/* for( i = 0, i < n_gmon_sections, i++ )[ */
/* putnum( _gmonparam[i].lowpc) , print("\t") */
/* putnum( _gmonparam[i].highpc) , print("\r\n") */
/* putnum( _gmonparam[i].textsize ), print("\r\n") */
/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n") */
/* ] */
#ifdef PROC_MICROBLAZE
microblaze_init();
(void)microblaze_init();
#elif defined PROC_PPC
powerpc405_init();
#else
cortexa9_init ();
(void)cortexa9_init();
#endif
}

387
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.c Normal file
View file

@ -0,0 +1,387 @@
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************
*
* _program_timer_hw.c:
* Timer related functions
*
******************************************************************************/
#include "profile.h"
#include "_profile_timer_hw.h"
#include "xil_exception.h"
#ifdef PROC_PPC
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif /* TIMER_CONNECT_INTC */
/* #ifndef PPC_PIT_INTERRUPT */
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
#endif
/* extern u32 timer_clk_ticks, */
#ifdef PROC_PPC405
#ifdef PPC_PIT_INTERRUPT
s32 ppc_pit_init( void );
#endif
s32 powerpc405_init()
#endif /* PROC_CORTEXA9 */
#ifdef PROC_PPC440
#ifdef PPC_PIT_INTERRUPT
s32 ppc_dec_init( void );
#endif
s32 powerpc405_init(void);
#endif /* PROC_PPC440 */
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
s32 opb_timer_init( void );
#endif
#ifdef PROC_MICROBLAZE
s32 microblaze_init(void);
#endif /* PROC_MICROBLAZE */
#ifdef PROC_CORTEXA9
s32 scu_timer_init( void );
s32 cortexa9_init(void);
#endif /* PROC_CORTEXA9 */
/*--------------------------------------------------------------------
* PowerPC Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_PPC405
/*--------------------------------------------------------------------
* PowerPC PIT Timer Init.
* Defined only if PIT Timer is used for Profiling
*
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
int ppc_pit_init( void )
{
/* 1. Register Profile_intr_handler as Interrupt handler */
/* 2. Set PIT Timer Interrupt and Enable it. */
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
(Xil_ExceptionHandler)profile_intr_handler,NULL);
XTime_PITSetInterval( timer_clk_ticks ) ;
XTime_PITEnableAutoReload() ;
return 0;
}
#endif
/* --------------------------------------------------------------------
* PowerPC Timer Initialization functions.
* For PowerPC, PIT and opb_timer can be used for Profiling. This
* is selected by the user in standalone BSP
*
*-------------------------------------------------------------------- */
s32 powerpc405_init()
{
Xil_ExceptionInit() ;
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
/* Initialize the Timer.
* 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
* 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
#ifdef PPC_PIT_INTERRUPT
ppc_pit_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,NULL);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,NULL);
#endif
/* Initialize the timer with Timer Ticks */
opb_timer_init() ;
#endif
/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
* in the System. */
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_PITEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
#endif
return 0;
}
#endif /* PROC_PPC */
/*--------------------------------------------------------------------
* PowerPC440 Target - Timer related functions
* -------------------------------------------------------------------- */
#ifdef PROC_PPC440
/*--------------------------------------------------------------------
* PowerPC DEC Timer Init.
* Defined only if DEC Timer is used for Profiling
*
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
s32 ppc_dec_init( void )
{
/* 1. Register Profile_intr_handler as Interrupt handler */
/* 2. Set DEC Timer Interrupt and Enable it. */
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
(Xil_ExceptionHandler)profile_intr_handler,NULL);
XTime_DECSetInterval( timer_clk_ticks ) ;
XTime_DECEnableAutoReload() ;
return 0;
}
#endif
/*--------------------------------------------------------------------
* PowerPC Timer Initialization functions.
* For PowerPC, DEC and opb_timer can be used for Profiling. This
* is selected by the user in standalone BSP
*
*-------------------------------------------------------------------- */
s32 powerpc405_init(void)
{
Xil_ExceptionInit();
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
/* Initialize the Timer.
* 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
* 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
#ifdef PPC_PIT_INTERRUPT
ppc_dec_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,NULL);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,NULL);
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,NULL);
#endif
/* Initialize the timer with Timer Ticks */
opb_timer_init() ;
#endif
/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
* in the System. */
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_DECEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
#endif
return 0;
}
#endif /* PROC_PPC440 */
/* --------------------------------------------------------------------
* opb_timer Initialization for PowerPC and MicroBlaze. This function
* is not needed if DEC timer is used in PowerPC
*
*-------------------------------------------------------------------- */
/* #ifndef PPC_PIT_INTERRUPT */
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
s32 opb_timer_init( void )
{
/* set the number of cycles the timer counts before interrupting */
XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks);
/* reset the timers, and clear interrupts */
XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0,
(u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK );
/* start the timers */
XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK
| (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK);
return 0;
}
#endif
/*--------------------------------------------------------------------
* MicroBlaze Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_MICROBLAZE
/* --------------------------------------------------------------------
* Initialize the Profile Timer for MicroBlaze Target.
* For MicroBlaze, opb_timer is used. The opb_timer can be directly
* connected to MicroBlaze or connected through Interrupt Controller.
*
*-------------------------------------------------------------------- */
s32 microblaze_init(void)
{
/* Register profile_intr_handler
* 1. If timer is connected to Interrupt Controller, register the handler
* to Interrupt Controllers vector table.
* 2. If timer is directly connected to MicroBlaze, register the handler
* as Interrupt handler */
Xil_ExceptionInit();
#ifdef TIMER_CONNECT_INTC
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,NULL);
#else
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)profile_intr_handler,
NULL) ;
#endif
/* Initialize the timer with Timer Ticks */
(void)opb_timer_init() ;
/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
* in the System. */
#ifdef ENABLE_SYS_INTR
#ifdef TIMER_CONNECT_INTC
XIntc_MasterEnable((u32)INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
#endif
#endif
Xil_ExceptionEnable();
return 0;
}
#endif /* PROC_MICROBLAZE */
/* --------------------------------------------------------------------
* Cortex A9 Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_CORTEXA9
/* --------------------------------------------------------------------
* Initialize the Profile Timer for Cortex A9 Target.
* The scu private timer is connected to the Scu GIC controller.
*
*-------------------------------------------------------------------- */
s32 scu_timer_init( void )
{
/* set the number of cycles the timer counts before interrupting
* scu timer runs at half the cpu clock */
XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U);
/* clear any pending interrupts */
XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U);
/* enable interrupts, auto-reload mode and start the timer */
XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
return 0;
}
s32 cortexa9_init(void)
{
Xil_ExceptionInit();
XScuGic_DeviceInitialize(0);
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
NULL);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
PROFILE_TIMER_INTR_ID,
(Xil_ExceptionHandler)profile_intr_handler,
NULL);
/*
* Enable the interrupt for scu timer.
*/
XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
/*
* Initialize the timer with Timer Ticks
*/
(void)scu_timer_init() ;
Xil_ExceptionEnable();
return 0;
}
#endif /* PROC_CORTEXA9 */

214
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/_profile_timer_hw.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.h
View file

@ -1,7 +1,6 @@
// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
/******************************************************************************
*
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -36,8 +35,8 @@
*
******************************************************************************/
#ifndef _PROFILE_TIMER_HW_H
#define _PROFILE_TIMER_HW_H
#ifndef PROFILE_TIMER_HW_H
#define PROFILE_TIMER_HW_H
#include "profile.h"
@ -52,26 +51,26 @@
#endif
#ifdef PROC_PPC
#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO;
#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
#else
#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); }
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
#endif
#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
(RegOffset)), (ValueToWrite))
ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
(u32)(RegOffset)), (u32)(ValueToWrite))
#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset))
ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(RegisterValue))
#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
@ -88,7 +87,7 @@ extern "C" {
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif // TIMER_CONNECT_INTC
#endif /* TIMER_CONNECT_INTC */
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
@ -99,15 +98,15 @@ extern "C" {
#include "xscugic.h"
#endif
extern unsigned int timer_clk_ticks ;
extern u32 timer_clk_ticks ;
//--------------------------------------------------------------------
// PowerPC Target - Timer related functions
//--------------------------------------------------------------------
/*--------------------------------------------------------------------
* PowerPC Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_PPC
#ifdef PPC_PIT_INTERRUPT
unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG
u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
#endif
#ifdef PROC_PPC440
@ -117,21 +116,21 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG
#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
#endif
//--------------------------------------------------------------------
// Disable the Timer - During Profiling
//
// For PIT Timer -
// 1. XTime_PITDisableInterrupt() ;
// 2. Store the remaining timer clk tick
// 3. Stop the PIT Timer
//--------------------------------------------------------------------
/* --------------------------------------------------------------------
* Disable the Timer - During Profiling
*
* For PIT Timer -
* 1. XTime_PITDisableInterrupt() ;
* 2. Store the remaining timer clk tick
* 3. Stop the PIT Timer
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define disable_timer() \
{ \
unsigned long val; \
u32 val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \
mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
mtspr(XREG_SPR_PIT, 0); \
}
@ -140,24 +139,24 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
//--------------------------------------------------------------------
// Enable the Timer
//
// For PIT Timer -
// 1. Load the remaining timer clk ticks
// 2. XTime_PITEnableInterrupt() ;
//--------------------------------------------------------------------
/* --------------------------------------------------------------------
* Enable the Timer
*
* For PIT Timer -
* 1. Load the remaining timer clk ticks
* 2. XTime_PITEnableInterrupt() ;
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define enable_timer() \
{ \
unsigned long val; \
u32 val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
@ -174,18 +173,18 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
// For PIT Timer -
// 1. Load the timer clk ticks
// 2. Enable AutoReload and Interrupt
// 3. Clear PIT Timer Status bits
//--------------------------------------------------------------------
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
* For PIT Timer -
* 1. Load the timer clk ticks
* 2. Enable AutoReload and Interrupt
* 3. Clear PIT Timer Status bits
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define timer_ack() \
{ \
unsigned long val; \
u32 val; \
mtspr(XREG_SPR_PIT, timer_clk_ticks); \
mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
val=mfspr(XREG_SPR_TCR); \
@ -194,109 +193,116 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG
#else
#define timer_ack() \
{ \
unsigned int csr; \
u32 csr; \
csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
#endif
//--------------------------------------------------------------------
#endif // PROC_PPC
//--------------------------------------------------------------------
/*-------------------------------------------------------------------- */
#endif /* PROC_PPC */
/* -------------------------------------------------------------------- */
//--------------------------------------------------------------------
// MicroBlaze Target - Timer related functions
//--------------------------------------------------------------------
/* --------------------------------------------------------------------
* MicroBlaze Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_MICROBLAZE
//--------------------------------------------------------------------
// Disable the Timer during Call-Graph Data collection
//
//--------------------------------------------------------------------
/* --------------------------------------------------------------------
* Disable the Timer during Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define disable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
Addr += (u32)XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(Addr); \
tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
OutAddr += (u32)XTC_TCSR_OFFSET; \
ProfIo_Out32(OutAddr, (u32)tmp_v); \
}
//--------------------------------------------------------------------
// Enable the Timer after Call-Graph Data collection
//
//--------------------------------------------------------------------
/* --------------------------------------------------------------------
* Enable the Timer after Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define enable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
Addr += (u32)XTC_TCSR_OFFSET; \
u32 tmp_v = (u32)ProfIo_In32(Addr); \
tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
}
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
//--------------------------------------------------------------------
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
*-------------------------------------------------------------------- */
#define timer_ack() \
{ \
unsigned int csr; \
csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
u32 csr; \
csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
}
//--------------------------------------------------------------------
#endif // PROC_MICROBLAZE
//--------------------------------------------------------------------
/*-------------------------------------------------------------------- */
#endif /* PROC_MICROBLAZE */
/*-------------------------------------------------------------------- */
//--------------------------------------------------------------------
// Cortex A9 Target - Timer related functions
//--------------------------------------------------------------------
/* --------------------------------------------------------------------
* Cortex A9 Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_CORTEXA9
//--------------------------------------------------------------------
// Disable the Timer during Call-Graph Data collection
//
//--------------------------------------------------------------------
/* --------------------------------------------------------------------
* Disable the Timer during Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define disable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\
Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
} \
}
//--------------------------------------------------------------------
// Enable the Timer after Call-Graph Data collection
//
//--------------------------------------------------------------------
/* --------------------------------------------------------------------
* Enable the Timer after Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define enable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
} \
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
//--------------------------------------------------------------------
#define timer_ack() \
{ \
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \
XSCUTIMER_ISR_EVENT_FLAG_MASK);\
}
//--------------------------------------------------------------------
#endif // PROC_CORTEXA9
//--------------------------------------------------------------------
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
*-------------------------------------------------------------------- */
#define timer_ack() \
{ \
Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
(u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
}
/*-------------------------------------------------------------------- */
#endif /* PROC_CORTEXA9 */
/*-------------------------------------------------------------------- */
#ifdef __cplusplus

23
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/dummy.S → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/dummy.S
View file

@ -1,7 +1,6 @@
// $Id: dummy.S,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -34,32 +33,32 @@
.globl dummy_f
#ifdef PROC_MICROBLAZE
.text
.text
.align 2
.ent dummy_f
dummy_f:
nop
.end dummy_f
.end dummy_f
#endif
#ifdef PROC_PPC
#ifdef PROC_PPC
.section .text
.align 2
.type dummy_f@function
dummy_f:
dummy_f:
b dummy_f
#endif
#ifdef PROC_CORTEXA9
#ifdef PROC_CORTEXA9
.section .text
.align 2
.type dummy_f, %function
dummy_f:
dummy_f:
b dummy_f
#endif

3
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v4_2/src/profile/mblaze_nt_types.h → FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/profile/mblaze_nt_types.h
View file

@ -1,7 +1,6 @@
// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal

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