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Support configurable RISC-V chip extension (#773)

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* Support configurable RISC-V chip extension

Added the FREERTOS_RISCV_EXTENSION option to allow the user
to select which chip extension they want included. Removed the
port for pulpino to instead use the new option.

* Add port GCC_RISC_V_GENERIC and IAR_RISC_V_GENERIC

* Add two rics-v generic ports to support FREERTOS_RISCV_EXTENSION
  config

---------

Co-authored-by: Joe Benczarski <jbenczarski@trijicon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Ching-Hsin Lee <chinglee@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
This commit is contained in:
Joe Benczarski 2023-10-27 14:57:52 -04:00 • committed by GitHub
parent 5281427a99
commit 37678b0656
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4 changed files with 61 additions and 0 deletions
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24
portable/CMakeLists.txt
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@ -1,3 +1,11 @@
if( FREERTOS_PORT STREQUAL "GCC_RISC_V_GENERIC" )
include( GCC/RISC-V/chip_extensions.cmake )
endif()
if( FREERTOS_PORT STREQUAL "IAR_RISC_V_GENERIC" )
include( IAR/RISC-V/chip_extensions.cmake )
endif()
# FreeRTOS internal cmake file. Do not use it in user top-level project
if (FREERTOS_PORT STREQUAL "A_CUSTOM_PORT")
@ -292,6 +300,10 @@ add_library(freertos_kernel_port STATIC
GCC/RISC-V/port.c
GCC/RISC-V/portASM.S>
$<$<STREQUAL:${FREERTOS_PORT},GCC_RISC_V_GENERIC>:
GCC/RISC-V/port.c
GCC/RISC-V/portASM.S>
# Renesas RL78 port for GCC
$<$<STREQUAL:${FREERTOS_PORT},GCC_RL78>:
GCC/RL78/port.c
@ -497,6 +509,10 @@ add_library(freertos_kernel_port STATIC
IAR/RISC-V/port.c
IAR/RISC-V/portASM.s>
$<$<STREQUAL:${FREERTOS_PORT},IAR_RISC_V_GENERIC>:
IAR/RISC-V/port.c
IAR/RISC-V/portASM.s>
# Renesas RL78 port for IAR EWRL78
$<$<STREQUAL:${FREERTOS_PORT},IAR_RL78>:
IAR/RL78/port.c
@ -845,6 +861,10 @@ target_include_directories(freertos_kernel_port PUBLIC
${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V
${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM>
$<$<STREQUAL:${FREERTOS_PORT},GCC_RISC_V_GENERIC>:
${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V
${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/${FREERTOS_RISCV_EXTENSION}>
# Renesas RL78 port for GCC
$<$<STREQUAL:${FREERTOS_PORT},GCC_RL78>:${CMAKE_CURRENT_LIST_DIR}/GCC/RL78>
@ -942,6 +962,10 @@ target_include_directories(freertos_kernel_port PUBLIC
${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V
${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions>
$<$<STREQUAL:${FREERTOS_PORT},IAR_RISC_V_GENERIC>:
${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V
${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V/chip_specific_extensions/${FREERTOS_RISCV_EXTENSION}>
# Renesas RL78 port for IAR EWRL78
$<$<STREQUAL:${FREERTOS_PORT},IAR_RL78>:${CMAKE_CURRENT_LIST_DIR}/IAR/RL78>