mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-06-05 20:09:05 -04:00
Style: uncrustify
This commit is contained in:
Alfred Gedeon
alfred gedeon
parent
718178c68a
commit
2c530ba5c3
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@ -218,18 +218,18 @@
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#define portDISABLE_INTERRUPTS() \
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asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */\
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"MRS R0, CPSR \n\t" /* Get CPSR. */\
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t" /* Write back modified value. */\
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"STMDB SP!, {R0} \n\t"/* Push R0. */\
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"MRS R0, CPSR \n\t"/* Get CPSR. */\
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"ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t"/* Write back modified value. */\
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"LDMIA SP!, {R0} ") /* Pop R0. */
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#define portENABLE_INTERRUPTS() \
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asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */\
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"MRS R0, CPSR \n\t" /* Get CPSR. */\
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t" /* Write back modified value. */\
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"STMDB SP!, {R0} \n\t"/* Push R0. */\
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"MRS R0, CPSR \n\t"/* Get CPSR. */\
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"BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t"/* Write back modified value. */\
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"LDMIA SP!, {R0} ") /* Pop R0. */
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#endif /* THUMB_INTERWORK */
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@ -213,18 +213,18 @@
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#define portDISABLE_INTERRUPTS() \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */\
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"MRS R0, CPSR \n\t" /* Get CPSR. */\
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t" /* Write back modified value. */\
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"STMDB SP!, {R0} \n\t"/* Push R0. */\
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"MRS R0, CPSR \n\t"/* Get CPSR. */\
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"ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t"/* Write back modified value. */\
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"LDMIA SP!, {R0} ") /* Pop R0. */
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#define portENABLE_INTERRUPTS() \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */\
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"MRS R0, CPSR \n\t" /* Get CPSR. */\
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t" /* Write back modified value. */\
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"STMDB SP!, {R0} \n\t"/* Push R0. */\
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"MRS R0, CPSR \n\t"/* Get CPSR. */\
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"BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t"/* Write back modified value. */\
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"LDMIA SP!, {R0} ") /* Pop R0. */
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#endif /* THUMB_INTERWORK */
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@ -190,18 +190,18 @@
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#define portDISABLE_INTERRUPTS() \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */\
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"MRS R0, CPSR \n\t" /* Get CPSR. */\
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t" /* Write back modified value. */\
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"STMDB SP!, {R0} \n\t"/* Push R0. */\
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"MRS R0, CPSR \n\t"/* Get CPSR. */\
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"ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t"/* Write back modified value. */\
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"LDMIA SP!, {R0} ") /* Pop R0. */
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#define portENABLE_INTERRUPTS() \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */\
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"MRS R0, CPSR \n\t" /* Get CPSR. */\
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t" /* Write back modified value. */\
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"STMDB SP!, {R0} \n\t"/* Push R0. */\
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"MRS R0, CPSR \n\t"/* Get CPSR. */\
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"BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t"/* Write back modified value. */\
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"LDMIA SP!, {R0} ") /* Pop R0. */
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#endif /* THUMB_INTERWORK */
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@ -213,18 +213,18 @@
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#define portDISABLE_INTERRUPTS() \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */\
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"MRS R0, CPSR \n\t" /* Get CPSR. */\
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t" /* Write back modified value. */\
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"STMDB SP!, {R0} \n\t"/* Push R0. */\
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"MRS R0, CPSR \n\t"/* Get CPSR. */\
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"ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t"/* Write back modified value. */\
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"LDMIA SP!, {R0} ") /* Pop R0. */
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#define portENABLE_INTERRUPTS() \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */\
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"MRS R0, CPSR \n\t" /* Get CPSR. */\
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t" /* Write back modified value. */\
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"STMDB SP!, {R0} \n\t"/* Push R0. */\
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"MRS R0, CPSR \n\t"/* Get CPSR. */\
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"BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
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"MSR CPSR, R0 \n\t"/* Write back modified value. */\
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"LDMIA SP!, {R0} ") /* Pop R0. */
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#endif /* THUMB_INTERWORK */
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@ -220,11 +220,11 @@ static void prvTaskExitError( void )
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void vPortSVCHandler( void )
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{
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__asm volatile (
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" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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" ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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" msr psp, r0 \n" /* Restore the task stack pointer. */
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" ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
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" ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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" ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
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" ldmia r0!, {r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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" msr psp, r0 \n"/* Restore the task stack pointer. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"
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@ -240,15 +240,15 @@ void vPortSVCHandler( void )
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static void prvPortStartFirstTask( void )
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{
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__asm volatile (
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" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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" ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n"
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" ldr r0, [r0] \n"
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" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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" cpsie i \n" /* Globally enable interrupts. */
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" msr msp, r0 \n"/* Set the msp back to the start of the stack. */
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" cpsie i \n"/* Globally enable interrupts. */
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" cpsie f \n"
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" dsb \n"
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" isb \n"
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" svc 0 \n" /* System call to start first task. */
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" svc 0 \n"/* System call to start first task. */
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" nop \n"
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" .ltorg \n"
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);
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@ -82,7 +82,7 @@
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
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\
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/* Barriers are normally not required but do ensure the code is completely \
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* within the specified behaviour for the architecture. */\
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* within the specified behaviour for the architecture. */ \
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__asm volatile ( "dsb" ::: "memory" ); \
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__asm volatile ( "isb" ); \
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}
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@ -294,9 +294,9 @@ static void prvSVCHandler( uint32_t * pulParam )
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{
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__asm volatile
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(
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" mrs r1, control \n" /* Obtain current control value. */
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" bic r1, #1 \n" /* Set privilege bit. */
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" msr control, r1 \n" /* Write back new control value. */
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" mrs r1, control \n"/* Obtain current control value. */
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" bic r1, #1 \n"/* Set privilege bit. */
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" msr control, r1 \n"/* Write back new control value. */
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::: "r1", "memory"
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);
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}
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@ -306,9 +306,9 @@ static void prvSVCHandler( uint32_t * pulParam )
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case portSVC_RAISE_PRIVILEGE:
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__asm volatile
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(
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" mrs r1, control \n" /* Obtain current control value. */
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" bic r1, #1 \n" /* Set privilege bit. */
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" msr control, r1 \n" /* Write back new control value. */
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" mrs r1, control \n"/* Obtain current control value. */
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" bic r1, #1 \n"/* Set privilege bit. */
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" msr control, r1 \n"/* Write back new control value. */
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::: "r1", "memory"
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);
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break;
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@ -453,15 +453,15 @@ BaseType_t xPortStartScheduler( void )
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/* Start the first task. */
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__asm volatile (
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" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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" ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n"
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" ldr r0, [r0] \n"
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" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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" cpsie i \n" /* Globally enable interrupts. */
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" msr msp, r0 \n"/* Set the msp back to the start of the stack. */
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" cpsie i \n"/* Globally enable interrupts. */
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" cpsie f \n"
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" dsb \n"
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" isb \n"
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" svc %0 \n" /* System call to start first task. */
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" svc %0 \n"/* System call to start first task. */
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" nop \n"
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" .ltorg \n"
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::"i" ( portSVC_START_SCHEDULER ) : "memory" );
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@ -125,7 +125,7 @@
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
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\
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/* Barriers are normally not required but do ensure the code is completely \
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* within the specified behaviour for the architecture. */\
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* within the specified behaviour for the architecture. */ \
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__asm volatile ( "dsb" ::: "memory" ); \
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__asm volatile ( "isb" ); \
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}
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@ -245,11 +245,11 @@ static void prvTaskExitError( void )
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void vPortSVCHandler( void )
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{
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__asm volatile (
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" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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" ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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" msr psp, r0 \n" /* Restore the task stack pointer. */
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" ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
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" ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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" ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
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" ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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" msr psp, r0 \n"/* Restore the task stack pointer. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"
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@ -268,17 +268,17 @@ static void prvPortStartFirstTask( void )
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* would otherwise result in the unnecessary leaving of space in the SVC stack
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* for lazy saving of FPU registers. */
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__asm volatile (
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" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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" ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n"
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" ldr r0, [r0] \n"
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" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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" mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
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" msr msp, r0 \n"/* Set the msp back to the start of the stack. */
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" mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
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" msr control, r0 \n"
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" cpsie i \n" /* Globally enable interrupts. */
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" cpsie i \n"/* Globally enable interrupts. */
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" cpsie f \n"
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" dsb \n"
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" isb \n"
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" svc 0 \n" /* System call to start first task. */
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" svc 0 \n"/* System call to start first task. */
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" nop \n"
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" .ltorg \n"
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);
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@ -82,7 +82,7 @@
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
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\
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/* Barriers are normally not required but do ensure the code is completely \
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* within the specified behaviour for the architecture. */\
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* within the specified behaviour for the architecture. */ \
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__asm volatile ( "dsb" ::: "memory" ); \
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__asm volatile ( "isb" ); \
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}
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|
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@ -313,9 +313,9 @@ static void prvSVCHandler( uint32_t * pulParam )
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{
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__asm volatile
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(
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" mrs r1, control \n" /* Obtain current control value. */
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" bic r1, #1 \n" /* Set privilege bit. */
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" msr control, r1 \n" /* Write back new control value. */
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" mrs r1, control \n"/* Obtain current control value. */
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" bic r1, #1 \n"/* Set privilege bit. */
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" msr control, r1 \n"/* Write back new control value. */
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::: "r1", "memory"
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);
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}
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@ -325,9 +325,9 @@ static void prvSVCHandler( uint32_t * pulParam )
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case portSVC_RAISE_PRIVILEGE:
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__asm volatile
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(
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" mrs r1, control \n" /* Obtain current control value. */
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" bic r1, #1 \n" /* Set privilege bit. */
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" msr control, r1 \n" /* Write back new control value. */
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" mrs r1, control \n"/* Obtain current control value. */
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" bic r1, #1 \n"/* Set privilege bit. */
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" msr control, r1 \n"/* Write back new control value. */
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::: "r1", "memory"
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);
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break;
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@ -480,17 +480,17 @@ BaseType_t xPortStartScheduler( void )
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* would otherwise result in the unnecessary leaving of space in the SVC stack
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* for lazy saving of FPU registers. */
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__asm volatile (
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" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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" ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n"
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" ldr r0, [r0] \n"
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" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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" mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
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" msr msp, r0 \n"/* Set the msp back to the start of the stack. */
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" mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
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" msr control, r0 \n"
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" cpsie i \n" /* Globally enable interrupts. */
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" cpsie i \n"/* Globally enable interrupts. */
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" cpsie f \n"
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" dsb \n"
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" isb \n"
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" svc %0 \n" /* System call to start first task. */
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" svc %0 \n"/* System call to start first task. */
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" nop \n"
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" .ltorg \n"
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::"i" ( portSVC_START_SCHEDULER ) : "memory" );
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|
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@ -125,7 +125,7 @@
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
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\
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/* Barriers are normally not required but do ensure the code is completely \
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* within the specified behaviour for the architecture. */\
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* within the specified behaviour for the architecture. */ \
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__asm volatile ( "dsb" ::: "memory" ); \
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__asm volatile ( "isb" ); \
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}
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|
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@ -239,11 +239,11 @@ static void prvTaskExitError( void )
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void vPortSVCHandler( void )
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{
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__asm volatile (
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" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
|
||||
" ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
|
||||
" msr psp, r0 \n" /* Restore the task stack pointer. */
|
||||
" ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
|
||||
" ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
|
||||
" ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
|
||||
" ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
|
||||
" msr psp, r0 \n"/* Restore the task stack pointer. */
|
||||
" isb \n"
|
||||
" mov r0, #0 \n"
|
||||
" msr basepri, r0 \n"
|
||||
|
|
@ -262,17 +262,17 @@ static void prvPortStartFirstTask( void )
|
|||
* would otherwise result in the unnecessary leaving of space in the SVC stack
|
||||
* for lazy saving of FPU registers. */
|
||||
__asm volatile (
|
||||
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
|
||||
" ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
|
||||
" ldr r0, [r0] \n"
|
||||
" ldr r0, [r0] \n"
|
||||
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
|
||||
" mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
|
||||
" msr msp, r0 \n"/* Set the msp back to the start of the stack. */
|
||||
" mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
|
||||
" msr control, r0 \n"
|
||||
" cpsie i \n" /* Globally enable interrupts. */
|
||||
" cpsie i \n"/* Globally enable interrupts. */
|
||||
" cpsie f \n"
|
||||
" dsb \n"
|
||||
" isb \n"
|
||||
" svc 0 \n" /* System call to start first task. */
|
||||
" svc 0 \n"/* System call to start first task. */
|
||||
" nop \n"
|
||||
" .ltorg \n"
|
||||
);
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@
|
|||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
|
||||
\
|
||||
/* Barriers are normally not required but do ensure the code is completely \
|
||||
* within the specified behaviour for the architecture. */\
|
||||
* within the specified behaviour for the architecture. */ \
|
||||
__asm volatile ( "dsb" ::: "memory" ); \
|
||||
__asm volatile ( "isb" ); \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -399,13 +399,13 @@
|
|||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* in order to save R0-R7 */ \
|
||||
"sub sp, 6*4 \n\t" \
|
||||
"sub sp, 6*4 \n\t"\
|
||||
/* Save R0..R7 */ \
|
||||
"stm --sp, r0-r7 \n\t" \
|
||||
"stm --sp, r0-r7 \n\t"\
|
||||
\
|
||||
/* in order to save R8-R12 and LR */ \
|
||||
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
|
||||
"sub r7, sp,-16*4 \n\t" \
|
||||
"sub r7, sp,-16*4 \n\t"\
|
||||
/* Copy PC and SR in other places in the stack. */ \
|
||||
"ld.w r0, r7[-2*4] \n\t"/* Read SR */\
|
||||
"st.w r7[-8*4], r0 \n\t"/* Copy SR */\
|
||||
|
|
@ -413,7 +413,7 @@
|
|||
"st.w r7[-7*4], r0 \n\t"/* Copy PC */\
|
||||
\
|
||||
/* Save R8..R12 and LR on the stack. */ \
|
||||
"stm --r7, r8-r12, lr \n\t" \
|
||||
"stm --r7, r8-r12, lr \n\t"\
|
||||
\
|
||||
/* Arriving here we have the following stack organizations: */ \
|
||||
/* R8..R12, LR, PC, SR, R0..R7. */ \
|
||||
|
|
@ -421,9 +421,9 @@
|
|||
/* Now we can finalize the save. */ \
|
||||
\
|
||||
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
|
||||
"ld.w r0, r8[0] \n\t" \
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w --sp, r0" \
|
||||
: \
|
||||
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
|
||||
|
|
@ -437,9 +437,9 @@
|
|||
\
|
||||
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
||||
__asm__ __volatile__ ( \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
|
||||
"ld.w r0, r8[0] \n\t" \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w r0[0], sp" \
|
||||
: \
|
||||
:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
|
||||
|
|
@ -458,9 +458,9 @@
|
|||
\
|
||||
/* Set SP to point to new stack */ \
|
||||
__asm__ __volatile__ ( \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
|
||||
"ld.w r0, r8[0] \n\t" \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"ld.w sp, r0[0]" \
|
||||
: \
|
||||
:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
|
||||
|
|
@ -471,16 +471,16 @@
|
|||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Restore ulCriticalNesting variable */ \
|
||||
"ld.w r0, sp++ \n\t" \
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
|
||||
"st.w r8[0], r0 \n\t" \
|
||||
"ld.w r0, sp++ \n\t"\
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
||||
"st.w r8[0], r0 \n\t"\
|
||||
\
|
||||
/* skip PC and SR */ \
|
||||
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
|
||||
"sub r7, sp, -10*4 \n\t" \
|
||||
"sub r7, sp, -10*4 \n\t"\
|
||||
/* Restore r8-r12 and LR */ \
|
||||
"ldm r7++, r8-r12, lr \n\t" \
|
||||
"ldm r7++, r8-r12, lr \n\t"\
|
||||
\
|
||||
/* RETS will take care of the extra PC and SR restore. */ \
|
||||
/* So, we have to prepare the stack for this. */ \
|
||||
|
|
@ -490,9 +490,9 @@
|
|||
"st.w r7[-1*4], r0 \n\t"/* Copy PC */\
|
||||
\
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t" \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
\
|
||||
"sub sp, -6*4 \n\t" \
|
||||
"sub sp, -6*4 \n\t"\
|
||||
\
|
||||
"rets" \
|
||||
: \
|
||||
|
|
@ -567,8 +567,8 @@
|
|||
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
||||
/* will just be restoring the interrupt handler, no way!!! */ \
|
||||
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
|
||||
"ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \
|
||||
"bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \
|
||||
"ld.w r0, sp[9*4] \n\t"/* Read SR in stack */\
|
||||
"bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */\
|
||||
"cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\
|
||||
"brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \
|
||||
\
|
||||
|
|
@ -600,15 +600,15 @@
|
|||
/* level and allow other lower interrupt level to occur). */ \
|
||||
/* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
|
||||
/* did not previously save SP in its TCB. */ \
|
||||
"ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \
|
||||
"bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \
|
||||
"ld.w r0, sp[9*4] \n\t"/* Read SR in stack */\
|
||||
"bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */\
|
||||
"cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\
|
||||
"brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \
|
||||
\
|
||||
/* If a switch is required then we just need to call */ \
|
||||
/* vTaskSwitchContext() as the context has already been */ \
|
||||
/* saved. */ \
|
||||
"cp.w r12, 1 \n\t"/* Check if Switch context is required. */ \
|
||||
"cp.w r12, 1 \n\t"/* Check if Switch context is required. */\
|
||||
"brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
|
||||
: \
|
||||
:[ LINE ] "i" ( __LINE__ ) \
|
||||
|
|
|
|||
|
|
@ -93,18 +93,18 @@
|
|||
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
asm volatile ( \
|
||||
"STMDB SP!, {R0} \n\t" /* Push R0. */\
|
||||
"MRS R0, CPSR \n\t" /* Get CPSR. */\
|
||||
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\
|
||||
"MSR CPSR, R0 \n\t" /* Write back modified value. */\
|
||||
"STMDB SP!, {R0} \n\t"/* Push R0. */\
|
||||
"MRS R0, CPSR \n\t"/* Get CPSR. */\
|
||||
"ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
|
||||
"MSR CPSR, R0 \n\t"/* Write back modified value. */\
|
||||
"LDMIA SP!, {R0} ") /* Pop R0. */
|
||||
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
asm volatile ( \
|
||||
"STMDB SP!, {R0} \n\t" /* Push R0. */\
|
||||
"MRS R0, CPSR \n\t" /* Get CPSR. */\
|
||||
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\
|
||||
"MSR CPSR, R0 \n\t" /* Write back modified value. */\
|
||||
"STMDB SP!, {R0} \n\t"/* Push R0. */\
|
||||
"MRS R0, CPSR \n\t"/* Get CPSR. */\
|
||||
"BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
|
||||
"MSR CPSR, R0 \n\t"/* Write back modified value. */\
|
||||
"LDMIA SP!, {R0} ") /* Pop R0. */
|
||||
|
||||
#endif /* THUMB_INTERWORK */
|
||||
|
|
|
|||
|
|
@ -303,9 +303,9 @@ void vPortSVCHandler_C( uint32_t * pulParam )
|
|||
{
|
||||
__asm volatile
|
||||
(
|
||||
" mrs r1, control \n" /* Obtain current control value. */
|
||||
" bic r1, r1, #1 \n" /* Set privilege bit. */
|
||||
" msr control, r1 \n" /* Write back new control value. */
|
||||
" mrs r1, control \n"/* Obtain current control value. */
|
||||
" bic r1, r1, #1 \n"/* Set privilege bit. */
|
||||
" msr control, r1 \n"/* Write back new control value. */
|
||||
::: "r1", "memory"
|
||||
);
|
||||
}
|
||||
|
|
@ -315,9 +315,9 @@ void vPortSVCHandler_C( uint32_t * pulParam )
|
|||
case portSVC_RAISE_PRIVILEGE:
|
||||
__asm volatile
|
||||
(
|
||||
" mrs r1, control \n" /* Obtain current control value. */
|
||||
" bic r1, r1, #1 \n" /* Set privilege bit. */
|
||||
" msr control, r1 \n" /* Write back new control value. */
|
||||
" mrs r1, control \n"/* Obtain current control value. */
|
||||
" bic r1, r1, #1 \n"/* Set privilege bit. */
|
||||
" msr control, r1 \n"/* Write back new control value. */
|
||||
::: "r1", "memory"
|
||||
);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -146,7 +146,7 @@ static void prvLowInterrupt( void );
|
|||
{ \
|
||||
_asm \
|
||||
/* Save the status and WREG registers first, as these will get modified \
|
||||
* by the operations below. */\
|
||||
* by the operations below. */ \
|
||||
MOVFF WREG, PREINC1 \
|
||||
MOVFF STATUS, PREINC1 \
|
||||
/* Save the INTCON register with the appropriate bits forced if \
|
||||
|
|
@ -243,12 +243,12 @@ static void prvLowInterrupt( void );
|
|||
MOVFF pxCurrentTCB + 1, FSR0H \
|
||||
\
|
||||
/* De-reference FSR0 to set the address it holds into FSR1. \
|
||||
* (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */\
|
||||
* (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
|
||||
MOVFF POSTINC0, FSR1L \
|
||||
MOVFF POSTINC0, FSR1H \
|
||||
\
|
||||
/* How many return addresses are there on the hardware stack? Discard \
|
||||
* the first byte as we are pointing to the next free space. */\
|
||||
* the first byte as we are pointing to the next free space. */ \
|
||||
MOVFF POSTDEC1, FSR0L \
|
||||
MOVFF POSTDEC1, FSR0L \
|
||||
_endasm \
|
||||
|
|
@ -308,7 +308,7 @@ static void prvLowInterrupt( void );
|
|||
MOVFF POSTDEC1, FSR2L \
|
||||
MOVFF POSTDEC1, BSR \
|
||||
/* The next byte is the INTCON register. Read this into WREG as some \
|
||||
* manipulation is required. */\
|
||||
* manipulation is required. */ \
|
||||
MOVFF POSTDEC1, WREG \
|
||||
_endasm \
|
||||
\
|
||||
|
|
@ -331,7 +331,7 @@ static void prvLowInterrupt( void );
|
|||
MOVFF POSTDEC1, STATUS \
|
||||
MOVFF POSTDEC1, WREG \
|
||||
/* Return without effecting interrupts. The context may have \
|
||||
* been saved from a critical region. */\
|
||||
* been saved from a critical region. */ \
|
||||
RETURN 0 \
|
||||
_endasm \
|
||||
} \
|
||||
|
|
|
|||
|
|
@ -69,15 +69,15 @@ UBaseType_t uxCriticalNesting = 0xef;
|
|||
|
||||
#ifdef __HAS_EDS__
|
||||
#define portRESTORE_CONTEXT() \
|
||||
asm volatile ( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
|
||||
asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
|
||||
"MOV [W0], W15 \n" \
|
||||
"POP W0 \n" /* Restore the critical nesting counter for the task. */ \
|
||||
"POP W0 \n"/* Restore the critical nesting counter for the task. */\
|
||||
"MOV W0, _uxCriticalNesting \n" \
|
||||
"POP DSWPAG \n" \
|
||||
"POP DSRPAG \n" \
|
||||
"POP CORCON \n" \
|
||||
"POP TBLPAG \n" \
|
||||
"POP RCOUNT \n" /* Restore the registers from the stack. */ \
|
||||
"POP RCOUNT \n"/* Restore the registers from the stack. */ \
|
||||
"POP W14 \n" \
|
||||
"POP.D W12 \n" \
|
||||
"POP.D W10 \n" \
|
||||
|
|
@ -89,14 +89,14 @@ UBaseType_t uxCriticalNesting = 0xef;
|
|||
"POP SR ");
|
||||
#else /* __HAS_EDS__ */
|
||||
#define portRESTORE_CONTEXT() \
|
||||
asm volatile ( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
|
||||
asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
|
||||
"MOV [W0], W15 \n" \
|
||||
"POP W0 \n" /* Restore the critical nesting counter for the task. */ \
|
||||
"POP W0 \n"/* Restore the critical nesting counter for the task. */\
|
||||
"MOV W0, _uxCriticalNesting \n" \
|
||||
"POP PSVPAG \n" \
|
||||
"POP CORCON \n" \
|
||||
"POP TBLPAG \n" \
|
||||
"POP RCOUNT \n" /* Restore the registers from the stack. */ \
|
||||
"POP RCOUNT \n"/* Restore the registers from the stack. */ \
|
||||
"POP W14 \n" \
|
||||
"POP.D W12 \n" \
|
||||
"POP.D W10 \n" \
|
||||
|
|
@ -112,9 +112,9 @@ UBaseType_t uxCriticalNesting = 0xef;
|
|||
#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
|
||||
|
||||
#define portRESTORE_CONTEXT() \
|
||||
asm volatile ( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
|
||||
asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
|
||||
"MOV [W0], W15 \n" \
|
||||
"POP W0 \n" /* Restore the critical nesting counter for the task. */ \
|
||||
"POP W0 \n"/* Restore the critical nesting counter for the task. */\
|
||||
"MOV W0, _uxCriticalNesting \n" \
|
||||
"POP PSVPAG \n" \
|
||||
"POP CORCON \n" \
|
||||
|
|
@ -130,7 +130,7 @@ UBaseType_t uxCriticalNesting = 0xef;
|
|||
"POP ACCAH \n" \
|
||||
"POP ACCAL \n" \
|
||||
"POP TBLPAG \n" \
|
||||
"POP RCOUNT \n" /* Restore the registers from the stack. */ \
|
||||
"POP RCOUNT \n"/* Restore the registers from the stack. */ \
|
||||
"POP W14 \n" \
|
||||
"POP.D W12 \n" \
|
||||
"POP.D W10 \n" \
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@
|
|||
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
|
||||
|
||||
/* The application writer has already defined the array used for the RTOS
|
||||
* heap - probably so it can be placed in a special segment or address. */
|
||||
* heap - probably so it can be placed in a special segment or address. */
|
||||
extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
|
||||
#else
|
||||
static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ static void prvHeapInit( void );
|
|||
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
|
||||
|
||||
/* The application writer has already defined the array used for the RTOS
|
||||
* heap - probably so it can be placed in a special segment or address. */
|
||||
* heap - probably so it can be placed in a special segment or address. */
|
||||
extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
|
||||
#else
|
||||
static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@
|
|||
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
|
||||
|
||||
/* The application writer has already defined the array used for the RTOS
|
||||
* heap - probably so it can be placed in a special segment or address. */
|
||||
* heap - probably so it can be placed in a special segment or address. */
|
||||
extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
|
||||
#else
|
||||
static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@
|
|||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
|
||||
\
|
||||
/* Barriers are normally not required but do ensure the code is completely \
|
||||
* within the specified behaviour for the architecture. */\
|
||||
* within the specified behaviour for the architecture. */ \
|
||||
__asm{ dsb }; \
|
||||
__asm{ isb }; \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@
|
|||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
|
||||
\
|
||||
/* Barriers are normally not required but do ensure the code is completely \
|
||||
* within the specified behaviour for the architecture. */\
|
||||
* within the specified behaviour for the architecture. */ \
|
||||
__dsb( portSY_FULL_READ_WRITE ); \
|
||||
__isb( portSY_FULL_READ_WRITE ); \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@
|
|||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
|
||||
\
|
||||
/* Barriers are normally not required but do ensure the code is completely \
|
||||
* within the specified behaviour for the architecture. */\
|
||||
* within the specified behaviour for the architecture. */ \
|
||||
__dsb( portSY_FULL_READ_WRITE ); \
|
||||
__isb( portSY_FULL_READ_WRITE ); \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -129,7 +129,7 @@
|
|||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
|
||||
\
|
||||
/* Barriers are normally not required but do ensure the code is completely \
|
||||
* within the specified behaviour for the architecture. */\
|
||||
* within the specified behaviour for the architecture. */ \
|
||||
__dsb( portSY_FULL_READ_WRITE ); \
|
||||
__isb( portSY_FULL_READ_WRITE ); \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@
|
|||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
|
||||
\
|
||||
/* Barriers are normally not required but do ensure the code is completely \
|
||||
* within the specified behaviour for the architecture. */\
|
||||
* within the specified behaviour for the architecture. */ \
|
||||
__dsb( portSY_FULL_READ_WRITE ); \
|
||||
__isb( portSY_FULL_READ_WRITE ); \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -95,11 +95,11 @@ static void prvSetupTimerInterrupt( void );
|
|||
ucStackBytes = SP - ( configSTACK_START - 1 ); \
|
||||
\
|
||||
/* Before starting to copy the stack, store the calculated stack size so \
|
||||
* the stack can be restored when the task is resumed. */\
|
||||
* the stack can be restored when the task is resumed. */ \
|
||||
* pxXRAMStack = ucStackBytes; \
|
||||
\
|
||||
/* Copy each stack byte in turn. pxXRAMStack is incremented first as we \
|
||||
* have already stored the stack size into XRAM. */\
|
||||
* have already stored the stack size into XRAM. */ \
|
||||
while( ucStackBytes ) \
|
||||
{ \
|
||||
pxXRAMStack ++; \
|
||||
|
|
@ -194,7 +194,7 @@ static void prvSetupTimerInterrupt( void );
|
|||
pop DPL \
|
||||
/* The next byte of the stack is the IE register. Only the global \
|
||||
* enable bit forms part of the task context. Pop off the IE then set \
|
||||
* the global enable bit to match that of the stored IE register. */\
|
||||
* the global enable bit to match that of the stored IE register. */ \
|
||||
pop ACC \
|
||||
JB ACC .7, 00 98$ \
|
||||
CLR IE .7 \
|
||||
|
|
|
|||
|
|
@ -45,53 +45,53 @@
|
|||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* STACK REQUIREMENTS
|
||||
*
|
||||
* This section defines the minimum stack size, and the extra space required to
|
||||
* be allocated for saving coprocessor state and/or C library state information
|
||||
* (if thread safety is enabled for the C library). The sizes are in bytes.
|
||||
*
|
||||
* Stack sizes for individual tasks should be derived from these minima based on
|
||||
* the maximum call depth of the task and the maximum level of interrupt nesting.
|
||||
* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
|
||||
* on the requirement for a task that calls nothing else but can be interrupted.
|
||||
* This assumes that interrupt handlers do not call more than a few levels deep.
|
||||
* If this is not true, i.e. one or more interrupt handlers make deep calls then
|
||||
* the minimum must be increased.
|
||||
*
|
||||
* If the Xtensa processor configuration includes coprocessors, then space is
|
||||
* allocated to save the coprocessor state on the stack.
|
||||
*
|
||||
* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
|
||||
* is defined) then space is allocated to save the C library context in the TCB.
|
||||
*
|
||||
* Allocating insufficient stack space is a common source of hard-to-find errors.
|
||||
* During development, it is best to enable the FreeRTOS stack checking features.
|
||||
*
|
||||
* Usage:
|
||||
*
|
||||
* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
|
||||
* use of the C library. This will require extra stack
|
||||
* space to be allocated for tasks that use the C library
|
||||
* reentrant functions. See below for more information.
|
||||
*
|
||||
* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
|
||||
* support thread safety. Check your core configuration to see which C library
|
||||
* was chosen for your system.
|
||||
*
|
||||
* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended
|
||||
* that you do not use a stack smaller than this for any
|
||||
* task. In case you want to use stacks smaller than this
|
||||
* size, you must verify that the smaller size(s) will work
|
||||
* under all operating conditions.
|
||||
*
|
||||
* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task
|
||||
* that does not make C library reentrant calls. Add this
|
||||
* to the amount of stack space required by the task itself.
|
||||
*
|
||||
* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state.
|
||||
*
|
||||
* -----------------------------------------------------------------------------*/
|
||||
* STACK REQUIREMENTS
|
||||
*
|
||||
* This section defines the minimum stack size, and the extra space required to
|
||||
* be allocated for saving coprocessor state and/or C library state information
|
||||
* (if thread safety is enabled for the C library). The sizes are in bytes.
|
||||
*
|
||||
* Stack sizes for individual tasks should be derived from these minima based on
|
||||
* the maximum call depth of the task and the maximum level of interrupt nesting.
|
||||
* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
|
||||
* on the requirement for a task that calls nothing else but can be interrupted.
|
||||
* This assumes that interrupt handlers do not call more than a few levels deep.
|
||||
* If this is not true, i.e. one or more interrupt handlers make deep calls then
|
||||
* the minimum must be increased.
|
||||
*
|
||||
* If the Xtensa processor configuration includes coprocessors, then space is
|
||||
* allocated to save the coprocessor state on the stack.
|
||||
*
|
||||
* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
|
||||
* is defined) then space is allocated to save the C library context in the TCB.
|
||||
*
|
||||
* Allocating insufficient stack space is a common source of hard-to-find errors.
|
||||
* During development, it is best to enable the FreeRTOS stack checking features.
|
||||
*
|
||||
* Usage:
|
||||
*
|
||||
* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
|
||||
* use of the C library. This will require extra stack
|
||||
* space to be allocated for tasks that use the C library
|
||||
* reentrant functions. See below for more information.
|
||||
*
|
||||
* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
|
||||
* support thread safety. Check your core configuration to see which C library
|
||||
* was chosen for your system.
|
||||
*
|
||||
* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended
|
||||
* that you do not use a stack smaller than this for any
|
||||
* task. In case you want to use stacks smaller than this
|
||||
* size, you must verify that the smaller size(s) will work
|
||||
* under all operating conditions.
|
||||
*
|
||||
* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task
|
||||
* that does not make C library reentrant calls. Add this
|
||||
* to the amount of stack space required by the task itself.
|
||||
*
|
||||
* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state.
|
||||
*
|
||||
* -----------------------------------------------------------------------------*/
|
||||
|
||||
/* Extra space required for interrupt/exception hooks. */
|
||||
#ifdef XT_INTEXC_HOOKS
|
||||
|
|
@ -107,9 +107,9 @@
|
|||
#define XT_CLIB_CONTEXT_AREA_SIZE 0
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Extra size -- interrupt frame plus coprocessor save area plus hook space.
|
||||
* NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
|
||||
* ------------------------------------------------------------------------------*/
|
||||
* Extra size -- interrupt frame plus coprocessor save area plus hook space.
|
||||
* NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
|
||||
* ------------------------------------------------------------------------------*/
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
#define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
|
||||
#else
|
||||
|
|
@ -117,13 +117,13 @@
|
|||
#endif
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Space allocated for user code -- function calls and local variables.
|
||||
* NOTE: This number can be adjusted to suit your needs. You must verify that the
|
||||
* amount of space you reserve is adequate for the worst-case conditions in your
|
||||
* application.
|
||||
* NOTE: The windowed ABI requires more stack, since space has to be reserved
|
||||
* for spilling register windows.
|
||||
* ------------------------------------------------------------------------------*/
|
||||
* Space allocated for user code -- function calls and local variables.
|
||||
* NOTE: This number can be adjusted to suit your needs. You must verify that the
|
||||
* amount of space you reserve is adequate for the worst-case conditions in your
|
||||
* application.
|
||||
* NOTE: The windowed ABI requires more stack, since space has to be reserved
|
||||
* for spilling register windows.
|
||||
* ------------------------------------------------------------------------------*/
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
#define XT_USER_SIZE 0x200
|
||||
#else
|
||||
|
|
|
|||
2
portable/ThirdParty/XCC/Xtensa/portmacro.h
vendored
2
portable/ThirdParty/XCC/Xtensa/portmacro.h
vendored
|
|
@ -109,7 +109,7 @@
|
|||
#define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 )
|
||||
|
||||
/* These can be nested */
|
||||
#define portCRITICAL_NESTING_IN_TCB 1/* For now, let FreeRTOS' (tasks.c) manage critical nesting */
|
||||
#define portCRITICAL_NESTING_IN_TCB 1 /* For now, let FreeRTOS' (tasks.c) manage critical nesting */
|
||||
void vTaskEnterCritical( void );
|
||||
void vTaskExitCritical( void );
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
|
|
|
|||
114
portable/ThirdParty/XCC/Xtensa/xtensa_config.h
vendored
114
portable/ThirdParty/XCC/Xtensa/xtensa_config.h
vendored
|
|
@ -45,53 +45,53 @@
|
|||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* STACK REQUIREMENTS
|
||||
*
|
||||
* This section defines the minimum stack size, and the extra space required to
|
||||
* be allocated for saving coprocessor state and/or C library state information
|
||||
* (if thread safety is enabled for the C library). The sizes are in bytes.
|
||||
*
|
||||
* Stack sizes for individual tasks should be derived from these minima based on
|
||||
* the maximum call depth of the task and the maximum level of interrupt nesting.
|
||||
* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
|
||||
* on the requirement for a task that calls nothing else but can be interrupted.
|
||||
* This assumes that interrupt handlers do not call more than a few levels deep.
|
||||
* If this is not true, i.e. one or more interrupt handlers make deep calls then
|
||||
* the minimum must be increased.
|
||||
*
|
||||
* If the Xtensa processor configuration includes coprocessors, then space is
|
||||
* allocated to save the coprocessor state on the stack.
|
||||
*
|
||||
* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
|
||||
* is defined) then space is allocated to save the C library context in the TCB.
|
||||
*
|
||||
* Allocating insufficient stack space is a common source of hard-to-find errors.
|
||||
* During development, it is best to enable the FreeRTOS stack checking features.
|
||||
*
|
||||
* Usage:
|
||||
*
|
||||
* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
|
||||
* use of the C library. This will require extra stack
|
||||
* space to be allocated for tasks that use the C library
|
||||
* reentrant functions. See below for more information.
|
||||
*
|
||||
* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
|
||||
* support thread safety. Check your core configuration to see which C library
|
||||
* was chosen for your system.
|
||||
*
|
||||
* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended
|
||||
* that you do not use a stack smaller than this for any
|
||||
* task. In case you want to use stacks smaller than this
|
||||
* size, you must verify that the smaller size(s) will work
|
||||
* under all operating conditions.
|
||||
*
|
||||
* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task
|
||||
* that does not make C library reentrant calls. Add this
|
||||
* to the amount of stack space required by the task itself.
|
||||
*
|
||||
* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state.
|
||||
*
|
||||
* -----------------------------------------------------------------------------*/
|
||||
* STACK REQUIREMENTS
|
||||
*
|
||||
* This section defines the minimum stack size, and the extra space required to
|
||||
* be allocated for saving coprocessor state and/or C library state information
|
||||
* (if thread safety is enabled for the C library). The sizes are in bytes.
|
||||
*
|
||||
* Stack sizes for individual tasks should be derived from these minima based on
|
||||
* the maximum call depth of the task and the maximum level of interrupt nesting.
|
||||
* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
|
||||
* on the requirement for a task that calls nothing else but can be interrupted.
|
||||
* This assumes that interrupt handlers do not call more than a few levels deep.
|
||||
* If this is not true, i.e. one or more interrupt handlers make deep calls then
|
||||
* the minimum must be increased.
|
||||
*
|
||||
* If the Xtensa processor configuration includes coprocessors, then space is
|
||||
* allocated to save the coprocessor state on the stack.
|
||||
*
|
||||
* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
|
||||
* is defined) then space is allocated to save the C library context in the TCB.
|
||||
*
|
||||
* Allocating insufficient stack space is a common source of hard-to-find errors.
|
||||
* During development, it is best to enable the FreeRTOS stack checking features.
|
||||
*
|
||||
* Usage:
|
||||
*
|
||||
* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
|
||||
* use of the C library. This will require extra stack
|
||||
* space to be allocated for tasks that use the C library
|
||||
* reentrant functions. See below for more information.
|
||||
*
|
||||
* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
|
||||
* support thread safety. Check your core configuration to see which C library
|
||||
* was chosen for your system.
|
||||
*
|
||||
* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended
|
||||
* that you do not use a stack smaller than this for any
|
||||
* task. In case you want to use stacks smaller than this
|
||||
* size, you must verify that the smaller size(s) will work
|
||||
* under all operating conditions.
|
||||
*
|
||||
* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task
|
||||
* that does not make C library reentrant calls. Add this
|
||||
* to the amount of stack space required by the task itself.
|
||||
*
|
||||
* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state.
|
||||
*
|
||||
* -----------------------------------------------------------------------------*/
|
||||
|
||||
/* Extra space required for interrupt/exception hooks. */
|
||||
#ifdef XT_INTEXC_HOOKS
|
||||
|
|
@ -143,9 +143,9 @@
|
|||
#endif /* if XT_USE_THREAD_SAFE_CLIB > 0u */
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Extra size -- interrupt frame plus coprocessor save area plus hook space.
|
||||
* NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
|
||||
* ------------------------------------------------------------------------------*/
|
||||
* Extra size -- interrupt frame plus coprocessor save area plus hook space.
|
||||
* NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
|
||||
* ------------------------------------------------------------------------------*/
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
#define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
|
||||
#else
|
||||
|
|
@ -153,13 +153,13 @@
|
|||
#endif
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Space allocated for user code -- function calls and local variables.
|
||||
* NOTE: This number can be adjusted to suit your needs. You must verify that the
|
||||
* amount of space you reserve is adequate for the worst-case conditions in your
|
||||
* application.
|
||||
* NOTE: The windowed ABI requires more stack, since space has to be reserved
|
||||
* for spilling register windows.
|
||||
* ------------------------------------------------------------------------------*/
|
||||
* Space allocated for user code -- function calls and local variables.
|
||||
* NOTE: This number can be adjusted to suit your needs. You must verify that the
|
||||
* amount of space you reserve is adequate for the worst-case conditions in your
|
||||
* application.
|
||||
* NOTE: The windowed ABI requires more stack, since space has to be reserved
|
||||
* for spilling register windows.
|
||||
* ------------------------------------------------------------------------------*/
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
#define XT_USER_SIZE 0x200
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -421,3 +421,4 @@ extern void vPortYield( void );
|
|||
#endif /* PORTMACRO_H */
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue