From 2c530ba5c352fdf420d1b13709a3970f04e9e6c6 Mon Sep 17 00:00:00 2001 From: Alfred Gedeon Date: Wed, 1 Jul 2020 22:55:52 -0700 Subject: [PATCH] Style: uncrustify --- croutine.c | 10 +- include/list.h | 10 +- include/queue.h | 2 +- include/timers.h | 4 +- portable/ARMv8M/non_secure/port.c | 56 +-- portable/BCC/16BitDOS/Flsh186/port.c | 2 +- portable/BCC/16BitDOS/PC/port.c | 2 +- portable/BCC/16BitDOS/common/portasm.h | 22 +- portable/CCS/ARM_Cortex-R4/port.c | 4 +- portable/CCS/MSP430X/port.c | 2 +- portable/CodeWarrior/HCS12/port.c | 2 +- portable/Common/mpu_wrappers.c | 98 ++--- portable/GCC/ARM7_AT91FR40008/portmacro.h | 24 +- portable/GCC/ARM7_AT91SAM7S/portISR.c | 2 +- portable/GCC/ARM7_AT91SAM7S/portmacro.h | 24 +- portable/GCC/ARM7_LPC2000/portmacro.h | 24 +- portable/GCC/ARM7_LPC23xx/portISR.c | 2 +- portable/GCC/ARM7_LPC23xx/portmacro.h | 24 +- portable/GCC/ARM_CA9/port.c | 2 +- portable/GCC/ARM_CM23/non_secure/port.c | 56 +-- portable/GCC/ARM_CM23_NTZ/non_secure/port.c | 56 +-- portable/GCC/ARM_CM3/port.c | 18 +- portable/GCC/ARM_CM3/portmacro.h | 6 +- portable/GCC/ARM_CM33/non_secure/port.c | 56 +-- portable/GCC/ARM_CM33_NTZ/non_secure/port.c | 56 +-- portable/GCC/ARM_CM3_MPU/port.c | 34 +- portable/GCC/ARM_CM3_MPU/portmacro.h | 6 +- portable/GCC/ARM_CM4F/port.c | 20 +- portable/GCC/ARM_CM4F/portmacro.h | 6 +- portable/GCC/ARM_CM4_MPU/port.c | 36 +- portable/GCC/ARM_CM4_MPU/portmacro.h | 6 +- portable/GCC/ARM_CM7/r0p1/port.c | 20 +- portable/GCC/ARM_CM7/r0p1/portmacro.h | 6 +- portable/GCC/ATMega323/port.c | 6 +- portable/GCC/AVR32_UC3/port.c | 4 +- portable/GCC/AVR32_UC3/portmacro.h | 410 +++++++++--------- portable/GCC/H8S2329/port.c | 2 +- portable/GCC/HCS12/port.c | 2 +- portable/GCC/IA32_flat/ISR_Support.h | 4 +- portable/GCC/IA32_flat/port.c | 2 +- portable/GCC/MCF5235/port.c | 2 +- portable/GCC/MSP430F449/port.c | 2 +- portable/GCC/MicroBlaze/port.c | 2 +- portable/GCC/MicroBlaze/portmacro.h | 6 +- portable/GCC/MicroBlazeV8/port.c | 4 +- portable/GCC/MicroBlazeV8/portmacro.h | 6 +- portable/GCC/MicroBlazeV9/port.c | 4 +- portable/GCC/MicroBlazeV9/portmacro.h | 6 +- ...freertos_risc_v_chip_specific_extensions.h | 4 +- portable/GCC/RISC-V/port.c | 2 +- portable/GCC/RL78/isr_support.h | 2 +- portable/GCC/RX100/port.c | 4 +- portable/GCC/RX600/port.c | 2 +- portable/GCC/RX600v2/port.c | 2 +- portable/GCC/STR75x/portmacro.h | 24 +- portable/GCC/TriCore_1782/portmacro.h | 58 +-- portable/IAR/78K0R/port.c | 2 +- portable/IAR/ARM_CM23/non_secure/port.c | 56 +-- portable/IAR/ARM_CM23_NTZ/non_secure/port.c | 56 +-- portable/IAR/ARM_CM33/non_secure/port.c | 56 +-- portable/IAR/ARM_CM33_NTZ/non_secure/port.c | 56 +-- portable/IAR/ARM_CM4F_MPU/port.c | 26 +- portable/IAR/ATMega323/port.c | 6 +- portable/IAR/AVR32_UC3/port.c | 4 +- portable/IAR/AtmelSAM7S64/port.c | 2 +- portable/IAR/LPC2000/port.c | 2 +- portable/IAR/MSP430X/port.c | 2 +- portable/IAR/RISC-V/port.c | 2 +- portable/IAR/RL78/port.c | 6 +- portable/IAR/RX100/port.c | 4 +- portable/IAR/RX600/port.c | 2 +- portable/IAR/RXv2/port.c | 2 +- portable/IAR/STR91x/port.c | 2 +- portable/IAR/V850ES/port.c | 4 +- portable/MPLAB/PIC18F/port.c | 148 +++---- portable/MPLAB/PIC24_dsPIC/port.c | 126 +++--- portable/MPLAB/PIC32MEC14xx/port.c | 2 +- portable/MPLAB/PIC32MX/port.c | 2 +- portable/MPLAB/PIC32MZ/ISR_Support.h | 6 +- portable/MPLAB/PIC32MZ/port.c | 2 +- portable/MSVC-MingW/port.c | 12 +- portable/MemMang/heap_1.c | 2 +- portable/MemMang/heap_2.c | 2 +- portable/MemMang/heap_4.c | 2 +- portable/MemMang/heap_5.c | 2 +- portable/MikroC/ARM_CM4F/port.c | 18 +- portable/MikroC/ARM_CM4F/portmacro.h | 6 +- .../Paradigm/Tern_EE/large_untested/port.c | 2 +- .../Paradigm/Tern_EE/large_untested/portasm.h | 22 +- portable/Paradigm/Tern_EE/small/port.c | 2 +- portable/RVDS/ARM7_LPC21xx/port.c | 2 +- portable/RVDS/ARM_CA9/port.c | 2 +- portable/RVDS/ARM_CM0/port.c | 16 +- portable/RVDS/ARM_CM3/port.c | 6 +- portable/RVDS/ARM_CM3/portmacro.h | 6 +- portable/RVDS/ARM_CM4F/portmacro.h | 6 +- portable/RVDS/ARM_CM4_MPU/port.c | 40 +- portable/RVDS/ARM_CM4_MPU/portmacro.h | 6 +- portable/RVDS/ARM_CM7/r0p1/portmacro.h | 6 +- portable/Renesas/RX100/port.c | 4 +- portable/Renesas/RX200/port.c | 2 +- portable/Renesas/RX600/port.c | 2 +- portable/Renesas/RX600v2/port.c | 2 +- portable/Renesas/SH2A_FPU/port.c | 6 +- portable/SDCC/Cygnal/port.c | 48 +- portable/Softune/MB91460/port.c | 2 +- portable/Softune/MB96340/port.c | 2 +- .../ThirdParty/GCC/ARC_EM_HS/freertos_tls.c | 2 +- portable/ThirdParty/GCC/ARC_EM_HS/port.c | 14 +- portable/ThirdParty/GCC/ATmega/port.c | 12 +- portable/ThirdParty/GCC/ATmega/portmacro.h | 6 +- .../GCC/Xtensa_ESP32/include/xtensa_config.h | 114 ++--- portable/ThirdParty/GCC/Xtensa_ESP32/port.c | 2 +- .../ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c | 6 +- portable/ThirdParty/XCC/Xtensa/portmacro.h | 2 +- .../ThirdParty/XCC/Xtensa/xtensa_config.h | 114 ++--- portable/ThirdParty/XCC/Xtensa/xtensa_intr.c | 6 +- portable/WizC/PIC18/Drivers/Tick/Tick.c | 2 +- portable/WizC/PIC18/portmacro.h | 3 +- portable/oWatcom/16BitDOS/Flsh186/port.c | 2 +- portable/oWatcom/16BitDOS/PC/port.c | 2 +- queue.c | 34 +- stream_buffer.c | 2 +- tasks.c | 22 +- timers.c | 28 +- 125 files changed, 1218 insertions(+), 1217 deletions(-) diff --git a/croutine.c b/croutine.c index 612793b59..b2784bbd4 100644 --- a/croutine.c +++ b/croutine.c @@ -111,7 +111,7 @@ if( pxCoRoutine ) { /* If pxCurrentCoRoutine is NULL then this is the first co-routine to - * be created and the co-routine data structures need initialising. */ + * be created and the co-routine data structures need initialising. */ if( pxCurrentCoRoutine == NULL ) { pxCurrentCoRoutine = pxCoRoutine; @@ -257,10 +257,10 @@ portDISABLE_INTERRUPTS(); { /* The event could have occurred just before this critical - * section. If this is the case then the generic list item will - * have been moved to the pending ready list and the following - * line is still valid. Also the pvContainer parameter will have - * been set to NULL so the following lines are also valid. */ + * section. If this is the case then the generic list item will + * have been moved to the pending ready list and the following + * line is still valid. Also the pvContainer parameter will have + * been set to NULL so the following lines are also valid. */ ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); /* Is the co-routine waiting on an event also? */ diff --git a/include/list.h b/include/list.h index 12cf53746..0d0db52c8 100644 --- a/include/list.h +++ b/include/list.h @@ -150,7 +150,7 @@ struct xMINI_LIST_ITEM { - listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ configLIST_VOLATILE TickType_t xItemValue; struct xLIST_ITEM * configLIST_VOLATILE pxNext; struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; @@ -162,11 +162,11 @@ */ typedef struct xLIST { - listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ volatile UBaseType_t uxNumberOfItems; - ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ - MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ - listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ } List_t; /* diff --git a/include/queue.h b/include/queue.h index 92d5360dd..cb2d656f2 100644 --- a/include/queue.h +++ b/include/queue.h @@ -1483,7 +1483,7 @@ */ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, - const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ #endif /* diff --git a/include/timers.h b/include/timers.h index 044b0bf5b..26445d42a 100644 --- a/include/timers.h +++ b/include/timers.h @@ -225,7 +225,7 @@ * @endverbatim */ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, @@ -355,7 +355,7 @@ * @endverbatim */ #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) - TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c index 48becec54..37f5d4812 100644 --- a/portable/ARMv8M/non_secure/port.c +++ b/portable/ARMv8M/non_secure/port.c @@ -611,7 +611,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -801,22 +801,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -834,21 +834,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -881,12 +881,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/BCC/16BitDOS/Flsh186/port.c b/portable/BCC/16BitDOS/Flsh186/port.c index 3da59644b..4faed8bf6 100644 --- a/portable/BCC/16BitDOS/Flsh186/port.c +++ b/portable/BCC/16BitDOS/Flsh186/port.c @@ -158,7 +158,7 @@ BaseType_t xPortStartScheduler( void ) /* Reset the PIC ready for the next time. */ portRESET_PIC(); } -#else /* if ( configUSE_PREEMPTION == 1 ) */ +#else /* if ( configUSE_PREEMPTION == 1 ) */ static void __interrupt __far prvNonPreemptiveTick( void ) { /* Same as preemptive tick, but the cooperative scheduler is being used diff --git a/portable/BCC/16BitDOS/PC/port.c b/portable/BCC/16BitDOS/PC/port.c index 61cb5e1d7..b3a31d675 100644 --- a/portable/BCC/16BitDOS/PC/port.c +++ b/portable/BCC/16BitDOS/PC/port.c @@ -179,7 +179,7 @@ BaseType_t xPortStartScheduler( void ) /* Reset the PIC ready for the next time. */ prvPortResetPIC(); } -#else /* if ( configUSE_PREEMPTION == 1 ) */ +#else /* if ( configUSE_PREEMPTION == 1 ) */ static void __interrupt __far prvNonPreemptiveTick( void ) { /* Same as preemptive tick, but the cooperative scheduler is being used diff --git a/portable/BCC/16BitDOS/common/portasm.h b/portable/BCC/16BitDOS/common/portasm.h index 75f421692..5118bcfd2 100644 --- a/portable/BCC/16BitDOS/common/portasm.h +++ b/portable/BCC/16BitDOS/common/portasm.h @@ -51,17 +51,17 @@ void portFIRST_CONTEXT( void ); * debugger). The true stack pointer is then stored in the bp register. We add * 2 to the stack pointer to remove the extra bytes before we restore our context. */ -#define portSWITCH_CONTEXT() \ - asm { mov ax, seg pxCurrentTCB } \ - asm { mov ds, ax } \ - asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ - asm { mov es : 0x2[ bx ], ss } \ - asm { mov es:[ bx ], sp } \ - asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ - asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ - asm { mov ds, ax } \ - asm { les bx, dword ptr pxCurrentTCB } \ - asm { mov ss, es:[ bx + 2 ] } \ +#define portSWITCH_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ + asm { mov es : 0x2[ bx ], ss } \ + asm { mov es:[ bx ], sp } \ + asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ + asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ asm { mov sp, es:[ bx ] } #define portFIRST_CONTEXT() \ diff --git a/portable/CCS/ARM_Cortex-R4/port.c b/portable/CCS/ARM_Cortex-R4/port.c index 63c7ac747..ca0ce953b 100644 --- a/portable/CCS/ARM_Cortex-R4/port.c +++ b/portable/CCS/ARM_Cortex-R4/port.c @@ -132,7 +132,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; } - #else /* ifdef portPRELOAD_TASK_REGISTERS */ + #else /* ifdef portPRELOAD_TASK_REGISTERS */ { pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS; } @@ -241,7 +241,7 @@ void vPortEndScheduler( void ) xTaskIncrementTick(); } -#else /* if configUSE_PREEMPTION == 0 */ +#else /* if configUSE_PREEMPTION == 0 */ /* ************************************************************************** diff --git a/portable/CCS/MSP430X/port.c b/portable/CCS/MSP430X/port.c index 366b9f530..9a9115607 100644 --- a/portable/CCS/MSP430X/port.c +++ b/portable/CCS/MSP430X/port.c @@ -137,7 +137,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x4444; pxTopOfStack--; - #else /* ifdef PRELOAD_REGISTER_VALUES */ + #else /* ifdef PRELOAD_REGISTER_VALUES */ pxTopOfStack -= 3; *pxTopOfStack = ( StackType_t ) pvParameters; pxTopOfStack -= 9; diff --git a/portable/CodeWarrior/HCS12/port.c b/portable/CodeWarrior/HCS12/port.c index 881d07a0a..acdef63e9 100644 --- a/portable/CodeWarrior/HCS12/port.c +++ b/portable/CodeWarrior/HCS12/port.c @@ -225,7 +225,7 @@ void interrupt vPortTickInterrupt( void ) * to that interrupted. */ portRESTORE_CONTEXT(); } - #else /* if configUSE_PREEMPTION == 1 */ + #else /* if configUSE_PREEMPTION == 1 */ { xTaskIncrementTick(); TFLG1 = 1; diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c index c7e0da08e..8dcb89d1b 100644 --- a/portable/Common/mpu_wrappers.c +++ b/portable/Common/mpu_wrappers.c @@ -87,7 +87,7 @@ void vPortResetPrivilege( BaseType_t xRunningPrivileged ) #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, - TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */ + TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -101,7 +101,7 @@ void vPortResetPrivilege( BaseType_t xRunningPrivileged ) #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, - TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */ + TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -119,7 +119,7 @@ void vPortResetPrivilege( BaseType_t xRunningPrivileged ) uint16_t usStackDepth, void * pvParameters, UBaseType_t uxPriority, - TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */ + TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -138,7 +138,7 @@ void vPortResetPrivilege( BaseType_t xRunningPrivileged ) void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, - StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */ + StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */ { TaskHandle_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -151,7 +151,7 @@ void vPortResetPrivilege( BaseType_t xRunningPrivileged ) /*-----------------------------------------------------------*/ void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, - const MemoryRegion_t * const xRegions ) /* FREERTOS_SYSTEM_CALL */ + const MemoryRegion_t * const xRegions ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -173,7 +173,7 @@ void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, #if ( INCLUDE_vTaskDelayUntil == 1 ) void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, - TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -222,7 +222,7 @@ void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, #if ( INCLUDE_vTaskPrioritySet == 1 ) void MPU_vTaskPrioritySet( TaskHandle_t pxTask, - UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */ + UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -249,7 +249,7 @@ void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t * pxTaskStatus, BaseType_t xGetFreeStackSpace, - eTaskState eState ) /* FREERTOS_SYSTEM_CALL */ + eTaskState eState ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -397,7 +397,7 @@ char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */ #if ( configUSE_APPLICATION_TASK_TAG == 1 ) void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, - TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */ + TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -423,7 +423,7 @@ char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */ #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, - void * pvValue ) /* FREERTOS_SYSTEM_CALL */ + void * pvValue ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -435,7 +435,7 @@ char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */ #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, - BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */ + BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */ { void * pvReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -449,7 +449,7 @@ char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */ #if ( configUSE_APPLICATION_TASK_TAG == 1 ) BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, - void * pvParameter ) /* FREERTOS_SYSTEM_CALL */ + void * pvParameter ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -464,7 +464,7 @@ char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */ #if ( configUSE_TRACE_FACILITY == 1 ) UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * pxTaskStatusArray, UBaseType_t uxArraySize, - uint32_t * pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */ + uint32_t * pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */ { UBaseType_t uxReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -549,7 +549,7 @@ void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_ /*-----------------------------------------------------------*/ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, - TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -565,7 +565,7 @@ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, - uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */ + uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -582,7 +582,7 @@ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t * pulNotificationValue, - TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -597,7 +597,7 @@ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, #if ( configUSE_TASK_NOTIFICATIONS == 1 ) uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, - TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { uint32_t ulReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -611,7 +611,7 @@ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, #if ( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, - UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */ + UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -626,7 +626,7 @@ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, #if ( configUSE_TASK_NOTIFICATIONS == 1 ) uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, UBaseType_t uxIndexToClear, - uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */ + uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */ { uint32_t ulReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -641,7 +641,7 @@ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, - uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */ + uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */ { QueueHandle_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -658,7 +658,7 @@ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, const UBaseType_t uxItemSize, uint8_t * pucQueueStorage, StaticQueue_t * pxStaticQueue, - const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */ + const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */ { QueueHandle_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -671,7 +671,7 @@ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, /*-----------------------------------------------------------*/ BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, - BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */ + BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -685,7 +685,7 @@ BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, - BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */ + BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -720,7 +720,7 @@ UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, void * const pvBuffer, - TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); BaseType_t xReturn; @@ -733,7 +733,7 @@ BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, - TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); BaseType_t xReturn; @@ -745,7 +745,7 @@ BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, /*-----------------------------------------------------------*/ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, - TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); BaseType_t xReturn; @@ -784,7 +784,7 @@ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, - StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */ + StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */ { QueueHandle_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -798,7 +798,7 @@ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, - UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */ + UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */ { QueueHandle_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -814,7 +814,7 @@ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, - StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */ + StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */ { QueueHandle_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -828,7 +828,7 @@ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, - TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -868,7 +868,7 @@ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, #if ( configUSE_QUEUE_SETS == 1 ) QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, - TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */ { QueueSetMemberHandle_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -882,7 +882,7 @@ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, #if ( configUSE_QUEUE_SETS == 1 ) BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, - QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */ + QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -896,7 +896,7 @@ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, #if ( configUSE_QUEUE_SETS == 1 ) BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, - QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */ + QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -910,7 +910,7 @@ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, #if configQUEUE_REGISTRY_SIZE > 0 void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, - const char * pcName ) /* FREERTOS_SYSTEM_CALL */ + const char * pcName ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1016,7 +1016,7 @@ void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, - TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */ + TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */ { TimerHandle_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1035,7 +1035,7 @@ void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, - StaticTimer_t * pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */ + StaticTimer_t * pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */ { TimerHandle_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1064,7 +1064,7 @@ void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ #if ( configUSE_TIMERS == 1 ) void MPU_vTimerSetTimerID( TimerHandle_t xTimer, - void * pvNewID ) /* FREERTOS_SYSTEM_CALL */ + void * pvNewID ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1106,7 +1106,7 @@ void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void * pvParameter1, uint32_t ulParameter2, - TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1121,7 +1121,7 @@ void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ #if ( configUSE_TIMERS == 1 ) void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, - const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */ + const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1191,7 +1191,7 @@ void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, - const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1236,7 +1236,7 @@ EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, - TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { EventBits_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1249,7 +1249,7 @@ EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, /*-----------------------------------------------------------*/ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, - const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */ + const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */ { EventBits_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1262,7 +1262,7 @@ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, /*-----------------------------------------------------------*/ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, - const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */ + const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */ { EventBits_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1277,7 +1277,7 @@ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, - TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { EventBits_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1301,7 +1301,7 @@ void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void * pvTxData, size_t xDataLengthBytes, - TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { size_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1328,7 +1328,7 @@ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuff size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void * pvRxData, size_t xBufferLengthBytes, - TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ { size_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1410,7 +1410,7 @@ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* /*-----------------------------------------------------------*/ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, - size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */ + size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */ { BaseType_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1425,7 +1425,7 @@ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, - BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */ + BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */ { StreamBufferHandle_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); @@ -1443,7 +1443,7 @@ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, - StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ { StreamBufferHandle_t xReturn; BaseType_t xRunningPrivileged = xPortRaisePrivilege(); diff --git a/portable/GCC/ARM7_AT91FR40008/portmacro.h b/portable/GCC/ARM7_AT91FR40008/portmacro.h index 180c9cf2a..472e085d4 100644 --- a/portable/GCC/ARM7_AT91FR40008/portmacro.h +++ b/portable/GCC/ARM7_AT91FR40008/portmacro.h @@ -216,20 +216,20 @@ #else - #define portDISABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */\ - "MRS R0, CPSR \n\t" /* Get CPSR. */\ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\ - "MSR CPSR, R0 \n\t" /* Write back modified value. */\ + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t"/* Push R0. */\ + "MRS R0, CPSR \n\t"/* Get CPSR. */\ + "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\ + "MSR CPSR, R0 \n\t"/* Write back modified value. */\ "LDMIA SP!, {R0} ") /* Pop R0. */ - #define portENABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */\ - "MRS R0, CPSR \n\t" /* Get CPSR. */\ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\ - "MSR CPSR, R0 \n\t" /* Write back modified value. */\ + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t"/* Push R0. */\ + "MRS R0, CPSR \n\t"/* Get CPSR. */\ + "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\ + "MSR CPSR, R0 \n\t"/* Write back modified value. */\ "LDMIA SP!, {R0} ") /* Pop R0. */ #endif /* THUMB_INTERWORK */ diff --git a/portable/GCC/ARM7_AT91SAM7S/portISR.c b/portable/GCC/ARM7_AT91SAM7S/portISR.c index 0b464da26..7eb0efa59 100644 --- a/portable/GCC/ARM7_AT91SAM7S/portISR.c +++ b/portable/GCC/ARM7_AT91SAM7S/portISR.c @@ -124,7 +124,7 @@ void vPortYieldProcessor( void ) AT91C_BASE_AIC->AIC_EOICR = ulDummy; } -#else /* if configUSE_PREEMPTION == 0 */ +#else /* if configUSE_PREEMPTION == 0 */ /* The preemptive scheduler is defined as "naked" as the full context is * saved on entry as part of the context switch. */ diff --git a/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/portable/GCC/ARM7_AT91SAM7S/portmacro.h index 138c439e1..3a97f811c 100644 --- a/portable/GCC/ARM7_AT91SAM7S/portmacro.h +++ b/portable/GCC/ARM7_AT91SAM7S/portmacro.h @@ -211,20 +211,20 @@ #else - #define portDISABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */\ - "MRS R0, CPSR \n\t" /* Get CPSR. */\ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\ - "MSR CPSR, R0 \n\t" /* Write back modified value. */\ + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t"/* Push R0. */\ + "MRS R0, CPSR \n\t"/* Get CPSR. */\ + "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\ + "MSR CPSR, R0 \n\t"/* Write back modified value. */\ "LDMIA SP!, {R0} ") /* Pop R0. */ - #define portENABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */\ - "MRS R0, CPSR \n\t" /* Get CPSR. */\ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\ - "MSR CPSR, R0 \n\t" /* Write back modified value. */\ + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t"/* Push R0. */\ + "MRS R0, CPSR \n\t"/* Get CPSR. */\ + "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\ + "MSR CPSR, R0 \n\t"/* Write back modified value. */\ "LDMIA SP!, {R0} ") /* Pop R0. */ #endif /* THUMB_INTERWORK */ diff --git a/portable/GCC/ARM7_LPC2000/portmacro.h b/portable/GCC/ARM7_LPC2000/portmacro.h index 0d701bca6..327f42609 100644 --- a/portable/GCC/ARM7_LPC2000/portmacro.h +++ b/portable/GCC/ARM7_LPC2000/portmacro.h @@ -188,20 +188,20 @@ #else - #define portDISABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */\ - "MRS R0, CPSR \n\t" /* Get CPSR. */\ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\ - "MSR CPSR, R0 \n\t" /* Write back modified value. */\ + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t"/* Push R0. */\ + "MRS R0, CPSR \n\t"/* Get CPSR. */\ + "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\ + "MSR CPSR, R0 \n\t"/* Write back modified value. */\ "LDMIA SP!, {R0} ") /* Pop R0. */ - #define portENABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */\ - "MRS R0, CPSR \n\t" /* Get CPSR. */\ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\ - "MSR CPSR, R0 \n\t" /* Write back modified value. */\ + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t"/* Push R0. */\ + "MRS R0, CPSR \n\t"/* Get CPSR. */\ + "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\ + "MSR CPSR, R0 \n\t"/* Write back modified value. */\ "LDMIA SP!, {R0} ") /* Pop R0. */ #endif /* THUMB_INTERWORK */ diff --git a/portable/GCC/ARM7_LPC23xx/portISR.c b/portable/GCC/ARM7_LPC23xx/portISR.c index 25918a8c4..551b0ba10 100644 --- a/portable/GCC/ARM7_LPC23xx/portISR.c +++ b/portable/GCC/ARM7_LPC23xx/portISR.c @@ -107,7 +107,7 @@ void vPortYieldProcessor( void ) VICVectAddr = portCLEAR_VIC_INTERRUPT; } -#else /* if configUSE_PREEMPTION == 0 */ +#else /* if configUSE_PREEMPTION == 0 */ /* The preemptive scheduler is defined as "naked" as the full context is * saved on entry as part of the context switch. */ diff --git a/portable/GCC/ARM7_LPC23xx/portmacro.h b/portable/GCC/ARM7_LPC23xx/portmacro.h index 138c439e1..3a97f811c 100644 --- a/portable/GCC/ARM7_LPC23xx/portmacro.h +++ b/portable/GCC/ARM7_LPC23xx/portmacro.h @@ -211,20 +211,20 @@ #else - #define portDISABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */\ - "MRS R0, CPSR \n\t" /* Get CPSR. */\ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\ - "MSR CPSR, R0 \n\t" /* Write back modified value. */\ + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t"/* Push R0. */\ + "MRS R0, CPSR \n\t"/* Get CPSR. */\ + "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\ + "MSR CPSR, R0 \n\t"/* Write back modified value. */\ "LDMIA SP!, {R0} ") /* Pop R0. */ - #define portENABLE_INTERRUPTS() \ - __asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */\ - "MRS R0, CPSR \n\t" /* Get CPSR. */\ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\ - "MSR CPSR, R0 \n\t" /* Write back modified value. */\ + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t"/* Push R0. */\ + "MRS R0, CPSR \n\t"/* Get CPSR. */\ + "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\ + "MSR CPSR, R0 \n\t"/* Write back modified value. */\ "LDMIA SP!, {R0} ") /* Pop R0. */ #endif /* THUMB_INTERWORK */ diff --git a/portable/GCC/ARM_CA9/port.c b/portable/GCC/ARM_CA9/port.c index 86066fe17..ca7a7fb88 100644 --- a/portable/GCC/ARM_CA9/port.c +++ b/portable/GCC/ARM_CA9/port.c @@ -298,7 +298,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = pdTRUE; ulPortTaskHasFPUContext = pdTRUE; } - #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */ { #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined. } diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c index 48becec54..37f5d4812 100644 --- a/portable/GCC/ARM_CM23/non_secure/port.c +++ b/portable/GCC/ARM_CM23/non_secure/port.c @@ -611,7 +611,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -801,22 +801,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -834,21 +834,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -881,12 +881,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c index 48becec54..37f5d4812 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c @@ -611,7 +611,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -801,22 +801,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -834,21 +834,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -881,12 +881,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c index e2396a58b..69b832238 100644 --- a/portable/GCC/ARM_CM3/port.c +++ b/portable/GCC/ARM_CM3/port.c @@ -220,11 +220,11 @@ static void prvTaskExitError( void ) void vPortSVCHandler( void ) { __asm volatile ( - " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ - " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ - " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ - " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ - " msr psp, r0 \n" /* Restore the task stack pointer. */ + " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ + " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n"/* Restore the task stack pointer. */ " isb \n" " mov r0, #0 \n" " msr basepri, r0 \n" @@ -240,15 +240,15 @@ void vPortSVCHandler( void ) static void prvPortStartFirstTask( void ) { __asm volatile ( - " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ " ldr r0, [r0] \n" " ldr r0, [r0] \n" - " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ - " cpsie i \n" /* Globally enable interrupts. */ + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ " cpsie f \n" " dsb \n" " isb \n" - " svc 0 \n" /* System call to start first task. */ + " svc 0 \n"/* System call to start first task. */ " nop \n" " .ltorg \n" ); diff --git a/portable/GCC/ARM_CM3/portmacro.h b/portable/GCC/ARM_CM3/portmacro.h index 3bdafe5be..a64b01a0b 100644 --- a/portable/GCC/ARM_CM3/portmacro.h +++ b/portable/GCC/ARM_CM3/portmacro.h @@ -82,9 +82,9 @@ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ - * within the specified behaviour for the architecture. */\ - __asm volatile ( "dsb" ::: "memory" ); \ - __asm volatile ( "isb" ); \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ } #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c index 48becec54..37f5d4812 100644 --- a/portable/GCC/ARM_CM33/non_secure/port.c +++ b/portable/GCC/ARM_CM33/non_secure/port.c @@ -611,7 +611,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -801,22 +801,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -834,21 +834,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -881,12 +881,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c index 48becec54..37f5d4812 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -611,7 +611,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -801,22 +801,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -834,21 +834,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -881,12 +881,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c index 0b492778d..0dc4f573f 100644 --- a/portable/GCC/ARM_CM3_MPU/port.c +++ b/portable/GCC/ARM_CM3_MPU/port.c @@ -294,27 +294,27 @@ static void prvSVCHandler( uint32_t * pulParam ) { __asm volatile ( - " mrs r1, control \n" /* Obtain current control value. */ - " bic r1, #1 \n" /* Set privilege bit. */ - " msr control, r1 \n" /* Write back new control value. */ + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ ::: "r1", "memory" ); } break; - #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ case portSVC_RAISE_PRIVILEGE: __asm volatile ( - " mrs r1, control \n" /* Obtain current control value. */ - " bic r1, #1 \n" /* Set privilege bit. */ - " msr control, r1 \n" /* Write back new control value. */ + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ ::: "r1", "memory" ); break; #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ - default: /* Unknown SVC call. */ + default: /* Unknown SVC call. */ break; } } @@ -453,15 +453,15 @@ BaseType_t xPortStartScheduler( void ) /* Start the first task. */ __asm volatile ( - " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ " ldr r0, [r0] \n" " ldr r0, [r0] \n" - " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ - " cpsie i \n" /* Globally enable interrupts. */ + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ " cpsie f \n" " dsb \n" " isb \n" - " svc %0 \n" /* System call to start first task. */ + " svc %0 \n"/* System call to start first task. */ " nop \n" " .ltorg \n" ::"i" ( portSVC_START_SCHEDULER ) : "memory" ); @@ -730,7 +730,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, { /* No MPU regions are specified so allow access to all RAM. */ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = - ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ ( portMPU_REGION_VALID ) | ( portSTACK_REGION ); @@ -743,7 +743,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have * just removed the privileged only parameters. */ xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress = - ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ ( portMPU_REGION_VALID ) | ( portSTACK_REGION + 1 ); @@ -772,10 +772,10 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = ( ( uint32_t ) pxBottomOfStack ) | ( portMPU_REGION_VALID ) | - ( portSTACK_REGION ); /* Region number. */ + ( portSTACK_REGION ); /* Region number. */ xMPUSettings->xRegion[ 0 ].ulRegionAttribute = - ( portMPU_REGION_READ_WRITE ) | /* Read and write. */ + ( portMPU_REGION_READ_WRITE ) | /* Read and write. */ ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) | ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | ( portMPU_REGION_ENABLE ); @@ -793,7 +793,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | ( portMPU_REGION_VALID ) | - ( portSTACK_REGION + ul ); /* Region number. */ + ( portSTACK_REGION + ul ); /* Region number. */ xMPUSettings->xRegion[ ul ].ulRegionAttribute = ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h index e1b276619..426242014 100644 --- a/portable/GCC/ARM_CM3_MPU/portmacro.h +++ b/portable/GCC/ARM_CM3_MPU/portmacro.h @@ -125,9 +125,9 @@ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ - * within the specified behaviour for the architecture. */\ - __asm volatile ( "dsb" ::: "memory" ); \ - __asm volatile ( "isb" ); \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ } #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c index 41cdd9985..ef1bd2bd8 100644 --- a/portable/GCC/ARM_CM4F/port.c +++ b/portable/GCC/ARM_CM4F/port.c @@ -245,11 +245,11 @@ static void prvTaskExitError( void ) void vPortSVCHandler( void ) { __asm volatile ( - " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ - " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ - " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ - " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ - " msr psp, r0 \n" /* Restore the task stack pointer. */ + " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ + " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n"/* Restore the task stack pointer. */ " isb \n" " mov r0, #0 \n" " msr basepri, r0 \n" @@ -268,17 +268,17 @@ static void prvPortStartFirstTask( void ) * would otherwise result in the unnecessary leaving of space in the SVC stack * for lazy saving of FPU registers. */ __asm volatile ( - " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ " ldr r0, [r0] \n" " ldr r0, [r0] \n" - " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ - " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */ " msr control, r0 \n" - " cpsie i \n" /* Globally enable interrupts. */ + " cpsie i \n"/* Globally enable interrupts. */ " cpsie f \n" " dsb \n" " isb \n" - " svc 0 \n" /* System call to start first task. */ + " svc 0 \n"/* System call to start first task. */ " nop \n" " .ltorg \n" ); diff --git a/portable/GCC/ARM_CM4F/portmacro.h b/portable/GCC/ARM_CM4F/portmacro.h index bee5b4f6c..719f3fd50 100644 --- a/portable/GCC/ARM_CM4F/portmacro.h +++ b/portable/GCC/ARM_CM4F/portmacro.h @@ -82,9 +82,9 @@ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ - * within the specified behaviour for the architecture. */\ - __asm volatile ( "dsb" ::: "memory" ); \ - __asm volatile ( "isb" ); \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ } #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c index eddd0c6b7..ba07a1254 100644 --- a/portable/GCC/ARM_CM4_MPU/port.c +++ b/portable/GCC/ARM_CM4_MPU/port.c @@ -313,27 +313,27 @@ static void prvSVCHandler( uint32_t * pulParam ) { __asm volatile ( - " mrs r1, control \n" /* Obtain current control value. */ - " bic r1, #1 \n" /* Set privilege bit. */ - " msr control, r1 \n" /* Write back new control value. */ + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ ::: "r1", "memory" ); } break; - #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ case portSVC_RAISE_PRIVILEGE: __asm volatile ( - " mrs r1, control \n" /* Obtain current control value. */ - " bic r1, #1 \n" /* Set privilege bit. */ - " msr control, r1 \n" /* Write back new control value. */ + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ ::: "r1", "memory" ); break; #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ - default: /* Unknown SVC call. */ + default: /* Unknown SVC call. */ break; } } @@ -480,17 +480,17 @@ BaseType_t xPortStartScheduler( void ) * would otherwise result in the unnecessary leaving of space in the SVC stack * for lazy saving of FPU registers. */ __asm volatile ( - " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ " ldr r0, [r0] \n" " ldr r0, [r0] \n" - " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ - " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */ " msr control, r0 \n" - " cpsie i \n" /* Globally enable interrupts. */ + " cpsie i \n"/* Globally enable interrupts. */ " cpsie f \n" " dsb \n" " isb \n" - " svc %0 \n" /* System call to start first task. */ + " svc %0 \n"/* System call to start first task. */ " nop \n" " .ltorg \n" ::"i" ( portSVC_START_SCHEDULER ) : "memory" ); @@ -809,7 +809,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, { /* No MPU regions are specified so allow access to all RAM. */ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = - ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ ( portMPU_REGION_VALID ) | ( portSTACK_REGION ); @@ -822,7 +822,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have * just removed the privileged only parameters. */ xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress = - ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ ( portMPU_REGION_VALID ) | ( portSTACK_REGION + 1 ); @@ -851,10 +851,10 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = ( ( uint32_t ) pxBottomOfStack ) | ( portMPU_REGION_VALID ) | - ( portSTACK_REGION ); /* Region number. */ + ( portSTACK_REGION ); /* Region number. */ xMPUSettings->xRegion[ 0 ].ulRegionAttribute = - ( portMPU_REGION_READ_WRITE ) | /* Read and write. */ + ( portMPU_REGION_READ_WRITE ) | /* Read and write. */ ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) | ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | ( portMPU_REGION_ENABLE ); @@ -872,7 +872,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | ( portMPU_REGION_VALID ) | - ( portSTACK_REGION + ul ); /* Region number. */ + ( portSTACK_REGION + ul ); /* Region number. */ xMPUSettings->xRegion[ ul ].ulRegionAttribute = ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h index e1b276619..426242014 100644 --- a/portable/GCC/ARM_CM4_MPU/portmacro.h +++ b/portable/GCC/ARM_CM4_MPU/portmacro.h @@ -125,9 +125,9 @@ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ - * within the specified behaviour for the architecture. */\ - __asm volatile ( "dsb" ::: "memory" ); \ - __asm volatile ( "isb" ); \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ } #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c index 5f8daea6b..d969e5b20 100644 --- a/portable/GCC/ARM_CM7/r0p1/port.c +++ b/portable/GCC/ARM_CM7/r0p1/port.c @@ -239,11 +239,11 @@ static void prvTaskExitError( void ) void vPortSVCHandler( void ) { __asm volatile ( - " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ - " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ - " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ - " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ - " msr psp, r0 \n" /* Restore the task stack pointer. */ + " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ + " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n"/* Restore the task stack pointer. */ " isb \n" " mov r0, #0 \n" " msr basepri, r0 \n" @@ -262,17 +262,17 @@ static void prvPortStartFirstTask( void ) * would otherwise result in the unnecessary leaving of space in the SVC stack * for lazy saving of FPU registers. */ __asm volatile ( - " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ " ldr r0, [r0] \n" " ldr r0, [r0] \n" - " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ - " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */ " msr control, r0 \n" - " cpsie i \n" /* Globally enable interrupts. */ + " cpsie i \n"/* Globally enable interrupts. */ " cpsie f \n" " dsb \n" " isb \n" - " svc 0 \n" /* System call to start first task. */ + " svc 0 \n"/* System call to start first task. */ " nop \n" " .ltorg \n" ); diff --git a/portable/GCC/ARM_CM7/r0p1/portmacro.h b/portable/GCC/ARM_CM7/r0p1/portmacro.h index 725b13dd3..4e336ec58 100644 --- a/portable/GCC/ARM_CM7/r0p1/portmacro.h +++ b/portable/GCC/ARM_CM7/r0p1/portmacro.h @@ -82,9 +82,9 @@ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ - * within the specified behaviour for the architecture. */\ - __asm volatile ( "dsb" ::: "memory" ); \ - __asm volatile ( "isb" ); \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ } #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) diff --git a/portable/GCC/ATMega323/port.c b/portable/GCC/ATMega323/port.c index daad578ce..a84356a55 100644 --- a/portable/GCC/ATMega323/port.c +++ b/portable/GCC/ATMega323/port.c @@ -213,9 +213,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, pxTopOfStack--; /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - * portSAVE_CONTEXT places the flags on the stack immediately after r0 - * to ensure the interrupts get disabled as soon as possible, and so ensuring - * the stack use is minimal should a context switch interrupt occur. */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; diff --git a/portable/GCC/AVR32_UC3/port.c b/portable/GCC/AVR32_UC3/port.c index c3ead1a31..88054e10f 100644 --- a/portable/GCC/AVR32_UC3/port.c +++ b/portable/GCC/AVR32_UC3/port.c @@ -357,7 +357,7 @@ void vPortEndScheduler( void ) Set_system_register( AVR32_COMPARE, lCycles ); } -#else /* if ( configTICK_USE_TC == 0 ) */ +#else /* if ( configTICK_USE_TC == 0 ) */ __attribute__( ( __noinline__ ) ) static void prvClearTcInt( void ) { AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr; @@ -434,7 +434,7 @@ static void prvSetupTimerInterrupt( void ) /* Start the timer/counter. */ tc_start( tc, configTICK_TC_CHANNEL ); } - #else /* if ( configTICK_USE_TC == 1 ) */ + #else /* if ( configTICK_USE_TC == 1 ) */ { INTC_register_interrupt( &vTick, AVR32_CORE_COMPARE_IRQ, INT0 ); prvScheduleFirstTick(); diff --git a/portable/GCC/AVR32_UC3/portmacro.h b/portable/GCC/AVR32_UC3/portmacro.h index 034da6b91..a85e88884 100644 --- a/portable/GCC/AVR32_UC3/portmacro.h +++ b/portable/GCC/AVR32_UC3/portmacro.h @@ -382,122 +382,122 @@ * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. * */ - #define portSAVE_CONTEXT_SCALL() \ - { \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void * volatile pxCurrentTCB; \ - \ - /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ - /* If SR[M2:M0] == 001 */ \ - /* PC and SR are on the stack. */ \ - /* Else (other modes) */ \ - /* Nothing on the stack. */ \ - \ - /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ - /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ - /* in an interrupt|exception handler. */ \ - \ - __asm__ __volatile__ ( \ - /* in order to save R0-R7 */ \ - "sub sp, 6*4 \n\t" \ - /* Save R0..R7 */ \ - "stm --sp, r0-r7 \n\t" \ - \ - /* in order to save R8-R12 and LR */ \ - /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ - "sub r7, sp,-16*4 \n\t" \ - /* Copy PC and SR in other places in the stack. */ \ + #define portSAVE_CONTEXT_SCALL() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ + /* If SR[M2:M0] == 001 */ \ + /* PC and SR are on the stack. */ \ + /* Else (other modes) */ \ + /* Nothing on the stack. */ \ + \ + /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ + /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ + /* in an interrupt|exception handler. */ \ + \ + __asm__ __volatile__ ( \ + /* in order to save R0-R7 */ \ + "sub sp, 6*4 \n\t"\ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* in order to save R8-R12 and LR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp,-16*4 \n\t"\ + /* Copy PC and SR in other places in the stack. */ \ "ld.w r0, r7[-2*4] \n\t"/* Read SR */\ "st.w r7[-8*4], r0 \n\t"/* Copy SR */\ "ld.w r0, r7[-1*4] \n\t"/* Read PC */\ "st.w r7[-7*4], r0 \n\t"/* Copy PC */\ - \ - /* Save R8..R12 and LR on the stack. */ \ - "stm --r7, r8-r12, lr \n\t" \ - \ - /* Arriving here we have the following stack organizations: */ \ - /* R8..R12, LR, PC, SR, R0..R7. */ \ - \ - /* Now we can finalize the save. */ \ - \ - /* Save ulCriticalNesting variable - R0 is overwritten */ \ - "mov r8, LO(%[ulCriticalNesting]) \n\t" \ - "orh r8, HI(%[ulCriticalNesting]) \n\t" \ - "ld.w r0, r8[0] \n\t" \ - "st.w --sp, r0" \ - : \ - :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \ - ); \ - \ - /* Disable the its which may cause a context switch (i.e. cause a change of */ \ - /* pxCurrentTCB). */ \ - /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ - /* critical section because it is a global structure. */ \ - portENTER_CRITICAL(); \ - \ - /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ - __asm__ __volatile__ ( \ - "mov r8, LO(%[pxCurrentTCB]) \n\t" \ - "orh r8, HI(%[pxCurrentTCB]) \n\t" \ - "ld.w r0, r8[0] \n\t" \ - "st.w r0[0], sp" \ - : \ - :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \ - ); \ + \ + /* Save R8..R12 and LR on the stack. */ \ + "stm --r7, r8-r12, lr \n\t"\ + \ + /* Arriving here we have the following stack organizations: */ \ + /* R8..R12, LR, PC, SR, R0..R7. */ \ + \ + /* Now we can finalize the save. */ \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \ + ); \ + \ + /* Disable the its which may cause a context switch (i.e. cause a change of */ \ + /* pxCurrentTCB). */ \ + /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ + /* critical section because it is a global structure. */ \ + portENTER_CRITICAL(); \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + __asm__ __volatile__ ( \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp" \ + : \ + :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \ + ); \ } /* * portRESTORE_CONTEXT() for SupervisorCALL exception. */ - #define portRESTORE_CONTEXT_SCALL() \ - { \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void * volatile pxCurrentTCB; \ - \ - /* Restore all registers */ \ - \ - /* Set SP to point to new stack */ \ - __asm__ __volatile__ ( \ - "mov r8, LO(%[pxCurrentTCB]) \n\t" \ - "orh r8, HI(%[pxCurrentTCB]) \n\t" \ - "ld.w r0, r8[0] \n\t" \ - "ld.w sp, r0[0]" \ - : \ - :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \ - ); \ - \ - /* Leave pxCurrentTCB variable access critical section */ \ - portEXIT_CRITICAL(); \ - \ - __asm__ __volatile__ ( \ - /* Restore ulCriticalNesting variable */ \ - "ld.w r0, sp++ \n\t" \ - "mov r8, LO(%[ulCriticalNesting]) \n\t" \ - "orh r8, HI(%[ulCriticalNesting]) \n\t" \ - "st.w r8[0], r0 \n\t" \ - \ - /* skip PC and SR */ \ - /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ - "sub r7, sp, -10*4 \n\t" \ - /* Restore r8-r12 and LR */ \ - "ldm r7++, r8-r12, lr \n\t" \ - \ - /* RETS will take care of the extra PC and SR restore. */ \ - /* So, we have to prepare the stack for this. */ \ + #define portRESTORE_CONTEXT_SCALL() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + __asm__ __volatile__ ( \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0]" \ + : \ + :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \ + ); \ + \ + /* Leave pxCurrentTCB variable access critical section */ \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* skip PC and SR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp, -10*4 \n\t"\ + /* Restore r8-r12 and LR */ \ + "ldm r7++, r8-r12, lr \n\t"\ + \ + /* RETS will take care of the extra PC and SR restore. */ \ + /* So, we have to prepare the stack for this. */ \ "ld.w r0, r7[-8*4] \n\t"/* Read SR */\ "st.w r7[-2*4], r0 \n\t"/* Copy SR */\ "ld.w r0, r7[-7*4] \n\t"/* Read PC */\ "st.w r7[-1*4], r0 \n\t"/* Copy PC */\ - \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t" \ - \ - "sub sp, -6*4 \n\t" \ - \ - "rets" \ - : \ - :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \ - ); \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + "sub sp, -6*4 \n\t"\ + \ + "rets" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \ + ); \ } @@ -541,115 +541,115 @@ * ISR entry and exit macros. These are only required if a task switch * is required from the ISR. */ - #define portENTER_SWITCHING_ISR() \ - { \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void * volatile pxCurrentTCB; \ - \ - /* When we come here */ \ - /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ - \ - __asm__ __volatile__ ( \ - /* Save R0..R7 */ \ - "stm --sp, r0-r7 \n\t" \ - \ - /* Save ulCriticalNesting variable - R0 is overwritten */ \ - "mov r8, LO(%[ulCriticalNesting]) \n\t" \ - "orh r8, HI(%[ulCriticalNesting]) \n\t" \ - "ld.w r0, r8[0] \n\t" \ - "st.w --sp, r0 \n\t" \ - \ - /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ - /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ - /* level and allow other lower interrupt level to occur). */ \ - /* In this case we don't want to do a task switch because we don't know what the stack */ \ - /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ - /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ - /* will just be restoring the interrupt handler, no way!!! */ \ - /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ - "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \ - "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \ + #define portENTER_SWITCHING_ISR() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0 \n\t" \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */\ "cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\ - "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \ - \ - /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ - "mov r8, LO(%[pxCurrentTCB]) \n\t" \ - "orh r8, HI(%[pxCurrentTCB]) \n\t" \ - "ld.w r0, r8[0] \n\t" \ - "st.w r0[0], sp \n" \ - \ - "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \ - : \ - :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ - [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ - [ LINE ] "i" ( __LINE__ ) \ - ); \ + "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w r0[0], sp \n" \ + \ + "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ LINE ] "i" ( __LINE__ ) \ + ); \ } /* * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 */ - #define portEXIT_SWITCHING_ISR() \ - { \ - extern volatile uint32_t ulCriticalNesting; \ - extern volatile void * volatile pxCurrentTCB; \ - \ - __asm__ __volatile__ ( \ - /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ - /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ - /* level and allow other lower interrupt level to occur). */ \ - /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \ - /* did not previously save SP in its TCB. */ \ - "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \ - "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \ + #define portEXIT_SWITCHING_ISR() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \ + /* did not previously save SP in its TCB. */ \ + "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */\ "cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\ - "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \ - \ - /* If a switch is required then we just need to call */ \ - /* vTaskSwitchContext() as the context has already been */ \ - /* saved. */ \ - "cp.w r12, 1 \n\t"/* Check if Switch context is required. */ \ - "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \ - : \ - :[ LINE ] "i" ( __LINE__ ) \ - ); \ - \ - /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ - portENTER_CRITICAL(); \ - vTaskSwitchContext(); \ - portEXIT_CRITICAL(); \ - \ - __asm__ __volatile__ ( \ - "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t" \ - /* Restore the context of which ever task is now the highest */ \ - /* priority that is ready to run. */ \ - \ - /* Restore all registers */ \ - \ - /* Set SP to point to new stack */ \ - "mov r8, LO(%[pxCurrentTCB]) \n\t" \ - "orh r8, HI(%[pxCurrentTCB]) \n\t" \ - "ld.w r0, r8[0] \n\t" \ - "ld.w sp, r0[0] \n" \ - \ - "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \ - \ - /* Restore ulCriticalNesting variable */ \ - "ld.w r0, sp++ \n\t" \ - "mov r8, LO(%[ulCriticalNesting]) \n\t" \ - "orh r8, HI(%[ulCriticalNesting]) \n\t" \ - "st.w r8[0], r0 \n\t" \ - \ - /* Restore R0..R7 */ \ - "ldm sp++, r0-r7 \n\t" \ - \ - /* Now, the stack should be R8..R12, LR, PC and SR */ \ - "rete" \ - : \ - :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ - [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ - [ LINE ] "i" ( __LINE__ ) \ - ); \ + "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \ + \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + "cp.w r12, 1 \n\t"/* Check if Switch context is required. */\ + "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \ + : \ + :[ LINE ] "i" ( __LINE__ ) \ + ); \ + \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t" \ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n" \ + \ + "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ LINE ] "i" ( __LINE__ ) \ + ); \ } #endif /* if configUSE_PREEMPTION == 0 */ diff --git a/portable/GCC/H8S2329/port.c b/portable/GCC/H8S2329/port.c index ae1677b8d..5a20808d3 100644 --- a/portable/GCC/H8S2329/port.c +++ b/portable/GCC/H8S2329/port.c @@ -259,7 +259,7 @@ void vPortYield( void ) portRESTORE_STACK_POINTER(); } -#else /* if ( configUSE_PREEMPTION == 1 ) */ +#else /* if ( configUSE_PREEMPTION == 1 ) */ /* * The cooperative scheduler is being used so all we have to do is diff --git a/portable/GCC/HCS12/port.c b/portable/GCC/HCS12/port.c index 4c9f3d43c..75817d39a 100644 --- a/portable/GCC/HCS12/port.c +++ b/portable/GCC/HCS12/port.c @@ -227,7 +227,7 @@ void vPortTickInterrupt( void ) * to that interrupted. */ portRESTORE_CONTEXT(); } - #else /* if configUSE_PREEMPTION == 1 */ + #else /* if configUSE_PREEMPTION == 1 */ { xTaskIncrementTick(); } diff --git a/portable/GCC/IA32_flat/ISR_Support.h b/portable/GCC/IA32_flat/ISR_Support.h index 5376b9ccc..01adca2d1 100644 --- a/portable/GCC/IA32_flat/ISR_Support.h +++ b/portable/GCC/IA32_flat/ISR_Support.h @@ -48,14 +48,14 @@ jne 2f movl pucPortTaskFPUContextBuffer, % eax test % eax, % eax je 1f -fnsave( % eax ) /* Save FLOP context into ucTempFPUBuffer array. */ +fnsave( % eax ) /* Save FLOP context into ucTempFPUBuffer array. */ fwait 1 : /* Save the address of the FPU context, if any. */ push pucPortTaskFPUContextBuffer - .endif /* configSUPPORT_FPU */ + .endif /* configSUPPORT_FPU */ /* Find the TCB. */ movl pxCurrentTCB, % eax diff --git a/portable/GCC/IA32_flat/port.c b/portable/GCC/IA32_flat/port.c index 07d4a8684..6f16a6122 100644 --- a/portable/GCC/IA32_flat/port.c +++ b/portable/GCC/IA32_flat/port.c @@ -158,7 +158,7 @@ typedef struct IDTEntry IDTEntry_t; struct IDTPointer { uint16_t usTableLimit; - uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */ + uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */ } __attribute__( ( __packed__ ) ); typedef struct IDTPointer IDTPointer_t; diff --git a/portable/GCC/MCF5235/port.c b/portable/GCC/MCF5235/port.c index b6a006242..647ffd755 100644 --- a/portable/GCC/MCF5235/port.c +++ b/portable/GCC/MCF5235/port.c @@ -197,7 +197,7 @@ static void prvPortYield( void ) MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF; } -#else /* if configUSE_PREEMPTION == 0 */ +#else /* if configUSE_PREEMPTION == 0 */ static void prvPortPreemptiveTick( void ) { diff --git a/portable/GCC/MSP430F449/port.c b/portable/GCC/MSP430F449/port.c index 1735e5c32..9f4607f4c 100644 --- a/portable/GCC/MSP430F449/port.c +++ b/portable/GCC/MSP430F449/port.c @@ -311,7 +311,7 @@ static void prvSetupTimerInterrupt( void ) portRESTORE_CONTEXT(); } -#else /* if configUSE_PREEMPTION == 1 */ +#else /* if configUSE_PREEMPTION == 1 */ /* * Tick ISR for the cooperative scheduler. All this does is increment the diff --git a/portable/GCC/MicroBlaze/port.c b/portable/GCC/MicroBlaze/port.c index 17f3aecaf..9ddca70a3 100644 --- a/portable/GCC/MicroBlaze/port.c +++ b/portable/GCC/MicroBlaze/port.c @@ -104,7 +104,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, pxTopOfStack--; /* First stack an initial value for the critical section nesting. This - * is initialised to zero as tasks are started with interrupts enabled. */ + * is initialised to zero as tasks are started with interrupts enabled. */ *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */ /* Place an initial value for all the general purpose registers. */ diff --git a/portable/GCC/MicroBlaze/portmacro.h b/portable/GCC/MicroBlaze/portmacro.h index c91e85473..f317120e3 100644 --- a/portable/GCC/MicroBlaze/portmacro.h +++ b/portable/GCC/MicroBlaze/portmacro.h @@ -93,9 +93,9 @@ if( uxCriticalNesting == 0 ) \ { \ /* The nesting has unwound and we \ - * can enable interrupts again. */ \ - portENABLE_INTERRUPTS(); \ - } \ + * can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ } /*-----------------------------------------------------------*/ diff --git a/portable/GCC/MicroBlazeV8/port.c b/portable/GCC/MicroBlazeV8/port.c index b41175f6a..38a76d842 100644 --- a/portable/GCC/MicroBlazeV8/port.c +++ b/portable/GCC/MicroBlazeV8/port.c @@ -173,7 +173,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */ pxTopOfStack--; - #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ pxTopOfStack -= 8; #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ @@ -223,7 +223,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ pxTopOfStack -= 13; #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ diff --git a/portable/GCC/MicroBlazeV8/portmacro.h b/portable/GCC/MicroBlazeV8/portmacro.h index 5620b9122..7a80272db 100644 --- a/portable/GCC/MicroBlazeV8/portmacro.h +++ b/portable/GCC/MicroBlazeV8/portmacro.h @@ -97,9 +97,9 @@ if( uxCriticalNesting == 0 ) \ { \ /* The nesting has unwound and we \ - * can enable interrupts again. */ \ - portENABLE_INTERRUPTS(); \ - } \ + * can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ } /*-----------------------------------------------------------*/ diff --git a/portable/GCC/MicroBlazeV9/port.c b/portable/GCC/MicroBlazeV9/port.c index f34b5fd24..d0e16bbee 100644 --- a/portable/GCC/MicroBlazeV9/port.c +++ b/portable/GCC/MicroBlazeV9/port.c @@ -175,7 +175,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */ pxTopOfStack--; - #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ pxTopOfStack -= 8; #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ @@ -225,7 +225,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */ pxTopOfStack--; - #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ pxTopOfStack -= 13; #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ diff --git a/portable/GCC/MicroBlazeV9/portmacro.h b/portable/GCC/MicroBlazeV9/portmacro.h index 5620b9122..7a80272db 100644 --- a/portable/GCC/MicroBlazeV9/portmacro.h +++ b/portable/GCC/MicroBlazeV9/portmacro.h @@ -97,9 +97,9 @@ if( uxCriticalNesting == 0 ) \ { \ /* The nesting has unwound and we \ - * can enable interrupts again. */ \ - portENABLE_INTERRUPTS(); \ - } \ + * can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ } /*-----------------------------------------------------------*/ diff --git a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h index 04579126a..cc7f05fa3 100644 --- a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h +++ b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h @@ -90,7 +90,7 @@ sw t5, 6 * portWORD_SIZE( sp ) /* Restore the additional registers found on the Pulpino. */ .macro portasmRESTORE_ADDITIONAL_REGISTERS -lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */ +lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */ lw t1, 2 * portWORD_SIZE( sp ) lw t2, 3 * portWORD_SIZE( sp ) lw t3, 4 * portWORD_SIZE( sp ) @@ -102,7 +102,7 @@ csrw lpcount0, t2 csrw lpstart1, t3 csrw lpend1, t4 csrw lpcount1, t5 -addi sp, sp, ( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Remove space added for additional registers. */ +addi sp, sp, ( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Remove space added for additional registers. */ .endm #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/portable/GCC/RISC-V/port.c b/portable/GCC/RISC-V/port.c index 12f3b1236..3ce5490f0 100644 --- a/portable/GCC/RISC-V/port.c +++ b/portable/GCC/RISC-V/port.c @@ -110,7 +110,7 @@ volatile uint64_t * pullMachineTimerCompareRegister = NULL; }; \ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) -#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ +#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ /* Define the function away. */ #define portCHECK_ISR_STACK() #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ diff --git a/portable/GCC/RL78/isr_support.h b/portable/GCC/RL78/isr_support.h index 59049a578..b698781de 100644 --- a/portable/GCC/RL78/isr_support.h +++ b/portable/GCC/RL78/isr_support.h @@ -72,7 +72,7 @@ MOVW HL, AX MOVW AX, SP MOVW[ HL ], AX /* Switch stack pointers. */ -movw sp, # _stack /* Set stack pointer */ +movw sp, # _stack /* Set stack pointer */ .endm diff --git a/portable/GCC/RX100/port.c b/portable/GCC/RX100/port.c index d92a156a7..1430bfe22 100644 --- a/portable/GCC/RX100/port.c +++ b/portable/GCC/RX100/port.c @@ -205,7 +205,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { /* Leave space for the registers that will get popped from the stack * when the task first starts executing. */ @@ -487,7 +487,7 @@ static void prvSetupTimerInterrupt( void ) { CMT0.CMCR.BIT.CKS = 0; } - #else /* if portCLOCK_DIVISOR == 512 */ + #else /* if portCLOCK_DIVISOR == 512 */ { #error Invalid portCLOCK_DIVISOR setting } diff --git a/portable/GCC/RX600/port.c b/portable/GCC/RX600/port.c index 5f0e8253f..631ec7c18 100644 --- a/portable/GCC/RX600/port.c +++ b/portable/GCC/RX600/port.c @@ -129,7 +129,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } diff --git a/portable/GCC/RX600v2/port.c b/portable/GCC/RX600v2/port.c index 95cb05adf..20e4fcbbd 100644 --- a/portable/GCC/RX600v2/port.c +++ b/portable/GCC/RX600v2/port.c @@ -129,7 +129,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } diff --git a/portable/GCC/STR75x/portmacro.h b/portable/GCC/STR75x/portmacro.h index d2b522d13..f217eace2 100644 --- a/portable/GCC/STR75x/portmacro.h +++ b/portable/GCC/STR75x/portmacro.h @@ -91,20 +91,20 @@ #else - #define portDISABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */\ - "MRS R0, CPSR \n\t" /* Get CPSR. */\ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\ - "MSR CPSR, R0 \n\t" /* Write back modified value. */\ + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t"/* Push R0. */\ + "MRS R0, CPSR \n\t"/* Get CPSR. */\ + "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\ + "MSR CPSR, R0 \n\t"/* Write back modified value. */\ "LDMIA SP!, {R0} ") /* Pop R0. */ - #define portENABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */\ - "MRS R0, CPSR \n\t" /* Get CPSR. */\ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\ - "MSR CPSR, R0 \n\t" /* Write back modified value. */\ + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t"/* Push R0. */\ + "MRS R0, CPSR \n\t"/* Get CPSR. */\ + "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\ + "MSR CPSR, R0 \n\t"/* Write back modified value. */\ "LDMIA SP!, {R0} ") /* Pop R0. */ #endif /* THUMB_INTERWORK */ diff --git a/portable/GCC/TriCore_1782/portmacro.h b/portable/GCC/TriCore_1782/portmacro.h index 8e887cd15..3ac22ab4e 100644 --- a/portable/GCC/TriCore_1782/portmacro.h +++ b/portable/GCC/TriCore_1782/portmacro.h @@ -109,41 +109,41 @@ /* Critical section management. */ /* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - #define portDISABLE_INTERRUPTS() \ - { \ - uint32_t ulICR; \ - _disable(); \ - ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ - ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ - ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \ - _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ - _isync(); \ - _enable(); \ + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ } /* Clear ICR.CCPN to allow all interrupt priorities. */ - #define portENABLE_INTERRUPTS() \ - { \ - uint32_t ulICR; \ - _disable(); \ - ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ - ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ - _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ - _isync(); \ - _enable(); \ + #define portENABLE_INTERRUPTS() \ + { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ } /* Set ICR.CCPN to uxSavedMaskValue. */ - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) \ - { \ - uint32_t ulICR; \ - _disable(); \ - ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ - ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ - ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \ - _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ - _isync(); \ - _enable(); \ + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) \ + { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ } diff --git a/portable/IAR/78K0R/port.c b/portable/IAR/78K0R/port.c index d2d57e320..396ba5c38 100644 --- a/portable/IAR/78K0R/port.c +++ b/portable/IAR/78K0R/port.c @@ -117,7 +117,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = ( StackType_t ) 0x1111; pxTopOfStack--; } - #else /* if configMEMORY_MODE == 1 */ + #else /* if configMEMORY_MODE == 1 */ { /* Task function address is written to the stack first. As it is * written as a 32bit value a space is left on the stack for the second diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c index 48becec54..37f5d4812 100644 --- a/portable/IAR/ARM_CM23/non_secure/port.c +++ b/portable/IAR/ARM_CM23/non_secure/port.c @@ -611,7 +611,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -801,22 +801,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -834,21 +834,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -881,12 +881,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c index 48becec54..37f5d4812 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c @@ -611,7 +611,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -801,22 +801,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -834,21 +834,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -881,12 +881,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c index 48becec54..37f5d4812 100644 --- a/portable/IAR/ARM_CM33/non_secure/port.c +++ b/portable/IAR/ARM_CM33/non_secure/port.c @@ -611,7 +611,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -801,22 +801,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -834,21 +834,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -881,12 +881,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c index 48becec54..37f5d4812 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c @@ -611,7 +611,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -801,22 +801,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -834,21 +834,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -881,12 +881,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c index 27aa0fd2d..71b06fbac 100644 --- a/portable/IAR/ARM_CM4F_MPU/port.c +++ b/portable/IAR/ARM_CM4F_MPU/port.c @@ -303,27 +303,27 @@ void vPortSVCHandler_C( uint32_t * pulParam ) { __asm volatile ( - " mrs r1, control \n" /* Obtain current control value. */ - " bic r1, r1, #1 \n" /* Set privilege bit. */ - " msr control, r1 \n" /* Write back new control value. */ + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ ::: "r1", "memory" ); } break; - #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ case portSVC_RAISE_PRIVILEGE: __asm volatile ( - " mrs r1, control \n" /* Obtain current control value. */ - " bic r1, r1, #1 \n" /* Set privilege bit. */ - " msr control, r1 \n" /* Write back new control value. */ + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ ::: "r1", "memory" ); break; #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ - default: /* Unknown SVC call. */ + default: /* Unknown SVC call. */ break; } } @@ -620,7 +620,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, { /* No MPU regions are specified so allow access to all RAM. */ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = - ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ ( portMPU_REGION_VALID ) | ( portSTACK_REGION ); @@ -633,7 +633,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have * just removed the privileged only parameters. */ xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress = - ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ ( portMPU_REGION_VALID ) | ( portSTACK_REGION + 1 ); @@ -662,10 +662,10 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = ( ( uint32_t ) pxBottomOfStack ) | ( portMPU_REGION_VALID ) | - ( portSTACK_REGION ); /* Region number. */ + ( portSTACK_REGION ); /* Region number. */ xMPUSettings->xRegion[ 0 ].ulRegionAttribute = - ( portMPU_REGION_READ_WRITE ) | /* Read and write. */ + ( portMPU_REGION_READ_WRITE ) | /* Read and write. */ ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) | ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | ( portMPU_REGION_ENABLE ); @@ -683,7 +683,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | ( portMPU_REGION_VALID ) | - ( portSTACK_REGION + ul ); /* Region number. */ + ( portSTACK_REGION + ul ); /* Region number. */ xMPUSettings->xRegion[ ul ].ulRegionAttribute = ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | diff --git a/portable/IAR/ATMega323/port.c b/portable/IAR/ATMega323/port.c index a3fe92c2c..6837e5427 100644 --- a/portable/IAR/ATMega323/port.c +++ b/portable/IAR/ATMega323/port.c @@ -129,9 +129,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - * portSAVE_CONTEXT places the flags on the stack immediately after r0 - * to ensure the interrupts get disabled as soon as possible, and so ensuring - * the stack use is minimal should a context switch interrupt occur. */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; diff --git a/portable/IAR/AVR32_UC3/port.c b/portable/IAR/AVR32_UC3/port.c index 90d34cba8..60fbb3dc9 100644 --- a/portable/IAR/AVR32_UC3/port.c +++ b/portable/IAR/AVR32_UC3/port.c @@ -329,7 +329,7 @@ void vPortEndScheduler( void ) Set_system_register( AVR32_COMPARE, lCycles ); } -#else /* if ( configTICK_USE_TC == 0 ) */ +#else /* if ( configTICK_USE_TC == 0 ) */ #pragma optimize = no_inline static void prvClearTcInt( void ) { @@ -407,7 +407,7 @@ static void prvSetupTimerInterrupt( void ) /* Start the timer/counter. */ tc_start( tc, configTICK_TC_CHANNEL ); } - #else /* if ( configTICK_USE_TC == 1 ) */ + #else /* if ( configTICK_USE_TC == 1 ) */ { INTC_register_interrupt( ( __int_handler ) & vTick, AVR32_CORE_COMPARE_IRQ, INT0 ); prvScheduleFirstTick(); diff --git a/portable/IAR/AtmelSAM7S64/port.c b/portable/IAR/AtmelSAM7S64/port.c index a52166a4b..dd4b9c626 100644 --- a/portable/IAR/AtmelSAM7S64/port.c +++ b/portable/IAR/AtmelSAM7S64/port.c @@ -189,7 +189,7 @@ void vPortEndScheduler( void ) AT91C_BASE_AIC->AIC_EOICR = ulDummy; } -#else /* if configUSE_PREEMPTION == 0 */ +#else /* if configUSE_PREEMPTION == 0 */ /* Currently the IAR port requires the preemptive tick function to be * defined in an asm file. */ diff --git a/portable/IAR/LPC2000/port.c b/portable/IAR/LPC2000/port.c index 9646283bd..941a8e3a2 100644 --- a/portable/IAR/LPC2000/port.c +++ b/portable/IAR/LPC2000/port.c @@ -205,7 +205,7 @@ void vPortEndScheduler( void ) VICVectAddr = portCLEAR_VIC_INTERRUPT; } -#else /* if configUSE_PREEMPTION == 0 */ +#else /* if configUSE_PREEMPTION == 0 */ /* This function is called from an asm wrapper, so does not require the __irq * keyword. */ diff --git a/portable/IAR/MSP430X/port.c b/portable/IAR/MSP430X/port.c index ead91c4c9..2e2b6953a 100644 --- a/portable/IAR/MSP430X/port.c +++ b/portable/IAR/MSP430X/port.c @@ -138,7 +138,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x4444; pxTopOfStack--; - #else /* ifdef PRELOAD_REGISTER_VALUES */ + #else /* ifdef PRELOAD_REGISTER_VALUES */ pxTopOfStack -= 3; *pxTopOfStack = ( StackType_t ) pvParameters; pxTopOfStack -= 9; diff --git a/portable/IAR/RISC-V/port.c b/portable/IAR/RISC-V/port.c index 0e9abf48c..601e77cc0 100644 --- a/portable/IAR/RISC-V/port.c +++ b/portable/IAR/RISC-V/port.c @@ -110,7 +110,7 @@ volatile uint64_t * pullMachineTimerCompareRegister = NULL; }; \ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) -#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ +#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ /* Define the function away. */ #define portCHECK_ISR_STACK() #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ diff --git a/portable/IAR/RL78/port.c b/portable/IAR/RL78/port.c index 0295db3d3..ddf4057a4 100644 --- a/portable/IAR/RL78/port.c +++ b/portable/IAR/RL78/port.c @@ -102,8 +102,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, uint32_t * pulLocal; /* With large code and large data sizeof( StackType_t ) == 2, and - * sizeof( StackType_t * ) == 4. With small code and small data - * sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */ + * sizeof( StackType_t * ) == 4. With small code and small data + * sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */ #if __DATA_MODEL__ == __DATA_MODEL_FAR__ { @@ -137,7 +137,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = ( StackType_t ) 0x1111; pxTopOfStack--; } - #else /* if __DATA_MODEL__ == __DATA_MODEL_FAR__ */ + #else /* if __DATA_MODEL__ == __DATA_MODEL_FAR__ */ { /* The return address, leaving space for the first two bytes of the * 32-bit value. See the comments above the prvTaskExitError() prototype diff --git a/portable/IAR/RX100/port.c b/portable/IAR/RX100/port.c index 09892ffe8..f444c55c9 100644 --- a/portable/IAR/RX100/port.c +++ b/portable/IAR/RX100/port.c @@ -193,7 +193,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { /* Leave space for the registers that will get popped from the stack * when the task first starts executing. */ @@ -321,7 +321,7 @@ static void prvSetupTimerInterrupt( void ) { CMT0.CMCR.BIT.CKS = 0; } - #else /* if portCLOCK_DIVISOR == 512 */ + #else /* if portCLOCK_DIVISOR == 512 */ { #error Invalid portCLOCK_DIVISOR setting } diff --git a/portable/IAR/RX600/port.c b/portable/IAR/RX600/port.c index 1560eab60..517d77f53 100644 --- a/portable/IAR/RX600/port.c +++ b/portable/IAR/RX600/port.c @@ -115,7 +115,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } diff --git a/portable/IAR/RXv2/port.c b/portable/IAR/RXv2/port.c index 45db1859f..6725acfd7 100644 --- a/portable/IAR/RXv2/port.c +++ b/portable/IAR/RXv2/port.c @@ -115,7 +115,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } diff --git a/portable/IAR/STR91x/port.c b/portable/IAR/STR91x/port.c index bec1a50ca..c3d8409d2 100644 --- a/portable/IAR/STR91x/port.c +++ b/portable/IAR/STR91x/port.c @@ -297,7 +297,7 @@ void vPortEndScheduler( void ) } } -#else /* if configUSE_WATCHDOG_TICK == 1 */ +#else /* if configUSE_WATCHDOG_TICK == 1 */ static void prvFindFactors( u32 n, u8 * a, diff --git a/portable/IAR/V850ES/port.c b/portable/IAR/V850ES/port.c index 51b9d5fad..038a509d5 100644 --- a/portable/IAR/V850ES/port.c +++ b/portable/IAR/V850ES/port.c @@ -72,7 +72,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = ( StackType_t ) 0x24242424; /* Initial Value of R24 */ pxTopOfStack--; #if ( __DATA_MODEL__ == 0 ) || ( __DATA_MODEL__ == 1 ) - *pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 */ + *pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 */ pxTopOfStack--; #endif /* configDATA_MODE */ *pxTopOfStack = ( StackType_t ) 0x26262626; /* Initial Value of R26 */ @@ -116,7 +116,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = ( StackType_t ) 0x55555555; /* Initial Value of R05 */ pxTopOfStack--; #if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1 - *pxTopOfStack = ( StackType_t ) 0x44444444; /* Initial Value of R04 */ + *pxTopOfStack = ( StackType_t ) 0x44444444; /* Initial Value of R04 */ pxTopOfStack--; #endif /* configDATA_MODE */ *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R02 */ diff --git a/portable/MPLAB/PIC18F/port.c b/portable/MPLAB/PIC18F/port.c index 1ef2e115f..15c67a3ed 100644 --- a/portable/MPLAB/PIC18F/port.c +++ b/portable/MPLAB/PIC18F/port.c @@ -146,9 +146,9 @@ static void prvLowInterrupt( void ); { \ _asm \ /* Save the status and WREG registers first, as these will get modified \ - * by the operations below. */\ - MOVFF WREG, PREINC1 \ - MOVFF STATUS, PREINC1 \ + * by the operations below. */ \ + MOVFF WREG, PREINC1 \ + MOVFF STATUS, PREINC1 \ /* Save the INTCON register with the appropriate bits forced if \ * necessary - as described above. */ \ MOVFF INTCON, WREG \ @@ -243,75 +243,75 @@ static void prvLowInterrupt( void ); MOVFF pxCurrentTCB + 1, FSR0H \ \ /* De-reference FSR0 to set the address it holds into FSR1. \ - * (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */\ - MOVFF POSTINC0, FSR1L \ - MOVFF POSTINC0, FSR1H \ - \ + * (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \ + MOVFF POSTINC0, FSR1L \ + MOVFF POSTINC0, FSR1H \ + \ /* How many return addresses are there on the hardware stack? Discard \ - * the first byte as we are pointing to the next free space. */\ - MOVFF POSTDEC1, FSR0L \ - MOVFF POSTDEC1, FSR0L \ - _endasm \ - \ - /* Fill the hardware stack from our software stack. */ \ - STKPTR = 0; \ - \ - while( STKPTR < FSR0L ) \ - { \ - _asm \ - PUSH \ - MOVF POSTDEC1, 0, 0 \ - MOVWF TOSU, 0 \ - MOVF POSTDEC1, 0, 0 \ - MOVWF TOSH, 0 \ - MOVF POSTDEC1, 0, 0 \ - MOVWF TOSL, 0 \ - _endasm \ - } \ - \ - _asm \ - /* Restore the .tmpdata and MATH_DATA memory. */ \ - MOVFF POSTDEC1, FSR0H \ - MOVFF POSTDEC1, FSR0L \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, INDF0 \ - /* Restore the other registers forming the tasks context. */ \ - MOVFF POSTDEC1, PCLATH \ - MOVFF POSTDEC1, PCLATU \ - MOVFF POSTDEC1, PRODL \ - MOVFF POSTDEC1, PRODH \ - MOVFF POSTDEC1, TBLPTRL \ - MOVFF POSTDEC1, TBLPTRH \ - MOVFF POSTDEC1, TBLPTRU \ - MOVFF POSTDEC1, TABLAT \ - MOVFF POSTDEC1, FSR0H \ - MOVFF POSTDEC1, FSR0L \ - MOVFF POSTDEC1, FSR2H \ - MOVFF POSTDEC1, FSR2L \ - MOVFF POSTDEC1, BSR \ + * the first byte as we are pointing to the next free space. */ \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, FSR0L \ + _endasm \ + \ + /* Fill the hardware stack from our software stack. */ \ + STKPTR = 0; \ + \ + while( STKPTR < FSR0L ) \ + { \ + _asm \ + PUSH \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSU, 0 \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSH, 0 \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSL, 0 \ + _endasm \ + } \ + \ + _asm \ + /* Restore the .tmpdata and MATH_DATA memory. */ \ + MOVFF POSTDEC1, FSR0H \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, INDF0 \ + /* Restore the other registers forming the tasks context. */ \ + MOVFF POSTDEC1, PCLATH \ + MOVFF POSTDEC1, PCLATU \ + MOVFF POSTDEC1, PRODL \ + MOVFF POSTDEC1, PRODH \ + MOVFF POSTDEC1, TBLPTRL \ + MOVFF POSTDEC1, TBLPTRH \ + MOVFF POSTDEC1, TBLPTRU \ + MOVFF POSTDEC1, TABLAT \ + MOVFF POSTDEC1, FSR0H \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, FSR2H \ + MOVFF POSTDEC1, FSR2L \ + MOVFF POSTDEC1, BSR \ /* The next byte is the INTCON register. Read this into WREG as some \ - * manipulation is required. */\ - MOVFF POSTDEC1, WREG \ - _endasm \ - \ + * manipulation is required. */ \ + MOVFF POSTDEC1, WREG \ + _endasm \ + \ /* From the INTCON register, only the interrupt enable bits form part \ * of the tasks context. It is perfectly legitimate for another task to \ * have modified any other bits. We therefore only restore the top two bits. \ @@ -331,10 +331,10 @@ static void prvLowInterrupt( void ); MOVFF POSTDEC1, STATUS \ MOVFF POSTDEC1, WREG \ /* Return without effecting interrupts. The context may have \ - * been saved from a critical region. */\ - RETURN 0 \ - _endasm \ - } \ + * been saved from a critical region. */ \ + RETURN 0 \ + _endasm \ + } \ } /*-----------------------------------------------------------*/ diff --git a/portable/MPLAB/PIC24_dsPIC/port.c b/portable/MPLAB/PIC24_dsPIC/port.c index 5279b8ccf..e9e1088b3 100644 --- a/portable/MPLAB/PIC24_dsPIC/port.c +++ b/portable/MPLAB/PIC24_dsPIC/port.c @@ -68,77 +68,77 @@ UBaseType_t uxCriticalNesting = 0xef; #if defined( __PIC24E__ ) || defined( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) #ifdef __HAS_EDS__ - #define portRESTORE_CONTEXT() \ - asm volatile ( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ - "MOV [W0], W15 \n" \ - "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ - "MOV W0, _uxCriticalNesting \n" \ - "POP DSWPAG \n" \ - "POP DSRPAG \n" \ - "POP CORCON \n" \ - "POP TBLPAG \n" \ - "POP RCOUNT \n" /* Restore the registers from the stack. */ \ - "POP W14 \n" \ - "POP.D W12 \n" \ - "POP.D W10 \n" \ - "POP.D W8 \n" \ - "POP.D W6 \n" \ - "POP.D W4 \n" \ - "POP.D W2 \n" \ - "POP.D W0 \n" \ + #define portRESTORE_CONTEXT() \ + asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \ + "MOV [W0], W15 \n" \ + "POP W0 \n"/* Restore the critical nesting counter for the task. */\ + "MOV W0, _uxCriticalNesting \n" \ + "POP DSWPAG \n" \ + "POP DSRPAG \n" \ + "POP CORCON \n" \ + "POP TBLPAG \n" \ + "POP RCOUNT \n"/* Restore the registers from the stack. */ \ + "POP W14 \n" \ + "POP.D W12 \n" \ + "POP.D W10 \n" \ + "POP.D W8 \n" \ + "POP.D W6 \n" \ + "POP.D W4 \n" \ + "POP.D W2 \n" \ + "POP.D W0 \n" \ "POP SR "); #else /* __HAS_EDS__ */ - #define portRESTORE_CONTEXT() \ - asm volatile ( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ - "MOV [W0], W15 \n" \ - "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ - "MOV W0, _uxCriticalNesting \n" \ - "POP PSVPAG \n" \ - "POP CORCON \n" \ - "POP TBLPAG \n" \ - "POP RCOUNT \n" /* Restore the registers from the stack. */ \ - "POP W14 \n" \ - "POP.D W12 \n" \ - "POP.D W10 \n" \ - "POP.D W8 \n" \ - "POP.D W6 \n" \ - "POP.D W4 \n" \ - "POP.D W2 \n" \ - "POP.D W0 \n" \ + #define portRESTORE_CONTEXT() \ + asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \ + "MOV [W0], W15 \n" \ + "POP W0 \n"/* Restore the critical nesting counter for the task. */\ + "MOV W0, _uxCriticalNesting \n" \ + "POP PSVPAG \n" \ + "POP CORCON \n" \ + "POP TBLPAG \n" \ + "POP RCOUNT \n"/* Restore the registers from the stack. */ \ + "POP W14 \n" \ + "POP.D W12 \n" \ + "POP.D W10 \n" \ + "POP.D W8 \n" \ + "POP.D W6 \n" \ + "POP.D W4 \n" \ + "POP.D W2 \n" \ + "POP.D W0 \n" \ "POP SR "); #endif /* __HAS_EDS__ */ #endif /* MPLAB_PIC24_PORT */ #if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) - #define portRESTORE_CONTEXT() \ - asm volatile ( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ - "MOV [W0], W15 \n" \ - "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ - "MOV W0, _uxCriticalNesting \n" \ - "POP PSVPAG \n" \ - "POP CORCON \n" \ - "POP DOENDH \n" \ - "POP DOENDL \n" \ - "POP DOSTARTH \n" \ - "POP DOSTARTL \n" \ - "POP DCOUNT \n" \ - "POP ACCBU \n" \ - "POP ACCBH \n" \ - "POP ACCBL \n" \ - "POP ACCAU \n" \ - "POP ACCAH \n" \ - "POP ACCAL \n" \ - "POP TBLPAG \n" \ - "POP RCOUNT \n" /* Restore the registers from the stack. */ \ - "POP W14 \n" \ - "POP.D W12 \n" \ - "POP.D W10 \n" \ - "POP.D W8 \n" \ - "POP.D W6 \n" \ - "POP.D W4 \n" \ - "POP.D W2 \n" \ - "POP.D W0 \n" \ + #define portRESTORE_CONTEXT() \ + asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \ + "MOV [W0], W15 \n" \ + "POP W0 \n"/* Restore the critical nesting counter for the task. */\ + "MOV W0, _uxCriticalNesting \n" \ + "POP PSVPAG \n" \ + "POP CORCON \n" \ + "POP DOENDH \n" \ + "POP DOENDL \n" \ + "POP DOSTARTH \n" \ + "POP DOSTARTL \n" \ + "POP DCOUNT \n" \ + "POP ACCBU \n" \ + "POP ACCBH \n" \ + "POP ACCBL \n" \ + "POP ACCAU \n" \ + "POP ACCAH \n" \ + "POP ACCAL \n" \ + "POP TBLPAG \n" \ + "POP RCOUNT \n"/* Restore the registers from the stack. */ \ + "POP W14 \n" \ + "POP.D W12 \n" \ + "POP.D W10 \n" \ + "POP.D W8 \n" \ + "POP.D W6 \n" \ + "POP.D W4 \n" \ + "POP.D W2 \n" \ + "POP.D W0 \n" \ "POP SR "); #endif /* MPLAB_DSPIC_PORT */ diff --git a/portable/MPLAB/PIC32MEC14xx/port.c b/portable/MPLAB/PIC32MEC14xx/port.c index 206fba0a8..802e81859 100644 --- a/portable/MPLAB/PIC32MEC14xx/port.c +++ b/portable/MPLAB/PIC32MEC14xx/port.c @@ -123,7 +123,7 @@ }; \ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) -#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ +#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ /* Define the function away. */ #define portCHECK_ISR_STACK() #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ diff --git a/portable/MPLAB/PIC32MX/port.c b/portable/MPLAB/PIC32MX/port.c index ecec3657e..57b6eefed 100644 --- a/portable/MPLAB/PIC32MX/port.c +++ b/portable/MPLAB/PIC32MX/port.c @@ -108,7 +108,7 @@ }; \ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) -#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ +#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ /* Define the function away. */ #define portCHECK_ISR_STACK() #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ diff --git a/portable/MPLAB/PIC32MZ/ISR_Support.h b/portable/MPLAB/PIC32MZ/ISR_Support.h index d8d0d1d45..6a3a968ec 100644 --- a/portable/MPLAB/PIC32MZ/ISR_Support.h +++ b/portable/MPLAB/PIC32MZ/ISR_Support.h @@ -164,7 +164,7 @@ sw k1, portSTATUS_STACK_LOCATION( sp ) /* Prepare to enable interrupts above the current priority. */ srl k0, k0, 0xa ins k1, k0, 10, 7 -srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */ +srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */ ins k1, k0, 18, 1 ins k1, zero, 1, 4 @@ -395,7 +395,7 @@ sw k1, 0 ( k0 ) beq zero, zero, 2f nop - 1 : /* Restore the STATUS and EPC registers */ + 1 : /* Restore the STATUS and EPC registers */ lw k0, portSTATUS_STACK_LOCATION( s5 ) lw k1, portEPC_STACK_LOCATION( s5 ) @@ -404,7 +404,7 @@ sw k1, 0 ( k0 ) add sp, zero, s5 lw s5, 40 ( sp ) - 2 : /* Adjust the stack pointer */ + 2 : /* Adjust the stack pointer */ addiu sp, sp, portCONTEXT_SIZE #else /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */ diff --git a/portable/MPLAB/PIC32MZ/port.c b/portable/MPLAB/PIC32MZ/port.c index ae049949a..e43430a8e 100644 --- a/portable/MPLAB/PIC32MZ/port.c +++ b/portable/MPLAB/PIC32MZ/port.c @@ -130,7 +130,7 @@ }; \ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) -#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ +#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ /* Define the function away. */ #define portCHECK_ISR_STACK() #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c index 6279a2c53..6dd33229d 100644 --- a/portable/MSVC-MingW/port.c +++ b/portable/MSVC-MingW/port.c @@ -461,12 +461,12 @@ static void prvProcessSimulatedInterrupts( void ) SuspendThread( pxThreadState->pvThread ); /* Ensure the thread is actually suspended by performing a - * synchronous operation that can only complete when the thread is - * actually suspended. The below code asks for dummy register - * data. Experimentation shows that these two lines don't appear - * to do anything now, but according to - * https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743 - * they do - so as they do not harm (slight run-time hit). */ + * synchronous operation that can only complete when the thread is + * actually suspended. The below code asks for dummy register + * data. Experimentation shows that these two lines don't appear + * to do anything now, but according to + * https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743 + * they do - so as they do not harm (slight run-time hit). */ xContext.ContextFlags = CONTEXT_INTEGER; ( void ) GetThreadContext( pxThreadState->pvThread, &xContext ); diff --git a/portable/MemMang/heap_1.c b/portable/MemMang/heap_1.c index 769926739..4206b8142 100644 --- a/portable/MemMang/heap_1.c +++ b/portable/MemMang/heap_1.c @@ -55,7 +55,7 @@ #if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) /* The application writer has already defined the array used for the RTOS - * heap - probably so it can be placed in a special segment or address. */ +* heap - probably so it can be placed in a special segment or address. */ extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; #else static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; diff --git a/portable/MemMang/heap_2.c b/portable/MemMang/heap_2.c index 0d0bc4348..fd05a51a3 100644 --- a/portable/MemMang/heap_2.c +++ b/portable/MemMang/heap_2.c @@ -61,7 +61,7 @@ static void prvHeapInit( void ); #if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) /* The application writer has already defined the array used for the RTOS - * heap - probably so it can be placed in a special segment or address. */ +* heap - probably so it can be placed in a special segment or address. */ extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; #else static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c index baf91f846..f4b68b922 100644 --- a/portable/MemMang/heap_4.c +++ b/portable/MemMang/heap_4.c @@ -58,7 +58,7 @@ #if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) /* The application writer has already defined the array used for the RTOS - * heap - probably so it can be placed in a special segment or address. */ +* heap - probably so it can be placed in a special segment or address. */ extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; #else static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c index 1383cbe84..76771ed0d 100644 --- a/portable/MemMang/heap_5.c +++ b/portable/MemMang/heap_5.c @@ -432,7 +432,7 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) if( xDefinedRegions == 0 ) { /* xStart is used to hold a pointer to the first item in the list of - * free blocks. The void cast is used to prevent compiler warnings. */ + * free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap; xStart.xBlockSize = ( size_t ) 0; } diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c index f85900491..2766807ce 100644 --- a/portable/MikroC/ARM_CM4F/port.c +++ b/portable/MikroC/ARM_CM4F/port.c @@ -261,10 +261,10 @@ void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF static void prvPortStartFirstTask( void ) { __asm { - ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */ ldr r0, [ r0 ] ldr r0, [ r0 ] - msr msp, r0 /* Set the msp back to the start of the stack. */ + msr msp, r0 /* Set the msp back to the start of the stack. */ /* Clear the bit that indicates the FPU is in use in case the FPU was used * before the scheduler was started - which would otherwise result in the @@ -272,11 +272,11 @@ static void prvPortStartFirstTask( void ) * registers. */ mov r0, # 0 msr control, r0 - cpsie i /* Globally enable interrupts. */ + cpsie i /* Globally enable interrupts. */ cpsie f dsb isb - svc # 0 /* System call to start first task. */ + svc # 0 /* System call to start first task. */ nop }; } @@ -439,10 +439,10 @@ void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF mrs r0, psp isb - ldr r3, = _pxCurrentTCB /* Get the location of the current TCB. */ + ldr r3, = _pxCurrentTCB /* Get the location of the current TCB. */ ldr r2, [ r3 ] - tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */ it eq vstmdbeq r0 !, ( s16 - s31 ) @@ -461,7 +461,7 @@ void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF msr basepri, r0 ldm sp !, ( r0, r3 ) - ldr r1, [ r3 ] /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [ r3 ] /* The first item in pxCurrentTCB is the task top of stack. */ ldr r0, [ r1 ] ldm r0 !, ( r4 - r11, r14 ) /* Pop the core registers. */ @@ -729,10 +729,10 @@ void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO static void vPortEnableVFP( void ) { __asm { - ldr r0, = 0xE000ED88 /* The FPU enable bits are in the CPACR. */ + ldr r0, = 0xE000ED88 /* The FPU enable bits are in the CPACR. */ ldr r1, [ r0 ] - orr r1, r1, # 0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, # 0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */ str r1, [ r0 ] bx r14 }; diff --git a/portable/MikroC/ARM_CM4F/portmacro.h b/portable/MikroC/ARM_CM4F/portmacro.h index d35fc1b43..09508ce51 100644 --- a/portable/MikroC/ARM_CM4F/portmacro.h +++ b/portable/MikroC/ARM_CM4F/portmacro.h @@ -86,9 +86,9 @@ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ - * within the specified behaviour for the architecture. */\ - __asm{ dsb }; \ - __asm{ isb }; \ + * within the specified behaviour for the architecture. */ \ + __asm{ dsb }; \ + __asm{ isb }; \ } #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) diff --git a/portable/Paradigm/Tern_EE/large_untested/port.c b/portable/Paradigm/Tern_EE/large_untested/port.c index 604ee4f88..487a54792 100644 --- a/portable/Paradigm/Tern_EE/large_untested/port.c +++ b/portable/Paradigm/Tern_EE/large_untested/port.c @@ -187,7 +187,7 @@ static void __interrupt __far prvDummyISR( void ) /* Reset interrupt. */ outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); } -#else /* if ( configUSE_PREEMPTION == 1 ) */ +#else /* if ( configUSE_PREEMPTION == 1 ) */ static void __interrupt __far prvNonPreemptiveTick( void ) { /* Same as preemptive tick, but the cooperative scheduler is being used diff --git a/portable/Paradigm/Tern_EE/large_untested/portasm.h b/portable/Paradigm/Tern_EE/large_untested/portasm.h index 7628f570d..b56cd4cea 100644 --- a/portable/Paradigm/Tern_EE/large_untested/portasm.h +++ b/portable/Paradigm/Tern_EE/large_untested/portasm.h @@ -42,17 +42,17 @@ void portSWITCH_CONTEXT( void ); */ void portFIRST_CONTEXT( void ); -#define portSWITCH_CONTEXT() \ - asm { mov ax, seg pxCurrentTCB } \ - asm { mov ds, ax } \ - asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ - asm { mov es : 0x2[ bx ], ss } \ - asm { mov es:[ bx ], sp } \ - asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ - asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ - asm { mov ds, ax } \ - asm { les bx, dword ptr pxCurrentTCB } \ - asm { mov ss, es:[ bx + 2 ] } \ +#define portSWITCH_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ + asm { mov es : 0x2[ bx ], ss } \ + asm { mov es:[ bx ], sp } \ + asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ + asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ asm { mov sp, es:[ bx ] } #define portFIRST_CONTEXT() \ diff --git a/portable/Paradigm/Tern_EE/small/port.c b/portable/Paradigm/Tern_EE/small/port.c index ab63820c7..8eb6f3bef 100644 --- a/portable/Paradigm/Tern_EE/small/port.c +++ b/portable/Paradigm/Tern_EE/small/port.c @@ -171,7 +171,7 @@ BaseType_t xPortStartScheduler( void ) /* Reset interrupt. */ outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); } -#else /* if ( configUSE_PREEMPTION == 1 ) */ +#else /* if ( configUSE_PREEMPTION == 1 ) */ static void __interrupt __far prvNonPreemptiveTick( void ) { /* Same as preemptive tick, but the cooperative scheduler is being used diff --git a/portable/RVDS/ARM7_LPC21xx/port.c b/portable/RVDS/ARM7_LPC21xx/port.c index ef27a42ec..a8e28e68d 100644 --- a/portable/RVDS/ARM7_LPC21xx/port.c +++ b/portable/RVDS/ARM7_LPC21xx/port.c @@ -196,7 +196,7 @@ void vPortEndScheduler( void ) VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */ } -#else /* if configUSE_PREEMPTION == 0 */ +#else /* if configUSE_PREEMPTION == 0 */ /* ************************************************************************** diff --git a/portable/RVDS/ARM_CA9/port.c b/portable/RVDS/ARM_CA9/port.c index 90bc09af4..9f97f3c1e 100644 --- a/portable/RVDS/ARM_CA9/port.c +++ b/portable/RVDS/ARM_CA9/port.c @@ -92,7 +92,7 @@ #elif configUNIQUE_INTERRUPT_PRIORITIES == 256 #define portPRIORITY_SHIFT 0 #define portMAX_BINARY_POINT_VALUE 0 -#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware #endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ diff --git a/portable/RVDS/ARM_CM0/port.c b/portable/RVDS/ARM_CM0/port.c index e1679abac..48a536da1 100644 --- a/portable/RVDS/ARM_CM0/port.c +++ b/portable/RVDS/ARM_CM0/port.c @@ -187,16 +187,16 @@ __asm void prvPortStartFirstTask( void ) isb pop { r0 - r5 - } /* Pop the registers that are saved automatically. */ + } /* Pop the registers that are saved automatically. */ mov lr, r5 /* lr is now in r5. */ pop { r3 - } /* The return address is now in r3. */ + } /* The return address is now in r3. */ pop { r2 - } /* Pop and discard the XPSR. */ + } /* Pop and discard the XPSR. */ cpsie i /* The first task has its context and interrupts can be enabled. */ - bx r3 /* Finally, jump to the user defined task code. */ + bx r3 /* Finally, jump to the user defined task code. */ ALIGN } @@ -299,7 +299,7 @@ __asm void xPortPendSVHandler( void ) str r0, [ r2 ] /* Save the new top of stack. */ stmia r0 !, { r4 - r7 - } /* Store the low registers that are not saved automatically. */ + } /* Store the low registers that are not saved automatically. */ mov r4, r8 /* Store the high registers. */ mov r5, r9 mov r6, r10 @@ -316,14 +316,14 @@ __asm void xPortPendSVHandler( void ) cpsie i pop { r2, r3 - } /* lr goes in r3. r2 now holds tcb pointer. */ + } /* lr goes in r3. r2 now holds tcb pointer. */ ldr r1, [ r2 ] ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ adds r0, # 16 /* Move to the high registers. */ ldmia r0 !, { r4 - r7 - } /* Pop the high registers. */ + } /* Pop the high registers. */ mov r8, r4 mov r9, r5 mov r10, r6 @@ -334,7 +334,7 @@ __asm void xPortPendSVHandler( void ) subs r0, # 32 /* Go back for the low registers that are not automatically restored. */ ldmia r0 !, { r4 - r7 - } /* Pop low registers. */ + } /* Pop low registers. */ bx r3 ALIGN diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c index 420a06407..e3ba34dbe 100644 --- a/portable/RVDS/ARM_CM3/port.c +++ b/portable/RVDS/ARM_CM3/port.c @@ -219,7 +219,7 @@ __asm void vPortSVCHandler( void ) ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ ldmia r0 !, { r4 - r11 - } /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + } /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ msr psp, r0 /* Restore the task stack pointer. */ isb mov r0, # 0 @@ -397,7 +397,7 @@ __asm void xPortPendSVHandler( void ) stmdb r0 !, { r4 - r11 - } /* Save the remaining registers. */ + } /* Save the remaining registers. */ str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */ stmdb sp !, { @@ -418,7 +418,7 @@ __asm void xPortPendSVHandler( void ) ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ ldmia r0 !, { r4 - r11 - } /* Pop the registers and the critical nesting count. */ + } /* Pop the registers and the critical nesting count. */ msr psp, r0 isb bx r14 diff --git a/portable/RVDS/ARM_CM3/portmacro.h b/portable/RVDS/ARM_CM3/portmacro.h index 8fe7700c2..a44cc7eeb 100644 --- a/portable/RVDS/ARM_CM3/portmacro.h +++ b/portable/RVDS/ARM_CM3/portmacro.h @@ -85,9 +85,9 @@ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ - * within the specified behaviour for the architecture. */\ - __dsb( portSY_FULL_READ_WRITE ); \ - __isb( portSY_FULL_READ_WRITE ); \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ } /*-----------------------------------------------------------*/ diff --git a/portable/RVDS/ARM_CM4F/portmacro.h b/portable/RVDS/ARM_CM4F/portmacro.h index 8fe7700c2..a44cc7eeb 100644 --- a/portable/RVDS/ARM_CM4F/portmacro.h +++ b/portable/RVDS/ARM_CM4F/portmacro.h @@ -85,9 +85,9 @@ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ - * within the specified behaviour for the architecture. */\ - __dsb( portSY_FULL_READ_WRITE ); \ - __isb( portSY_FULL_READ_WRITE ); \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ } /*-----------------------------------------------------------*/ diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c index 99eb5aae2..5bd5d8da2 100644 --- a/portable/RVDS/ARM_CM4_MPU/port.c +++ b/portable/RVDS/ARM_CM4_MPU/port.c @@ -281,25 +281,25 @@ void prvSVCHandler( uint32_t * pulParam ) { __asm { - mrs ulReg, control /* Obtain current control value. */ - bic ulReg, # 1 /* Set privilege bit. */ - msr control, ulReg /* Write back new control value. */ + mrs ulReg, control /* Obtain current control value. */ + bic ulReg, # 1 /* Set privilege bit. */ + msr control, ulReg /* Write back new control value. */ } } break; - #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ case portSVC_RAISE_PRIVILEGE: __asm { - mrs ulReg, control /* Obtain current control value. */ - bic ulReg, # 1 /* Set privilege bit. */ - msr control, ulReg /* Write back new control value. */ + mrs ulReg, control /* Obtain current control value. */ + bic ulReg, # 1 /* Set privilege bit. */ + msr control, ulReg /* Write back new control value. */ } break; #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ - default: /* Unknown SVC call. */ + default: /* Unknown SVC call. */ break; } } @@ -346,10 +346,10 @@ __asm void prvRestoreContextOfFirstTask( void ) ldr r2, = 0xe000ed9c /* Region Base Address register. */ ldmia r1 !, { r4 - r11 - } /* Read 4 sets of MPU registers. */ + } /* Read 4 sets of MPU registers. */ stmia r2 !, { r4 - r11 - } /* Write 4 sets of MPU registers. */ + } /* Write 4 sets of MPU registers. */ ldr r2, = 0xe000ed94 /* MPU_CTRL register. */ ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ @@ -359,7 +359,7 @@ __asm void prvRestoreContextOfFirstTask( void ) ldmia r0 !, { r3 - r11, r14 - } /* Pop the registers that are not automatically saved on exception entry. */ + } /* Pop the registers that are not automatically saved on exception entry. */ msr control, r3 msr psp, r0 /* Restore the task stack pointer. */ mov r0, # 0 @@ -555,7 +555,7 @@ __asm void xPortPendSVHandler( void ) mrs r1, control stmdb r0 !, { r1, r4 - r11, r14 - } /* Save the remaining registers. */ + } /* Save the remaining registers. */ str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */ stmdb sp !, { @@ -585,10 +585,10 @@ __asm void xPortPendSVHandler( void ) ldr r2, = 0xe000ed9c /* Region Base Address register. */ ldmia r1 !, { r4 - r11 - } /* Read 4 sets of MPU registers. */ + } /* Read 4 sets of MPU registers. */ stmia r2 !, { r4 - r11 - } /* Write 4 sets of MPU registers. */ + } /* Write 4 sets of MPU registers. */ ldr r2, = 0xe000ed94 /* MPU_CTRL register. */ ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ @@ -598,7 +598,7 @@ __asm void xPortPendSVHandler( void ) ldmia r0 !, { r3 - r11, r14 - } /* Pop the registers that are not automatically saved on exception entry. */ + } /* Pop the registers that are not automatically saved on exception entry. */ msr control, r3 tst r14, # 0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */ @@ -801,7 +801,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, { /* No MPU regions are specified so allow access to all RAM. */ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = - ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ ( portMPU_REGION_VALID ) | ( portSTACK_REGION ); @@ -814,7 +814,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have * just removed the privileged only parameters. */ xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress = - ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ ( portMPU_REGION_VALID ) | ( portSTACK_REGION + 1 ); @@ -843,10 +843,10 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = ( ( uint32_t ) pxBottomOfStack ) | ( portMPU_REGION_VALID ) | - ( portSTACK_REGION ); /* Region number. */ + ( portSTACK_REGION ); /* Region number. */ xMPUSettings->xRegion[ 0 ].ulRegionAttribute = - ( portMPU_REGION_READ_WRITE ) | /* Read and write. */ + ( portMPU_REGION_READ_WRITE ) | /* Read and write. */ ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) | ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | ( portMPU_REGION_ENABLE ); @@ -864,7 +864,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | ( portMPU_REGION_VALID ) | - ( portSTACK_REGION + ul ); /* Region number. */ + ( portSTACK_REGION + ul ); /* Region number. */ xMPUSettings->xRegion[ ul ].ulRegionAttribute = ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h index 9e574c28f..ae8f6b73c 100644 --- a/portable/RVDS/ARM_CM4_MPU/portmacro.h +++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h @@ -129,9 +129,9 @@ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ - * within the specified behaviour for the architecture. */\ - __dsb( portSY_FULL_READ_WRITE ); \ - __isb( portSY_FULL_READ_WRITE ); \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ } /*-----------------------------------------------------------*/ diff --git a/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/portable/RVDS/ARM_CM7/r0p1/portmacro.h index b0e9817b2..a3eb46eb4 100644 --- a/portable/RVDS/ARM_CM7/r0p1/portmacro.h +++ b/portable/RVDS/ARM_CM7/r0p1/portmacro.h @@ -85,9 +85,9 @@ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ - * within the specified behaviour for the architecture. */\ - __dsb( portSY_FULL_READ_WRITE ); \ - __isb( portSY_FULL_READ_WRITE ); \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ } /*-----------------------------------------------------------*/ diff --git a/portable/Renesas/RX100/port.c b/portable/Renesas/RX100/port.c index 408f3b4cb..7ca0c881c 100644 --- a/portable/Renesas/RX100/port.c +++ b/portable/Renesas/RX100/port.c @@ -212,7 +212,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { /* Leave space for the registers that will get popped from the stack * when the task first starts executing. */ @@ -458,7 +458,7 @@ static void prvSetupTimerInterrupt( void ) { CMT0.CMCR.BIT.CKS = 0; } - #else /* if portCLOCK_DIVISOR == 512 */ + #else /* if portCLOCK_DIVISOR == 512 */ { #error Invalid portCLOCK_DIVISOR setting } diff --git a/portable/Renesas/RX200/port.c b/portable/Renesas/RX200/port.c index 891f3c93f..4b08a283f 100644 --- a/portable/Renesas/RX200/port.c +++ b/portable/Renesas/RX200/port.c @@ -138,7 +138,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } diff --git a/portable/Renesas/RX600/port.c b/portable/Renesas/RX600/port.c index 5c36758f9..b2ef81d77 100644 --- a/portable/Renesas/RX600/port.c +++ b/portable/Renesas/RX600/port.c @@ -135,7 +135,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } diff --git a/portable/Renesas/RX600v2/port.c b/portable/Renesas/RX600v2/port.c index bc4afd684..e64d3d327 100644 --- a/portable/Renesas/RX600v2/port.c +++ b/portable/Renesas/RX600v2/port.c @@ -139,7 +139,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = 0x22222222; pxTopOfStack--; } - #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ { pxTopOfStack -= 15; } diff --git a/portable/Renesas/SH2A_FPU/port.c b/portable/Renesas/SH2A_FPU/port.c index fd20e7032..08a9f1329 100644 --- a/portable/Renesas/SH2A_FPU/port.c +++ b/portable/Renesas/SH2A_FPU/port.c @@ -170,9 +170,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, *pxTopOfStack = ulPortGetGBR(); /* GBR = global base register. - * VBR = vector base register. - * TBR = jump table base register. - * R15 is the stack pointer. */ + * VBR = vector base register. + * TBR = jump table base register. + * R15 is the stack pointer. */ return pxTopOfStack; } diff --git a/portable/SDCC/Cygnal/port.c b/portable/SDCC/Cygnal/port.c index de5b87875..cbdb98489 100644 --- a/portable/SDCC/Cygnal/port.c +++ b/portable/SDCC/Cygnal/port.c @@ -95,18 +95,18 @@ static void prvSetupTimerInterrupt( void ); ucStackBytes = SP - ( configSTACK_START - 1 ); \ \ /* Before starting to copy the stack, store the calculated stack size so \ - * the stack can be restored when the task is resumed. */\ - * pxXRAMStack = ucStackBytes; \ - \ + * the stack can be restored when the task is resumed. */ \ + * pxXRAMStack = ucStackBytes; \ + \ /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \ - * have already stored the stack size into XRAM. */\ - while( ucStackBytes ) \ - { \ - pxXRAMStack ++; \ - * pxXRAMStack = * pxRAMStack; \ - pxRAMStack ++; \ - ucStackBytes --; \ - } \ + * have already stored the stack size into XRAM. */ \ + while( ucStackBytes ) \ + { \ + pxXRAMStack ++; \ + * pxXRAMStack = * pxRAMStack; \ + pxRAMStack ++; \ + ucStackBytes --; \ + } \ } /*-----------------------------------------------------------*/ @@ -194,18 +194,18 @@ static void prvSetupTimerInterrupt( void ); pop DPL \ /* The next byte of the stack is the IE register. Only the global \ * enable bit forms part of the task context. Pop off the IE then set \ - * the global enable bit to match that of the stored IE register. */\ - pop ACC \ - JB ACC .7, 00 98$ \ - CLR IE .7 \ - LJMP 00 99$ \ - 00 98$ : \ - SETB IE .7 \ - 00 99$ : \ - /* Finally pop off the ACC, which was the first register saved. */ \ - pop ACC \ - reti \ - _endasm; \ + * the global enable bit to match that of the stored IE register. */ \ + pop ACC \ + JB ACC .7, 00 98$ \ + CLR IE .7 \ + LJMP 00 99$ \ + 00 98$ : \ + SETB IE .7 \ + 00 99$ : \ + /* Finally pop off the ACC, which was the first register saved. */ \ + pop ACC \ + reti \ + _endasm; \ } /*-----------------------------------------------------------*/ @@ -369,7 +369,7 @@ void vPortYield( void ) _naked portCOPY_XRAM_TO_STACK(); portRESTORE_CONTEXT(); } -#else /* if configUSE_PREEMPTION == 1 */ +#else /* if configUSE_PREEMPTION == 1 */ void vTimer2ISR( void ) interrupt 5 { /* When using the cooperative scheduler the timer 2 ISR is only diff --git a/portable/Softune/MB91460/port.c b/portable/Softune/MB91460/port.c index e19e78aa3..32d00345d 100644 --- a/portable/Softune/MB91460/port.c +++ b/portable/Softune/MB91460/port.c @@ -257,7 +257,7 @@ static void prvSetupTimerInterrupt( void ) #pragma endasm -#else /* if configUSE_PREEMPTION == 1 */ +#else /* if configUSE_PREEMPTION == 1 */ /* * Tick ISR for the cooperative scheduler. All this does is increment the diff --git a/portable/Softune/MB96340/port.c b/portable/Softune/MB96340/port.c index b45b5bcf9..d13f16a82 100644 --- a/portable/Softune/MB96340/port.c +++ b/portable/Softune/MB96340/port.c @@ -443,7 +443,7 @@ void vPortEndScheduler( void ) __EI(); } -#else /* if configUSE_PREEMPTION == 1 */ +#else /* if configUSE_PREEMPTION == 1 */ /* * Tick ISR for the cooperative scheduler. All this does is increment the diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c b/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c index 81635aa84..f838280bd 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c +++ b/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c @@ -231,6 +231,6 @@ } } -#else /* if defined( __MW__ ) */ +#else /* if defined( __MW__ ) */ #endif /* __MW__ */ diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/port.c b/portable/ThirdParty/GCC/ARC_EM_HS/port.c index 4679d5821..9eb326e00 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/port.c +++ b/portable/ThirdParty/GCC/ARC_EM_HS/port.c @@ -203,7 +203,7 @@ void vPortEndTask( void ) volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ #if ( portUSING_MPU_WRAPPERS == 1 ) - xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ + xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ #endif ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ @@ -213,20 +213,20 @@ void vPortEndTask( void ) char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) - StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ + StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ #endif #if ( portCRITICAL_NESTING_IN_TCB == 1 ) - UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ + UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ #endif #if ( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ - UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ + UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ + UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ #endif #if ( configUSE_MUTEXES == 1 ) - UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ + UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ UBaseType_t uxMutexesHeld; #endif @@ -239,7 +239,7 @@ void vPortEndTask( void ) #endif #if ( configGENERATE_RUN_TIME_STATS == 1 ) - uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ + uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ #endif #if ( configUSE_NEWLIB_REENTRANT == 1 ) diff --git a/portable/ThirdParty/GCC/ATmega/port.c b/portable/ThirdParty/GCC/ATmega/port.c index 28e88ba54..4dcaacd32 100644 --- a/portable/ThirdParty/GCC/ATmega/port.c +++ b/portable/ThirdParty/GCC/ATmega/port.c @@ -321,7 +321,7 @@ extern volatile TCB_t * volatile pxCurrentTCB; "in __tmp_reg__, __SP_H__ \n\t" \ "st x+, __tmp_reg__ \n\t" \ ); -#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ +#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ /* 2-Byte PC Save */ #define portSAVE_CONTEXT() \ __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ @@ -467,7 +467,7 @@ extern volatile TCB_t * volatile pxCurrentTCB; "out __SREG__, __tmp_reg__ \n\t" \ "pop __tmp_reg__ \n\t" \ ); -#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ +#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ /* 2-Byte PC Restore */ #define portRESTORE_CONTEXT() \ __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ @@ -559,9 +559,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, #endif /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - * portSAVE_CONTEXT places the flags on the stack immediately after r0 - * to ensure the interrupts get disabled as soon as possible, and so ensuring - * the stack use is minimal should a context switch interrupt occur. */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; @@ -755,7 +755,7 @@ void vPortYieldFromTick( void ) vPortYieldFromTick(); __asm__ __volatile__ ( "reti" ); } -#else /* if configUSE_PREEMPTION == 1 */ +#else /* if configUSE_PREEMPTION == 1 */ /* * Tick ISR for the cooperative scheduler. All this does is increment the diff --git a/portable/ThirdParty/GCC/ATmega/portmacro.h b/portable/ThirdParty/GCC/ATmega/portmacro.h index e22c948b2..c28bff5f9 100644 --- a/portable/ThirdParty/GCC/ATmega/portmacro.h +++ b/portable/ThirdParty/GCC/ATmega/portmacro.h @@ -92,9 +92,9 @@ * Prefer to use the enhanced Watchdog Timer, but also Timer0 is ok. */ - #if defined( WDIE ) && defined( WDIF ) /* If Enhanced WDT with interrupt capability is available */ + #if defined( WDIE ) && defined( WDIF ) /* If Enhanced WDT with interrupt capability is available */ - #define portUSE_WDTO WDTO_15MS /* use the Watchdog Timer for xTaskIncrementTick */ + #define portUSE_WDTO WDTO_15MS /* use the Watchdog Timer for xTaskIncrementTick */ /* Watchdog period options: WDTO_15MS * WDTO_30MS @@ -108,7 +108,7 @@ #else - #define portUSE_TIMER0 /* use the 8-bit Timer0 for xTaskIncrementTick */ + #define portUSE_TIMER0 /* use the 8-bit Timer0 for xTaskIncrementTick */ #endif diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h index abf00f7e0..4ac32d71e 100644 --- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h @@ -45,53 +45,53 @@ /*----------------------------------------------------------------------------- -* STACK REQUIREMENTS -* -* This section defines the minimum stack size, and the extra space required to -* be allocated for saving coprocessor state and/or C library state information -* (if thread safety is enabled for the C library). The sizes are in bytes. -* -* Stack sizes for individual tasks should be derived from these minima based on -* the maximum call depth of the task and the maximum level of interrupt nesting. -* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based -* on the requirement for a task that calls nothing else but can be interrupted. -* This assumes that interrupt handlers do not call more than a few levels deep. -* If this is not true, i.e. one or more interrupt handlers make deep calls then -* the minimum must be increased. -* -* If the Xtensa processor configuration includes coprocessors, then space is -* allocated to save the coprocessor state on the stack. -* -* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB -* is defined) then space is allocated to save the C library context in the TCB. -* -* Allocating insufficient stack space is a common source of hard-to-find errors. -* During development, it is best to enable the FreeRTOS stack checking features. -* -* Usage: -* -* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe -* use of the C library. This will require extra stack -* space to be allocated for tasks that use the C library -* reentrant functions. See below for more information. -* -* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them -* support thread safety. Check your core configuration to see which C library -* was chosen for your system. -* -* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended -* that you do not use a stack smaller than this for any -* task. In case you want to use stacks smaller than this -* size, you must verify that the smaller size(s) will work -* under all operating conditions. -* -* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task -* that does not make C library reentrant calls. Add this -* to the amount of stack space required by the task itself. -* -* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state. -* -* -----------------------------------------------------------------------------*/ + * STACK REQUIREMENTS + * + * This section defines the minimum stack size, and the extra space required to + * be allocated for saving coprocessor state and/or C library state information + * (if thread safety is enabled for the C library). The sizes are in bytes. + * + * Stack sizes for individual tasks should be derived from these minima based on + * the maximum call depth of the task and the maximum level of interrupt nesting. + * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based + * on the requirement for a task that calls nothing else but can be interrupted. + * This assumes that interrupt handlers do not call more than a few levels deep. + * If this is not true, i.e. one or more interrupt handlers make deep calls then + * the minimum must be increased. + * + * If the Xtensa processor configuration includes coprocessors, then space is + * allocated to save the coprocessor state on the stack. + * + * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB + * is defined) then space is allocated to save the C library context in the TCB. + * + * Allocating insufficient stack space is a common source of hard-to-find errors. + * During development, it is best to enable the FreeRTOS stack checking features. + * + * Usage: + * + * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe + * use of the C library. This will require extra stack + * space to be allocated for tasks that use the C library + * reentrant functions. See below for more information. + * + * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them + * support thread safety. Check your core configuration to see which C library + * was chosen for your system. + * + * XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended + * that you do not use a stack smaller than this for any + * task. In case you want to use stacks smaller than this + * size, you must verify that the smaller size(s) will work + * under all operating conditions. + * + * XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task + * that does not make C library reentrant calls. Add this + * to the amount of stack space required by the task itself. + * + * XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state. + * + * -----------------------------------------------------------------------------*/ /* Extra space required for interrupt/exception hooks. */ #ifdef XT_INTEXC_HOOKS @@ -107,9 +107,9 @@ #define XT_CLIB_CONTEXT_AREA_SIZE 0 /*------------------------------------------------------------------------------ -* Extra size -- interrupt frame plus coprocessor save area plus hook space. -* NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. -* ------------------------------------------------------------------------------*/ + * Extra size -- interrupt frame plus coprocessor save area plus hook space. + * NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. + * ------------------------------------------------------------------------------*/ #ifdef __XTENSA_CALL0_ABI__ #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE ) #else @@ -117,13 +117,13 @@ #endif /*------------------------------------------------------------------------------ -* Space allocated for user code -- function calls and local variables. -* NOTE: This number can be adjusted to suit your needs. You must verify that the -* amount of space you reserve is adequate for the worst-case conditions in your -* application. -* NOTE: The windowed ABI requires more stack, since space has to be reserved -* for spilling register windows. -* ------------------------------------------------------------------------------*/ + * Space allocated for user code -- function calls and local variables. + * NOTE: This number can be adjusted to suit your needs. You must verify that the + * amount of space you reserve is adequate for the worst-case conditions in your + * application. + * NOTE: The windowed ABI requires more stack, since space has to be reserved + * for spilling register windows. + * ------------------------------------------------------------------------------*/ #ifdef __XTENSA_CALL0_ABI__ #define XT_USER_SIZE 0x200 #else diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c index 91cb07c52..e4b22b08f 100644 --- a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c @@ -375,7 +375,7 @@ void vPortCPUInitializeMutex( portMUX_TYPE * mux ) return result; } -#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ +#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ void vPortCPUAcquireMutex( portMUX_TYPE * mux ) { unsigned int irqStatus = portENTER_CRITICAL_NESTED(); diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c index 416ec52b4..ee4b7cb90 100644 --- a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c @@ -67,7 +67,7 @@ if( ( n < 0 ) || ( n >= XCHAL_EXCCAUSE_NUM ) ) { - return 0; /* invalid exception number */ + return 0; /* invalid exception number */ } /* Convert exception number to _xt_exception_table name */ @@ -125,12 +125,12 @@ if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) ) { - return 0; /* invalid interrupt number */ + return 0; /* invalid interrupt number */ } if( Xthal_intlevel[ n ] > XCHAL_EXCM_LEVEL ) { - return 0; /* priority level too high to safely handle in C */ + return 0; /* priority level too high to safely handle in C */ } /* Convert exception number to _xt_exception_table name */ diff --git a/portable/ThirdParty/XCC/Xtensa/portmacro.h b/portable/ThirdParty/XCC/Xtensa/portmacro.h index c5b652317..1d7485981 100644 --- a/portable/ThirdParty/XCC/Xtensa/portmacro.h +++ b/portable/ThirdParty/XCC/Xtensa/portmacro.h @@ -109,7 +109,7 @@ #define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 ) /* These can be nested */ - #define portCRITICAL_NESTING_IN_TCB 1/* For now, let FreeRTOS' (tasks.c) manage critical nesting */ + #define portCRITICAL_NESTING_IN_TCB 1 /* For now, let FreeRTOS' (tasks.c) manage critical nesting */ void vTaskEnterCritical( void ); void vTaskExitCritical( void ); #define portENTER_CRITICAL() vTaskEnterCritical() diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h b/portable/ThirdParty/XCC/Xtensa/xtensa_config.h index 5ecbce79d..07b1f911a 100644 --- a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h +++ b/portable/ThirdParty/XCC/Xtensa/xtensa_config.h @@ -45,53 +45,53 @@ /*----------------------------------------------------------------------------- -* STACK REQUIREMENTS -* -* This section defines the minimum stack size, and the extra space required to -* be allocated for saving coprocessor state and/or C library state information -* (if thread safety is enabled for the C library). The sizes are in bytes. -* -* Stack sizes for individual tasks should be derived from these minima based on -* the maximum call depth of the task and the maximum level of interrupt nesting. -* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based -* on the requirement for a task that calls nothing else but can be interrupted. -* This assumes that interrupt handlers do not call more than a few levels deep. -* If this is not true, i.e. one or more interrupt handlers make deep calls then -* the minimum must be increased. -* -* If the Xtensa processor configuration includes coprocessors, then space is -* allocated to save the coprocessor state on the stack. -* -* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB -* is defined) then space is allocated to save the C library context in the TCB. -* -* Allocating insufficient stack space is a common source of hard-to-find errors. -* During development, it is best to enable the FreeRTOS stack checking features. -* -* Usage: -* -* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe -* use of the C library. This will require extra stack -* space to be allocated for tasks that use the C library -* reentrant functions. See below for more information. -* -* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them -* support thread safety. Check your core configuration to see which C library -* was chosen for your system. -* -* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended -* that you do not use a stack smaller than this for any -* task. In case you want to use stacks smaller than this -* size, you must verify that the smaller size(s) will work -* under all operating conditions. -* -* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task -* that does not make C library reentrant calls. Add this -* to the amount of stack space required by the task itself. -* -* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state. -* -* -----------------------------------------------------------------------------*/ + * STACK REQUIREMENTS + * + * This section defines the minimum stack size, and the extra space required to + * be allocated for saving coprocessor state and/or C library state information + * (if thread safety is enabled for the C library). The sizes are in bytes. + * + * Stack sizes for individual tasks should be derived from these minima based on + * the maximum call depth of the task and the maximum level of interrupt nesting. + * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based + * on the requirement for a task that calls nothing else but can be interrupted. + * This assumes that interrupt handlers do not call more than a few levels deep. + * If this is not true, i.e. one or more interrupt handlers make deep calls then + * the minimum must be increased. + * + * If the Xtensa processor configuration includes coprocessors, then space is + * allocated to save the coprocessor state on the stack. + * + * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB + * is defined) then space is allocated to save the C library context in the TCB. + * + * Allocating insufficient stack space is a common source of hard-to-find errors. + * During development, it is best to enable the FreeRTOS stack checking features. + * + * Usage: + * + * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe + * use of the C library. This will require extra stack + * space to be allocated for tasks that use the C library + * reentrant functions. See below for more information. + * + * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them + * support thread safety. Check your core configuration to see which C library + * was chosen for your system. + * + * XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended + * that you do not use a stack smaller than this for any + * task. In case you want to use stacks smaller than this + * size, you must verify that the smaller size(s) will work + * under all operating conditions. + * + * XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task + * that does not make C library reentrant calls. Add this + * to the amount of stack space required by the task itself. + * + * XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state. + * + * -----------------------------------------------------------------------------*/ /* Extra space required for interrupt/exception hooks. */ #ifdef XT_INTEXC_HOOKS @@ -143,9 +143,9 @@ #endif /* if XT_USE_THREAD_SAFE_CLIB > 0u */ /*------------------------------------------------------------------------------ -* Extra size -- interrupt frame plus coprocessor save area plus hook space. -* NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. -* ------------------------------------------------------------------------------*/ + * Extra size -- interrupt frame plus coprocessor save area plus hook space. + * NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. + * ------------------------------------------------------------------------------*/ #ifdef __XTENSA_CALL0_ABI__ #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE ) #else @@ -153,13 +153,13 @@ #endif /*------------------------------------------------------------------------------ -* Space allocated for user code -- function calls and local variables. -* NOTE: This number can be adjusted to suit your needs. You must verify that the -* amount of space you reserve is adequate for the worst-case conditions in your -* application. -* NOTE: The windowed ABI requires more stack, since space has to be reserved -* for spilling register windows. -* ------------------------------------------------------------------------------*/ + * Space allocated for user code -- function calls and local variables. + * NOTE: This number can be adjusted to suit your needs. You must verify that the + * amount of space you reserve is adequate for the worst-case conditions in your + * application. + * NOTE: The windowed ABI requires more stack, since space has to be reserved + * for spilling register windows. + * ------------------------------------------------------------------------------*/ #ifdef __XTENSA_CALL0_ABI__ #define XT_USER_SIZE 0x200 #else diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c b/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c index 395ea4b10..fa8d3a1b0 100644 --- a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c +++ b/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c @@ -61,7 +61,7 @@ if( ( n < 0 ) || ( n >= XCHAL_EXCCAUSE_NUM ) ) { - return 0; /* invalid exception number */ + return 0; /* invalid exception number */ } old = _xt_exception_table[ n ]; @@ -117,12 +117,12 @@ if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) ) { - return 0; /* invalid interrupt number */ + return 0; /* invalid interrupt number */ } if( Xthal_intlevel[ n ] > XCHAL_EXCM_LEVEL ) { - return 0; /* priority level too high to safely handle in C */ + return 0; /* priority level too high to safely handle in C */ } entry = _xt_interrupt_table + n; diff --git a/portable/WizC/PIC18/Drivers/Tick/Tick.c b/portable/WizC/PIC18/Drivers/Tick/Tick.c index 4ccc47ab2..54a19766a 100644 --- a/portable/WizC/PIC18/Drivers/Tick/Tick.c +++ b/portable/WizC/PIC18/Drivers/Tick/Tick.c @@ -66,7 +66,7 @@ #define portTIMER_COMPARE_VALUE ( portTIMER_COMPARE_BASE / 8 ) #define portTIMER_COMPARE_PS1 ( portBIT_SET ) #define portTIMER_COMPARE_PS0 ( portBIT_SET ) -#else /* if portTIMER_COMPARE_BASE < 0x10000 */ +#else /* if portTIMER_COMPARE_BASE < 0x10000 */ #error "TickRate out of range" #endif /* if portTIMER_COMPARE_BASE < 0x10000 */ diff --git a/portable/WizC/PIC18/portmacro.h b/portable/WizC/PIC18/portmacro.h index 98aedc1d9..f94975b02 100644 --- a/portable/WizC/PIC18/portmacro.h +++ b/portable/WizC/PIC18/portmacro.h @@ -270,7 +270,7 @@ _rtos_s3: clrf POSTDEC2, ACCESS \ else{ \ movff ucCriticalNesting, POSTDEC2 \ - endif \ + endif \ ; } \ ; Save the new top of the software stack in the TCB. \ ; \ @@ -421,3 +421,4 @@ extern void vPortYield( void ); #endif /* PORTMACRO_H */ + diff --git a/portable/oWatcom/16BitDOS/Flsh186/port.c b/portable/oWatcom/16BitDOS/Flsh186/port.c index 6f99ca46a..f64ea3a5e 100644 --- a/portable/oWatcom/16BitDOS/Flsh186/port.c +++ b/portable/oWatcom/16BitDOS/Flsh186/port.c @@ -160,7 +160,7 @@ BaseType_t xPortStartScheduler( void ) /* Reset the PIC ready for the next time. */ portRESET_PIC(); } -#else /* if configUSE_PREEMPTION == 1 */ +#else /* if configUSE_PREEMPTION == 1 */ static void __interrupt __far prvNonPreemptiveTick( void ) { /* Same as preemptive tick, but the cooperative scheduler is being used diff --git a/portable/oWatcom/16BitDOS/PC/port.c b/portable/oWatcom/16BitDOS/PC/port.c index d6668d9f0..857cd0208 100644 --- a/portable/oWatcom/16BitDOS/PC/port.c +++ b/portable/oWatcom/16BitDOS/PC/port.c @@ -192,7 +192,7 @@ BaseType_t xPortStartScheduler( void ) /* Reset the PIC ready for the next time. */ prvPortResetPIC(); } -#else /* if configUSE_PREEMPTION == 1 */ +#else /* if configUSE_PREEMPTION == 1 */ static void __interrupt __far prvNonPreemptiveTick( void ) { /* Same as preemptive tick, but the cooperative scheduler is being used diff --git a/queue.c b/queue.c index cc52deb81..bb75c50ef 100644 --- a/queue.c +++ b/queue.c @@ -491,9 +491,9 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, if( pxNewQueue != NULL ) { /* The queue create function will set all the queue structure members - * correctly for a generic queue, but this function is creating a - * mutex. Overwrite those members that need to be set differently - - * in particular the information required for priority inheritance. */ + * correctly for a generic queue, but this function is creating a + * mutex. Overwrite those members that need to be set differently - + * in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; @@ -1021,10 +1021,10 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, traceQUEUE_SEND_FROM_ISR( pxQueue ); /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a - * semaphore or mutex. That means prvCopyDataToQueue() cannot result - * in a task disinheriting a priority and prvCopyDataToQueue() can be - * called here even though the disinherit function does not check if - * the scheduler is suspended before accessing the ready lists. */ + * semaphore or mutex. That means prvCopyDataToQueue() cannot result + * in a task disinheriting a priority and prvCopyDataToQueue() can be + * called here even though the disinherit function does not check if + * the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); /* The event list is not altered if the queue is locked. This will @@ -1068,7 +1068,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) { /* The task waiting has a higher priority so - * record that a context switch is required. */ + * record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) { *pxHigherPriorityTaskWoken = pdTRUE; @@ -1239,7 +1239,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) { /* The task waiting has a higher priority so - * record that a context switch is required. */ + * record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) { *pxHigherPriorityTaskWoken = pdTRUE; @@ -1780,7 +1780,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) { /* Timeout has not expired yet, check to see if there is data in the - * queue now, and if not enter the Blocked state to wait for data. */ + * queue now, and if not enter the Blocked state to wait for data. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) { traceBLOCKING_ON_QUEUE_PEEK( pxQueue ); @@ -2052,7 +2052,7 @@ void vQueueDelete( QueueHandle_t xQueue ) mtCOVERAGE_TEST_MARKER(); } } - #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */ + #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */ { /* The queue must have been statically allocated, so is not going to be * deleted. Avoid compiler warnings about the unused parameter. */ @@ -2716,7 +2716,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, - const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { UBaseType_t ux; @@ -2820,11 +2820,11 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) * section. */ /* Only do anything if there are no messages in the queue. This function - * will not actually cause the task to block, just place it on a blocked - * list. It will not block until the scheduler is unlocked - at which - * time a yield will be performed. If an item is added to the queue while - * the queue is locked, and the calling task blocks on the queue, then the - * calling task will be immediately unblocked when the queue is unlocked. */ + * will not actually cause the task to block, just place it on a blocked + * list. It will not block until the scheduler is unlocked - at which + * time a yield will be performed. If an item is added to the queue while + * the queue is locked, and the calling task blocks on the queue, then the + * calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) diff --git a/stream_buffer.c b/stream_buffer.c index c55fff3cb..a1e91e945 100644 --- a/stream_buffer.c +++ b/stream_buffer.c @@ -373,7 +373,7 @@ void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Both the structure and the buffer were allocated using a single call - * to pvPortMalloc(), hence only one call to vPortFree() is required. */ + * to pvPortMalloc(), hence only one call to vPortFree() is required. */ vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */ } #else diff --git a/tasks.c b/tasks.c index 1f75f9747..4c5fe06e8 100644 --- a/tasks.c +++ b/tasks.c @@ -420,7 +420,7 @@ PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( extern void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, - uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */ + uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */ #endif @@ -558,7 +558,7 @@ static void prvResetNextTaskUnblockTime( void ); * dynamically to fill in the structure's members. */ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, - const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, @@ -832,7 +832,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, - const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, @@ -1451,7 +1451,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) } } } - #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ { eReturn = eSuspended; } @@ -1651,7 +1651,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) /* The base priority gets set whatever. */ pxTCB->uxBasePriority = uxNewPriority; } - #else /* if ( configUSE_MUTEXES == 1 ) */ + #else /* if ( configUSE_MUTEXES == 1 ) */ { pxTCB->uxPriority = uxNewPriority; } @@ -2025,7 +2025,7 @@ void vTaskStartScheduler( void ) xReturn = pdFAIL; } } - #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ { /* The Idle task is being created using dynamically allocated RAM. */ xReturn = xTaskCreate( prvIdleTask, @@ -2576,7 +2576,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char #endif } } - #else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ + #else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ { if( pulTotalRunTime != NULL ) { @@ -2700,8 +2700,8 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) #if ( configUSE_PREEMPTION == 1 ) { /* Preemption is on, but a context switch should only be - * performed if the unblocked task has a priority that is - * equal to or higher than the currently executing task. */ + * performed if the unblocked task has a priority that is + * equal to or higher than the currently executing task. */ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) { /* Pend the yield to be performed when the scheduler @@ -3764,8 +3764,8 @@ static void prvCheckTasksWaitingTermination( void ) #if ( INCLUDE_vTaskSuspend == 1 ) { /* If the task is in the suspended list then there is a - * chance it is actually just blocked indefinitely - so really - * it should be reported as being in the Blocked state. */ + * chance it is actually just blocked indefinitely - so really + * it should be reported as being in the Blocked state. */ if( eState == eSuspended ) { vTaskSuspendAll(); diff --git a/timers.c b/timers.c index 1a911cfd5..7cebee5ce 100644 --- a/timers.c +++ b/timers.c @@ -93,8 +93,8 @@ * and xCallbackParametersType respectively. */ typedef struct tmrTimerParameters { - TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */ - Timer_t * pxTimer; /*<< The timer to which the command will be applied. */ + TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */ + Timer_t * pxTimer; /*<< The timer to which the command will be applied. */ } TimerParameter_t; @@ -109,7 +109,7 @@ * that is used to determine which message type is valid. */ typedef struct tmrTimerQueueMessage { - BaseType_t xMessageID; /*<< The command being sent to the timer service task. */ + BaseType_t xMessageID; /*<< The command being sent to the timer service task. */ union { TimerParameter_t xTimerParameters; @@ -222,7 +222,7 @@ * Called after a Timer_t structure has been allocated either statically or * dynamically to fill in the structure's members. */ - static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, @@ -262,7 +262,7 @@ xReturn = pdPASS; } } - #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ { xReturn = xTaskCreate( prvTimerTask, configTIMER_SERVICE_TASK_NAME, @@ -285,7 +285,7 @@ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, @@ -312,7 +312,7 @@ #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) - TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, @@ -352,7 +352,7 @@ #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ - static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, @@ -804,11 +804,11 @@ traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue ); /* In this case the xTimerListsWereSwitched parameter is not used, but - * it must be present in the function call. prvSampleTimeNow() must be - * called after the message is received from xTimerQueue so there is no - * possibility of a higher priority task adding a message to the message - * queue with a time that is ahead of the timer daemon task (because it - * pre-empted the timer daemon task after the xTimeNow value was set). */ + * it must be present in the function call. prvSampleTimeNow() must be + * called after the message is received from xTimerQueue so there is no + * possibility of a higher priority task adding a message to the message + * queue with a time that is ahead of the timer daemon task (because it + * pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); switch( xMessage.xMessageID ) @@ -882,7 +882,7 @@ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } } - #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ { /* If dynamic allocation is not enabled, the memory * could not have been dynamically allocated. So there is