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Alfred Gedeon 2020-07-01 22:55:52 -07:00 committed by alfred gedeon
parent 718178c68a
commit 2c530ba5c3
125 changed files with 1218 additions and 1217 deletions
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16
portable/GCC/ARM7_AT91FR40008/portmacro.h
View file

@ -218,18 +218,18 @@
#define portDISABLE_INTERRUPTS() \ #define portDISABLE_INTERRUPTS() \
asm volatile ( \ asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */\ "STMDB SP!, {R0} \n\t"/* Push R0. */\
"MRS R0, CPSR \n\t" /* Get CPSR. */\ "MRS R0, CPSR \n\t"/* Get CPSR. */\
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\ "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
"MSR CPSR, R0 \n\t" /* Write back modified value. */\ "MSR CPSR, R0 \n\t"/* Write back modified value. */\
"LDMIA SP!, {R0} ") /* Pop R0. */ "LDMIA SP!, {R0} ") /* Pop R0. */
#define portENABLE_INTERRUPTS() \ #define portENABLE_INTERRUPTS() \
asm volatile ( \ asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */\ "STMDB SP!, {R0} \n\t"/* Push R0. */\
"MRS R0, CPSR \n\t" /* Get CPSR. */\ "MRS R0, CPSR \n\t"/* Get CPSR. */\
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\ "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
"MSR CPSR, R0 \n\t" /* Write back modified value. */\ "MSR CPSR, R0 \n\t"/* Write back modified value. */\
"LDMIA SP!, {R0} ") /* Pop R0. */ "LDMIA SP!, {R0} ") /* Pop R0. */
#endif /* THUMB_INTERWORK */ #endif /* THUMB_INTERWORK */

16
portable/GCC/ARM7_AT91SAM7S/portmacro.h
View file

@ -213,18 +213,18 @@
#define portDISABLE_INTERRUPTS() \ #define portDISABLE_INTERRUPTS() \
__asm volatile ( \ __asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */\ "STMDB SP!, {R0} \n\t"/* Push R0. */\
"MRS R0, CPSR \n\t" /* Get CPSR. */\ "MRS R0, CPSR \n\t"/* Get CPSR. */\
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\ "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
"MSR CPSR, R0 \n\t" /* Write back modified value. */\ "MSR CPSR, R0 \n\t"/* Write back modified value. */\
"LDMIA SP!, {R0} ") /* Pop R0. */ "LDMIA SP!, {R0} ") /* Pop R0. */
#define portENABLE_INTERRUPTS() \ #define portENABLE_INTERRUPTS() \
__asm volatile ( \ __asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */\ "STMDB SP!, {R0} \n\t"/* Push R0. */\
"MRS R0, CPSR \n\t" /* Get CPSR. */\ "MRS R0, CPSR \n\t"/* Get CPSR. */\
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\ "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
"MSR CPSR, R0 \n\t" /* Write back modified value. */\ "MSR CPSR, R0 \n\t"/* Write back modified value. */\
"LDMIA SP!, {R0} ") /* Pop R0. */ "LDMIA SP!, {R0} ") /* Pop R0. */
#endif /* THUMB_INTERWORK */ #endif /* THUMB_INTERWORK */

16
portable/GCC/ARM7_LPC2000/portmacro.h
View file

@ -190,18 +190,18 @@
#define portDISABLE_INTERRUPTS() \ #define portDISABLE_INTERRUPTS() \
__asm volatile ( \ __asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */\ "STMDB SP!, {R0} \n\t"/* Push R0. */\
"MRS R0, CPSR \n\t" /* Get CPSR. */\ "MRS R0, CPSR \n\t"/* Get CPSR. */\
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\ "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
"MSR CPSR, R0 \n\t" /* Write back modified value. */\ "MSR CPSR, R0 \n\t"/* Write back modified value. */\
"LDMIA SP!, {R0} ") /* Pop R0. */ "LDMIA SP!, {R0} ") /* Pop R0. */
#define portENABLE_INTERRUPTS() \ #define portENABLE_INTERRUPTS() \
__asm volatile ( \ __asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */\ "STMDB SP!, {R0} \n\t"/* Push R0. */\
"MRS R0, CPSR \n\t" /* Get CPSR. */\ "MRS R0, CPSR \n\t"/* Get CPSR. */\
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\ "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
"MSR CPSR, R0 \n\t" /* Write back modified value. */\ "MSR CPSR, R0 \n\t"/* Write back modified value. */\
"LDMIA SP!, {R0} ") /* Pop R0. */ "LDMIA SP!, {R0} ") /* Pop R0. */
#endif /* THUMB_INTERWORK */ #endif /* THUMB_INTERWORK */

16
portable/GCC/ARM7_LPC23xx/portmacro.h
View file

@ -213,18 +213,18 @@
#define portDISABLE_INTERRUPTS() \ #define portDISABLE_INTERRUPTS() \
__asm volatile ( \ __asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */\ "STMDB SP!, {R0} \n\t"/* Push R0. */\
"MRS R0, CPSR \n\t" /* Get CPSR. */\ "MRS R0, CPSR \n\t"/* Get CPSR. */\
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\ "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
"MSR CPSR, R0 \n\t" /* Write back modified value. */\ "MSR CPSR, R0 \n\t"/* Write back modified value. */\
"LDMIA SP!, {R0} ") /* Pop R0. */ "LDMIA SP!, {R0} ") /* Pop R0. */
#define portENABLE_INTERRUPTS() \ #define portENABLE_INTERRUPTS() \
__asm volatile ( \ __asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */\ "STMDB SP!, {R0} \n\t"/* Push R0. */\
"MRS R0, CPSR \n\t" /* Get CPSR. */\ "MRS R0, CPSR \n\t"/* Get CPSR. */\
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\ "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
"MSR CPSR, R0 \n\t" /* Write back modified value. */\ "MSR CPSR, R0 \n\t"/* Write back modified value. */\
"LDMIA SP!, {R0} ") /* Pop R0. */ "LDMIA SP!, {R0} ") /* Pop R0. */
#endif /* THUMB_INTERWORK */ #endif /* THUMB_INTERWORK */

18
portable/GCC/ARM_CM3/port.c
View file

@ -220,11 +220,11 @@ static void prvTaskExitError( void )
void vPortSVCHandler( void ) void vPortSVCHandler( void )
{ {
__asm volatile ( __asm volatile (
" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
" ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ " ldmia r0!, {r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
" msr psp, r0 \n" /* Restore the task stack pointer. */ " msr psp, r0 \n"/* Restore the task stack pointer. */
" isb \n" " isb \n"
" mov r0, #0 \n" " mov r0, #0 \n"
" msr basepri, r0 \n" " msr basepri, r0 \n"
@ -240,15 +240,15 @@ void vPortSVCHandler( void )
static void prvPortStartFirstTask( void ) static void prvPortStartFirstTask( void )
{ {
__asm volatile ( __asm volatile (
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
" cpsie i \n" /* Globally enable interrupts. */ " cpsie i \n"/* Globally enable interrupts. */
" cpsie f \n" " cpsie f \n"
" dsb \n" " dsb \n"
" isb \n" " isb \n"
" svc 0 \n" /* System call to start first task. */ " svc 0 \n"/* System call to start first task. */
" nop \n" " nop \n"
" .ltorg \n" " .ltorg \n"
); );

2
portable/GCC/ARM_CM3/portmacro.h
View file

@ -82,7 +82,7 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\ * within the specified behaviour for the architecture. */ \
__asm volatile ( "dsb" ::: "memory" ); \ __asm volatile ( "dsb" ::: "memory" ); \
__asm volatile ( "isb" ); \ __asm volatile ( "isb" ); \
} }

20
portable/GCC/ARM_CM3_MPU/port.c
View file

@ -294,9 +294,9 @@ static void prvSVCHandler( uint32_t * pulParam )
{ {
__asm volatile __asm volatile
( (
" mrs r1, control \n" /* Obtain current control value. */ " mrs r1, control \n"/* Obtain current control value. */
" bic r1, #1 \n" /* Set privilege bit. */ " bic r1, #1 \n"/* Set privilege bit. */
" msr control, r1 \n" /* Write back new control value. */ " msr control, r1 \n"/* Write back new control value. */
::: "r1", "memory" ::: "r1", "memory"
); );
} }
@ -306,9 +306,9 @@ static void prvSVCHandler( uint32_t * pulParam )
case portSVC_RAISE_PRIVILEGE: case portSVC_RAISE_PRIVILEGE:
__asm volatile __asm volatile
( (
" mrs r1, control \n" /* Obtain current control value. */ " mrs r1, control \n"/* Obtain current control value. */
" bic r1, #1 \n" /* Set privilege bit. */ " bic r1, #1 \n"/* Set privilege bit. */
" msr control, r1 \n" /* Write back new control value. */ " msr control, r1 \n"/* Write back new control value. */
::: "r1", "memory" ::: "r1", "memory"
); );
break; break;
@ -453,15 +453,15 @@ BaseType_t xPortStartScheduler( void )
/* Start the first task. */ /* Start the first task. */
__asm volatile ( __asm volatile (
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
" cpsie i \n" /* Globally enable interrupts. */ " cpsie i \n"/* Globally enable interrupts. */
" cpsie f \n" " cpsie f \n"
" dsb \n" " dsb \n"
" isb \n" " isb \n"
" svc %0 \n" /* System call to start first task. */ " svc %0 \n"/* System call to start first task. */
" nop \n" " nop \n"
" .ltorg \n" " .ltorg \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory" ); ::"i" ( portSVC_START_SCHEDULER ) : "memory" );

2
portable/GCC/ARM_CM3_MPU/portmacro.h
View file

@ -125,7 +125,7 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\ * within the specified behaviour for the architecture. */ \
__asm volatile ( "dsb" ::: "memory" ); \ __asm volatile ( "dsb" ::: "memory" ); \
__asm volatile ( "isb" ); \ __asm volatile ( "isb" ); \
} }

20
portable/GCC/ARM_CM4F/port.c
View file

@ -245,11 +245,11 @@ static void prvTaskExitError( void )
void vPortSVCHandler( void ) void vPortSVCHandler( void )
{ {
__asm volatile ( __asm volatile (
" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
" ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
" msr psp, r0 \n" /* Restore the task stack pointer. */ " msr psp, r0 \n"/* Restore the task stack pointer. */
" isb \n" " isb \n"
" mov r0, #0 \n" " mov r0, #0 \n"
" msr basepri, r0 \n" " msr basepri, r0 \n"
@ -268,17 +268,17 @@ static void prvPortStartFirstTask( void )
* would otherwise result in the unnecessary leaving of space in the SVC stack * would otherwise result in the unnecessary leaving of space in the SVC stack
* for lazy saving of FPU registers. */ * for lazy saving of FPU registers. */
__asm volatile ( __asm volatile (
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
" mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */ " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
" msr control, r0 \n" " msr control, r0 \n"
" cpsie i \n" /* Globally enable interrupts. */ " cpsie i \n"/* Globally enable interrupts. */
" cpsie f \n" " cpsie f \n"
" dsb \n" " dsb \n"
" isb \n" " isb \n"
" svc 0 \n" /* System call to start first task. */ " svc 0 \n"/* System call to start first task. */
" nop \n" " nop \n"
" .ltorg \n" " .ltorg \n"
); );

2
portable/GCC/ARM_CM4F/portmacro.h
View file

@ -82,7 +82,7 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\ * within the specified behaviour for the architecture. */ \
__asm volatile ( "dsb" ::: "memory" ); \ __asm volatile ( "dsb" ::: "memory" ); \
__asm volatile ( "isb" ); \ __asm volatile ( "isb" ); \
} }

22
portable/GCC/ARM_CM4_MPU/port.c
View file

@ -313,9 +313,9 @@ static void prvSVCHandler( uint32_t * pulParam )
{ {
__asm volatile __asm volatile
( (
" mrs r1, control \n" /* Obtain current control value. */ " mrs r1, control \n"/* Obtain current control value. */
" bic r1, #1 \n" /* Set privilege bit. */ " bic r1, #1 \n"/* Set privilege bit. */
" msr control, r1 \n" /* Write back new control value. */ " msr control, r1 \n"/* Write back new control value. */
::: "r1", "memory" ::: "r1", "memory"
); );
} }
@ -325,9 +325,9 @@ static void prvSVCHandler( uint32_t * pulParam )
case portSVC_RAISE_PRIVILEGE: case portSVC_RAISE_PRIVILEGE:
__asm volatile __asm volatile
( (
" mrs r1, control \n" /* Obtain current control value. */ " mrs r1, control \n"/* Obtain current control value. */
" bic r1, #1 \n" /* Set privilege bit. */ " bic r1, #1 \n"/* Set privilege bit. */
" msr control, r1 \n" /* Write back new control value. */ " msr control, r1 \n"/* Write back new control value. */
::: "r1", "memory" ::: "r1", "memory"
); );
break; break;
@ -480,17 +480,17 @@ BaseType_t xPortStartScheduler( void )
* would otherwise result in the unnecessary leaving of space in the SVC stack * would otherwise result in the unnecessary leaving of space in the SVC stack
* for lazy saving of FPU registers. */ * for lazy saving of FPU registers. */
__asm volatile ( __asm volatile (
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
" mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */ " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
" msr control, r0 \n" " msr control, r0 \n"
" cpsie i \n" /* Globally enable interrupts. */ " cpsie i \n"/* Globally enable interrupts. */
" cpsie f \n" " cpsie f \n"
" dsb \n" " dsb \n"
" isb \n" " isb \n"
" svc %0 \n" /* System call to start first task. */ " svc %0 \n"/* System call to start first task. */
" nop \n" " nop \n"
" .ltorg \n" " .ltorg \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory" ); ::"i" ( portSVC_START_SCHEDULER ) : "memory" );

2
portable/GCC/ARM_CM4_MPU/portmacro.h
View file

@ -125,7 +125,7 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\ * within the specified behaviour for the architecture. */ \
__asm volatile ( "dsb" ::: "memory" ); \ __asm volatile ( "dsb" ::: "memory" ); \
__asm volatile ( "isb" ); \ __asm volatile ( "isb" ); \
} }

20
portable/GCC/ARM_CM7/r0p1/port.c
View file

@ -239,11 +239,11 @@ static void prvTaskExitError( void )
void vPortSVCHandler( void ) void vPortSVCHandler( void )
{ {
__asm volatile ( __asm volatile (
" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
" ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
" msr psp, r0 \n" /* Restore the task stack pointer. */ " msr psp, r0 \n"/* Restore the task stack pointer. */
" isb \n" " isb \n"
" mov r0, #0 \n" " mov r0, #0 \n"
" msr basepri, r0 \n" " msr basepri, r0 \n"
@ -262,17 +262,17 @@ static void prvPortStartFirstTask( void )
* would otherwise result in the unnecessary leaving of space in the SVC stack * would otherwise result in the unnecessary leaving of space in the SVC stack
* for lazy saving of FPU registers. */ * for lazy saving of FPU registers. */
__asm volatile ( __asm volatile (
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
" mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */ " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
" msr control, r0 \n" " msr control, r0 \n"
" cpsie i \n" /* Globally enable interrupts. */ " cpsie i \n"/* Globally enable interrupts. */
" cpsie f \n" " cpsie f \n"
" dsb \n" " dsb \n"
" isb \n" " isb \n"
" svc 0 \n" /* System call to start first task. */ " svc 0 \n"/* System call to start first task. */
" nop \n" " nop \n"
" .ltorg \n" " .ltorg \n"
); );

2
portable/GCC/ARM_CM7/r0p1/portmacro.h
View file

@ -82,7 +82,7 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\ * within the specified behaviour for the architecture. */ \
__asm volatile ( "dsb" ::: "memory" ); \ __asm volatile ( "dsb" ::: "memory" ); \
__asm volatile ( "isb" ); \ __asm volatile ( "isb" ); \
} }

52
portable/GCC/AVR32_UC3/portmacro.h
View file

@ -399,13 +399,13 @@
\ \
__asm__ __volatile__ ( \ __asm__ __volatile__ ( \
/* in order to save R0-R7 */ \ /* in order to save R0-R7 */ \
"sub sp, 6*4 \n\t" \ "sub sp, 6*4 \n\t"\
/* Save R0..R7 */ \ /* Save R0..R7 */ \
"stm --sp, r0-r7 \n\t" \ "stm --sp, r0-r7 \n\t"\
\ \
/* in order to save R8-R12 and LR */ \ /* in order to save R8-R12 and LR */ \
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
"sub r7, sp,-16*4 \n\t" \ "sub r7, sp,-16*4 \n\t"\
/* Copy PC and SR in other places in the stack. */ \ /* Copy PC and SR in other places in the stack. */ \
"ld.w r0, r7[-2*4] \n\t"/* Read SR */\ "ld.w r0, r7[-2*4] \n\t"/* Read SR */\
"st.w r7[-8*4], r0 \n\t"/* Copy SR */\ "st.w r7[-8*4], r0 \n\t"/* Copy SR */\
@ -413,7 +413,7 @@
"st.w r7[-7*4], r0 \n\t"/* Copy PC */\ "st.w r7[-7*4], r0 \n\t"/* Copy PC */\
\ \
/* Save R8..R12 and LR on the stack. */ \ /* Save R8..R12 and LR on the stack. */ \
"stm --r7, r8-r12, lr \n\t" \ "stm --r7, r8-r12, lr \n\t"\
\ \
/* Arriving here we have the following stack organizations: */ \ /* Arriving here we have the following stack organizations: */ \
/* R8..R12, LR, PC, SR, R0..R7. */ \ /* R8..R12, LR, PC, SR, R0..R7. */ \
@ -421,9 +421,9 @@
/* Now we can finalize the save. */ \ /* Now we can finalize the save. */ \
\ \
/* Save ulCriticalNesting variable - R0 is overwritten */ \ /* Save ulCriticalNesting variable - R0 is overwritten */ \
"mov r8, LO(%[ulCriticalNesting]) \n\t" \ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
"orh r8, HI(%[ulCriticalNesting]) \n\t" \ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
"ld.w r0, r8[0] \n\t" \ "ld.w r0, r8[0] \n\t"\
"st.w --sp, r0" \ "st.w --sp, r0" \
: \ : \
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \ :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
@ -437,9 +437,9 @@
\ \
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
__asm__ __volatile__ ( \ __asm__ __volatile__ ( \
"mov r8, LO(%[pxCurrentTCB]) \n\t" \ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
"orh r8, HI(%[pxCurrentTCB]) \n\t" \ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
"ld.w r0, r8[0] \n\t" \ "ld.w r0, r8[0] \n\t"\
"st.w r0[0], sp" \ "st.w r0[0], sp" \
: \ : \
:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \ :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
@ -458,9 +458,9 @@
\ \
/* Set SP to point to new stack */ \ /* Set SP to point to new stack */ \
__asm__ __volatile__ ( \ __asm__ __volatile__ ( \
"mov r8, LO(%[pxCurrentTCB]) \n\t" \ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
"orh r8, HI(%[pxCurrentTCB]) \n\t" \ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
"ld.w r0, r8[0] \n\t" \ "ld.w r0, r8[0] \n\t"\
"ld.w sp, r0[0]" \ "ld.w sp, r0[0]" \
: \ : \
:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \ :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
@ -471,16 +471,16 @@
\ \
__asm__ __volatile__ ( \ __asm__ __volatile__ ( \
/* Restore ulCriticalNesting variable */ \ /* Restore ulCriticalNesting variable */ \
"ld.w r0, sp++ \n\t" \ "ld.w r0, sp++ \n\t"\
"mov r8, LO(%[ulCriticalNesting]) \n\t" \ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
"orh r8, HI(%[ulCriticalNesting]) \n\t" \ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
"st.w r8[0], r0 \n\t" \ "st.w r8[0], r0 \n\t"\
\ \
/* skip PC and SR */ \ /* skip PC and SR */ \
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
"sub r7, sp, -10*4 \n\t" \ "sub r7, sp, -10*4 \n\t"\
/* Restore r8-r12 and LR */ \ /* Restore r8-r12 and LR */ \
"ldm r7++, r8-r12, lr \n\t" \ "ldm r7++, r8-r12, lr \n\t"\
\ \
/* RETS will take care of the extra PC and SR restore. */ \ /* RETS will take care of the extra PC and SR restore. */ \
/* So, we have to prepare the stack for this. */ \ /* So, we have to prepare the stack for this. */ \
@ -490,9 +490,9 @@
"st.w r7[-1*4], r0 \n\t"/* Copy PC */\ "st.w r7[-1*4], r0 \n\t"/* Copy PC */\
\ \
/* Restore R0..R7 */ \ /* Restore R0..R7 */ \
"ldm sp++, r0-r7 \n\t" \ "ldm sp++, r0-r7 \n\t"\
\ \
"sub sp, -6*4 \n\t" \ "sub sp, -6*4 \n\t"\
\ \
"rets" \ "rets" \
: \ : \
@ -567,8 +567,8 @@
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
/* will just be restoring the interrupt handler, no way!!! */ \ /* will just be restoring the interrupt handler, no way!!! */ \
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
"ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \ "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */\
"bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \ "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */\
"cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\ "cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\
"brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \ "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \
\ \
@ -600,15 +600,15 @@
/* level and allow other lower interrupt level to occur). */ \ /* level and allow other lower interrupt level to occur). */ \
/* In this case it's of no use to switch context and restore a new SP because we purposedly */ \ /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
/* did not previously save SP in its TCB. */ \ /* did not previously save SP in its TCB. */ \
"ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \ "ld.w r0, sp[9*4] \n\t"/* Read SR in stack */\
"bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \ "bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */\
"cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\ "cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\
"brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \ "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \
\ \
/* If a switch is required then we just need to call */ \ /* If a switch is required then we just need to call */ \
/* vTaskSwitchContext() as the context has already been */ \ /* vTaskSwitchContext() as the context has already been */ \
/* saved. */ \ /* saved. */ \
"cp.w r12, 1 \n\t"/* Check if Switch context is required. */ \ "cp.w r12, 1 \n\t"/* Check if Switch context is required. */\
"brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \ "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
: \ : \
:[ LINE ] "i" ( __LINE__ ) \ :[ LINE ] "i" ( __LINE__ ) \

16
portable/GCC/STR75x/portmacro.h
View file

@ -93,18 +93,18 @@
#define portDISABLE_INTERRUPTS() \ #define portDISABLE_INTERRUPTS() \
asm volatile ( \ asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */\ "STMDB SP!, {R0} \n\t"/* Push R0. */\
"MRS R0, CPSR \n\t" /* Get CPSR. */\ "MRS R0, CPSR \n\t"/* Get CPSR. */\
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\ "ORR R0, R0, #0xC0 \n\t"/* Disable IRQ, FIQ. */\
"MSR CPSR, R0 \n\t" /* Write back modified value. */\ "MSR CPSR, R0 \n\t"/* Write back modified value. */\
"LDMIA SP!, {R0} ") /* Pop R0. */ "LDMIA SP!, {R0} ") /* Pop R0. */
#define portENABLE_INTERRUPTS() \ #define portENABLE_INTERRUPTS() \
asm volatile ( \ asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */\ "STMDB SP!, {R0} \n\t"/* Push R0. */\
"MRS R0, CPSR \n\t" /* Get CPSR. */\ "MRS R0, CPSR \n\t"/* Get CPSR. */\
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\ "BIC R0, R0, #0xC0 \n\t"/* Enable IRQ, FIQ. */\
"MSR CPSR, R0 \n\t" /* Write back modified value. */\ "MSR CPSR, R0 \n\t"/* Write back modified value. */\
"LDMIA SP!, {R0} ") /* Pop R0. */ "LDMIA SP!, {R0} ") /* Pop R0. */
#endif /* THUMB_INTERWORK */ #endif /* THUMB_INTERWORK */

12
portable/IAR/ARM_CM4F_MPU/port.c
View file

@ -303,9 +303,9 @@ void vPortSVCHandler_C( uint32_t * pulParam )
{ {
__asm volatile __asm volatile
( (
" mrs r1, control \n" /* Obtain current control value. */ " mrs r1, control \n"/* Obtain current control value. */
" bic r1, r1, #1 \n" /* Set privilege bit. */ " bic r1, r1, #1 \n"/* Set privilege bit. */
" msr control, r1 \n" /* Write back new control value. */ " msr control, r1 \n"/* Write back new control value. */
::: "r1", "memory" ::: "r1", "memory"
); );
} }
@ -315,9 +315,9 @@ void vPortSVCHandler_C( uint32_t * pulParam )
case portSVC_RAISE_PRIVILEGE: case portSVC_RAISE_PRIVILEGE:
__asm volatile __asm volatile
( (
" mrs r1, control \n" /* Obtain current control value. */ " mrs r1, control \n"/* Obtain current control value. */
" bic r1, r1, #1 \n" /* Set privilege bit. */ " bic r1, r1, #1 \n"/* Set privilege bit. */
" msr control, r1 \n" /* Write back new control value. */ " msr control, r1 \n"/* Write back new control value. */
::: "r1", "memory" ::: "r1", "memory"
); );
break; break;

10
portable/MPLAB/PIC18F/port.c
View file

@ -146,7 +146,7 @@ static void prvLowInterrupt( void );
{ \ { \
_asm \ _asm \
/* Save the status and WREG registers first, as these will get modified \ /* Save the status and WREG registers first, as these will get modified \
* by the operations below. */\ * by the operations below. */ \
MOVFF WREG, PREINC1 \ MOVFF WREG, PREINC1 \
MOVFF STATUS, PREINC1 \ MOVFF STATUS, PREINC1 \
/* Save the INTCON register with the appropriate bits forced if \ /* Save the INTCON register with the appropriate bits forced if \
@ -243,12 +243,12 @@ static void prvLowInterrupt( void );
MOVFF pxCurrentTCB + 1, FSR0H \ MOVFF pxCurrentTCB + 1, FSR0H \
\ \
/* De-reference FSR0 to set the address it holds into FSR1. \ /* De-reference FSR0 to set the address it holds into FSR1. \
* (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */\ * (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
MOVFF POSTINC0, FSR1L \ MOVFF POSTINC0, FSR1L \
MOVFF POSTINC0, FSR1H \ MOVFF POSTINC0, FSR1H \
\ \
/* How many return addresses are there on the hardware stack? Discard \ /* How many return addresses are there on the hardware stack? Discard \
* the first byte as we are pointing to the next free space. */\ * the first byte as we are pointing to the next free space. */ \
MOVFF POSTDEC1, FSR0L \ MOVFF POSTDEC1, FSR0L \
MOVFF POSTDEC1, FSR0L \ MOVFF POSTDEC1, FSR0L \
_endasm \ _endasm \
@ -308,7 +308,7 @@ static void prvLowInterrupt( void );
MOVFF POSTDEC1, FSR2L \ MOVFF POSTDEC1, FSR2L \
MOVFF POSTDEC1, BSR \ MOVFF POSTDEC1, BSR \
/* The next byte is the INTCON register. Read this into WREG as some \ /* The next byte is the INTCON register. Read this into WREG as some \
* manipulation is required. */\ * manipulation is required. */ \
MOVFF POSTDEC1, WREG \ MOVFF POSTDEC1, WREG \
_endasm \ _endasm \
\ \
@ -331,7 +331,7 @@ static void prvLowInterrupt( void );
MOVFF POSTDEC1, STATUS \ MOVFF POSTDEC1, STATUS \
MOVFF POSTDEC1, WREG \ MOVFF POSTDEC1, WREG \
/* Return without effecting interrupts. The context may have \ /* Return without effecting interrupts. The context may have \
* been saved from a critical region. */\ * been saved from a critical region. */ \
RETURN 0 \ RETURN 0 \
_endasm \ _endasm \
} \ } \

18
portable/MPLAB/PIC24_dsPIC/port.c
View file

@ -69,15 +69,15 @@ UBaseType_t uxCriticalNesting = 0xef;
#ifdef __HAS_EDS__ #ifdef __HAS_EDS__
#define portRESTORE_CONTEXT() \ #define portRESTORE_CONTEXT() \
asm volatile ( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
"MOV [W0], W15 \n" \ "MOV [W0], W15 \n" \
"POP W0 \n" /* Restore the critical nesting counter for the task. */ \ "POP W0 \n"/* Restore the critical nesting counter for the task. */\
"MOV W0, _uxCriticalNesting \n" \ "MOV W0, _uxCriticalNesting \n" \
"POP DSWPAG \n" \ "POP DSWPAG \n" \
"POP DSRPAG \n" \ "POP DSRPAG \n" \
"POP CORCON \n" \ "POP CORCON \n" \
"POP TBLPAG \n" \ "POP TBLPAG \n" \
"POP RCOUNT \n" /* Restore the registers from the stack. */ \ "POP RCOUNT \n"/* Restore the registers from the stack. */ \
"POP W14 \n" \ "POP W14 \n" \
"POP.D W12 \n" \ "POP.D W12 \n" \
"POP.D W10 \n" \ "POP.D W10 \n" \
@ -89,14 +89,14 @@ UBaseType_t uxCriticalNesting = 0xef;
"POP SR "); "POP SR ");
#else /* __HAS_EDS__ */ #else /* __HAS_EDS__ */
#define portRESTORE_CONTEXT() \ #define portRESTORE_CONTEXT() \
asm volatile ( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
"MOV [W0], W15 \n" \ "MOV [W0], W15 \n" \
"POP W0 \n" /* Restore the critical nesting counter for the task. */ \ "POP W0 \n"/* Restore the critical nesting counter for the task. */\
"MOV W0, _uxCriticalNesting \n" \ "MOV W0, _uxCriticalNesting \n" \
"POP PSVPAG \n" \ "POP PSVPAG \n" \
"POP CORCON \n" \ "POP CORCON \n" \
"POP TBLPAG \n" \ "POP TBLPAG \n" \
"POP RCOUNT \n" /* Restore the registers from the stack. */ \ "POP RCOUNT \n"/* Restore the registers from the stack. */ \
"POP W14 \n" \ "POP W14 \n" \
"POP.D W12 \n" \ "POP.D W12 \n" \
"POP.D W10 \n" \ "POP.D W10 \n" \
@ -112,9 +112,9 @@ UBaseType_t uxCriticalNesting = 0xef;
#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) #if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
#define portRESTORE_CONTEXT() \ #define portRESTORE_CONTEXT() \
asm volatile ( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ asm volatile ( "MOV _pxCurrentTCB, W0 \n"/* Restore the stack pointer for the task. */ \
"MOV [W0], W15 \n" \ "MOV [W0], W15 \n" \
"POP W0 \n" /* Restore the critical nesting counter for the task. */ \ "POP W0 \n"/* Restore the critical nesting counter for the task. */\
"MOV W0, _uxCriticalNesting \n" \ "MOV W0, _uxCriticalNesting \n" \
"POP PSVPAG \n" \ "POP PSVPAG \n" \
"POP CORCON \n" \ "POP CORCON \n" \
@ -130,7 +130,7 @@ UBaseType_t uxCriticalNesting = 0xef;
"POP ACCAH \n" \ "POP ACCAH \n" \
"POP ACCAL \n" \ "POP ACCAL \n" \
"POP TBLPAG \n" \ "POP TBLPAG \n" \
"POP RCOUNT \n" /* Restore the registers from the stack. */ \ "POP RCOUNT \n"/* Restore the registers from the stack. */ \
"POP W14 \n" \ "POP W14 \n" \
"POP.D W12 \n" \ "POP.D W12 \n" \
"POP.D W10 \n" \ "POP.D W10 \n" \

2
portable/MemMang/heap_1.c
View file

@ -55,7 +55,7 @@
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) #if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
/* The application writer has already defined the array used for the RTOS /* The application writer has already defined the array used for the RTOS
* heap - probably so it can be placed in a special segment or address. */ * heap - probably so it can be placed in a special segment or address. */
extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
#else #else
static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];

2
portable/MemMang/heap_2.c
View file

@ -61,7 +61,7 @@ static void prvHeapInit( void );
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) #if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
/* The application writer has already defined the array used for the RTOS /* The application writer has already defined the array used for the RTOS
* heap - probably so it can be placed in a special segment or address. */ * heap - probably so it can be placed in a special segment or address. */
extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
#else #else
static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];

2
portable/MemMang/heap_4.c
View file

@ -58,7 +58,7 @@
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) #if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
/* The application writer has already defined the array used for the RTOS /* The application writer has already defined the array used for the RTOS
* heap - probably so it can be placed in a special segment or address. */ * heap - probably so it can be placed in a special segment or address. */
extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
#else #else
static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];

2
portable/MikroC/ARM_CM4F/portmacro.h
View file

@ -86,7 +86,7 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\ * within the specified behaviour for the architecture. */ \
__asm{ dsb }; \ __asm{ dsb }; \
__asm{ isb }; \ __asm{ isb }; \
} }

2
portable/RVDS/ARM_CM3/portmacro.h
View file

@ -85,7 +85,7 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\ * within the specified behaviour for the architecture. */ \
__dsb( portSY_FULL_READ_WRITE ); \ __dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \ __isb( portSY_FULL_READ_WRITE ); \
} }

2
portable/RVDS/ARM_CM4F/portmacro.h
View file

@ -85,7 +85,7 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\ * within the specified behaviour for the architecture. */ \
__dsb( portSY_FULL_READ_WRITE ); \ __dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \ __isb( portSY_FULL_READ_WRITE ); \
} }

2
portable/RVDS/ARM_CM4_MPU/portmacro.h
View file

@ -129,7 +129,7 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\ * within the specified behaviour for the architecture. */ \
__dsb( portSY_FULL_READ_WRITE ); \ __dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \ __isb( portSY_FULL_READ_WRITE ); \
} }

2
portable/RVDS/ARM_CM7/r0p1/portmacro.h
View file

@ -85,7 +85,7 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\ * within the specified behaviour for the architecture. */ \
__dsb( portSY_FULL_READ_WRITE ); \ __dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \ __isb( portSY_FULL_READ_WRITE ); \
} }

6
portable/SDCC/Cygnal/port.c
View file

@ -95,11 +95,11 @@ static void prvSetupTimerInterrupt( void );
ucStackBytes = SP - ( configSTACK_START - 1 ); \ ucStackBytes = SP - ( configSTACK_START - 1 ); \
\ \
/* Before starting to copy the stack, store the calculated stack size so \ /* Before starting to copy the stack, store the calculated stack size so \
* the stack can be restored when the task is resumed. */\ * the stack can be restored when the task is resumed. */ \
* pxXRAMStack = ucStackBytes; \ * pxXRAMStack = ucStackBytes; \
\ \
/* Copy each stack byte in turn. pxXRAMStack is incremented first as we \ /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \
* have already stored the stack size into XRAM. */\ * have already stored the stack size into XRAM. */ \
while( ucStackBytes ) \ while( ucStackBytes ) \
{ \ { \
pxXRAMStack ++; \ pxXRAMStack ++; \
@ -194,7 +194,7 @@ static void prvSetupTimerInterrupt( void );
pop DPL \ pop DPL \
/* The next byte of the stack is the IE register. Only the global \ /* The next byte of the stack is the IE register. Only the global \
* enable bit forms part of the task context. Pop off the IE then set \ * enable bit forms part of the task context. Pop off the IE then set \
* the global enable bit to match that of the stored IE register. */\ * the global enable bit to match that of the stored IE register. */ \
pop ACC \ pop ACC \
JB ACC .7, 00 98$ \ JB ACC .7, 00 98$ \
CLR IE .7 \ CLR IE .7 \

114
portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h vendored
View file

@ -45,53 +45,53 @@
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* STACK REQUIREMENTS * STACK REQUIREMENTS
* *
* This section defines the minimum stack size, and the extra space required to * This section defines the minimum stack size, and the extra space required to
* be allocated for saving coprocessor state and/or C library state information * be allocated for saving coprocessor state and/or C library state information
* (if thread safety is enabled for the C library). The sizes are in bytes. * (if thread safety is enabled for the C library). The sizes are in bytes.
* *
* Stack sizes for individual tasks should be derived from these minima based on * Stack sizes for individual tasks should be derived from these minima based on
* the maximum call depth of the task and the maximum level of interrupt nesting. * the maximum call depth of the task and the maximum level of interrupt nesting.
* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
* on the requirement for a task that calls nothing else but can be interrupted. * on the requirement for a task that calls nothing else but can be interrupted.
* This assumes that interrupt handlers do not call more than a few levels deep. * This assumes that interrupt handlers do not call more than a few levels deep.
* If this is not true, i.e. one or more interrupt handlers make deep calls then * If this is not true, i.e. one or more interrupt handlers make deep calls then
* the minimum must be increased. * the minimum must be increased.
* *
* If the Xtensa processor configuration includes coprocessors, then space is * If the Xtensa processor configuration includes coprocessors, then space is
* allocated to save the coprocessor state on the stack. * allocated to save the coprocessor state on the stack.
* *
* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
* is defined) then space is allocated to save the C library context in the TCB. * is defined) then space is allocated to save the C library context in the TCB.
* *
* Allocating insufficient stack space is a common source of hard-to-find errors. * Allocating insufficient stack space is a common source of hard-to-find errors.
* During development, it is best to enable the FreeRTOS stack checking features. * During development, it is best to enable the FreeRTOS stack checking features.
* *
* Usage: * Usage:
* *
* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
* use of the C library. This will require extra stack * use of the C library. This will require extra stack
* space to be allocated for tasks that use the C library * space to be allocated for tasks that use the C library
* reentrant functions. See below for more information. * reentrant functions. See below for more information.
* *
* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
* support thread safety. Check your core configuration to see which C library * support thread safety. Check your core configuration to see which C library
* was chosen for your system. * was chosen for your system.
* *
* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended * XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended
* that you do not use a stack smaller than this for any * that you do not use a stack smaller than this for any
* task. In case you want to use stacks smaller than this * task. In case you want to use stacks smaller than this
* size, you must verify that the smaller size(s) will work * size, you must verify that the smaller size(s) will work
* under all operating conditions. * under all operating conditions.
* *
* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task * XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task
* that does not make C library reentrant calls. Add this * that does not make C library reentrant calls. Add this
* to the amount of stack space required by the task itself. * to the amount of stack space required by the task itself.
* *
* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state. * XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state.
* *
* -----------------------------------------------------------------------------*/ * -----------------------------------------------------------------------------*/
/* Extra space required for interrupt/exception hooks. */ /* Extra space required for interrupt/exception hooks. */
#ifdef XT_INTEXC_HOOKS #ifdef XT_INTEXC_HOOKS
@ -107,9 +107,9 @@
#define XT_CLIB_CONTEXT_AREA_SIZE 0 #define XT_CLIB_CONTEXT_AREA_SIZE 0
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* Extra size -- interrupt frame plus coprocessor save area plus hook space. * Extra size -- interrupt frame plus coprocessor save area plus hook space.
* NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. * NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
* ------------------------------------------------------------------------------*/ * ------------------------------------------------------------------------------*/
#ifdef __XTENSA_CALL0_ABI__ #ifdef __XTENSA_CALL0_ABI__
#define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE ) #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
#else #else
@ -117,13 +117,13 @@
#endif #endif
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* Space allocated for user code -- function calls and local variables. * Space allocated for user code -- function calls and local variables.
* NOTE: This number can be adjusted to suit your needs. You must verify that the * NOTE: This number can be adjusted to suit your needs. You must verify that the
* amount of space you reserve is adequate for the worst-case conditions in your * amount of space you reserve is adequate for the worst-case conditions in your
* application. * application.
* NOTE: The windowed ABI requires more stack, since space has to be reserved * NOTE: The windowed ABI requires more stack, since space has to be reserved
* for spilling register windows. * for spilling register windows.
* ------------------------------------------------------------------------------*/ * ------------------------------------------------------------------------------*/
#ifdef __XTENSA_CALL0_ABI__ #ifdef __XTENSA_CALL0_ABI__
#define XT_USER_SIZE 0x200 #define XT_USER_SIZE 0x200
#else #else

2
portable/ThirdParty/XCC/Xtensa/portmacro.h vendored
View file

@ -109,7 +109,7 @@
#define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 ) #define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 )
/* These can be nested */ /* These can be nested */
#define portCRITICAL_NESTING_IN_TCB 1/* For now, let FreeRTOS' (tasks.c) manage critical nesting */ #define portCRITICAL_NESTING_IN_TCB 1 /* For now, let FreeRTOS' (tasks.c) manage critical nesting */
void vTaskEnterCritical( void ); void vTaskEnterCritical( void );
void vTaskExitCritical( void ); void vTaskExitCritical( void );
#define portENTER_CRITICAL() vTaskEnterCritical() #define portENTER_CRITICAL() vTaskEnterCritical()

114
portable/ThirdParty/XCC/Xtensa/xtensa_config.h vendored
View file

@ -45,53 +45,53 @@
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* STACK REQUIREMENTS * STACK REQUIREMENTS
* *
* This section defines the minimum stack size, and the extra space required to * This section defines the minimum stack size, and the extra space required to
* be allocated for saving coprocessor state and/or C library state information * be allocated for saving coprocessor state and/or C library state information
* (if thread safety is enabled for the C library). The sizes are in bytes. * (if thread safety is enabled for the C library). The sizes are in bytes.
* *
* Stack sizes for individual tasks should be derived from these minima based on * Stack sizes for individual tasks should be derived from these minima based on
* the maximum call depth of the task and the maximum level of interrupt nesting. * the maximum call depth of the task and the maximum level of interrupt nesting.
* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
* on the requirement for a task that calls nothing else but can be interrupted. * on the requirement for a task that calls nothing else but can be interrupted.
* This assumes that interrupt handlers do not call more than a few levels deep. * This assumes that interrupt handlers do not call more than a few levels deep.
* If this is not true, i.e. one or more interrupt handlers make deep calls then * If this is not true, i.e. one or more interrupt handlers make deep calls then
* the minimum must be increased. * the minimum must be increased.
* *
* If the Xtensa processor configuration includes coprocessors, then space is * If the Xtensa processor configuration includes coprocessors, then space is
* allocated to save the coprocessor state on the stack. * allocated to save the coprocessor state on the stack.
* *
* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
* is defined) then space is allocated to save the C library context in the TCB. * is defined) then space is allocated to save the C library context in the TCB.
* *
* Allocating insufficient stack space is a common source of hard-to-find errors. * Allocating insufficient stack space is a common source of hard-to-find errors.
* During development, it is best to enable the FreeRTOS stack checking features. * During development, it is best to enable the FreeRTOS stack checking features.
* *
* Usage: * Usage:
* *
* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
* use of the C library. This will require extra stack * use of the C library. This will require extra stack
* space to be allocated for tasks that use the C library * space to be allocated for tasks that use the C library
* reentrant functions. See below for more information. * reentrant functions. See below for more information.
* *
* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
* support thread safety. Check your core configuration to see which C library * support thread safety. Check your core configuration to see which C library
* was chosen for your system. * was chosen for your system.
* *
* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended * XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended
* that you do not use a stack smaller than this for any * that you do not use a stack smaller than this for any
* task. In case you want to use stacks smaller than this * task. In case you want to use stacks smaller than this
* size, you must verify that the smaller size(s) will work * size, you must verify that the smaller size(s) will work
* under all operating conditions. * under all operating conditions.
* *
* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task * XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task
* that does not make C library reentrant calls. Add this * that does not make C library reentrant calls. Add this
* to the amount of stack space required by the task itself. * to the amount of stack space required by the task itself.
* *
* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state. * XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state.
* *
* -----------------------------------------------------------------------------*/ * -----------------------------------------------------------------------------*/
/* Extra space required for interrupt/exception hooks. */ /* Extra space required for interrupt/exception hooks. */
#ifdef XT_INTEXC_HOOKS #ifdef XT_INTEXC_HOOKS
@ -143,9 +143,9 @@
#endif /* if XT_USE_THREAD_SAFE_CLIB > 0u */ #endif /* if XT_USE_THREAD_SAFE_CLIB > 0u */
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* Extra size -- interrupt frame plus coprocessor save area plus hook space. * Extra size -- interrupt frame plus coprocessor save area plus hook space.
* NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. * NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
* ------------------------------------------------------------------------------*/ * ------------------------------------------------------------------------------*/
#ifdef __XTENSA_CALL0_ABI__ #ifdef __XTENSA_CALL0_ABI__
#define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE ) #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
#else #else
@ -153,13 +153,13 @@
#endif #endif
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* Space allocated for user code -- function calls and local variables. * Space allocated for user code -- function calls and local variables.
* NOTE: This number can be adjusted to suit your needs. You must verify that the * NOTE: This number can be adjusted to suit your needs. You must verify that the
* amount of space you reserve is adequate for the worst-case conditions in your * amount of space you reserve is adequate for the worst-case conditions in your
* application. * application.
* NOTE: The windowed ABI requires more stack, since space has to be reserved * NOTE: The windowed ABI requires more stack, since space has to be reserved
* for spilling register windows. * for spilling register windows.
* ------------------------------------------------------------------------------*/ * ------------------------------------------------------------------------------*/
#ifdef __XTENSA_CALL0_ABI__ #ifdef __XTENSA_CALL0_ABI__
#define XT_USER_SIZE 0x200 #define XT_USER_SIZE 0x200
#else #else

1
portable/WizC/PIC18/portmacro.h
View file

@ -421,3 +421,4 @@ extern void vPortYield( void );
#endif /* PORTMACRO_H */ #endif /* PORTMACRO_H */