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Alfred Gedeon 2020-07-01 22:55:52 -07:00 • committed by alfred gedeon
parent 718178c68a
commit 2c530ba5c3
125 changed files with 1218 additions and 1217 deletions
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2
portable/RVDS/ARM7_LPC21xx/port.c
View file

@ -196,7 +196,7 @@ void vPortEndScheduler( void )
VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */
}
#else /* if configUSE_PREEMPTION == 0 */
#else /* if configUSE_PREEMPTION == 0 */
/*
**************************************************************************

2
portable/RVDS/ARM_CA9/port.c
View file

@ -92,7 +92,7 @@
#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
#define portPRIORITY_SHIFT 0
#define portMAX_BINARY_POINT_VALUE 0
#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */

16
portable/RVDS/ARM_CM0/port.c
View file

@ -187,16 +187,16 @@ __asm void prvPortStartFirstTask( void )
isb
pop {
r0 - r5
} /* Pop the registers that are saved automatically. */
} /* Pop the registers that are saved automatically. */
mov lr, r5 /* lr is now in r5. */
pop {
r3
} /* The return address is now in r3. */
} /* The return address is now in r3. */
pop {
r2
} /* Pop and discard the XPSR. */
} /* Pop and discard the XPSR. */
cpsie i /* The first task has its context and interrupts can be enabled. */
bx r3 /* Finally, jump to the user defined task code. */
bx r3 /* Finally, jump to the user defined task code. */
ALIGN
}
@ -299,7 +299,7 @@ __asm void xPortPendSVHandler( void )
str r0, [ r2 ] /* Save the new top of stack. */
stmia r0 !, {
r4 - r7
} /* Store the low registers that are not saved automatically. */
} /* Store the low registers that are not saved automatically. */
mov r4, r8 /* Store the high registers. */
mov r5, r9
mov r6, r10
@ -316,14 +316,14 @@ __asm void xPortPendSVHandler( void )
cpsie i
pop {
r2, r3
} /* lr goes in r3. r2 now holds tcb pointer. */
} /* lr goes in r3. r2 now holds tcb pointer. */
ldr r1, [ r2 ]
ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
adds r0, # 16 /* Move to the high registers. */
ldmia r0 !, {
r4 - r7
} /* Pop the high registers. */
} /* Pop the high registers. */
mov r8, r4
mov r9, r5
mov r10, r6
@ -334,7 +334,7 @@ __asm void xPortPendSVHandler( void )
subs r0, # 32 /* Go back for the low registers that are not automatically restored. */
ldmia r0 !, {
r4 - r7
} /* Pop low registers. */
} /* Pop low registers. */
bx r3
ALIGN

6
portable/RVDS/ARM_CM3/port.c
View file

@ -219,7 +219,7 @@ __asm void vPortSVCHandler( void )
ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
ldmia r0 !, {
r4 - r11
} /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
} /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
msr psp, r0 /* Restore the task stack pointer. */
isb
mov r0, # 0
@ -397,7 +397,7 @@ __asm void xPortPendSVHandler( void )
stmdb r0 !, {
r4 - r11
} /* Save the remaining registers. */
} /* Save the remaining registers. */
str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
stmdb sp !, {
@ -418,7 +418,7 @@ __asm void xPortPendSVHandler( void )
ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
ldmia r0 !, {
r4 - r11
} /* Pop the registers and the critical nesting count. */
} /* Pop the registers and the critical nesting count. */
msr psp, r0
isb
bx r14

6
portable/RVDS/ARM_CM3/portmacro.h
View file

@ -85,9 +85,9 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\
/* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\
__dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \
* within the specified behaviour for the architecture. */ \
__dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \
}
/*-----------------------------------------------------------*/

6
portable/RVDS/ARM_CM4F/portmacro.h
View file

@ -85,9 +85,9 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\
/* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\
__dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \
* within the specified behaviour for the architecture. */ \
__dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \
}
/*-----------------------------------------------------------*/

40
portable/RVDS/ARM_CM4_MPU/port.c
View file

@ -281,25 +281,25 @@ void prvSVCHandler( uint32_t * pulParam )
{
__asm
{
mrs ulReg, control /* Obtain current control value. */
bic ulReg, # 1 /* Set privilege bit. */
msr control, ulReg /* Write back new control value. */
mrs ulReg, control /* Obtain current control value. */
bic ulReg, # 1 /* Set privilege bit. */
msr control, ulReg /* Write back new control value. */
}
}
break;
#else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
#else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
case portSVC_RAISE_PRIVILEGE:
__asm
{
mrs ulReg, control /* Obtain current control value. */
bic ulReg, # 1 /* Set privilege bit. */
msr control, ulReg /* Write back new control value. */
mrs ulReg, control /* Obtain current control value. */
bic ulReg, # 1 /* Set privilege bit. */
msr control, ulReg /* Write back new control value. */
}
break;
#endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
default: /* Unknown SVC call. */
default: /* Unknown SVC call. */
break;
}
}
@ -346,10 +346,10 @@ __asm void prvRestoreContextOfFirstTask( void )
ldr r2, = 0xe000ed9c /* Region Base Address register. */
ldmia r1 !, {
r4 - r11
} /* Read 4 sets of MPU registers. */
} /* Read 4 sets of MPU registers. */
stmia r2 !, {
r4 - r11
} /* Write 4 sets of MPU registers. */
} /* Write 4 sets of MPU registers. */
ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
@ -359,7 +359,7 @@ __asm void prvRestoreContextOfFirstTask( void )
ldmia r0 !, {
r3 - r11, r14
} /* Pop the registers that are not automatically saved on exception entry. */
} /* Pop the registers that are not automatically saved on exception entry. */
msr control, r3
msr psp, r0 /* Restore the task stack pointer. */
mov r0, # 0
@ -555,7 +555,7 @@ __asm void xPortPendSVHandler( void )
mrs r1, control
stmdb r0 !, {
r1, r4 - r11, r14
} /* Save the remaining registers. */
} /* Save the remaining registers. */
str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
stmdb sp !, {
@ -585,10 +585,10 @@ __asm void xPortPendSVHandler( void )
ldr r2, = 0xe000ed9c /* Region Base Address register. */
ldmia r1 !, {
r4 - r11
} /* Read 4 sets of MPU registers. */
} /* Read 4 sets of MPU registers. */
stmia r2 !, {
r4 - r11
} /* Write 4 sets of MPU registers. */
} /* Write 4 sets of MPU registers. */
ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
@ -598,7 +598,7 @@ __asm void xPortPendSVHandler( void )
ldmia r0 !, {
r3 - r11, r14
} /* Pop the registers that are not automatically saved on exception entry. */
} /* Pop the registers that are not automatically saved on exception entry. */
msr control, r3
tst r14, # 0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
@ -801,7 +801,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
{
/* No MPU regions are specified so allow access to all RAM. */
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
( portSTACK_REGION );
@ -814,7 +814,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
* just removed the privileged only parameters. */
xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
( portSTACK_REGION + 1 );
@ -843,10 +843,10 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
( ( uint32_t ) pxBottomOfStack ) |
( portMPU_REGION_VALID ) |
( portSTACK_REGION ); /* Region number. */
( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) | /* Read and write. */
( portMPU_REGION_READ_WRITE ) | /* Read and write. */
( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( portMPU_REGION_ENABLE );
@ -864,7 +864,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
( portMPU_REGION_VALID ) |
( portSTACK_REGION + ul ); /* Region number. */
( portSTACK_REGION + ul ); /* Region number. */
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |

6
portable/RVDS/ARM_CM4_MPU/portmacro.h
View file

@ -129,9 +129,9 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\
/* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\
__dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \
* within the specified behaviour for the architecture. */ \
__dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \
}
/*-----------------------------------------------------------*/

6
portable/RVDS/ARM_CM7/r0p1/portmacro.h
View file

@ -85,9 +85,9 @@
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\
/* Barriers are normally not required but do ensure the code is completely \
* within the specified behaviour for the architecture. */\
__dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \
* within the specified behaviour for the architecture. */ \
__dsb( portSY_FULL_READ_WRITE ); \
__isb( portSY_FULL_READ_WRITE ); \
}
/*-----------------------------------------------------------*/