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Style: uncrustify
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parent
718178c68a
commit
2c530ba5c3
125 changed files with 1218 additions and 1217 deletions
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@ -261,10 +261,10 @@ void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF
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static void prvPortStartFirstTask( void )
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{
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__asm {
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ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, [ r0 ]
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ldr r0, [ r0 ]
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msr msp, r0 /* Set the msp back to the start of the stack. */
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msr msp, r0 /* Set the msp back to the start of the stack. */
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/* Clear the bit that indicates the FPU is in use in case the FPU was used
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* before the scheduler was started - which would otherwise result in the
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@ -272,11 +272,11 @@ static void prvPortStartFirstTask( void )
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* registers. */
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mov r0, # 0
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msr control, r0
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cpsie i /* Globally enable interrupts. */
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cpsie i /* Globally enable interrupts. */
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cpsie f
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dsb
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isb
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svc # 0 /* System call to start first task. */
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svc # 0 /* System call to start first task. */
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nop
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};
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}
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@ -439,10 +439,10 @@ void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF
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mrs r0, psp
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isb
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ldr r3, = _pxCurrentTCB /* Get the location of the current TCB. */
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ldr r3, = _pxCurrentTCB /* Get the location of the current TCB. */
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ldr r2, [ r3 ]
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tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
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tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
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it eq
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vstmdbeq r0 !, ( s16 - s31 )
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@ -461,7 +461,7 @@ void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF
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msr basepri, r0
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ldm sp !, ( r0, r3 )
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ldr r1, [ r3 ] /* The first item in pxCurrentTCB is the task top of stack. */
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ldr r1, [ r3 ] /* The first item in pxCurrentTCB is the task top of stack. */
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ldr r0, [ r1 ]
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ldm r0 !, ( r4 - r11, r14 ) /* Pop the core registers. */
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@ -729,10 +729,10 @@ void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO
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static void vPortEnableVFP( void )
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{
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__asm {
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ldr r0, = 0xE000ED88 /* The FPU enable bits are in the CPACR. */
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ldr r0, = 0xE000ED88 /* The FPU enable bits are in the CPACR. */
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ldr r1, [ r0 ]
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orr r1, r1, # 0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */
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orr r1, r1, # 0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */
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str r1, [ r0 ]
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bx r14
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};
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@ -86,9 +86,9 @@
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
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\
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/* Barriers are normally not required but do ensure the code is completely \
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* within the specified behaviour for the architecture. */\
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__asm{ dsb }; \
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__asm{ isb }; \
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* within the specified behaviour for the architecture. */ \
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__asm{ dsb }; \
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__asm{ isb }; \
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}
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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