mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-01 11:53:53 -04:00
Style: uncrustify
This commit is contained in:
Alfred Gedeon
alfred gedeon
parent
718178c68a
commit
2c530ba5c3
125 changed files with 1218 additions and 1217 deletions
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@ -357,7 +357,7 @@ void vPortEndScheduler( void )
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Set_system_register( AVR32_COMPARE, lCycles );
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}
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#else /* if ( configTICK_USE_TC == 0 ) */
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#else /* if ( configTICK_USE_TC == 0 ) */
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__attribute__( ( __noinline__ ) ) static void prvClearTcInt( void )
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{
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AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr;
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@ -434,7 +434,7 @@ static void prvSetupTimerInterrupt( void )
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/* Start the timer/counter. */
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tc_start( tc, configTICK_TC_CHANNEL );
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}
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#else /* if ( configTICK_USE_TC == 1 ) */
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#else /* if ( configTICK_USE_TC == 1 ) */
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{
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INTC_register_interrupt( &vTick, AVR32_CORE_COMPARE_IRQ, INT0 );
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prvScheduleFirstTick();
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@ -382,122 +382,122 @@
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* NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
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*
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*/
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#define portSAVE_CONTEXT_SCALL() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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/* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
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/* If SR[M2:M0] == 001 */ \
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/* PC and SR are on the stack. */ \
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/* Else (other modes) */ \
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/* Nothing on the stack. */ \
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\
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/* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
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/* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
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/* in an interrupt|exception handler. */ \
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\
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__asm__ __volatile__ ( \
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/* in order to save R0-R7 */ \
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"sub sp, 6*4 \n\t" \
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/* Save R0..R7 */ \
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"stm --sp, r0-r7 \n\t" \
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\
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/* in order to save R8-R12 and LR */ \
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/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
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"sub r7, sp,-16*4 \n\t" \
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/* Copy PC and SR in other places in the stack. */ \
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#define portSAVE_CONTEXT_SCALL() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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/* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
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/* If SR[M2:M0] == 001 */ \
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/* PC and SR are on the stack. */ \
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/* Else (other modes) */ \
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/* Nothing on the stack. */ \
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\
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/* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
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/* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
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/* in an interrupt|exception handler. */ \
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\
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__asm__ __volatile__ ( \
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/* in order to save R0-R7 */ \
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"sub sp, 6*4 \n\t"\
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/* Save R0..R7 */ \
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"stm --sp, r0-r7 \n\t"\
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\
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/* in order to save R8-R12 and LR */ \
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/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
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"sub r7, sp,-16*4 \n\t"\
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/* Copy PC and SR in other places in the stack. */ \
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"ld.w r0, r7[-2*4] \n\t"/* Read SR */\
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"st.w r7[-8*4], r0 \n\t"/* Copy SR */\
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"ld.w r0, r7[-1*4] \n\t"/* Read PC */\
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"st.w r7[-7*4], r0 \n\t"/* Copy PC */\
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\
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/* Save R8..R12 and LR on the stack. */ \
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"stm --r7, r8-r12, lr \n\t" \
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\
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/* Arriving here we have the following stack organizations: */ \
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/* R8..R12, LR, PC, SR, R0..R7. */ \
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\
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/* Now we can finalize the save. */ \
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\
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/* Save ulCriticalNesting variable - R0 is overwritten */ \
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"mov r8, LO(%[ulCriticalNesting]) \n\t" \
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"orh r8, HI(%[ulCriticalNesting]) \n\t" \
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"ld.w r0, r8[0] \n\t" \
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"st.w --sp, r0" \
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: \
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:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
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); \
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\
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/* Disable the its which may cause a context switch (i.e. cause a change of */ \
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/* pxCurrentTCB). */ \
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/* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
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/* critical section because it is a global structure. */ \
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portENTER_CRITICAL(); \
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\
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/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
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__asm__ __volatile__ ( \
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"mov r8, LO(%[pxCurrentTCB]) \n\t" \
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"orh r8, HI(%[pxCurrentTCB]) \n\t" \
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"ld.w r0, r8[0] \n\t" \
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"st.w r0[0], sp" \
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: \
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:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
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); \
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\
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/* Save R8..R12 and LR on the stack. */ \
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"stm --r7, r8-r12, lr \n\t"\
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\
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/* Arriving here we have the following stack organizations: */ \
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/* R8..R12, LR, PC, SR, R0..R7. */ \
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\
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/* Now we can finalize the save. */ \
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\
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/* Save ulCriticalNesting variable - R0 is overwritten */ \
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"mov r8, LO(%[ulCriticalNesting]) \n\t"\
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"orh r8, HI(%[ulCriticalNesting]) \n\t"\
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"ld.w r0, r8[0] \n\t"\
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"st.w --sp, r0" \
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: \
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:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
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); \
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\
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/* Disable the its which may cause a context switch (i.e. cause a change of */ \
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/* pxCurrentTCB). */ \
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/* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
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/* critical section because it is a global structure. */ \
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portENTER_CRITICAL(); \
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\
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/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
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__asm__ __volatile__ ( \
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"mov r8, LO(%[pxCurrentTCB]) \n\t"\
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"orh r8, HI(%[pxCurrentTCB]) \n\t"\
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"ld.w r0, r8[0] \n\t"\
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"st.w r0[0], sp" \
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: \
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:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
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); \
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}
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/*
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* portRESTORE_CONTEXT() for SupervisorCALL exception.
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*/
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#define portRESTORE_CONTEXT_SCALL() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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/* Restore all registers */ \
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\
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/* Set SP to point to new stack */ \
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__asm__ __volatile__ ( \
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"mov r8, LO(%[pxCurrentTCB]) \n\t" \
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"orh r8, HI(%[pxCurrentTCB]) \n\t" \
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"ld.w r0, r8[0] \n\t" \
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"ld.w sp, r0[0]" \
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: \
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:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
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); \
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\
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/* Leave pxCurrentTCB variable access critical section */ \
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portEXIT_CRITICAL(); \
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\
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__asm__ __volatile__ ( \
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/* Restore ulCriticalNesting variable */ \
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"ld.w r0, sp++ \n\t" \
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"mov r8, LO(%[ulCriticalNesting]) \n\t" \
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"orh r8, HI(%[ulCriticalNesting]) \n\t" \
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"st.w r8[0], r0 \n\t" \
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\
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/* skip PC and SR */ \
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/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
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"sub r7, sp, -10*4 \n\t" \
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/* Restore r8-r12 and LR */ \
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"ldm r7++, r8-r12, lr \n\t" \
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\
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/* RETS will take care of the extra PC and SR restore. */ \
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/* So, we have to prepare the stack for this. */ \
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#define portRESTORE_CONTEXT_SCALL() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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/* Restore all registers */ \
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\
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/* Set SP to point to new stack */ \
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__asm__ __volatile__ ( \
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"mov r8, LO(%[pxCurrentTCB]) \n\t"\
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"orh r8, HI(%[pxCurrentTCB]) \n\t"\
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"ld.w r0, r8[0] \n\t"\
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"ld.w sp, r0[0]" \
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: \
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:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
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); \
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\
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/* Leave pxCurrentTCB variable access critical section */ \
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portEXIT_CRITICAL(); \
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\
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__asm__ __volatile__ ( \
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/* Restore ulCriticalNesting variable */ \
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"ld.w r0, sp++ \n\t"\
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"mov r8, LO(%[ulCriticalNesting]) \n\t"\
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"orh r8, HI(%[ulCriticalNesting]) \n\t"\
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"st.w r8[0], r0 \n\t"\
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\
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/* skip PC and SR */ \
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/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
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"sub r7, sp, -10*4 \n\t"\
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/* Restore r8-r12 and LR */ \
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"ldm r7++, r8-r12, lr \n\t"\
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\
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/* RETS will take care of the extra PC and SR restore. */ \
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/* So, we have to prepare the stack for this. */ \
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"ld.w r0, r7[-8*4] \n\t"/* Read SR */\
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"st.w r7[-2*4], r0 \n\t"/* Copy SR */\
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"ld.w r0, r7[-7*4] \n\t"/* Read PC */\
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"st.w r7[-1*4], r0 \n\t"/* Copy PC */\
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\
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/* Restore R0..R7 */ \
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"ldm sp++, r0-r7 \n\t" \
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\
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"sub sp, -6*4 \n\t" \
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\
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"rets" \
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: \
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:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
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); \
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\
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/* Restore R0..R7 */ \
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"ldm sp++, r0-r7 \n\t"\
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\
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"sub sp, -6*4 \n\t"\
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\
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"rets" \
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: \
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:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
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); \
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}
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@ -541,115 +541,115 @@
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* ISR entry and exit macros. These are only required if a task switch
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* is required from the ISR.
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*/
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#define portENTER_SWITCHING_ISR() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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/* When we come here */ \
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/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
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\
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__asm__ __volatile__ ( \
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/* Save R0..R7 */ \
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"stm --sp, r0-r7 \n\t" \
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\
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/* Save ulCriticalNesting variable - R0 is overwritten */ \
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"mov r8, LO(%[ulCriticalNesting]) \n\t" \
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"orh r8, HI(%[ulCriticalNesting]) \n\t" \
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"ld.w r0, r8[0] \n\t" \
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"st.w --sp, r0 \n\t" \
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\
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/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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/* level and allow other lower interrupt level to occur). */ \
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/* In this case we don't want to do a task switch because we don't know what the stack */ \
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/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
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/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
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/* will just be restoring the interrupt handler, no way!!! */ \
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/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
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"ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \
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"bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \
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#define portENTER_SWITCHING_ISR() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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/* When we come here */ \
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/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
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\
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__asm__ __volatile__ ( \
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/* Save R0..R7 */ \
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"stm --sp, r0-r7 \n\t" \
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\
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/* Save ulCriticalNesting variable - R0 is overwritten */ \
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"mov r8, LO(%[ulCriticalNesting]) \n\t" \
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"orh r8, HI(%[ulCriticalNesting]) \n\t" \
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"ld.w r0, r8[0] \n\t" \
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"st.w --sp, r0 \n\t" \
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\
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/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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/* level and allow other lower interrupt level to occur). */ \
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/* In this case we don't want to do a task switch because we don't know what the stack */ \
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/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
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/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
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/* will just be restoring the interrupt handler, no way!!! */ \
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/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
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"ld.w r0, sp[9*4] \n\t"/* Read SR in stack */\
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"bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */\
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"cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\
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"brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \
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\
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/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
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"mov r8, LO(%[pxCurrentTCB]) \n\t" \
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"orh r8, HI(%[pxCurrentTCB]) \n\t" \
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"ld.w r0, r8[0] \n\t" \
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"st.w r0[0], sp \n" \
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\
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"LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
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: \
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:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
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[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
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[ LINE ] "i" ( __LINE__ ) \
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); \
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"brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \
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\
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/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
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"mov r8, LO(%[pxCurrentTCB]) \n\t" \
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"orh r8, HI(%[pxCurrentTCB]) \n\t" \
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"ld.w r0, r8[0] \n\t" \
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"st.w r0[0], sp \n" \
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\
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"LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
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: \
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:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
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[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
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[ LINE ] "i" ( __LINE__ ) \
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); \
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}
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/*
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* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
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*/
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#define portEXIT_SWITCHING_ISR() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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__asm__ __volatile__ ( \
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/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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/* level and allow other lower interrupt level to occur). */ \
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/* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
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/* did not previously save SP in its TCB. */ \
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"ld.w r0, sp[9*4] \n\t"/* Read SR in stack */ \
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"bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */ \
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#define portEXIT_SWITCHING_ISR() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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__asm__ __volatile__ ( \
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/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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/* level and allow other lower interrupt level to occur). */ \
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/* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
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/* did not previously save SP in its TCB. */ \
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"ld.w r0, sp[9*4] \n\t"/* Read SR in stack */\
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"bfextu r0, r0, 22, 3 \n\t"/* Extract the mode bits to R0. */\
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"cp.w r0, 1 \n\t"/* Compare the mode bits with supervisor mode(b'001) */\
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"brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \
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\
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/* If a switch is required then we just need to call */ \
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/* vTaskSwitchContext() as the context has already been */ \
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/* saved. */ \
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"cp.w r12, 1 \n\t"/* Check if Switch context is required. */ \
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"brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
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: \
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:[ LINE ] "i" ( __LINE__ ) \
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); \
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\
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/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
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portENTER_CRITICAL(); \
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vTaskSwitchContext(); \
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portEXIT_CRITICAL(); \
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\
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__asm__ __volatile__ ( \
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"LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t" \
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/* Restore the context of which ever task is now the highest */ \
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/* priority that is ready to run. */ \
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\
|
||||
/* Restore all registers */ \
|
||||
\
|
||||
/* Set SP to point to new stack */ \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
|
||||
"ld.w r0, r8[0] \n\t" \
|
||||
"ld.w sp, r0[0] \n" \
|
||||
\
|
||||
"LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \
|
||||
\
|
||||
/* Restore ulCriticalNesting variable */ \
|
||||
"ld.w r0, sp++ \n\t" \
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
|
||||
"st.w r8[0], r0 \n\t" \
|
||||
\
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t" \
|
||||
\
|
||||
/* Now, the stack should be R8..R12, LR, PC and SR */ \
|
||||
"rete" \
|
||||
: \
|
||||
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
|
||||
[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
|
||||
[ LINE ] "i" ( __LINE__ ) \
|
||||
); \
|
||||
"brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \
|
||||
\
|
||||
/* If a switch is required then we just need to call */ \
|
||||
/* vTaskSwitchContext() as the context has already been */ \
|
||||
/* saved. */ \
|
||||
"cp.w r12, 1 \n\t"/* Check if Switch context is required. */\
|
||||
"brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
|
||||
: \
|
||||
:[ LINE ] "i" ( __LINE__ ) \
|
||||
); \
|
||||
\
|
||||
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
|
||||
portENTER_CRITICAL(); \
|
||||
vTaskSwitchContext(); \
|
||||
portEXIT_CRITICAL(); \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
"LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t" \
|
||||
/* Restore the context of which ever task is now the highest */ \
|
||||
/* priority that is ready to run. */ \
|
||||
\
|
||||
/* Restore all registers */ \
|
||||
\
|
||||
/* Set SP to point to new stack */ \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
|
||||
"ld.w r0, r8[0] \n\t" \
|
||||
"ld.w sp, r0[0] \n" \
|
||||
\
|
||||
"LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \
|
||||
\
|
||||
/* Restore ulCriticalNesting variable */ \
|
||||
"ld.w r0, sp++ \n\t" \
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
|
||||
"st.w r8[0], r0 \n\t" \
|
||||
\
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t" \
|
||||
\
|
||||
/* Now, the stack should be R8..R12, LR, PC and SR */ \
|
||||
"rete" \
|
||||
: \
|
||||
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
|
||||
[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
|
||||
[ LINE ] "i" ( __LINE__ ) \
|
||||
); \
|
||||
}
|
||||
|
||||
#endif /* if configUSE_PREEMPTION == 0 */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue