mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 09:38:32 -04:00
Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the 18.1 version of the Xilinx SDK - building BUT NOT YET TESTED.
This commit is contained in:
Richard Barry
parent
a3148ba638
commit
26d8c76996
827 changed files with 236693 additions and 152370 deletions
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@ -57,7 +57,7 @@
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</linkedResources>
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<filteredResources>
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<filter>
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<id>1461592609781</id>
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<id>1525142482332</id>
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<name>src/FreeRTOS_Source</name>
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<type>5</type>
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||||
<matcher>
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@ -66,7 +66,7 @@
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</matcher>
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||||
</filter>
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<filter>
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<id>1461592609791</id>
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<id>1525142482336</id>
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<name>src/FreeRTOS_Source</name>
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<type>5</type>
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<matcher>
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@ -75,7 +75,7 @@
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</matcher>
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||||
</filter>
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||||
<filter>
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||||
<id>1461592609811</id>
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<id>1525142482342</id>
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<name>src/FreeRTOS_Source</name>
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<type>5</type>
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||||
<matcher>
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||||
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@ -84,7 +84,7 @@
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|||
</matcher>
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||||
</filter>
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||||
<filter>
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||||
<id>1461592609821</id>
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<id>1525142482346</id>
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<name>src/FreeRTOS_Source</name>
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<type>5</type>
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<matcher>
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@ -93,7 +93,7 @@
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</matcher>
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||||
</filter>
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||||
<filter>
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||||
<id>1461592609921</id>
|
||||
<id>1525142482352</id>
|
||||
<name>src/FreeRTOS_Source</name>
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||||
<type>5</type>
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||||
<matcher>
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@ -102,7 +102,7 @@
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|||
</matcher>
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||||
</filter>
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<filter>
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||||
<id>1461592609921</id>
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||||
<id>1525142482356</id>
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<name>src/FreeRTOS_Source</name>
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<type>5</type>
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||||
<matcher>
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@ -111,7 +111,7 @@
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|||
</matcher>
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||||
</filter>
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||||
<filter>
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||||
<id>1461592609931</id>
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<id>1525142482360</id>
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<name>src/FreeRTOS_Source</name>
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<type>9</type>
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||||
<matcher>
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||||
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@ -120,7 +120,7 @@
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|||
</matcher>
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</filter>
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<filter>
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<id>1461592609941</id>
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<id>1525142482364</id>
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<name>src/FreeRTOS_Source</name>
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<type>9</type>
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||||
<matcher>
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@ -128,6 +128,15 @@
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<arguments>1.0-name-matches-false-false-portable</arguments>
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</matcher>
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</filter>
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<filter>
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<id>1525142482368</id>
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<name>src/FreeRTOS_Source</name>
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<type>5</type>
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<matcher>
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<id>org.eclipse.ui.ide.multiFilter</id>
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<arguments>1.0-name-matches-false-false-stream_buffer.c</arguments>
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</matcher>
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</filter>
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<filter>
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<id>1461592643370</id>
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<name>src/FreeRTOS_Source/portable</name>
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@ -127,6 +127,7 @@ to exclude the API function. */
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#define INCLUDE_xTaskAbortDelay 1
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#define INCLUDE_xTaskGetTaskHandle 1
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#define INCLUDE_xTaskGetHandle 1
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#define INCLUDE_xSemaphoreGetMutexHolder 1
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/* This demo makes use of one or more example stats formatting functions. These
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format the raw data provided by the uxTaskGetSystemState() function in to human
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@ -309,4 +309,7 @@ a lot of data that needs to be copied, this should be set high. */
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#define LWIP_NETIF_STATUS_CALLBACK 1
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/* Prevent conflict with struct timeval from compiler's library. */
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#define LWIP_TIMEVAL_PRIVATE 0
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#endif /* __LWIPOPTS_H__ */
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@ -1,8 +1,8 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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<storageModule moduleId="org.eclipse.cdt.core.settings">
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<cconfiguration id="org.eclipse.cdt.core.default.config.905492093">
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<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.905492093" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
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<cconfiguration id="org.eclipse.cdt.core.default.config.1763378738">
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<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1763378738" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
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<externalSettings/>
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<extensions/>
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</storageModule>
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@ -1,7 +1,7 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
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<name>RTOSDemo_bsp</name>
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<comment>Created by SDK v2016.1</comment>
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<comment>Created by SDK v2018.1</comment>
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<projects>
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</projects>
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<buildSpec>
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@ -16,16 +16,20 @@ include: $(addsuffix /make.include,$(SUBDIRS))
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libs: $(addsuffix /make.libs,$(SUBDIRS))
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clean: $(addsuffix /make.clean,$(SUBDIRS))
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$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
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cp -f $< $@
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%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
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@echo "Running Make include in $(subst /make.include,,$@)"
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$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles"
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$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
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%/make.libs: include
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@echo "Running Make libs in $(subst /make.libs,,$@)"
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$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles"
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$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
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%/make.clean:
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$(MAKE) -C $(subst /make.clean,,$@) -s clean
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clean:
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rm -f ${PROCESSOR}/lib/libxil.a
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@ -1,5 +1,8 @@
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#ifndef XPARAMETERS_H /* prevent circular inclusions */
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#define XPARAMETERS_H /* by using protection macros */
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/* Definition for CPU ID */
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#define XPAR_CPU_ID 0
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#define XPAR_CPU_ID 0U
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/* Definitions for peripheral PS7_CORTEXA9_0 */
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#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
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@ -20,6 +23,14 @@
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/******************************************************************/
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/* Platform specific definitions */
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#define PLATFORM_ZYNQ
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/* Definitions for sleep timer configuration */
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#define XSLEEP_TIMER_IS_DEFAULT_TIMER
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/******************************************************************/
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/* Definitions for driver CANPS */
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#define XPAR_XCANPS_NUM_INSTANCES 1
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@ -50,20 +61,20 @@
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/******************************************************************/
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/* Definitions for driver DEVCFG */
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#define XPAR_XDCFG_NUM_INSTANCES 1
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#define XPAR_XDCFG_NUM_INSTANCES 1U
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/* Definitions for peripheral PS7_DEV_CFG_0 */
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#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
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#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
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#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
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#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
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#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
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#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
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#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
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#define XPAR_XDCFG_0_BASEADDR 0xF8007000
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#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
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#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
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#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
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/******************************************************************/
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@ -112,10 +123,12 @@
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#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
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#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
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#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
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#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0
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/******************************************************************/
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#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0
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/* Canonical definitions for peripheral PS7_ETHERNET_0 */
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#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
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#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
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@ -127,6 +140,7 @@
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#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
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#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
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#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
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#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0
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/******************************************************************/
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@ -275,6 +289,7 @@
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#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
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#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
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#define XPAR_PS7_QSPI_0_QSPI_MODE 0
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#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
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/******************************************************************/
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@ -285,27 +300,28 @@
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#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
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#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
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#define XPAR_XQSPIPS_0_QSPI_MODE 0
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#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
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/******************************************************************/
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/* Definitions for driver SCUGIC */
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#define XPAR_XSCUGIC_NUM_INSTANCES 1
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#define XPAR_XSCUGIC_NUM_INSTANCES 1U
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/* Definitions for peripheral PS7_SCUGIC_0 */
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#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
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#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
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#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
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#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
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#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
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#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
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#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
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#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_SCUGIC_0 */
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#define XPAR_SCUGIC_0_DEVICE_ID 0
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#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
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#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
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#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
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#define XPAR_SCUGIC_0_DEVICE_ID 0U
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#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
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#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
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#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
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/******************************************************************/
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#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
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#define XPAR_PS7_SD_0_HAS_CD 1
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#define XPAR_PS7_SD_0_HAS_WP 1
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#define XPAR_PS7_SD_0_BUS_WIDTH 0
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#define XPAR_PS7_SD_0_MIO_BANK 0
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#define XPAR_PS7_SD_0_HAS_EMIO 0
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/******************************************************************/
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#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0
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/* Canonical definitions for peripheral PS7_SD_0 */
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#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
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#define XPAR_XSDPS_0_BASEADDR 0xE0100000
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@ -369,45 +389,48 @@
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#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
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#define XPAR_XSDPS_0_HAS_CD 1
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#define XPAR_XSDPS_0_HAS_WP 1
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#define XPAR_XSDPS_0_BUS_WIDTH 0
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#define XPAR_XSDPS_0_MIO_BANK 0
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#define XPAR_XSDPS_0_HAS_EMIO 0
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/******************************************************************/
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/* Definitions for driver TTCPS */
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#define XPAR_XTTCPS_NUM_INSTANCES 3
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#define XPAR_XTTCPS_NUM_INSTANCES 3U
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/* Definitions for peripheral PS7_TTC_0 */
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#define XPAR_PS7_TTC_0_DEVICE_ID 0
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#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
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#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
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#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
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#define XPAR_PS7_TTC_1_DEVICE_ID 1
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#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
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#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
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#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
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#define XPAR_PS7_TTC_2_DEVICE_ID 2
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#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
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#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
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#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
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#define XPAR_PS7_TTC_0_DEVICE_ID 0U
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#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U
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#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U
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#define XPAR_PS7_TTC_1_DEVICE_ID 1U
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#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U
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#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U
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#define XPAR_PS7_TTC_2_DEVICE_ID 2U
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#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U
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#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_TTC_0 */
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#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
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#define XPAR_XTTCPS_0_BASEADDR 0xF8001000
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#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115
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#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0
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#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U
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#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
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#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
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#define XPAR_XTTCPS_1_BASEADDR 0xF8001004
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#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115
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#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0
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#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U
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#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
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#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
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#define XPAR_XTTCPS_2_BASEADDR 0xF8001008
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#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115
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#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0
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#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U
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#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
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/******************************************************************/
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@ -473,3 +496,4 @@
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/******************************************************************/
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#endif /* end of protection macro */
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|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xcanps.c
|
||||
* @addtogroup canps_v3_0
|
||||
* @addtogroup canps_v3_2
|
||||
* @{
|
||||
*
|
||||
* Functions in this file are the minimum required functions for the XCanPs
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xcanps.h
|
||||
* @addtogroup canps_v3_0
|
||||
* @addtogroup canps_v3_2
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
|
|
@ -204,6 +204,8 @@
|
|||
* Data mismatch while sending data less than 8 bytes.
|
||||
* 3.1 nsk 12/21/15 Updated XCanPs_IntrHandler in xcanps_intr.c to handle
|
||||
* error interrupts correctly. CR#925615
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
|
||||
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XCanPs_Config XCanPs_ConfigTable[] =
|
||||
XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PS7_CAN_0_DEVICE_ID,
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xcanps_hw.c
|
||||
* @addtogroup canps_v3_0
|
||||
* @addtogroup canps_v3_2
|
||||
* @{
|
||||
*
|
||||
* This file contains the implementation of the canps interface reset sequence
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xcanps_hw.h
|
||||
* @addtogroup canps_v3_0
|
||||
* @addtogroup canps_v3_2
|
||||
* @{
|
||||
*
|
||||
* This header file contains the identifiers and basic driver functions (or
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xcanps_intr.c
|
||||
* @addtogroup canps_v3_0
|
||||
* @addtogroup canps_v3_2
|
||||
* @{
|
||||
*
|
||||
* This file contains functions related to CAN interrupt handling.
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xcanps_selftest.c
|
||||
* @addtogroup canps_v3_0
|
||||
* @addtogroup canps_v3_2
|
||||
* @{
|
||||
*
|
||||
* This file contains a diagnostic self-test function for the XCanPs driver.
|
||||
|
|
@ -166,7 +166,7 @@ s32 XCanPs_SelfTest(XCanPs *InstancePtr)
|
|||
for (Index = 0U; Index < 8U; Index++) {
|
||||
if(*FramePtr != 0U) {
|
||||
*FramePtr = (u8)Index;
|
||||
*FramePtr++;
|
||||
FramePtr++;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xcanps_sinit.c
|
||||
* @addtogroup canps_v3_0
|
||||
* @addtogroup canps_v3_2
|
||||
* @{
|
||||
*
|
||||
* This file contains the implementation of the XCanPs driver's static
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2015-2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xcoresightpsdcc.c
|
||||
* @addtogroup coresightps_dcc_v1_1
|
||||
* @addtogroup coresightps_dcc_v1_4
|
||||
* @{
|
||||
*
|
||||
* Functions in this file are the minimum required functions for the
|
||||
|
|
@ -51,12 +51,18 @@
|
|||
* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
|
||||
* kvn 08/18/15 Modified Makefile according to compiler changes.
|
||||
* 1.2 kvn 10/09/15 Add support for IAR Compiler.
|
||||
* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
|
||||
* for MB BSPs. Instead it throws up a warning. This
|
||||
* fixes the CR#953056.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#ifdef __MICROBLAZE__
|
||||
#warning "The driver is supported only for ARM architecture"
|
||||
#else
|
||||
|
||||
#include <xil_types.h>
|
||||
#include <xpseudo_asm.h>
|
||||
|
|
@ -126,7 +132,7 @@ void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
|
|||
******************************************************************************/
|
||||
u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
|
||||
{
|
||||
u8 Data;
|
||||
u8 Data = 0U;
|
||||
(void) BaseAddress;
|
||||
|
||||
while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
|
||||
|
|
@ -163,7 +169,7 @@ u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
|
|||
******************************************************************************/
|
||||
static INLINE u32 XCoresightPs_DccGetStatus(void)
|
||||
{
|
||||
u32 Status;
|
||||
u32 Status = 0U;
|
||||
|
||||
#ifdef __aarch64__
|
||||
asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
|
||||
|
|
@ -177,5 +183,6 @@ static INLINE u32 XCoresightPs_DccGetStatus(void)
|
|||
}
|
||||
#endif
|
||||
return Status;
|
||||
#endif
|
||||
}
|
||||
/** @} */
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xcoresightpsdcc.h
|
||||
* @addtogroup coresightps_dcc_v1_1
|
||||
* @addtogroup coresightps_dcc_v1_4
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
|
|
@ -55,16 +55,20 @@
|
|||
* 1.00 kvn 02/14/15 First release
|
||||
* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
|
||||
* kvn 08/18/15 Modified Makefile according to compiler changes.
|
||||
* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
|
||||
* for MB BSPs. Instead it throws up a warning. This
|
||||
* fixes the CR#953056.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#ifndef __MICROBLAZE__
|
||||
#include <xil_types.h>
|
||||
|
||||
void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
|
||||
|
||||
u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
|
||||
#endif
|
||||
/** @} */
|
||||
|
|
@ -10,7 +10,7 @@ INCLUDEDIR=../../../include
|
|||
INCLUDES=-I${INCLUDEDIR}
|
||||
|
||||
OUTS = *.o
|
||||
|
||||
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
|
||||
LIBSOURCES=*.c
|
||||
INCLUDEFILES=*.h
|
||||
|
||||
|
|
@ -21,3 +21,5 @@ libs:
|
|||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
|
||||
clean:
|
||||
rm -rf ${OBJECTS}
|
||||
|
|
@ -33,11 +33,16 @@
|
|||
/**
|
||||
*
|
||||
* @file xcpu_cortexa9.h
|
||||
* @addtogroup cpu_cortexa9_v2_1
|
||||
* @addtogroup cpu_cortexa9_v2_5
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
* dummy file
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------------
|
||||
* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
|
||||
* parameter of cpu_cortexa9 in xparameters.h
|
||||
******************************************************************************/
|
||||
/** @} */
|
||||
|
|
@ -18,8 +18,8 @@
|
|||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdevcfg.c
|
||||
* @addtogroup devcfg_v3_3
|
||||
* @addtogroup devcfg_v3_5
|
||||
* @{
|
||||
*
|
||||
* This file contains the implementation of the interface functions for XDcfg
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdevcfg.h
|
||||
* @addtogroup devcfg_v3_3
|
||||
* @addtogroup devcfg_v3_5
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
|
|
@ -152,7 +152,13 @@
|
|||
* configuration registers from the PL region.
|
||||
* xdevcfg_reg_readback_example.c
|
||||
* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
|
||||
*
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* ms 04/10/17 Modified filename tag in interrupt and polled examples
|
||||
* to include them in doxygen examples.
|
||||
* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
|
||||
* definitions of devcfg in xparameters.h
|
||||
* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
|
||||
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdevcfg_hw.c
|
||||
* @addtogroup devcfg_v3_3
|
||||
* @addtogroup devcfg_v3_5
|
||||
* @{
|
||||
*
|
||||
* This file contains the implementation of the interface reset functionality
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdevcfg_intr.c
|
||||
* @addtogroup devcfg_v3_3
|
||||
* @addtogroup devcfg_v3_5
|
||||
* @{
|
||||
*
|
||||
* Contains the implementation of interrupt related functions of the XDcfg
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdevcfg_selftest.c
|
||||
* @addtogroup devcfg_v3_3
|
||||
* @addtogroup devcfg_v3_5
|
||||
* @{
|
||||
*
|
||||
* Contains diagnostic self-test functions for the XDcfg driver.
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdevcfg_sinit.c
|
||||
* @addtogroup devcfg_v3_3
|
||||
* @addtogroup devcfg_v3_5
|
||||
* @{
|
||||
*
|
||||
* This file contains method for static initialization (compile-time) of the
|
||||
|
|
@ -45,6 +45,7 @@
|
|||
* Ver Who Date Changes
|
||||
* ----- --- -------- ---------------------------------------------
|
||||
* 1.00a hvm 02/07/11 First release
|
||||
* 3.5 ms 08/07/17 Fixed compilation warnings.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
@ -79,9 +80,9 @@ XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
|
|||
{
|
||||
extern XDcfg_Config XDcfg_ConfigTable[];
|
||||
XDcfg_Config *CfgPtr = NULL;
|
||||
int Index;
|
||||
u32 Index;
|
||||
|
||||
for (Index = 0; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
|
||||
for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
|
||||
if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) {
|
||||
CfgPtr = &XDcfg_ConfigTable[Index];
|
||||
break;
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdmaps.c
|
||||
* @addtogroup dmaps_v2_1
|
||||
* @addtogroup dmaps_v2_3
|
||||
* @{
|
||||
*
|
||||
* This file contains the implementation of the interface functions for XDmaPs
|
||||
|
|
@ -67,6 +67,9 @@
|
|||
* the IARCC compiler around PDBG, it is better to remove it.
|
||||
* Users can always use xil_printfs if they want to debug.
|
||||
* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
|
||||
* 2.2 mus 12/08/16 Remove definition of INLINE macro to avoid re-definition,
|
||||
* since it is being defined in xil_io.h
|
||||
* 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used.
|
||||
* </pre>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
|
@ -93,11 +96,6 @@
|
|||
|
||||
/**************************** Type Definitions ******************************/
|
||||
|
||||
#ifdef __ICCARM__
|
||||
#define INLINE
|
||||
#else
|
||||
#define INLINE __inline
|
||||
#endif
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
|
||||
|
|
@ -418,7 +416,7 @@ int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE int XDmaPs_Instr_DMAEND(char *DmaProg)
|
||||
static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg)
|
||||
{
|
||||
/*
|
||||
* DMAEND encoding:
|
||||
|
|
@ -430,7 +428,7 @@ INLINE int XDmaPs_Instr_DMAEND(char *DmaProg)
|
|||
return 1;
|
||||
}
|
||||
|
||||
INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
|
||||
static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
|
||||
{
|
||||
*Dst = *Src;
|
||||
*(Dst + 1) = *(Src + 1);
|
||||
|
|
@ -461,7 +459,7 @@ INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
|
|||
* @note None
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
|
||||
static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
|
||||
u32 Imm, unsigned int Ns)
|
||||
{
|
||||
/*
|
||||
|
|
@ -497,7 +495,7 @@ INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
|
||||
static INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
|
||||
{
|
||||
/*
|
||||
* DMALD encoding
|
||||
|
|
@ -528,7 +526,7 @@ INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
|
||||
static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
|
||||
unsigned LoopIterations)
|
||||
{
|
||||
/*
|
||||
|
|
@ -558,7 +556,7 @@ INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc)
|
||||
static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc)
|
||||
{
|
||||
/*
|
||||
* DMALPEND encoding
|
||||
|
|
@ -599,7 +597,7 @@ INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc)
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm)
|
||||
static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm)
|
||||
{
|
||||
/*
|
||||
* DMAMOV encoding
|
||||
|
|
@ -632,7 +630,7 @@ INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm)
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE int XDmaPs_Instr_DMANOP(char *DmaProg)
|
||||
static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg)
|
||||
{
|
||||
/*
|
||||
* DMANOP encoding
|
||||
|
|
@ -657,7 +655,7 @@ INLINE int XDmaPs_Instr_DMANOP(char *DmaProg)
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE int XDmaPs_Instr_DMARMB(char *DmaProg)
|
||||
static INLINE int XDmaPs_Instr_DMARMB(char *DmaProg)
|
||||
{
|
||||
/*
|
||||
* DMARMB encoding
|
||||
|
|
@ -683,7 +681,7 @@ INLINE int XDmaPs_Instr_DMARMB(char *DmaProg)
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber)
|
||||
static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber)
|
||||
{
|
||||
/*
|
||||
* DMASEV encoding
|
||||
|
|
@ -711,7 +709,7 @@ INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber)
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE int XDmaPs_Instr_DMAST(char *DmaProg)
|
||||
static INLINE int XDmaPs_Instr_DMAST(char *DmaProg)
|
||||
{
|
||||
/*
|
||||
* DMAST encoding
|
||||
|
|
@ -740,7 +738,7 @@ INLINE int XDmaPs_Instr_DMAST(char *DmaProg)
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg)
|
||||
static INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg)
|
||||
{
|
||||
/*
|
||||
* DMAWMB encoding
|
||||
|
|
@ -764,7 +762,7 @@ INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg)
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
|
||||
static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
|
||||
{
|
||||
switch (EndianSwapSize) {
|
||||
case 0:
|
||||
|
|
@ -797,7 +795,7 @@ INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
|
|||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize)
|
||||
static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize)
|
||||
{
|
||||
switch (BurstSize) {
|
||||
case 1:
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdmaps.h
|
||||
* @addtogroup dmaps_v2_1
|
||||
* @addtogroup dmaps_v2_3
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
|
|
@ -75,6 +75,14 @@
|
|||
* Users can always use xil_printfs if they want to debug.
|
||||
* 2.0 adk 10/12/13 Updated as per the New Tcl API's
|
||||
* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
|
||||
* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
|
||||
* linker error for IAR compiler
|
||||
* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
|
||||
* examples to ensure that "Successfully ran" and "Failed"
|
||||
* strings are available in all examples. This is a fix
|
||||
* for CR-965028.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* </pre>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
|
@ -281,6 +289,29 @@ int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
|
|||
|
||||
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
|
||||
|
||||
/**
|
||||
* To avoid linking error,Declare all inline functions as extern for
|
||||
* IAR compiler
|
||||
*/
|
||||
#ifdef __ICCARM__
|
||||
extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
|
||||
extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
|
||||
extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
|
||||
u32 Imm, unsigned int Ns);
|
||||
extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
|
||||
extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
|
||||
unsigned LoopIterations);
|
||||
extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
|
||||
extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
|
||||
extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
|
||||
extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg);
|
||||
extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
|
||||
extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
|
||||
extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg);
|
||||
extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
|
||||
extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Driver done interrupt service routines for the channels.
|
||||
* We need this done ISR mainly because the driver needs to release the
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
|
||||
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XDmaPs_Config XDmaPs_ConfigTable[] =
|
||||
XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PS7_DMA_NS_DEVICE_ID,
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdmaps_hw.c
|
||||
* @addtogroup dmaps_v2_1
|
||||
* @addtogroup dmaps_v2_3
|
||||
* @{
|
||||
*
|
||||
* This file contains the implementation of the interface reset functionality
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdmaps_hw.h
|
||||
* @addtogroup dmaps_v2_1
|
||||
* @addtogroup dmaps_v2_3
|
||||
* @{
|
||||
*
|
||||
* This header file contains the hardware interface of an XDmaPs device.
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdmaps_selftest.c
|
||||
* @addtogroup dmaps_v2_1
|
||||
* @addtogroup dmaps_v2_3
|
||||
* @{
|
||||
*
|
||||
* This file contains the self-test functions for the XDmaPs driver.
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xdmaps_sinit.c
|
||||
* @addtogroup dmaps_v2_1
|
||||
* @addtogroup dmaps_v2_3
|
||||
* @{
|
||||
*
|
||||
* The implementation of the XDmaPs driver's static initialzation
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xemacps.c
|
||||
* @addtogroup emacps_v3_1
|
||||
* @addtogroup emacps_v3_7
|
||||
* @{
|
||||
*
|
||||
* The XEmacPs driver. Functions in this file are the minimum required functions
|
||||
|
|
@ -52,6 +52,8 @@
|
|||
* Disable extended mode. Perform all 64 bit changes under
|
||||
* check for arch64.
|
||||
* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers
|
||||
* 3.5 hk 08/14/17 Update cache coherency information of the interface in
|
||||
* its config structure.
|
||||
*
|
||||
* </pre>
|
||||
******************************************************************************/
|
||||
|
|
@ -107,6 +109,7 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
|
|||
/* Set device base address and ID */
|
||||
InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
|
||||
InstancePtr->Config.BaseAddress = EffectiveAddress;
|
||||
InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
|
||||
|
||||
/* Set callbacks to an initial stub routine */
|
||||
InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xemacps.h
|
||||
* @addtogroup emacps_v3_1
|
||||
* @addtogroup emacps_v3_7
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
|
|
@ -316,6 +316,21 @@
|
|||
* there is no error. CR# 869403
|
||||
* 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
|
||||
* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
|
||||
* 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
|
||||
* examples to ensure that "Successfully ran" and "Failed"
|
||||
* strings are available in all examples. This is a fix
|
||||
* for CR-965028.
|
||||
* ms 03/17/17 Modified text file in examples folder for doxygen
|
||||
* generation.
|
||||
* ms 04/05/17 Added tabspace for return statements in functions of
|
||||
* xemacps_ieee1588_example.c for proper documentation
|
||||
* while generating doxygen.
|
||||
* 3.5 hk 08/14/17 Update cache coherency information of the interface in
|
||||
* its config structure.
|
||||
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
|
||||
* changed to volatile.
|
||||
* Add API XEmacPs_BdRingPtrReset() to reset pointers
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
****************************************************************************/
|
||||
|
|
@ -513,6 +528,8 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
|
|||
typedef struct {
|
||||
u16 DeviceId; /**< Unique ID of device */
|
||||
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
|
||||
u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
|
||||
* describes whether Cache Coherent or not */
|
||||
} XEmacPs_Config;
|
||||
|
||||
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xemacps_bd.h
|
||||
* @addtogroup emacps_v3_1
|
||||
* @addtogroup emacps_v3_7
|
||||
* @{
|
||||
*
|
||||
* This header provides operations to manage buffer descriptors in support
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xemacps_bdring.c
|
||||
* @addtogroup emacps_v3_1
|
||||
* @addtogroup emacps_v3_7
|
||||
* @{
|
||||
*
|
||||
* This file implements buffer descriptor ring related functions.
|
||||
|
|
@ -57,6 +57,8 @@
|
|||
* from uncached area. Fix for CR #663885.
|
||||
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
|
||||
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
|
||||
* pointers
|
||||
*
|
||||
* </pre>
|
||||
******************************************************************************/
|
||||
|
|
@ -505,7 +507,7 @@ LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
|
|||
XEmacPs_Bd * BdSetPtr)
|
||||
{
|
||||
LONG Status;
|
||||
(void *)BdSetPtr;
|
||||
(void) BdSetPtr;
|
||||
Xil_AssertNonvoid(RingPtr != NULL);
|
||||
Xil_AssertNonvoid(BdSetPtr != NULL);
|
||||
|
||||
|
|
@ -1072,4 +1074,29 @@ static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
|
|||
*TempPtr = DataValueTx;
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Reset BD ring head and tail pointers.
|
||||
*
|
||||
* @param RingPtr is the instance to be worked on.
|
||||
* @param VirtAddr is the virtual base address of the user memory region.
|
||||
*
|
||||
* @note
|
||||
* Should be called after XEmacPs_Stop()
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
|
||||
{
|
||||
RingPtr->FreeHead = virtaddrloc;
|
||||
RingPtr->PreHead = virtaddrloc;
|
||||
RingPtr->HwHead = virtaddrloc;
|
||||
RingPtr->HwTail = virtaddrloc;
|
||||
RingPtr->PostHead = virtaddrloc;
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xemacps_bdring.h
|
||||
* @addtogroup emacps_v3_1
|
||||
* @addtogroup emacps_v3_7
|
||||
* @{
|
||||
*
|
||||
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
|
||||
|
|
@ -47,6 +47,8 @@
|
|||
* 1.00a wsy 01/10/10 First release
|
||||
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
|
||||
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
|
||||
* changed to volatile.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
|
|
@ -81,7 +83,7 @@ typedef struct {
|
|||
XEmacPs_Bd *BdaRestart;
|
||||
/**< BDA to load when channel is started */
|
||||
|
||||
u32 HwCnt; /**< Number of BDs in work group */
|
||||
volatile u32 HwCnt; /**< Number of BDs in work group */
|
||||
u32 PreCnt; /**< Number of BDs in pre-work group */
|
||||
u32 FreeCnt; /**< Number of allocatable BDs in the free group */
|
||||
u32 PostCnt; /**< Number of BDs in post-work group */
|
||||
|
|
@ -228,6 +230,7 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
|
|||
XEmacPs_Bd ** BdSetPtr);
|
||||
LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
|
||||
|
||||
void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xemacps_control.c
|
||||
* @addtogroup emacps_v3_1
|
||||
* @addtogroup emacps_v3_7
|
||||
* @{
|
||||
*
|
||||
* Functions in this file implement general purpose command and control related
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
|
||||
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
|
|
@ -44,11 +44,12 @@
|
|||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XEmacPs_Config XEmacPs_ConfigTable[] =
|
||||
XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PS7_ETHERNET_0_DEVICE_ID,
|
||||
XPAR_PS7_ETHERNET_0_BASEADDR
|
||||
XPAR_PS7_ETHERNET_0_BASEADDR,
|
||||
XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT
|
||||
}
|
||||
};
|
||||
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xemacps_hw.c
|
||||
* @addtogroup emacps_v3_1
|
||||
* @addtogroup emacps_v3_7
|
||||
* @{
|
||||
*
|
||||
* This file contains the implementation of the ethernet interface reset sequence
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xemacps_hw.h
|
||||
* @addtogroup emacps_v3_1
|
||||
* @addtogroup emacps_v3_7
|
||||
* @{
|
||||
*
|
||||
* This header file contains identifiers and low-level driver functions (or
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xemacps_intr.c
|
||||
* @addtogroup emacps_v3_1
|
||||
* @addtogroup emacps_v3_7
|
||||
* @{
|
||||
*
|
||||
* Functions in this file implement general purpose interrupt processing related
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xemacps_sinit.c
|
||||
* @addtogroup emacps_v3_1
|
||||
* @addtogroup emacps_v3_7
|
||||
* @{
|
||||
*
|
||||
* This file contains lookup method by device ID when success, it returns
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xgpiops.c
|
||||
* @addtogroup gpiops_v3_1
|
||||
* @addtogroup gpiops_v3_3
|
||||
* @{
|
||||
*
|
||||
* The XGpioPs driver. Functions in this file are the minimum required functions
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
|
|
@ -33,7 +34,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xgpiops.h
|
||||
* @addtogroup gpiops_v3_1
|
||||
* @addtogroup gpiops_v3_3
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
|
|
@ -97,7 +98,15 @@
|
|||
* passed to APIs. CR# 822636
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
|
||||
*
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* ms 04/05/17 Added tabspace for return statements in functions of
|
||||
* gpiops examples for proper documentation while
|
||||
* generating doxygen.
|
||||
* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
|
||||
* for zcu102 and zc702 boards in polled and interrupt
|
||||
* example, configured Interrupt pin to input pin for
|
||||
* proper functioning of interrupt example.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
|
||||
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XGpioPs_Config XGpioPs_ConfigTable[] =
|
||||
XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PS7_GPIO_0_DEVICE_ID,
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xgpiops_hw.c
|
||||
* @addtogroup gpiops_v3_1
|
||||
* @addtogroup gpiops_v3_3
|
||||
* @{
|
||||
*
|
||||
* This file contains low level GPIO functions.
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xgpiops_hw.h
|
||||
* @addtogroup gpiops_v3_1
|
||||
* @addtogroup gpiops_v3_3
|
||||
* @{
|
||||
*
|
||||
* This header file contains the identifiers and basic driver functions (or
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xgpiops_intr.c
|
||||
* @addtogroup gpiops_v3_1
|
||||
* @addtogroup gpiops_v3_3
|
||||
* @{
|
||||
*
|
||||
* This file contains functions related to GPIO interrupt handling.
|
||||
|
|
@ -722,7 +722,7 @@ void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
|
|||
******************************************************************************/
|
||||
void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
|
||||
{
|
||||
(void*) CallBackRef;
|
||||
(void) CallBackRef;
|
||||
(void) Bank;
|
||||
(void) Status;
|
||||
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xgpiops_selftest.c
|
||||
* @addtogroup gpiops_v3_1
|
||||
* @addtogroup gpiops_v3_3
|
||||
* @{
|
||||
*
|
||||
* This file contains a diagnostic self-test function for the XGpioPs driver.
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xgpiops_sinit.c
|
||||
* @addtogroup gpiops_v3_1
|
||||
* @addtogroup gpiops_v3_3
|
||||
* @{
|
||||
*
|
||||
* This file contains the implementation of the XGpioPs driver's static
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xiicps.c
|
||||
* @addtogroup iicps_v3_0
|
||||
* @addtogroup iicps_v3_5
|
||||
* @{
|
||||
*
|
||||
* Contains implementation of required functions for the XIicPs driver.
|
||||
|
|
@ -54,6 +54,7 @@
|
|||
* in XIicPs_Reset.
|
||||
* 12/06/14 Implemented Repeated start feature.
|
||||
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
|
||||
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
|
|
@ -228,7 +229,7 @@ void XIicPs_Abort(XIicPs *InstancePtr)
|
|||
* Reset the settings in config register and clear the FIFOs.
|
||||
*/
|
||||
XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
|
||||
XIICPS_CR_RESET_VALUE | XIICPS_CR_CLR_FIFO_MASK);
|
||||
(u32)XIICPS_CR_RESET_VALUE | (u32)XIICPS_CR_CLR_FIFO_MASK);
|
||||
|
||||
/*
|
||||
* Read, then write the interrupt status to make sure there are no
|
||||
|
|
@ -242,7 +243,7 @@ void XIicPs_Abort(XIicPs *InstancePtr)
|
|||
/*
|
||||
* Restore the interrupt state.
|
||||
*/
|
||||
IntrMaskReg = XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
|
||||
IntrMaskReg = (u32)XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
|
||||
XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XIICPS_IER_OFFSET, IntrMaskReg);
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xiicps.h
|
||||
* @addtogroup iicps_v3_0
|
||||
* @addtogroup iicps_v3_5
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
|
|
@ -183,6 +183,9 @@
|
|||
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
|
||||
* 02/18/15 Implemented larger data transfer using repeated start
|
||||
* in Zynq UltraScale MP.
|
||||
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
|
||||
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XIicPs_Config XIicPs_ConfigTable[] =
|
||||
XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PS7_I2C_0_DEVICE_ID,
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xiicps_hw.c
|
||||
* @addtogroup iicps_v3_0
|
||||
* @addtogroup iicps_v3_5
|
||||
* @{
|
||||
*
|
||||
* Contains implementation of required functions for providing the reset sequence
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xiicps_hw.h
|
||||
* @addtogroup iicps_v3_0
|
||||
* @addtogroup iicps_v3_5
|
||||
* @{
|
||||
*
|
||||
* This header file contains the hardware definition for an IIC device.
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xiicps_intr.c
|
||||
* @addtogroup iicps_v3_0
|
||||
* @addtogroup iicps_v3_5
|
||||
* @{
|
||||
*
|
||||
* Contains functions of the XIicPs driver for interrupt-driven transfers.
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xiicps_master.c
|
||||
* @addtogroup iicps_v3_0
|
||||
* @addtogroup iicps_v3_5
|
||||
* @{
|
||||
*
|
||||
* Handles master mode transfers.
|
||||
|
|
@ -62,7 +62,9 @@
|
|||
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
|
||||
* 02/18/15 Implemented larger data transfer using repeated start
|
||||
* in Zynq UltraScale MP.
|
||||
*
|
||||
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
|
||||
* 3.6 ask 09/03/18 In XIicPs_MasterRecvPolled, set transfer size register
|
||||
* before slave address. Fix for CR996440.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
@ -106,6 +108,7 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
|
|||
u16 SlaveAddr)
|
||||
{
|
||||
u32 BaseAddr;
|
||||
u32 Platform = XGetPlatform_Info();
|
||||
|
||||
/*
|
||||
* Assert validates the input arguments.
|
||||
|
|
@ -147,6 +150,16 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
|
|||
*/
|
||||
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
|
||||
|
||||
/* Clear the Hold bit in ZYNQ if receive byte count is less than
|
||||
* the FIFO depth to get the completion interrupt properly.
|
||||
*/
|
||||
if ((ByteCount < XIICPS_FIFO_DEPTH) && (Platform == (u32)XPLAT_ZYNQ))
|
||||
{
|
||||
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
|
||||
XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) &
|
||||
(u32)(~XIICPS_CR_HOLD_MASK));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
|
@ -182,10 +195,8 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
|
|||
BaseAddr = InstancePtr->Config.BaseAddress;
|
||||
InstancePtr->RecvBufferPtr = MsgPtr;
|
||||
InstancePtr->RecvByteCount = ByteCount;
|
||||
InstancePtr->CurrByteCount = ByteCount;
|
||||
InstancePtr->SendBufferPtr = NULL;
|
||||
InstancePtr->IsSend = 0;
|
||||
InstancePtr->UpdateTxSize = 0;
|
||||
|
||||
if ((ByteCount > XIICPS_FIFO_DEPTH) ||
|
||||
((InstancePtr->IsRepeatedStart) !=0))
|
||||
|
|
@ -203,14 +214,16 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
|
|||
* Setup the transfer size register so the slave knows how much
|
||||
* to send to us.
|
||||
*/
|
||||
if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) {
|
||||
if (ByteCount > (s32)XIICPS_MAX_TRANSFER_SIZE) {
|
||||
XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
|
||||
XIICPS_MAX_TRANSFER_SIZE);
|
||||
InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
|
||||
InstancePtr->UpdateTxSize = 1;
|
||||
}else {
|
||||
InstancePtr->CurrByteCount = ByteCount;
|
||||
XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
|
||||
(u32)ByteCount);
|
||||
InstancePtr->UpdateTxSize = 0;
|
||||
}
|
||||
|
||||
XIicPs_EnableInterrupts(BaseAddr,
|
||||
|
|
@ -251,8 +264,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
|
|||
u32 StatusReg;
|
||||
u32 BaseAddr;
|
||||
u32 Intrs;
|
||||
u32 Value;
|
||||
s32 Status;
|
||||
_Bool Value;
|
||||
|
||||
/*
|
||||
* Assert validates the input arguments.
|
||||
|
|
@ -260,7 +272,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
|
|||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(MsgPtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
|
||||
Xil_AssertNonvoid((u16)XIICPS_ADDR_MASK >= SlaveAddr);
|
||||
|
||||
BaseAddr = InstancePtr->Config.BaseAddress;
|
||||
InstancePtr->SendBufferPtr = MsgPtr;
|
||||
|
|
@ -302,7 +314,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
|
|||
*/
|
||||
Value = ((InstancePtr->SendByteCount > (s32)0) &&
|
||||
((IntrStatusReg & Intrs) == (u32)0U));
|
||||
while (Value != (u32)0x00U) {
|
||||
while (Value != FALSE) {
|
||||
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
|
||||
|
||||
/*
|
||||
|
|
@ -374,14 +386,8 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
|
|||
u32 Intrs;
|
||||
u32 StatusReg;
|
||||
u32 BaseAddr;
|
||||
s32 BytesToRecv;
|
||||
s32 BytesToRead;
|
||||
s32 TransSize;
|
||||
s32 Tmp = 0;
|
||||
u32 Status_Rcv;
|
||||
u32 Status;
|
||||
s32 Result;
|
||||
s32 IsHold = 0;
|
||||
s32 IsHold;
|
||||
s32 UpdateTxSize = 0;
|
||||
s32 ByteCountVar = ByteCount;
|
||||
u32 Platform;
|
||||
|
|
@ -407,6 +413,8 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
|
|||
XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
|
||||
(u32)XIICPS_CR_HOLD_MASK);
|
||||
IsHold = 1;
|
||||
} else {
|
||||
IsHold = 0;
|
||||
}
|
||||
|
||||
(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
|
||||
|
|
@ -417,13 +425,12 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
|
|||
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
|
||||
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
|
||||
|
||||
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
|
||||
|
||||
/*
|
||||
* Set up the transfer size register so the slave knows how much
|
||||
* to send to us.
|
||||
*/
|
||||
if (ByteCountVar > XIICPS_MAX_TRANSFER_SIZE) {
|
||||
if (ByteCountVar > (s32)XIICPS_MAX_TRANSFER_SIZE) {
|
||||
XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
|
||||
XIICPS_MAX_TRANSFER_SIZE);
|
||||
ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
|
||||
|
|
@ -433,6 +440,9 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
|
|||
ByteCountVar);
|
||||
}
|
||||
|
||||
|
||||
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
|
||||
|
||||
/*
|
||||
* Intrs keeps all the error-related interrupts.
|
||||
*/
|
||||
|
|
@ -460,18 +470,18 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
|
|||
XIicPs_RecvByte(InstancePtr);
|
||||
ByteCountVar --;
|
||||
|
||||
if (Platform == XPLAT_ZYNQ) {
|
||||
if (Platform == (u32)XPLAT_ZYNQ) {
|
||||
if ((UpdateTxSize != 0) &&
|
||||
((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
|
||||
(ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
|
||||
}
|
||||
if (Platform == XPLAT_ZYNQ) {
|
||||
if (Platform == (u32)XPLAT_ZYNQ) {
|
||||
if ((UpdateTxSize != 0) &&
|
||||
((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
|
||||
(ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
|
||||
/* wait while fifo is full */
|
||||
while (XIicPs_ReadReg(BaseAddr,
|
||||
XIICPS_TRANS_SIZE_OFFSET) !=
|
||||
|
|
@ -479,7 +489,7 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
|
|||
}
|
||||
|
||||
if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
|
||||
XIICPS_MAX_TRANSFER_SIZE) {
|
||||
(s32)XIICPS_MAX_TRANSFER_SIZE) {
|
||||
|
||||
XIicPs_WriteReg(BaseAddr,
|
||||
XIICPS_TRANS_SIZE_OFFSET,
|
||||
|
|
@ -507,7 +517,7 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
|
|||
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
|
||||
|
||||
if ((InstancePtr->RecvByteCount) >
|
||||
XIICPS_MAX_TRANSFER_SIZE) {
|
||||
(s32)XIICPS_MAX_TRANSFER_SIZE) {
|
||||
|
||||
XIicPs_WriteReg(BaseAddr,
|
||||
XIICPS_TRANS_SIZE_OFFSET,
|
||||
|
|
@ -625,6 +635,11 @@ void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
|
|||
XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
|
||||
& (~XIICPS_CR_SLVMON_MASK));
|
||||
|
||||
/*
|
||||
* wait for slv monitor control bit to be clear
|
||||
*/
|
||||
while (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
|
||||
& XIICPS_CR_SLVMON_MASK);
|
||||
/*
|
||||
* Clear interrupt flag for slave monitor interrupt.
|
||||
*/
|
||||
|
|
@ -755,17 +770,17 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
|
|||
XIicPs_RecvByte(InstancePtr);
|
||||
ByteCnt--;
|
||||
|
||||
if (Platform == XPLAT_ZYNQ) {
|
||||
if (Platform == (u32)XPLAT_ZYNQ) {
|
||||
if ((InstancePtr->UpdateTxSize != 0) &&
|
||||
((ByteCnt == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
|
||||
(ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (Platform == XPLAT_ZYNQ) {
|
||||
if (Platform == (u32)XPLAT_ZYNQ) {
|
||||
if ((InstancePtr->UpdateTxSize != 0) &&
|
||||
((ByteCnt == (XIICPS_FIFO_DEPTH + 1))!= 0U)) {
|
||||
(ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
|
||||
/* wait while fifo is full */
|
||||
while (XIicPs_ReadReg(BaseAddr,
|
||||
XIICPS_TRANS_SIZE_OFFSET) !=
|
||||
|
|
@ -773,7 +788,7 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
|
|||
}
|
||||
|
||||
if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
|
||||
XIICPS_MAX_TRANSFER_SIZE) {
|
||||
(s32)XIICPS_MAX_TRANSFER_SIZE) {
|
||||
|
||||
XIicPs_WriteReg(BaseAddr,
|
||||
XIICPS_TRANS_SIZE_OFFSET,
|
||||
|
|
@ -798,11 +813,11 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
|
|||
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
|
||||
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
|
||||
|
||||
SlaveAddr = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
|
||||
SlaveAddr = (u16)XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
|
||||
XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
|
||||
|
||||
if ((InstancePtr->RecvByteCount) >
|
||||
XIICPS_MAX_TRANSFER_SIZE) {
|
||||
(s32)XIICPS_MAX_TRANSFER_SIZE) {
|
||||
|
||||
XIicPs_WriteReg(BaseAddr,
|
||||
XIICPS_TRANS_SIZE_OFFSET,
|
||||
|
|
@ -910,7 +925,6 @@ static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
|
|||
{
|
||||
u32 ControlReg;
|
||||
u32 BaseAddr;
|
||||
u32 EnabledIntr = 0x0U;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
|
||||
|
|
@ -935,11 +949,9 @@ static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
|
|||
|
||||
if (Role == RECVING_ROLE) {
|
||||
ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
|
||||
EnabledIntr = (u32)XIICPS_IXR_DATA_MASK |(u32)XIICPS_IXR_RX_OVR_MASK;
|
||||
}else {
|
||||
ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
|
||||
}
|
||||
EnabledIntr |= (u32)XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_ARB_LOST_MASK;
|
||||
|
||||
XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xiicps_options.c
|
||||
* @addtogroup iicps_v3_0
|
||||
* @addtogroup iicps_v3_5
|
||||
* @{
|
||||
*
|
||||
* Contains functions for the configuration of the XIccPs driver.
|
||||
|
|
@ -55,6 +55,7 @@
|
|||
* 2.3 sk 10/07/14 Repeated start feature removed.
|
||||
* 3.0 sk 12/06/14 Implemented Repeated start feature.
|
||||
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
|
||||
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
|
|
@ -135,7 +136,7 @@ s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
|
|||
* The hold bit in CR will be written by driver when the next transfer
|
||||
* is initiated.
|
||||
*/
|
||||
if ((OptionsVar & XIICPS_REP_START_OPTION) != 0U ) {
|
||||
if ((OptionsVar & (u32)XIICPS_REP_START_OPTION) != (u32)0 ) {
|
||||
InstancePtr->IsRepeatedStart = 1;
|
||||
OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
|
||||
}
|
||||
|
|
@ -349,8 +350,8 @@ s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
|
|||
u32 ControlReg;
|
||||
u32 CalcDivA;
|
||||
u32 CalcDivB;
|
||||
u32 BestDivA = 0;
|
||||
u32 BestDivB = 0;
|
||||
u32 BestDivA;
|
||||
u32 BestDivB;
|
||||
u32 FsclHzVar = FsclHz;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
|
|
@ -379,12 +380,12 @@ s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
|
|||
* If frequency 100KHz is selected, 90KHz should be set.
|
||||
* This is due to a hardware limitation.
|
||||
*/
|
||||
if(FsclHzVar > 384600U) {
|
||||
FsclHzVar = 384600U;
|
||||
if(FsclHzVar > (u32)384600U) {
|
||||
FsclHzVar = (u32)384600U;
|
||||
}
|
||||
|
||||
if((FsclHzVar <= 100000U) && (FsclHzVar > 90000U)) {
|
||||
FsclHzVar = 90000U;
|
||||
if((FsclHzVar <= (u32)100000U) && (FsclHzVar > (u32)90000U)) {
|
||||
FsclHzVar = (u32)90000U;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xiicps_selftest.c
|
||||
* @addtogroup iicps_v3_0
|
||||
* @addtogroup iicps_v3_5
|
||||
* @{
|
||||
*
|
||||
* This component contains the implementation of selftest functions for the
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xiicps_sinit.c
|
||||
* @addtogroup iicps_v3_0
|
||||
* @addtogroup iicps_v3_5
|
||||
* @{
|
||||
*
|
||||
* The implementation of the XIicPs component's static initialization
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -32,7 +32,7 @@
|
|||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xiicps_slave.c
|
||||
* @addtogroup iicps_v3_0
|
||||
* @addtogroup iicps_v3_5
|
||||
* @{
|
||||
*
|
||||
* Handles slave transfers
|
||||
|
|
@ -44,6 +44,7 @@
|
|||
* 1.00a jz 01/30/10 First release
|
||||
* 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
|
||||
* 3.00 sk 01/31/15 Modified the code according to MISRAC 2012 Compliant.
|
||||
* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
|
|
@ -210,7 +211,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
|
|||
s32 BytesToSend;
|
||||
s32 Error = 0;
|
||||
s32 Status = (s32)XST_SUCCESS;
|
||||
u32 Value;
|
||||
_Bool Value;
|
||||
_Bool Result;
|
||||
|
||||
/*
|
||||
* Assert validates the input arguments.
|
||||
|
|
@ -227,8 +229,9 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
|
|||
* Use RXRW bit in status register to wait master to start a read.
|
||||
*/
|
||||
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
|
||||
while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0U) &&
|
||||
((!Error) != 0)) {
|
||||
Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
|
||||
(Error == 0));
|
||||
while (Result != FALSE) {
|
||||
|
||||
/*
|
||||
* If master tries to send us data, it is an error.
|
||||
|
|
@ -238,6 +241,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
|
|||
}
|
||||
|
||||
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
|
||||
Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
|
||||
(Error == 0));
|
||||
}
|
||||
|
||||
if (Error != 0) {
|
||||
|
|
@ -255,8 +260,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
|
|||
* there are no errors.
|
||||
*/
|
||||
Value = (InstancePtr->SendByteCount > (s32)0) &&
|
||||
((!Error) != 0);
|
||||
while (Value != (u32)0x00U) {
|
||||
((Error == 0));
|
||||
while (Value != FALSE) {
|
||||
|
||||
/*
|
||||
* Find out how many can be sent.
|
||||
|
|
@ -276,7 +281,7 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
|
|||
* Wait for master to read the data out of fifo.
|
||||
*/
|
||||
while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
|
||||
((!Error) != 0)) {
|
||||
(Error == 0)) {
|
||||
|
||||
/*
|
||||
* If master terminates the transfer before all data is
|
||||
|
|
@ -296,12 +301,12 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
|
|||
StatusReg = XIicPs_ReadReg(BaseAddr,
|
||||
XIICPS_SR_OFFSET);
|
||||
}
|
||||
Value = (InstancePtr->SendByteCount > (s32)0U) &&
|
||||
((!Error) != 0);
|
||||
Value = ((InstancePtr->SendByteCount > (s32)0) &&
|
||||
(Error == 0));
|
||||
}
|
||||
}
|
||||
if (Error != 0) {
|
||||
Status = (s32)XST_FAILURE;
|
||||
Status = (s32)XST_FAILURE;
|
||||
}
|
||||
|
||||
return Status;
|
||||
|
|
@ -551,7 +556,7 @@ void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
|
|||
/*
|
||||
* Signal application if there are any events.
|
||||
*/
|
||||
if (0U != StatusEvent) {
|
||||
if ((u32)0U != StatusEvent) {
|
||||
InstancePtr->StatusHandler(InstancePtr->CallBackRef,
|
||||
StatusEvent);
|
||||
}
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xqspips.c
|
||||
* @addtogroup qspips_v3_2
|
||||
* @addtogroup qspips_v3_4
|
||||
* @{
|
||||
*
|
||||
* Contains implements the interface functions of the XQspiPs driver.
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xqspips.h
|
||||
* @addtogroup qspips_v3_2
|
||||
* @addtogroup qspips_v3_4
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
|
|
@ -273,6 +273,14 @@
|
|||
* when thresholds are used.
|
||||
* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
|
||||
* to remove compilation warnings. CR# 868893.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* ms 04/05/17 Modified Comment lines in functions of qspips
|
||||
* examples to recognize it as documentation block
|
||||
* and modified filename tag in
|
||||
* xqspips_dual_flash_stack_lqspi_example.c to include it in
|
||||
* doxygen examples.
|
||||
* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
|
||||
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XQspiPs_Config XQspiPs_ConfigTable[] =
|
||||
XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PS7_QSPI_0_DEVICE_ID,
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xqspips_hw.c
|
||||
* @addtogroup qspips_v3_2
|
||||
* @addtogroup qspips_v3_4
|
||||
* @{
|
||||
*
|
||||
* Contains low level functions, primarily reset related.
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xqspips_hw.h
|
||||
* @addtogroup qspips_v3_2
|
||||
* @addtogroup qspips_v3_4
|
||||
* @{
|
||||
*
|
||||
* This header file contains the identifiers and basic HW access driver
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xqspips_options.c
|
||||
* @addtogroup qspips_v3_2
|
||||
* @addtogroup qspips_v3_4
|
||||
* @{
|
||||
*
|
||||
* Contains functions for the configuration of the XQspiPs driver component.
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xqspips_selftest.c
|
||||
* @addtogroup qspips_v3_2
|
||||
* @addtogroup qspips_v3_4
|
||||
* @{
|
||||
*
|
||||
* This file contains the implementation of selftest function for the QSPI
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xqspips_sinit.c
|
||||
* @addtogroup qspips_v3_2
|
||||
* @addtogroup qspips_v3_4
|
||||
* @{
|
||||
*
|
||||
* The implementation of the XQspiPs component's static initialization
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xscugic.c
|
||||
* @addtogroup scugic_v3_1
|
||||
* @addtogroup scugic_v3_8
|
||||
* @{
|
||||
*
|
||||
* Contains required functions for the XScuGic driver for the Interrupt
|
||||
|
|
@ -46,45 +46,78 @@
|
|||
* ----- ---- -------- --------------------------------------------------------
|
||||
* 1.00a drg 01/19/10 First release
|
||||
* 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
|
||||
* "Config" entry is now made as pointer in the XScuGic
|
||||
* structure, necessary changes are made.
|
||||
* The HandlerTable can now be populated through the low
|
||||
* level routine XScuGic_RegisterHandler added in this
|
||||
* release. Hence necessary checks are added not to
|
||||
* overwrite the HandlerTable entriesin function
|
||||
* XScuGic_CfgInitialize.
|
||||
* "Config" entry is now made as pointer in the XScuGic
|
||||
* structure, necessary changes are made.
|
||||
* The HandlerTable can now be populated through the low
|
||||
* level routine XScuGic_RegisterHandler added in this
|
||||
* release. Hence necessary checks are added not to
|
||||
* overwrite the HandlerTable entriesin function
|
||||
* XScuGic_CfgInitialize.
|
||||
* 1.03a srt 02/27/13 Added APIs
|
||||
* - XScuGic_SetPriTrigTypeByDistAddr()
|
||||
* - XScuGic_GetPriTrigTypeByDistAddr()
|
||||
* Removed Offset calculation macros, defined in _hw.h
|
||||
* (CR 702687)
|
||||
* Added support to direct interrupts to the appropriate CPU. Earlier
|
||||
* interrupts were directed to CPU1 (hard coded). Now depending
|
||||
* upon the CPU selected by the user (xparameters.h), interrupts
|
||||
* will be directed to the relevant CPU. This fixes CR 699688.
|
||||
* - XScuGic_SetPriTrigTypeByDistAddr()
|
||||
* - XScuGic_GetPriTrigTypeByDistAddr()
|
||||
* Removed Offset calculation macros, defined in _hw.h
|
||||
* (CR 702687)
|
||||
* Added support to direct interrupts to the appropriate CPU. Earlier
|
||||
* interrupts were directed to CPU1 (hard coded). Now depending
|
||||
* upon the CPU selected by the user (xparameters.h), interrupts
|
||||
* will be directed to the relevant CPU. This fixes CR 699688.
|
||||
*
|
||||
* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
|
||||
* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
|
||||
* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
|
||||
* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
|
||||
* This is fix for CR#705621.
|
||||
* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
|
||||
* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
|
||||
* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
|
||||
* This is fix for CR#705621.
|
||||
* 1.06a asa 16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
|
||||
* in function XScuGic_CfgInitialize is removed as it was
|
||||
* a bug.
|
||||
* in function XScuGic_CfgInitialize is removed as it was
|
||||
* a bug.
|
||||
* 3.00 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.01 pkp 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
|
||||
* target CPU mapping
|
||||
* target CPU mapping
|
||||
* 3.02 pkp 11/09/15 Modified DistributorInit function for AMP case to add
|
||||
* the current cpu to interrupt processor targets registers
|
||||
* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
|
||||
* distributor is left uninitialized for Zynq AMP. It is assumed
|
||||
* that the distributor will be initialized by Linux master. However
|
||||
* for CortexR5 case, the earlier code is left unchanged where the
|
||||
* the interrupt processor target registers in the distributor is
|
||||
* initialized with the corresponding CPU ID on which the application
|
||||
* built over the scugic driver runs.
|
||||
* These changes fix CR#937243.
|
||||
* distributor is left uninitialized for Zynq AMP. It is assumed
|
||||
* that the distributor will be initialized by Linux master. However
|
||||
* for CortexR5 case, the earlier code is left unchanged where the
|
||||
* the interrupt processor target registers in the distributor is
|
||||
* initialized with the corresponding CPU ID on which the application
|
||||
* built over the scugic driver runs.
|
||||
* These changes fix CR#937243.
|
||||
* 3.3 pkp 05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
|
||||
* to interrupt target register to fix CR#951848
|
||||
*
|
||||
* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
|
||||
* the flow and avoid code duplication. Changes are made for
|
||||
* USE_AMP use case for R5. In a scenario (in R5 split mode) when
|
||||
* one R5 is operating with A53 in open amp config and other
|
||||
* R5 running baremetal app, the existing code
|
||||
* had the potential to stop the whole AMP solution to work (if
|
||||
* for some reason the R5 running the baremetal app tasked to
|
||||
* initialize the Distributor hangs or crashes before initializing).
|
||||
* Changes are made so that the R5 under AMP first checks if
|
||||
* the distributor is enabled or not and if not, it does the
|
||||
* standard Distributor initialization.
|
||||
* This fixes the CR#952962.
|
||||
* 3.4 mus 09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
|
||||
* for single core zynq-7000s
|
||||
* 3.5 mus 10/05/16 Modified DistributorInit function to avoid re-initialization of
|
||||
* distributor,If it is already initialized by other CPU.
|
||||
* 3.5 pkp 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id value
|
||||
* and properly mask interrupt target processor value to modify
|
||||
* interrupt target processor register for a given interrupt ID
|
||||
* and cpu ID
|
||||
* 3.6 pkp 20/01/17 Added new API XScuGic_Stop to Disable distributor and
|
||||
* interrupts in case they are being used only by current cpu.
|
||||
* It also removes current cpu from interrupt target registers
|
||||
* for all interrupts.
|
||||
* kvn 02/17/17 Add support for changing GIC CPU master at run time.
|
||||
* kvn 02/28/17 Make the CpuId as static variable and Added new
|
||||
* XScugiC_GetCpuId to access CpuId.
|
||||
* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
|
||||
* XScuGic_InterruptUnmapFromCpu, These API's can be used
|
||||
* by applications to unmap specific/all interrupts from
|
||||
* target CPU. It fixes CR#992490.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
|
|
@ -94,7 +127,6 @@
|
|||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xscugic.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
|
|
@ -105,6 +137,7 @@
|
|||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
|
|
@ -113,7 +146,7 @@ static void StubHandler(void *CallBackRef);
|
|||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* DistributorInit initializes the distributor of the GIC. The
|
||||
* DoDistributorInit initializes the distributor of the GIC. The
|
||||
* initialization entails:
|
||||
*
|
||||
* - Write the trigger mode, priority and target CPU
|
||||
|
|
@ -128,35 +161,11 @@ static void StubHandler(void *CallBackRef);
|
|||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
|
||||
static void DoDistributorInit(XScuGic *InstancePtr, u32 CpuID)
|
||||
{
|
||||
u32 Int_Id;
|
||||
u32 LocalCpuID = CpuID;
|
||||
|
||||
#if USE_AMP==1
|
||||
#warning "Building GIC for AMP"
|
||||
#ifdef ARMR5
|
||||
u32 RegValue;
|
||||
|
||||
/*
|
||||
* The overall distributor should not be initialized in AMP case where
|
||||
* another CPU is taking care of it.
|
||||
*/
|
||||
LocalCpuID |= LocalCpuID << 8U;
|
||||
LocalCpuID |= LocalCpuID << 16U;
|
||||
for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
|
||||
RegValue = XScuGic_DistReadReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
|
||||
RegValue |= LocalCpuID;
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
|
||||
RegValue);
|
||||
}
|
||||
#endif
|
||||
return;
|
||||
#endif
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
|
||||
|
||||
/*
|
||||
|
|
@ -207,8 +216,8 @@ static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
|
|||
LocalCpuID |= LocalCpuID << 16U;
|
||||
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
|
||||
LocalCpuID);
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
|
||||
LocalCpuID);
|
||||
}
|
||||
|
||||
for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
|
||||
|
|
@ -223,8 +232,59 @@ static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
|
|||
}
|
||||
|
||||
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
|
||||
XSCUGIC_EN_INT_MASK);
|
||||
XSCUGIC_EN_INT_MASK);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* DistributorInit initializes the distributor of the GIC. It calls
|
||||
* DoDistributorInit to finish the initialization.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance.
|
||||
* @param CpuID is the Cpu ID to be initialized.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
|
||||
{
|
||||
u32 Int_Id;
|
||||
u32 LocalCpuID = CpuID;
|
||||
u32 RegValue;
|
||||
|
||||
#if USE_AMP==1 && (defined (ARMA9) || defined(__aarch64__))
|
||||
#warning "Building GIC for AMP"
|
||||
/*
|
||||
* GIC initialization is taken care by master CPU in
|
||||
* openamp configuration, so do nothing and return.
|
||||
*/
|
||||
return;
|
||||
#endif
|
||||
|
||||
RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
|
||||
if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
DoDistributorInit(InstancePtr, CpuID);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* The overall distributor should not be initialized in AMP case where
|
||||
* another CPU is taking care of it.
|
||||
*/
|
||||
LocalCpuID |= LocalCpuID << 8U;
|
||||
LocalCpuID |= LocalCpuID << 16U;
|
||||
for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
|
||||
RegValue = XScuGic_DistReadReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
|
||||
RegValue |= LocalCpuID;
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
|
||||
RegValue);
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
|
@ -304,15 +364,26 @@ s32 XScuGic_CfgInitialize(XScuGic *InstancePtr,
|
|||
u32 EffectiveAddr)
|
||||
{
|
||||
u32 Int_Id;
|
||||
u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
|
||||
u32 Cpu_Id = CpuId + (u32)1;
|
||||
(void) EffectiveAddr;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(ConfigPtr != NULL);
|
||||
/*
|
||||
* Detect Zynq-7000 base silicon configuration,Dual or Single CPU.
|
||||
* If it is single CPU cnfiguration then invoke assert for CPU ID=1
|
||||
*/
|
||||
#ifdef ARMA9
|
||||
if ( XPAR_CPU_ID == 0x01 )
|
||||
{
|
||||
Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
|
||||
& EFUSE_STATUS_CPU_MASK ) == 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
|
||||
|
||||
InstancePtr->IsReady = 0;
|
||||
InstancePtr->IsReady = 0U;
|
||||
InstancePtr->Config = ConfigPtr;
|
||||
|
||||
|
||||
|
|
@ -332,7 +403,7 @@ s32 XScuGic_CfgInitialize(XScuGic *InstancePtr,
|
|||
InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
|
||||
InstancePtr;
|
||||
}
|
||||
|
||||
XScuGic_Stop(InstancePtr);
|
||||
DistributorInit(InstancePtr, Cpu_Id);
|
||||
CPUInitialize(InstancePtr);
|
||||
|
||||
|
|
@ -757,13 +828,193 @@ void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
|
|||
RegValue = XScuGic_DistReadReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
|
||||
|
||||
Offset = (Int_Id & 0x3);
|
||||
Offset = (Int_Id & 0x3U);
|
||||
Cpu_Id = (0x1U << Cpu_Id);
|
||||
|
||||
RegValue = (RegValue | (~(0xFF << (Offset*8))) );
|
||||
RegValue |= ((Cpu_Id) << (Offset*8));
|
||||
RegValue = (RegValue & (~(0xFFU << (Offset*8U))) );
|
||||
RegValue |= ((Cpu_Id) << (Offset*8U));
|
||||
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
|
||||
RegValue);
|
||||
}
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Unmaps specific SPI interrupt from the target CPU
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
* @param Cpu_Id is a CPU number from which the interrupt has to be
|
||||
* unmapped
|
||||
* @param Int_Id is the IRQ source number to modify
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
|
||||
{
|
||||
u32 RegValue;
|
||||
u8 BitPos;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
|
||||
RegValue = XScuGic_DistReadReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
|
||||
|
||||
/*
|
||||
* Identify bit position corresponding to Int_Id and Cpu_Id,
|
||||
* in interrupt target register and clear it
|
||||
*/
|
||||
BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
|
||||
RegValue &= (~ ( 1U << BitPos ));
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
|
||||
RegValue);
|
||||
}
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Unmaps all SPI interrupts from the target CPU
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
* @param Cpu_Id is a CPU number from which the interrupts has to be
|
||||
* unmapped
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id)
|
||||
{
|
||||
u32 Int_Id;
|
||||
u32 Target_Cpu;
|
||||
u32 LocalCpuID = (1U << Cpu_Id);
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
|
||||
LocalCpuID |= LocalCpuID << 8U;
|
||||
LocalCpuID |= LocalCpuID << 16U;
|
||||
|
||||
for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U)
|
||||
{
|
||||
|
||||
Target_Cpu = XScuGic_DistReadReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
|
||||
/* Remove LocalCpuID from interrupt target register */
|
||||
Target_Cpu &= (~LocalCpuID);
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
|
||||
|
||||
}
|
||||
}
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* It checks if the interrupt target register contains all interrupts to be
|
||||
* targeted for current CPU. If they are programmed to be forwarded to current
|
||||
* cpu, this API disable all interrupts and disable GIC distributor.
|
||||
* This API also removes current CPU from interrupt target registers for all
|
||||
* interrupt.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XScuGic_Stop(XScuGic *InstancePtr)
|
||||
{
|
||||
u32 Int_Id;
|
||||
u32 RegValue;
|
||||
u32 Target_Cpu;
|
||||
u32 DistDisable = 1; /* To track if distributor need to be disabled or not */
|
||||
u32 LocalCpuID = ((u32)0x1 << CpuId);
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
|
||||
/* If distributor is already disabled, no need to do anything */
|
||||
RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
|
||||
if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
|
||||
return;
|
||||
}
|
||||
|
||||
LocalCpuID |= LocalCpuID << 8U;
|
||||
LocalCpuID |= LocalCpuID << 16U;
|
||||
|
||||
/*
|
||||
* Check if the interrupt are targeted to current cpu only or not.
|
||||
* Also remove current cpu from interrupt target register for all
|
||||
* interrupts.
|
||||
*/
|
||||
for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
|
||||
|
||||
Target_Cpu = XScuGic_DistReadReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
|
||||
if ((Target_Cpu != LocalCpuID) && (Target_Cpu!= 0)) {
|
||||
/*
|
||||
* If any other CPU is also programmed to target register, GIC
|
||||
* distributor can not be disabled.
|
||||
*/
|
||||
DistDisable = 0;
|
||||
}
|
||||
|
||||
/* Remove current CPU from interrupt target register */
|
||||
Target_Cpu &= (~LocalCpuID);
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* If GIC distributor is safe to be disabled, disable all the interrupt
|
||||
* and then disable distributor.
|
||||
*/
|
||||
if ( DistDisable == 1) {
|
||||
for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
|
||||
/*
|
||||
* Disable all the interrupts
|
||||
*/
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
|
||||
Int_Id),
|
||||
0xFFFFFFFFU);
|
||||
}
|
||||
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* This updates the CpuId global variable.
|
||||
*
|
||||
* @param CpuCoreId is the CPU core number.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XScuGic_SetCpuID(u32 CpuCoreId)
|
||||
{
|
||||
Xil_AssertVoid(CpuCoreId <= 1U);
|
||||
|
||||
CpuId = CpuCoreId;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* This function returns the CpuId variable.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return The CPU core number.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
u32 XScuGic_GetCpuID(void)
|
||||
{
|
||||
return CpuId;
|
||||
}
|
||||
/** @} */
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xscugic.h
|
||||
* @addtogroup scugic_v3_1
|
||||
* @addtogroup scugic_v3_8
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
|
|
@ -145,6 +145,41 @@
|
|||
* built over the scugic driver runs.
|
||||
* These changes fix CR#937243.
|
||||
*
|
||||
* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
|
||||
* the flow and avoid code duplication. Changes are made for
|
||||
* USE_AMP use case for R5. In a scenario (in R5 split mode) when
|
||||
* one R5 is operating with A53 in open amp config and other
|
||||
* R5 running baremetal app, the existing code
|
||||
* had the potential to stop the whole AMP solution to work (if
|
||||
* for some reason the R5 running the baremetal app tasked to
|
||||
* initialize the Distributor hangs or crashes before initializing).
|
||||
* Changes are made so that the R5 under AMP first checks if
|
||||
* the distributor is enabled or not and if not, it does the
|
||||
* standard Distributor initialization.
|
||||
* This fixes the CR#952962.
|
||||
* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
|
||||
* examples to ensure that "Successfully ran" and "Failed"
|
||||
* strings are available in all examples. This is a fix
|
||||
* for CR-965028.
|
||||
* kvn 02/17/17 Add support for changing GIC CPU master at run time.
|
||||
* kvn 02/28/17 Make the CpuId as static variable and Added new
|
||||
* XScugiC_GetCpuId to access CpuId.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
|
||||
* definitions of scugic in xparameters.h
|
||||
* 3.8 mus 07/05/17 Updated scugic.tcl to add support for intrrupts connected
|
||||
* through util_reduced_vector IP(OR gate)
|
||||
* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
|
||||
* the HandlerTable in XScuGic_ConfigTable to 0, it removes
|
||||
* the compilation warning in xscugic_g.c. Fix for CR#978736.
|
||||
* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
|
||||
* definitions for pl to ps interrupts.Fix for CR#980534
|
||||
* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
|
||||
* XScuGic_InterruptUnmapFromCpu, These API's can be used
|
||||
* by applications to unmap specific/all interrupts from
|
||||
* target CPU.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
@ -166,7 +201,12 @@ extern "C" {
|
|||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#define EFUSE_STATUS_OFFSET 0x10
|
||||
#define EFUSE_STATUS_CPU_MASK 0x80
|
||||
|
||||
#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
|
||||
#define ARMA9
|
||||
#endif
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/* The following data type defines each entry in an interrupt vector table.
|
||||
|
|
@ -304,6 +344,11 @@ void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
|
|||
void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
|
||||
u8 Priority, u8 Trigger);
|
||||
void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
|
||||
void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
|
||||
void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
|
||||
void XScuGic_Stop(XScuGic *InstancePtr);
|
||||
void XScuGic_SetCpuID(u32 CpuCoreId);
|
||||
u32 XScuGic_GetCpuID(void);
|
||||
/*
|
||||
* Initialization functions in xscugic_sinit.c
|
||||
*/
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
|
||||
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
|
|
@ -44,12 +44,13 @@
|
|||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XScuGic_Config XScuGic_ConfigTable[] =
|
||||
XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PS7_SCUGIC_0_DEVICE_ID,
|
||||
XPAR_PS7_SCUGIC_0_BASEADDR,
|
||||
XPAR_PS7_SCUGIC_0_DIST_BASEADDR
|
||||
XPAR_PS7_SCUGIC_0_DIST_BASEADDR,
|
||||
{{0}} /**< Initialize the HandlerTable to 0 */
|
||||
}
|
||||
};
|
||||
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xscugic_hw.c
|
||||
* @addtogroup scugic_v3_1
|
||||
* @addtogroup scugic_v3_8
|
||||
* @{
|
||||
*
|
||||
* This file contains low-level driver functions that can be used to access the
|
||||
|
|
@ -62,6 +62,13 @@
|
|||
* XScuGic_SetPriTrigTypeByDistAddr and
|
||||
* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time.
|
||||
* kvn 02/28/17 Make the CpuId as static variable and Added new
|
||||
* XScugiC_GetCpuId to access CpuId.
|
||||
* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
|
||||
* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
|
||||
* API's can be used by applications to unmap specific/all
|
||||
* interrupts from target CPU. It fixes CR#992490.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
|
|
@ -90,6 +97,7 @@ static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
|
|||
/************************** Variable Definitions *****************************/
|
||||
|
||||
extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
|
||||
extern u32 CpuId;
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
|
|
@ -274,7 +282,7 @@ static void CPUInit(XScuGic_Config *Config)
|
|||
s32 XScuGic_DeviceInitialize(u32 DeviceId)
|
||||
{
|
||||
XScuGic_Config *Config;
|
||||
u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
|
||||
u32 Cpu_Id = XScuGic_GetCpuID() + (u32)1;
|
||||
|
||||
Config = &XScuGic_ConfigTable[(u32 )DeviceId];
|
||||
|
||||
|
|
@ -567,4 +575,75 @@ void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
|
|||
|
||||
*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Unmaps specific SPI interrupt from the target CPU
|
||||
*
|
||||
* @param DistBaseAddress is the device base address
|
||||
* @param Cpu_Id is a CPU number from which the interrupt has to be
|
||||
* unmapped
|
||||
* @param Int_Id is the IRQ source number to modify
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
|
||||
u8 Cpu_Id, u32 Int_Id)
|
||||
{
|
||||
u32 RegValue;
|
||||
u8 BitPos;
|
||||
|
||||
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
|
||||
|
||||
RegValue = XScuGic_ReadReg(DistBaseAddress,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
|
||||
|
||||
/*
|
||||
* Identify bit position corresponding to Int_Id and Cpu_Id,
|
||||
* in interrupt target register and clear it
|
||||
*/
|
||||
BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
|
||||
RegValue &= (~ ( 1U << BitPos ));
|
||||
XScuGic_WriteReg(DistBaseAddress,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Unmaps all SPI interrupts from the target CPU
|
||||
*
|
||||
* @param DistBaseAddress is the device base address
|
||||
* @param Cpu_Id is a CPU number from which the interrupts has to be
|
||||
* unmapped
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
|
||||
u8 Cpu_Id)
|
||||
{
|
||||
u32 Int_Id;
|
||||
u32 Target_Cpu;
|
||||
u32 LocalCpuID = (1U << Cpu_Id);
|
||||
|
||||
LocalCpuID |= LocalCpuID << 8U;
|
||||
LocalCpuID |= LocalCpuID << 16U;
|
||||
|
||||
for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U)
|
||||
{
|
||||
|
||||
Target_Cpu = XScuGic_ReadReg(DistBaseAddress,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
|
||||
/* Remove LocalCpuID from interrupt target register */
|
||||
Target_Cpu &= (~LocalCpuID);
|
||||
XScuGic_WriteReg(DistBaseAddress,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
|
||||
|
||||
}
|
||||
}
|
||||
/** @} */
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xscugic_hw.h
|
||||
* @addtogroup scugic_v3_1
|
||||
* @addtogroup scugic_v3_8
|
||||
* @{
|
||||
*
|
||||
* This header file contains identifiers and HW access functions (or
|
||||
|
|
@ -72,6 +72,10 @@
|
|||
* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
|
||||
* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
|
||||
* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
|
||||
* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
|
||||
* API's can be used by applications to unmap specific/all
|
||||
* interrupts from target CPU. It fixes CR#992490.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
@ -633,6 +637,10 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
|
|||
u8 Priority, u8 Trigger);
|
||||
void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
|
||||
u8 *Priority, u8 *Trigger);
|
||||
void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
|
||||
u8 Cpu_Id, u32 Int_Id);
|
||||
void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
|
||||
u8 Cpu_Id);
|
||||
/************************** Variable Definitions *****************************/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xscugic_intr.c
|
||||
* @addtogroup scugic_v3_1
|
||||
* @addtogroup scugic_v3_8
|
||||
* @{
|
||||
*
|
||||
* This file contains the interrupt processing for the driver for the Xilinx
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xscugic_selftest.c
|
||||
* @addtogroup scugic_v3_1
|
||||
* @addtogroup scugic_v3_8
|
||||
* @{
|
||||
*
|
||||
* Contains diagnostic self-test functions for the XScuGic driver.
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xscugic_sinit.c
|
||||
* @addtogroup scugic_v3_1
|
||||
* @addtogroup scugic_v3_8
|
||||
* @{
|
||||
*
|
||||
* Contains static init functions for the XScuGic driver for the Interrupt
|
||||
|
|
@ -103,6 +103,8 @@
|
|||
* the xstatus.h of the standalone BSP during the
|
||||
* libgen.
|
||||
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
|
||||
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XScuTimer_Config XScuTimer_ConfigTable[] =
|
||||
XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PS7_SCUTIMER_0_DEVICE_ID,
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
/* $Id: xscuwdt.c,v 1.1.2.1 2011/01/20 04:04:40 sadanan Exp $ */
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
|
|
|
|||
|
|
@ -125,6 +125,8 @@
|
|||
* the xstatus.h of the standalone BSP during the
|
||||
* libgen.
|
||||
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
|
||||
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XScuWdt_Config XScuWdt_ConfigTable[] =
|
||||
XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PS7_SCUWDT_0_DEVICE_ID,
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xsdps.c
|
||||
* @addtogroup sdps_v2_5
|
||||
* @addtogroup sdps_v3_4
|
||||
* @{
|
||||
*
|
||||
* Contains the interface functions of the XSdPs driver.
|
||||
|
|
@ -64,28 +64,40 @@
|
|||
* sk 12/10/15 Added support for MMC cards.
|
||||
* sk 02/16/16 Corrected the Tuning logic.
|
||||
* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
|
||||
* 2.8 sk 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
|
||||
* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
|
||||
* sk 07/16/16 Added support for UHS modes.
|
||||
* sk 07/07/16 Used usleep API for both arm and microblaze.
|
||||
* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
|
||||
* operating modes.
|
||||
* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
|
||||
* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
|
||||
* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
|
||||
* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
|
||||
* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
|
||||
* sk 02/01/17 Added HSD and DDR mode support for eMMC.
|
||||
* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
|
||||
* sk 03/20/17 Add support for EL1 non-secure mode.
|
||||
* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
|
||||
* mn 07/17/17 Add support for running SD at 200MHz
|
||||
* mn 07/26/17 Fixed compilation warnings
|
||||
* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
|
||||
* mn 08/17/17 Added CCI support for A53 and disabled data cache
|
||||
* operations when it is enabled.
|
||||
* mn 08/22/17 Updated for Word Access System support
|
||||
* mn 09/06/17 Resolved compilation errors with IAR toolchain
|
||||
* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
|
||||
* 3.4 mn 10/17/17 Use different commands for single and multi block
|
||||
* transfers
|
||||
* mn 03/02/18 Move UHS macro check to SD card initialization routine
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xsdps.h"
|
||||
/*
|
||||
* The header sleep.h and API usleep() can only be used with an arm design.
|
||||
* MB_Sleep() is used for microblaze design.
|
||||
*/
|
||||
#if defined (__arm__) || defined (__aarch64__)
|
||||
|
||||
#include "sleep.h"
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __MICROBLAZE__
|
||||
|
||||
#include "microblaze_sleep.h"
|
||||
|
||||
#endif
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
#define XSDPS_CMD8_VOL_PATTERN 0x1AAU
|
||||
#define XSDPS_RESPOCR_READY 0x80000000U
|
||||
|
|
@ -94,19 +106,23 @@
|
|||
#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U
|
||||
#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U
|
||||
#define HIGH_SPEED_SUPPORT 0x2U
|
||||
#define UHS_SDR50_SUPPORT 0x4U
|
||||
#define WIDTH_4_BIT_SUPPORT 0x4U
|
||||
#define SD_CLK_25_MHZ 25000000U
|
||||
#define SD_CLK_19_MHZ 19000000U
|
||||
#define SD_CLK_26_MHZ 26000000U
|
||||
#define EXT_CSD_DEVICE_TYPE_BYTE 196U
|
||||
#define EXT_CSD_SEC_COUNT_BYTE1 212U
|
||||
#define EXT_CSD_SEC_COUNT_BYTE2 213U
|
||||
#define EXT_CSD_SEC_COUNT_BYTE3 214U
|
||||
#define EXT_CSD_SEC_COUNT_BYTE4 215U
|
||||
#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U
|
||||
#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U
|
||||
#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U
|
||||
#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U
|
||||
#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U
|
||||
#define CSD_SPEC_VER_3 0x3U
|
||||
|
||||
/* Note: Remove this once fixed */
|
||||
#define UHS_BROKEN
|
||||
#define SCR_SPEC_VER_3 0x80U
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
|
|
@ -120,6 +136,7 @@ extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
|
|||
static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
|
||||
static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
|
||||
|
||||
u16 TransferMode;
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
|
|
@ -163,28 +180,32 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
|
|||
Xil_AssertNonvoid(ConfigPtr != NULL);
|
||||
|
||||
/* Set some default values. */
|
||||
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
|
||||
InstancePtr->Config.BaseAddress = EffectiveAddr;
|
||||
InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
|
||||
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
|
||||
InstancePtr->Config.CardDetect = ConfigPtr->CardDetect;
|
||||
InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect;
|
||||
InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
|
||||
InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
|
||||
InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
|
||||
InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
|
||||
InstancePtr->SectorCount = 0;
|
||||
InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
|
||||
InstancePtr->Config_TapDelay = NULL;
|
||||
|
||||
/* Disable bus power */
|
||||
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_POWER_CTRL_OFFSET, 0U);
|
||||
/* Disable bus power and issue emmc hw reset */
|
||||
if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) ==
|
||||
XSDPS_HC_SPEC_V3)
|
||||
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
|
||||
else
|
||||
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_POWER_CTRL_OFFSET, 0x0);
|
||||
|
||||
/* Delay to poweroff card */
|
||||
#if defined (__arm__) || defined (__aarch64__)
|
||||
|
||||
(void)sleep(1U);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __MICROBLAZE__
|
||||
|
||||
MB_Sleep(1000U);
|
||||
|
||||
#endif
|
||||
(void)usleep(1000U);
|
||||
|
||||
/* "Software reset for all" is initiated */
|
||||
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
|
||||
|
|
@ -210,9 +231,21 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
|
|||
XSDPS_CAPS_OFFSET);
|
||||
|
||||
/* Select voltage and enable bus power. */
|
||||
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_POWER_CTRL_OFFSET,
|
||||
XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
|
||||
if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
|
||||
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_POWER_CTRL_OFFSET,
|
||||
(XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
|
||||
~XSDPS_PC_EMMC_HW_RST_MASK);
|
||||
else
|
||||
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_POWER_CTRL_OFFSET,
|
||||
XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
|
||||
|
||||
/* Delay before issuing the command after emmc reset */
|
||||
if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
|
||||
if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) ==
|
||||
XSDPS_CAPS_EMB_SLOT)
|
||||
usleep(200);
|
||||
|
||||
/* Change the clock frequency to 400 KHz */
|
||||
Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
|
||||
|
|
@ -235,10 +268,18 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
|
|||
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_POWER_CTRL_OFFSET,
|
||||
PowerLevel | XSDPS_PC_BUS_PWR_MASK);
|
||||
|
||||
#ifdef __aarch64__
|
||||
/* Enable ADMA2 in 64bit mode. */
|
||||
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_HOST_CTRL1_OFFSET,
|
||||
XSDPS_HC_DMA_ADMA2_64_MASK);
|
||||
#else
|
||||
/* Enable ADMA2 in 32bit mode. */
|
||||
XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_HOST_CTRL1_OFFSET,
|
||||
XSDPS_HC_DMA_ADMA2_32_MASK);
|
||||
#endif
|
||||
|
||||
/* Enable all interrupt status except card interrupt initially */
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
||||
|
|
@ -259,10 +300,8 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
|
|||
* Transfer mode register - default value
|
||||
* DMA enabled, block count enabled, data direction card to host(read)
|
||||
*/
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_XFER_MODE_OFFSET,
|
||||
XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
|
||||
XSDPS_TM_DAT_DIR_SEL_MASK);
|
||||
TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
|
||||
XSDPS_TM_DAT_DIR_SEL_MASK;
|
||||
|
||||
/* Set block size to 512 by default */
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
||||
|
|
@ -308,10 +347,15 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
|
|||
u32 CSD[4];
|
||||
u32 Arg;
|
||||
u8 ReadReg;
|
||||
u32 BlkLen, DeviceSize, Mult;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
#ifndef UHS_MODE_ENABLE
|
||||
InstancePtr->Config.BusWidth = XSDPS_WIDTH_4;
|
||||
#endif
|
||||
|
||||
if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
|
||||
((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
|
||||
!= XSDPS_CAPS_EMB_SLOT)) {
|
||||
|
|
@ -379,9 +423,17 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
|
|||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
|
||||
if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
|
||||
Arg |= XSDPS_OCR_S18;
|
||||
Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
|
||||
/*
|
||||
* There is no support to switch to 1.8V and use UHS mode on
|
||||
* 1.0 silicon
|
||||
*/
|
||||
if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
|
||||
#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
|
||||
(XGetPSVersion_Info() > XPS_VERSION_1) &&
|
||||
#endif
|
||||
(InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
|
||||
Arg |= XSDPS_OCR_S18;
|
||||
}
|
||||
|
||||
/* 0x40300000 - Host High Capacity support & 3.3V window */
|
||||
|
|
@ -403,18 +455,14 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
|
|||
InstancePtr->HCS = 1U;
|
||||
}
|
||||
|
||||
/* There is no support to switch to 1.8V and use UHS mode on 1.0 silicon */
|
||||
#ifndef UHS_BROKEN
|
||||
if ((RespOCR & XSDPS_OCR_S18) != 0U) {
|
||||
if ((RespOCR & XSDPS_OCR_S18) != 0U) {
|
||||
InstancePtr->Switch1v8 = 1U;
|
||||
Status = XSdPs_Switch_Voltage(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/* CMD2 for Card ID */
|
||||
Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
|
||||
|
|
@ -470,6 +518,19 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
|
|||
CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_RESP3_OFFSET);
|
||||
|
||||
if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
|
||||
BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
|
||||
Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
|
||||
DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
|
||||
DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
|
||||
DeviceSize = (DeviceSize + 1U) * Mult;
|
||||
DeviceSize = DeviceSize * BlkLen;
|
||||
InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
|
||||
} else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
|
||||
InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
|
||||
1U) * 1024U;
|
||||
}
|
||||
|
||||
Status = XST_SUCCESS;
|
||||
|
||||
RETURN_PATH:
|
||||
|
|
@ -495,22 +556,20 @@ RETURN_PATH:
|
|||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XSdPs_CardInitialize(XSdPs *InstancePtr) {
|
||||
u8 Tmp;
|
||||
u32 Cnt;
|
||||
u32 PresentStateReg;
|
||||
u32 CtrlReg;
|
||||
u32 CSD[4];
|
||||
s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
|
||||
{
|
||||
#ifdef __ICCARM__
|
||||
#pragma data_alignment = 32
|
||||
static u8 ExtCsd[512];
|
||||
static u8 ExtCsd[512];
|
||||
u8 SCR[8] = { 0U };
|
||||
#pragma data_alignment = 4
|
||||
#else
|
||||
static u8 ExtCsd[512] __attribute__ ((aligned(32)));
|
||||
static u8 ExtCsd[512] __attribute__ ((aligned(32)));
|
||||
u8 SCR[8] __attribute__ ((aligned(32))) = { 0U };
|
||||
#endif
|
||||
u8 SCR[8] = { 0U };
|
||||
u8 ReadBuff[64] = { 0U };
|
||||
s32 Status;
|
||||
u32 Arg;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
|
@ -547,7 +606,15 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
|
|||
}
|
||||
|
||||
/* Change clock to default clock 25MHz */
|
||||
InstancePtr->BusSpeed = SD_CLK_25_MHZ;
|
||||
/*
|
||||
* SD default speed mode timing should be closed at 19 MHz.
|
||||
* The reason for this is SD requires a voltage level shifter.
|
||||
* This limitation applies to ZynqMPSoC.
|
||||
*/
|
||||
if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
|
||||
InstancePtr->BusSpeed = SD_CLK_19_MHZ;
|
||||
else
|
||||
InstancePtr->BusSpeed = SD_CLK_25_MHZ;
|
||||
Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
|
|
@ -601,33 +668,99 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
|
|||
}
|
||||
}
|
||||
|
||||
if ((InstancePtr->Switch1v8 != 0U) &&
|
||||
(InstancePtr->BusWidth == XSDPS_4_BIT_WIDTH)) {
|
||||
/* Set UHS-I SDR104 mode */
|
||||
Status = XSdPs_Uhs_ModeInit(InstancePtr,
|
||||
XSDPS_UHS_SPEED_MODE_SDR104);
|
||||
if (Status != XST_SUCCESS) {
|
||||
/* Get speed supported by device */
|
||||
Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
|
||||
if (Status != XST_SUCCESS) {
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
if (((SCR[2] & SCR_SPEC_VER_3) != 0U) &&
|
||||
(ReadBuff[13] >= UHS_SDR50_SUPPORT) &&
|
||||
(InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) &&
|
||||
#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
|
||||
(XGetPSVersion_Info() > XPS_VERSION_1) &&
|
||||
#endif
|
||||
(InstancePtr->Switch1v8 == 0U)) {
|
||||
u16 CtrlReg, ClockReg;
|
||||
|
||||
/* Stop the clock */
|
||||
CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET);
|
||||
CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
|
||||
CtrlReg);
|
||||
|
||||
/* Enabling 1.8V in controller */
|
||||
CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_HOST_CTRL2_OFFSET);
|
||||
CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
|
||||
CtrlReg);
|
||||
|
||||
/* Wait minimum 5mSec */
|
||||
(void)usleep(5000U);
|
||||
|
||||
/* Check for 1.8V signal enable bit is cleared by Host */
|
||||
CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_HOST_CTRL2_OFFSET);
|
||||
if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
} else {
|
||||
/* Wait for internal clock to stabilize */
|
||||
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET);
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET,
|
||||
ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
|
||||
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET);
|
||||
while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
|
||||
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET);
|
||||
}
|
||||
|
||||
/* Enable SD clock */
|
||||
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET);
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET,
|
||||
ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
|
||||
|
||||
/* Wait for 1mSec */
|
||||
(void)usleep(1000U);
|
||||
|
||||
InstancePtr->Switch1v8 = 1U;
|
||||
}
|
||||
|
||||
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
|
||||
if (InstancePtr->Switch1v8 != 0U) {
|
||||
|
||||
/* Identify the UHS mode supported by card */
|
||||
XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
|
||||
|
||||
/* Set UHS-I SDR104 mode */
|
||||
Status = XSdPs_Uhs_ModeInit(InstancePtr, InstancePtr->Mode);
|
||||
if (Status != XST_SUCCESS) {
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
} else {
|
||||
#endif
|
||||
/*
|
||||
* card supports CMD6 when SD_SPEC field in SCR register
|
||||
* indicates that the Physical Layer Specification Version
|
||||
* is 1.10 or later. So for SD v1.0 cmd6 is not supported.
|
||||
*/
|
||||
if (SCR[0] != 0U) {
|
||||
/* Get speed supported by device */
|
||||
Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
/* Check for high speed support */
|
||||
if ((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) {
|
||||
if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) &&
|
||||
(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
|
||||
InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
|
||||
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
|
||||
InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
|
||||
#endif
|
||||
Status = XSdPs_Change_BusSpeed(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
|
|
@ -635,7 +768,9 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
|
|||
}
|
||||
}
|
||||
}
|
||||
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
|
||||
}
|
||||
#endif
|
||||
|
||||
} else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
|
||||
(InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
|
||||
|
|
@ -653,8 +788,15 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
|
|||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
|
||||
EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) {
|
||||
InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
|
||||
InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
|
||||
InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
|
||||
InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
|
||||
|
||||
if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
|
||||
EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
|
||||
(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
|
||||
InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
|
||||
Status = XSdPs_Change_BusSpeed(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
|
|
@ -687,9 +829,39 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
|
|||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
|
||||
InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
|
||||
InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
|
||||
InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
|
||||
InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
|
||||
|
||||
/* Check for card supported speed */
|
||||
if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
|
||||
(EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
|
||||
EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) {
|
||||
EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) &&
|
||||
(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
|
||||
InstancePtr->Mode = XSDPS_HS200_MODE;
|
||||
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
|
||||
InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
|
||||
#endif
|
||||
} else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
|
||||
(EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED |
|
||||
EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) &&
|
||||
(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
|
||||
InstancePtr->Mode = XSDPS_DDR52_MODE;
|
||||
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
|
||||
InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
|
||||
#endif
|
||||
} else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
|
||||
EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
|
||||
(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
|
||||
InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
|
||||
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
|
||||
InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
|
||||
#endif
|
||||
} else
|
||||
InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
|
||||
|
||||
if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) {
|
||||
Status = XSdPs_Change_BusSpeed(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
|
|
@ -702,17 +874,47 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
|
|||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
|
||||
if (InstancePtr->Mode == XSDPS_HS200_MODE) {
|
||||
if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
}
|
||||
|
||||
if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) ||
|
||||
InstancePtr->Mode == XSDPS_DDR52_MODE) {
|
||||
if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
|
||||
Status = XSdPs_Change_BusWidth(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable Rst_n_Fun bit if it is disabled */
|
||||
if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
|
||||
Arg = XSDPS_MMC_RST_FUN_EN_ARG;
|
||||
Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
if ((InstancePtr->Mode != XSDPS_DDR52_MODE) ||
|
||||
(InstancePtr->CardType == XSDPS_CARD_SD)) {
|
||||
Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
}
|
||||
|
||||
RETURN_PATH:
|
||||
|
|
@ -731,26 +933,14 @@ RETURN_PATH:
|
|||
static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
|
||||
{
|
||||
s32 Status;
|
||||
u32 OperCondReg;
|
||||
u8 ReadReg;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/* 74 CLK delay after card is powered up, before the first command. */
|
||||
#if defined (__arm__) || defined (__aarch64__)
|
||||
|
||||
usleep(XSDPS_INIT_DELAY);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __MICROBLAZE__
|
||||
|
||||
/* 2 msec delay */
|
||||
MB_Sleep(2);
|
||||
|
||||
#endif
|
||||
|
||||
/* CMD0 no response expected */
|
||||
Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
|
||||
if (Status != XST_SUCCESS) {
|
||||
|
|
@ -803,7 +993,7 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
|
|||
{
|
||||
s32 Status;
|
||||
u16 CtrlReg;
|
||||
u32 ReadReg;
|
||||
u32 ReadReg, ClockReg;
|
||||
|
||||
/* Send switch voltage command */
|
||||
Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
|
||||
|
|
@ -827,19 +1017,6 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
|
|||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
|
||||
CtrlReg);
|
||||
|
||||
/* Wait minimum 5mSec */
|
||||
#if defined (__arm__) || defined (__aarch64__)
|
||||
|
||||
(void)usleep(5000U);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __MICROBLAZE__
|
||||
|
||||
MB_Sleep(5U);
|
||||
|
||||
#endif
|
||||
|
||||
/* Enabling 1.8V in controller */
|
||||
CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_HOST_CTRL2_OFFSET);
|
||||
|
|
@ -847,13 +1024,40 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
|
|||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
|
||||
CtrlReg);
|
||||
|
||||
/* Start clock */
|
||||
Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
|
||||
if (Status != XST_SUCCESS) {
|
||||
/* Wait minimum 5mSec */
|
||||
(void)usleep(5000U);
|
||||
|
||||
/* Check for 1.8V signal enable bit is cleared by Host */
|
||||
CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_HOST_CTRL2_OFFSET);
|
||||
if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
/* Wait for internal clock to stabilize */
|
||||
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET);
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET,
|
||||
ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
|
||||
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET);
|
||||
while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
|
||||
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET);
|
||||
}
|
||||
|
||||
/* Enable SD clock */
|
||||
ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET);
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CLK_CTRL_OFFSET,
|
||||
ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
|
||||
|
||||
/* Wait for 1mSec */
|
||||
(void)usleep(1000U);
|
||||
|
||||
/* Wait for CMD and DATA line to go high */
|
||||
ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_PRES_STATE_OFFSET);
|
||||
|
|
@ -945,8 +1149,8 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
|
|||
}
|
||||
}
|
||||
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET,
|
||||
(u16)CommandReg);
|
||||
XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
|
||||
(CommandReg << 16) | TransferMode);
|
||||
|
||||
/* Polling for response for now */
|
||||
do {
|
||||
|
|
@ -1137,20 +1341,32 @@ s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
|
|||
}
|
||||
|
||||
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
|
||||
if (InstancePtr->Config.IsCacheCoherent == 0) {
|
||||
Xil_DCacheInvalidateRange((INTPTR)Buff,
|
||||
BlkCnt * XSDPS_BLK_SIZE_512_MASK);
|
||||
}
|
||||
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_XFER_MODE_OFFSET,
|
||||
XSDPS_TM_AUTO_CMD12_EN_MASK |
|
||||
if (BlkCnt == 1U) {
|
||||
TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
|
||||
XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
|
||||
|
||||
/* Send single block read command */
|
||||
Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
} else {
|
||||
TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
|
||||
XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
|
||||
XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK);
|
||||
XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK;
|
||||
|
||||
Xil_DCacheInvalidateRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
|
||||
|
||||
/* Send block read command */
|
||||
Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
/* Send multiple blocks read command */
|
||||
Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for transfer complete */
|
||||
|
|
@ -1228,19 +1444,31 @@ s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
|
|||
}
|
||||
|
||||
XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
|
||||
Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
|
||||
if (InstancePtr->Config.IsCacheCoherent == 0) {
|
||||
Xil_DCacheFlushRange((INTPTR)Buff,
|
||||
BlkCnt * XSDPS_BLK_SIZE_512_MASK);
|
||||
}
|
||||
|
||||
XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_XFER_MODE_OFFSET,
|
||||
XSDPS_TM_AUTO_CMD12_EN_MASK |
|
||||
if (BlkCnt == 1U) {
|
||||
TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK;
|
||||
|
||||
/* Send single block write command */
|
||||
Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
} else {
|
||||
TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
|
||||
XSDPS_TM_BLK_CNT_EN_MASK |
|
||||
XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
|
||||
XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
|
||||
|
||||
/* Send block write command */
|
||||
Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
/* Send multiple blocks write command */
|
||||
Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1342,8 +1570,13 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
|
|||
}
|
||||
|
||||
for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
|
||||
#ifdef __aarch64__
|
||||
InstancePtr->Adma2_DescrTbl[DescNum].Address =
|
||||
(u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
|
||||
#else
|
||||
InstancePtr->Adma2_DescrTbl[DescNum].Address =
|
||||
(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
|
||||
#endif
|
||||
InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
|
||||
XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
|
||||
/* This will write '0' to length field which indicates 65536 */
|
||||
|
|
@ -1351,8 +1584,13 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
|
|||
(u16)XSDPS_DESC_MAX_LENGTH;
|
||||
}
|
||||
|
||||
#ifdef __aarch64__
|
||||
InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
|
||||
(u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
|
||||
#else
|
||||
InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
|
||||
(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
|
||||
#endif
|
||||
|
||||
InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
|
||||
XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
|
||||
|
|
@ -1360,13 +1598,18 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
|
|||
InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
|
||||
(u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
|
||||
|
||||
#ifdef __aarch64__
|
||||
XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET,
|
||||
(u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32));
|
||||
#endif
|
||||
|
||||
XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
|
||||
(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
|
||||
|
||||
Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
|
||||
if (InstancePtr->Config.IsCacheCoherent == 0) {
|
||||
Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
|
||||
sizeof(XSdPs_Adma2Descriptor) * 32U);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
|
@ -1398,6 +1641,7 @@ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
|
|||
s32 Status;
|
||||
u32 RespOCR;
|
||||
u32 CSD[4];
|
||||
u32 BlkLen, DeviceSize, Mult;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
|
@ -1498,6 +1742,16 @@ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
|
|||
|
||||
InstancePtr->Card_Version = (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
|
||||
|
||||
/* Calculating the memory capacity */
|
||||
BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
|
||||
Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
|
||||
DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
|
||||
DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
|
||||
DeviceSize = (DeviceSize + 1U) * Mult;
|
||||
DeviceSize = DeviceSize * BlkLen;
|
||||
|
||||
InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
|
||||
|
||||
Status = XST_SUCCESS;
|
||||
|
||||
RETURN_PATH:
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xsdps.h
|
||||
* @addtogroup sdps_v2_5
|
||||
* @addtogroup sdps_v3_4
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
|
|
@ -125,6 +125,30 @@
|
|||
* of SDR50, SDR104 and HS200.
|
||||
* sk 02/16/16 Corrected the Tuning logic.
|
||||
* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
|
||||
* 2.8 sk 04/20/16 Added new workaround for auto tuning.
|
||||
* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
|
||||
* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
|
||||
* sk 07/16/16 Added support for UHS modes.
|
||||
* sk 07/07/16 Used usleep API for both arm and microblaze.
|
||||
* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
|
||||
* operating modes.
|
||||
* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
|
||||
* CR#956899.
|
||||
* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
|
||||
* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
|
||||
* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
|
||||
* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
|
||||
* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
|
||||
* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
|
||||
* sk 02/01/17 Added HSD and DDR mode support for eMMC.
|
||||
* sk 02/01/17 Consider bus width parameter from design for switching
|
||||
* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
|
||||
* sk 03/20/17 Add support for EL1 non-secure mode.
|
||||
* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
|
||||
* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
|
||||
* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
|
||||
* information.
|
||||
* mn 09/06/17 Resolved compilation errors with IAR toolchain
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
|
|
@ -142,6 +166,7 @@ extern "C" {
|
|||
#include "xil_cache.h"
|
||||
#include "xstatus.h"
|
||||
#include "xsdps_hw.h"
|
||||
#include "xplatform_info.h"
|
||||
#include <string.h>
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
|
@ -150,6 +175,9 @@ extern "C" {
|
|||
#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information for the device.
|
||||
*/
|
||||
|
|
@ -159,14 +187,28 @@ typedef struct {
|
|||
u32 InputClockHz; /**< Input clock frequency */
|
||||
u32 CardDetect; /**< Card Detect */
|
||||
u32 WriteProtect; /**< Write Protect */
|
||||
u32 BusWidth; /**< Bus Width */
|
||||
u32 BankNumber; /**< MIO Bank selection for SD */
|
||||
u32 HasEMIO; /**< If SD is connected to EMIO */
|
||||
u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
|
||||
} XSdPs_Config;
|
||||
|
||||
/* ADMA2 descriptor table */
|
||||
typedef struct {
|
||||
u16 Attribute; /**< Attributes of descriptor */
|
||||
u16 Length; /**< Length of current dma transfer */
|
||||
#ifdef __aarch64__
|
||||
u64 Address; /**< Address of current dma transfer */
|
||||
#else
|
||||
u32 Address; /**< Address of current dma transfer */
|
||||
#endif
|
||||
#ifdef __ICCARM__
|
||||
#pragma data_alignment = 32
|
||||
} XSdPs_Adma2Descriptor;
|
||||
#pragma data_alignment = 4
|
||||
#else
|
||||
} __attribute__((__packed__))XSdPs_Adma2Descriptor;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* The XSdPs driver instance data. The user is required to allocate a
|
||||
|
|
@ -188,7 +230,10 @@ typedef struct {
|
|||
u32 CardID[4]; /**< Card ID Register */
|
||||
u32 RelCardAddr; /**< Relative Card Address */
|
||||
u32 CardSpecData[4]; /**< Card Specific Data Register */
|
||||
u32 SectorCount; /**< Sector Count */
|
||||
u32 SdCardConfig; /**< Sd Card Configuration Register */
|
||||
u32 Mode; /**< Bus Speed Mode */
|
||||
XSdPs_ConfigTap Config_TapDelay; /**< Configuring the tap delays */
|
||||
/**< ADMA Descriptors */
|
||||
#ifdef __ICCARM__
|
||||
#pragma data_alignment = 32
|
||||
|
|
@ -219,6 +264,13 @@ s32 XSdPs_Pullup(XSdPs *InstancePtr);
|
|||
s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
|
||||
s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
|
||||
s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
|
||||
s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
|
||||
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
|
||||
void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
|
||||
void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
|
||||
void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
|
||||
void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
|
||||
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
|
|
@ -44,14 +44,18 @@
|
|||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XSdPs_Config XSdPs_ConfigTable[] =
|
||||
XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PS7_SD_0_DEVICE_ID,
|
||||
XPAR_PS7_SD_0_BASEADDR,
|
||||
XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ,
|
||||
XPAR_PS7_SD_0_HAS_CD,
|
||||
XPAR_PS7_SD_0_HAS_WP
|
||||
XPAR_PS7_SD_0_HAS_WP,
|
||||
XPAR_PS7_SD_0_BUS_WIDTH,
|
||||
XPAR_PS7_SD_0_MIO_BANK,
|
||||
XPAR_PS7_SD_0_HAS_EMIO,
|
||||
XPAR_PS7_SD_0_IS_CACHE_COHERENT
|
||||
}
|
||||
};
|
||||
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
/**
|
||||
*
|
||||
* @file xsdps_hw.h
|
||||
* @addtogroup sdps_v2_5
|
||||
* @addtogroup sdps_v3_4
|
||||
* @{
|
||||
*
|
||||
* This header file contains the identifiers and basic HW access driver
|
||||
|
|
@ -50,6 +50,17 @@
|
|||
* kvn 07/15/15 Modified the code according to MISRAC-2012.
|
||||
* 2.7 sk 12/10/15 Added support for MMC cards.
|
||||
* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
|
||||
* 2.8 sk 04/20/16 Added new workaround for auto tuning.
|
||||
* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
|
||||
* sk 07/16/16 Added support for UHS modes.
|
||||
* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
|
||||
* operating modes.
|
||||
* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
|
||||
* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
|
||||
* 3.3 mn 08/22/17 Updated for Word Access System support
|
||||
* mn 09/06/17 Added support for ARMCC toolchain
|
||||
* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
@ -796,6 +807,12 @@ extern "C" {
|
|||
#define XSDPS_CUR_LIM_800 3U
|
||||
|
||||
#define CSD_SPEC_VER_MASK 0x3C0000U
|
||||
#define READ_BLK_LEN_MASK 0x00000F00U
|
||||
#define C_SIZE_MULT_MASK 0x00000380U
|
||||
#define C_SIZE_LOWER_MASK 0xFFC00000U
|
||||
#define C_SIZE_UPPER_MASK 0x00000003U
|
||||
#define CSD_STRUCT_MASK 0x00C00000U
|
||||
#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
|
||||
|
||||
/* EXT_CSD field definitions */
|
||||
#define XSDPS_EXT_CSD_SIZE 512U
|
||||
|
|
@ -842,6 +859,10 @@ extern "C" {
|
|||
#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
|
||||
#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
|
||||
|
||||
#define EXT_CSD_RST_N_FUN_BYTE 162U
|
||||
#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
|
||||
#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
|
||||
#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
|
||||
|
||||
#define XSDPS_EXT_CSD_CMD_SET 0U
|
||||
#define XSDPS_EXT_CSD_SET_BITS 1U
|
||||
|
|
@ -880,6 +901,10 @@ extern "C" {
|
|||
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
|
||||
| ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
|
||||
|
||||
#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
|
||||
| ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
|
||||
| ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
|
||||
|
||||
#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
|
||||
|
||||
/* @} */
|
||||
|
|
@ -930,6 +955,10 @@ extern "C" {
|
|||
#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
|
||||
#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
|
||||
#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
|
||||
#define XSDPS_HIGH_SPEED_MODE 0x5U
|
||||
#define XSDPS_DEFAULT_SPEED_MODE 0x6U
|
||||
#define XSDPS_HS200_MODE 0x7U
|
||||
#define XSDPS_DDR52_MODE 0x4U
|
||||
#define XSDPS_SWITCH_CMD_BLKCNT 1U
|
||||
#define XSDPS_SWITCH_CMD_BLKSIZE 64U
|
||||
#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
|
||||
|
|
@ -970,7 +999,16 @@ extern "C" {
|
|||
#define XSDPS_SD_SDR50_MAX_CLK 100000000U
|
||||
#define XSDPS_SD_DDR50_MAX_CLK 50000000U
|
||||
#define XSDPS_SD_SDR104_MAX_CLK 208000000U
|
||||
/*
|
||||
* XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
|
||||
* than the clock value coming from the core. This value is kept to safely
|
||||
* switch to SDR104 mode if the SD card supports it.
|
||||
*/
|
||||
#define XSDPS_SD_INPUT_MAX_CLK 175000000U
|
||||
|
||||
#define XSDPS_MMC_HS200_MAX_CLK 200000000U
|
||||
#define XSDPS_MMC_HSD_MAX_CLK 52000000U
|
||||
#define XSDPS_MMC_DDR_MAX_CLK 52000000U
|
||||
|
||||
#define XSDPS_CARD_STATE_IDLE 0U
|
||||
#define XSDPS_CARD_STATE_RDY 1U
|
||||
|
|
@ -987,15 +1025,51 @@ extern "C" {
|
|||
#define XSDPS_SLOT_REM 0U
|
||||
#define XSDPS_SLOT_EMB 1U
|
||||
|
||||
#if defined (__arm__) || defined (__aarch64__)
|
||||
#define SD_DLL_CTRL 0x00000358U
|
||||
#define SD_ITAPDLY 0x00000314U
|
||||
#define SD_OTAPDLYSEL 0x00000318U
|
||||
#define SD0_DLL_RST 0x00000004U
|
||||
#define SD0_ITAPCHGWIN 0x00000200U
|
||||
#define SD0_ITAPDLYENA 0x00000100U
|
||||
#define SD0_OTAPDLYENA 0x00000040U
|
||||
#define SD0_OTAPDLYSEL_HS200 0x00000003U
|
||||
#define XSDPS_WIDTH_8 8U
|
||||
#define XSDPS_WIDTH_4 4U
|
||||
|
||||
|
||||
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
|
||||
#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
|
||||
#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
|
||||
#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
|
||||
#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
|
||||
#define SD_DLL_CTRL 0x00000358U
|
||||
#define SD_ITAPDLY 0x00000314U
|
||||
#define SD_OTAPDLY 0x00000318U
|
||||
#define SD0_DLL_RST 0x00000004U
|
||||
#define SD1_DLL_RST 0x00040000U
|
||||
#define SD0_ITAPCHGWIN 0x00000200U
|
||||
#define SD0_ITAPDLYENA 0x00000100U
|
||||
#define SD0_OTAPDLYENA 0x00000040U
|
||||
#define SD1_ITAPCHGWIN 0x02000000U
|
||||
#define SD1_ITAPDLYENA 0x01000000U
|
||||
#define SD1_OTAPDLYENA 0x00400000U
|
||||
|
||||
#define SD0_OTAPDLYSEL_HS200_B0 0x00000003U
|
||||
#define SD0_OTAPDLYSEL_HS200_B2 0x00000002U
|
||||
#define SD0_ITAPDLYSEL_SD50 0x00000014U
|
||||
#define SD0_OTAPDLYSEL_SD50 0x00000003U
|
||||
#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU
|
||||
#define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U
|
||||
#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U
|
||||
#define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U
|
||||
#define SD0_ITAPDLYSEL_HSD 0x00000015U
|
||||
#define SD0_OTAPDLYSEL_SD_HSD 0x00000005U
|
||||
#define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U
|
||||
|
||||
#define SD1_OTAPDLYSEL_HS200_B0 0x00030000U
|
||||
#define SD1_OTAPDLYSEL_HS200_B2 0x00020000U
|
||||
#define SD1_ITAPDLYSEL_SD50 0x00140000U
|
||||
#define SD1_OTAPDLYSEL_SD50 0x00030000U
|
||||
#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U
|
||||
#define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U
|
||||
#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U
|
||||
#define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U
|
||||
#define SD1_ITAPDLYSEL_HSD 0x00150000U
|
||||
#define SD1_OTAPDLYSEL_SD_HSD 0x00050000U
|
||||
#define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U
|
||||
|
||||
#endif
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
|
@ -1100,8 +1174,18 @@ extern "C" {
|
|||
* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XSdPs_ReadReg16(BaseAddress, RegOffset) \
|
||||
XSdPs_In16((BaseAddress) + (RegOffset))
|
||||
static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
|
||||
{
|
||||
#if defined (__MICROBLAZE__)
|
||||
u32 Reg;
|
||||
BaseAddress += RegOffset & 0xFC;
|
||||
Reg = XSdPs_In32(BaseAddress);
|
||||
Reg >>= ((RegOffset & 0x3)*8);
|
||||
return (u16)Reg;
|
||||
#else
|
||||
return XSdPs_In16((BaseAddress) + (RegOffset));
|
||||
#endif
|
||||
}
|
||||
|
||||
/***************************************************************************/
|
||||
/**
|
||||
|
|
@ -1119,8 +1203,20 @@ extern "C" {
|
|||
* u16 RegisterValue)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \
|
||||
XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue))
|
||||
|
||||
static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
|
||||
{
|
||||
#if defined (__MICROBLAZE__)
|
||||
u32 Reg;
|
||||
BaseAddress += RegOffset & 0xFC;
|
||||
Reg = XSdPs_In32(BaseAddress);
|
||||
Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
|
||||
Reg |= RegisterValue <<((RegOffset & 0x3)*8);
|
||||
XSdPs_Out32(BaseAddress, Reg);
|
||||
#else
|
||||
XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
|
|
@ -1136,9 +1232,18 @@ extern "C" {
|
|||
* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XSdPs_ReadReg8(BaseAddress, RegOffset) \
|
||||
XSdPs_In8((BaseAddress) + (RegOffset))
|
||||
|
||||
static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
|
||||
{
|
||||
#if defined (__MICROBLAZE__)
|
||||
u32 Reg;
|
||||
BaseAddress += RegOffset & 0xFC;
|
||||
Reg = XSdPs_In32(BaseAddress);
|
||||
Reg >>= ((RegOffset & 0x3)*8);
|
||||
return (u8)Reg;
|
||||
#else
|
||||
return XSdPs_In8((BaseAddress) + (RegOffset));
|
||||
#endif
|
||||
}
|
||||
/***************************************************************************/
|
||||
/**
|
||||
* Write to a register.
|
||||
|
|
@ -1155,9 +1260,19 @@ extern "C" {
|
|||
* u8 RegisterValue)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \
|
||||
XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue))
|
||||
|
||||
static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
|
||||
{
|
||||
#if defined (__MICROBLAZE__)
|
||||
u32 Reg;
|
||||
BaseAddress += RegOffset & 0xFC;
|
||||
Reg = XSdPs_In32(BaseAddress);
|
||||
Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
|
||||
Reg |= RegisterValue <<((RegOffset & 0x3)*8);
|
||||
XSdPs_Out32(BaseAddress, Reg);
|
||||
#else
|
||||
XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
|
||||
#endif
|
||||
}
|
||||
/***************************************************************************/
|
||||
/**
|
||||
* Macro to get present status register
|
||||
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Add a link
Reference in a new issue