Add graphics to the SAM4E demo.

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/RTOSDemo.cproj

@@ -12,8 +12,11 @@
         <options>
           <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />
           <option id="common.services.ioport" value="Add" config="" content-id="Atmel.ASF" />
+          <option id="sam.components.display.aat31xx" value="Add" config="" content-id="Atmel.ASF" />
+          <option id="sam.components.display.ili93xx" value="Add" config="" content-id="Atmel.ASF" />
           <option id="sam.components.ethernet_phy.ksz8051mnl" value="Add" config="" content-id="Atmel.ASF" />
           <option id="sam.drivers.gmac" value="Add" config="" content-id="Atmel.ASF" />
+          <option id="sam.drivers.smc" value="Add" config="" content-id="Atmel.ASF" />
           <option id="common.applications.user_application" value="Add" config="" content-id="Atmel.ASF" />
           <option id="sam.utils.cmsis.sam4e.source.template" value="Add" config="" content-id="Atmel.ASF" />
         </options>
@@ -160,6 +163,16 @@
           <file path="src/ASF/sam/drivers/gmac/gmac.h" framework="" version="3.11.0" source="sam\drivers\gmac\gmac.h" changed="False" content-id="Atmel.ASF" />
           <file path="src/Config/conf_eth.h" framework="" version="3.11.0" source="sam\drivers\gmac\module_config\conf_eth.h" changed="False" content-id="Atmel.ASF" />
           <file path="src/ASF/sam/components/ethernet_phy/documentation.h" framework="" version="3.11.0" source="sam\components\ethernet_phy\documentation.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam/components/display/aat31xx/aat31xx.c" framework="" version="3.11.0" source="sam\components\display\aat31xx\aat31xx.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam/components/display/aat31xx/aat31xx.h" framework="" version="3.11.0" source="sam\components\display\aat31xx\aat31xx.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/Config/conf_aat31xx.h" framework="" version="3.11.0" source="sam\components\display\aat31xx\module_config\conf_aat31xx.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam/components/display/ili93xx/ili93xx.c" framework="" version="3.11.0" source="sam\components\display\ili93xx\ili93xx.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam/components/display/ili93xx/ili93xx.h" framework="" version="3.11.0" source="sam\components\display\ili93xx\ili93xx.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam/components/display/ili93xx/ili9325_regs.h" framework="" version="3.11.0" source="sam\components\display\ili93xx\ili9325_regs.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam/components/display/ili93xx/ili9341_regs.h" framework="" version="3.11.0" source="sam\components\display\ili93xx\ili9341_regs.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/Config/conf_ili93xx.h" framework="" version="3.11.0" source="sam\components\display\ili93xx\module_config\conf_ili93xx.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam/drivers/ebi/smc/smc.c" framework="" version="3.11.0" source="sam\drivers\ebi\smc\smc.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam/drivers/ebi/smc/smc.h" framework="" version="3.11.0" source="sam\drivers\ebi\smc\smc.h" changed="False" content-id="Atmel.ASF" />
         </files>
         <documentation help="http://asf.atmel.com/docs/3.11.0/common.applications.user_application.sam4e_ek/html/index.html" />
         <offline-documentation help="" />
@@ -245,6 +258,9 @@
       <Value>%24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL\sam4e\include</Value>
       <Value>../src/ASF/sam/components/ethernet_phy/ksz8051mnl</Value>
       <Value>../src/ASF/sam/drivers/gmac</Value>
+      <Value>../src/ASF/sam/components/display/aat31xx</Value>
+      <Value>../src/ASF/sam/components/display/ili93xx</Value>
+      <Value>../src/ASF/sam/drivers/ebi/smc</Value>
     </ListValues>
   </armgcc.compiler.directories.IncludePaths>
   <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
@@ -290,6 +306,9 @@
       <Value>%24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL\sam4e\include</Value>
       <Value>../src/ASF/sam/components/ethernet_phy/ksz8051mnl</Value>
       <Value>../src/ASF/sam/drivers/gmac</Value>
+      <Value>../src/ASF/sam/components/display/aat31xx</Value>
+      <Value>../src/ASF/sam/components/display/ili93xx</Value>
+      <Value>../src/ASF/sam/drivers/ebi/smc</Value>
     </ListValues>
   </armgcc.assembler.general.IncludePaths>
   <armgcc.preprocessingassembler.general.AssemblerFlags>-DARM_MATH_CM4=true -DBOARD=SAM4E_EK -D__SAM4E16E__ -Dprintf=iprintf</armgcc.preprocessingassembler.general.AssemblerFlags>
@@ -318,6 +337,9 @@
       <Value>%24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL\sam4e\include</Value>
       <Value>../src/ASF/sam/components/ethernet_phy/ksz8051mnl</Value>
       <Value>../src/ASF/sam/drivers/gmac</Value>
+      <Value>../src/ASF/sam/components/display/aat31xx</Value>
+      <Value>../src/ASF/sam/components/display/ili93xx</Value>
+      <Value>../src/ASF/sam/drivers/ebi/smc</Value>
     </ListValues>
   </armgcc.preprocessingassembler.general.IncludePaths>
 </ArmGcc>
@@ -376,6 +398,10 @@
       <Value>../../../../FreeRTOS-Plus/Source/FreeRTOS-Plus-FAT-SL/api</Value>
       <Value>../../../../FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands</Value>
       <Value>../../Common/include</Value>
+      <Value>../src/ASF/sam/components/display/aat31xx</Value>
+      <Value>../src/ASF/sam/components/display/ili93xx</Value>
+      <Value>../src/ASF/sam/drivers/ebi/smc</Value>
+      <Value>../../../../FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients</Value>
     </ListValues>
   </armgcc.compiler.directories.IncludePaths>
   <armgcc.compiler.optimization.OtherFlags>-fdata-sections</armgcc.compiler.optimization.OtherFlags>
@@ -421,6 +447,9 @@
       <Value>%24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL\sam4e\include</Value>
       <Value>../src/ASF/sam/components/ethernet_phy/ksz8051mnl</Value>
       <Value>../src/ASF/sam/drivers/gmac</Value>
+      <Value>../src/ASF/sam/components/display/aat31xx</Value>
+      <Value>../src/ASF/sam/components/display/ili93xx</Value>
+      <Value>../src/ASF/sam/drivers/ebi/smc</Value>
     </ListValues>
   </armgcc.assembler.general.IncludePaths>
   <armgcc.assembler.debugging.DebugLevel>Default (-g)</armgcc.assembler.debugging.DebugLevel>
@@ -450,6 +479,9 @@
       <Value>%24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL\sam4e\include</Value>
       <Value>../src/ASF/sam/components/ethernet_phy/ksz8051mnl</Value>
       <Value>../src/ASF/sam/drivers/gmac</Value>
+      <Value>../src/ASF/sam/components/display/aat31xx</Value>
+      <Value>../src/ASF/sam/components/display/ili93xx</Value>
+      <Value>../src/ASF/sam/drivers/ebi/smc</Value>
     </ListValues>
   </armgcc.preprocessingassembler.general.IncludePaths>
   <armgcc.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcc.preprocessingassembler.debugging.DebugLevel>
@@ -481,6 +513,10 @@
       <SubType>compile</SubType>
       <Link>src\UDPCommandServer.c</Link>
     </Compile>
+    <Compile Include="..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.c">
+      <SubType>compile</SubType>
+      <Link>src\TwoEchoClients.c</Link>
+    </Compile>
     <Compile Include="..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\dir.c">
       <SubType>compile</SubType>
       <Link>src\FreeRTOS+\FreeRTOS+FAT SL\dir.c</Link>
@@ -561,6 +597,30 @@
       <SubType>compile</SubType>
       <Link>src\Common Demo Tasks\semtest.c</Link>
     </Compile>
+    <Compile Include="src\ASF\sam\components\display\aat31xx\aat31xx.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="src\ASF\sam\components\display\aat31xx\aat31xx.h">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="src\ASF\sam\components\display\ili93xx\ili9325_regs.h">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="src\ASF\sam\components\display\ili93xx\ili9341_regs.h">
+      <SubType>compile</SubType>
+    </None>
+    <Compile Include="src\ASF\sam\components\display\ili93xx\ili93xx.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="src\ASF\sam\components\display\ili93xx\ili93xx.h">
+      <SubType>compile</SubType>
+    </None>
+    <Compile Include="src\ASF\sam\drivers\ebi\smc\smc.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="src\ASF\sam\drivers\ebi\smc\smc.h">
+      <SubType>compile</SubType>
+    </None>
     <Compile Include="src\ASF\sam\utils\syscalls\gcc\syscalls.c">
       <SubType>compile</SubType>
     </Compile>
@@ -570,9 +630,18 @@
     <Compile Include="src\config\config_mdriver_ram.h">
       <SubType>compile</SubType>
     </Compile>
+    <None Include="src\config\conf_aat31xx.h">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="src\config\conf_ili93xx.h">
+      <SubType>compile</SubType>
+    </None>
     <Compile Include="src\FreeRTOS+\FreeRTOS+FAT SL\API\fat_sl.h">
       <SubType>compile</SubType>
     </Compile>
+    <Compile Include="src\LCDUtils.c">
+      <SubType>compile</SubType>
+    </Compile>
     <Compile Include="src\main_blinky.c">
       <SubType>compile</SubType>
     </Compile>
@@ -1037,9 +1106,6 @@
     <None Include="src\ASF\sam\utils\status_codes.h">
       <SubType>compile</SubType>
     </None>
-    <None Include="src\ASF\thirdparty\CMSIS\CMSIS END USER LICENCE AGREEMENT.pdf">
-      <SubType>compile</SubType>
-    </None>
     <None Include="src\ASF\thirdparty\CMSIS\Include\arm_math.h">
       <SubType>compile</SubType>
     </None>
@@ -1081,9 +1147,14 @@
     <Folder Include="src\ASF\sam\boards\" />
     <Folder Include="src\ASF\sam\boards\sam4e_ek\" />
     <Folder Include="src\ASF\sam\components\" />
+    <Folder Include="src\ASF\sam\components\display\" />
+    <Folder Include="src\ASF\sam\components\display\aat31xx\" />
+    <Folder Include="src\ASF\sam\components\display\ili93xx\" />
     <Folder Include="src\ASF\sam\components\ethernet_phy\" />
     <Folder Include="src\ASF\sam\components\ethernet_phy\ksz8051mnl\" />
     <Folder Include="src\ASF\sam\drivers\" />
+    <Folder Include="src\ASF\sam\drivers\ebi\" />
+    <Folder Include="src\ASF\sam\drivers\ebi\smc\" />
     <Folder Include="src\ASF\sam\drivers\gmac\" />
     <Folder Include="src\ASF\sam\drivers\pmc\" />
     <Folder Include="src\ASF\sam\utils\" />

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/aat31xx/aat31xx.c

@@ -0,0 +1,137 @@
+/**
+ * \file
+ *
+ * \brief API driver for component aat31xx.
+ *
+ * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \defgroup aat31xx_display_group Display - AAT31XX Controller
+ *
+ * Low-level driver for the AAT31XX LCD backlight controller. This driver provides access to the main
+ * features of the AAT31XX controller.
+ *
+ * \{
+ */
+
+#include "board.h"
+#include "ioport.h"
+#include "aat31xx.h"
+#include "conf_aat31xx.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#define DELAY_PULSE      (0x18u)
+#define DELAY_ENABLE     (0x20000u)
+#define DELAY_DISABLE    (0x20000u)
+
+/**
+ * \brief Set the LCD backlight level.
+ *
+ * \param ul_level backlight level.
+ *
+ * \note pin BOARD_AAT31XX_SET_GPIO must be configured before calling aat31xx_set_backlight.
+ */
+void aat31xx_set_backlight(uint32_t ul_level)
+{
+	volatile uint32_t ul_delay;
+	uint32_t i;
+
+#ifdef CONF_BOARD_AAT3155
+	ul_level = AAT31XX_MAX_BACKLIGHT_LEVEL - ul_level + 1;
+#endif
+
+#ifdef CONF_BOARD_AAT3193
+	ul_level = AAT31XX_MAX_BACKLIGHT_LEVEL - ul_level + 1;
+#endif
+
+	/* Ensure valid level */
+	ul_level = (ul_level > AAT31XX_MAX_BACKLIGHT_LEVEL) ? AAT31XX_MAX_BACKLIGHT_LEVEL : ul_level;
+	ul_level = (ul_level < AAT31XX_MIN_BACKLIGHT_LEVEL) ? AAT31XX_MIN_BACKLIGHT_LEVEL : ul_level;
+
+	/* Set new backlight level */
+	for (i = 0; i < ul_level; i++) {
+		ioport_set_pin_level(BOARD_AAT31XX_SET_GPIO, IOPORT_PIN_LEVEL_LOW);
+		ul_delay = DELAY_PULSE;
+		while (ul_delay--) {
+		}
+
+		ioport_set_pin_level(BOARD_AAT31XX_SET_GPIO, IOPORT_PIN_LEVEL_HIGH);
+
+		ul_delay = DELAY_PULSE;
+		while (ul_delay--) {
+		}
+	}
+
+	ul_delay = DELAY_ENABLE;
+	while (ul_delay--) {
+	}
+}
+
+/**
+ * \brief Switch off backlight.
+ */
+void aat31xx_disable_backlight(void)
+{
+	volatile uint32_t ul_delay;
+
+	ioport_set_pin_level(BOARD_AAT31XX_SET_GPIO, IOPORT_PIN_LEVEL_LOW);
+
+	ul_delay = DELAY_DISABLE;
+	while (ul_delay--) {
+	}
+}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \}
+ */

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/aat31xx/aat31xx.h

@@ -0,0 +1,94 @@
+/**
+ * \file
+ *
+ * \brief API driver for component aat31xx.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef AAT31XX_H_INCLUDED
+#define AAT31XX_H_INCLUDED
+
+#include "compiler.h"
+#include "conf_board.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/* The minimum, average and maximum brightness level values */
+#ifdef CONF_BOARD_AAT3155
+#define AAT31XX_MIN_BACKLIGHT_LEVEL           1
+#define AAT31XX_AVG_BACKLIGHT_LEVEL           8
+#define AAT31XX_MAX_BACKLIGHT_LEVEL           16
+#endif
+#ifdef CONF_BOARD_AAT3193
+#define AAT31XX_MIN_BACKLIGHT_LEVEL           1
+#define AAT31XX_AVG_BACKLIGHT_LEVEL           8
+#define AAT31XX_MAX_BACKLIGHT_LEVEL           16
+#endif
+#ifdef CONF_BOARD_AAT3194
+#define AAT31XX_MIN_BACKLIGHT_LEVEL           1
+#define AAT31XX_AVG_BACKLIGHT_LEVEL           25
+#define AAT31XX_MAX_BACKLIGHT_LEVEL           32
+#endif
+
+/* No component found */
+#ifndef AAT31XX_MIN_BACKLIGHT_LEVEL
+#warning Cannot configure AAT31XX. The component must be declared in conf_board.h first!
+#define AAT31XX_MIN_BACKLIGHT_LEVEL           0
+#define AAT31XX_AVG_BACKLIGHT_LEVEL           0
+#define AAT31XX_MAX_BACKLIGHT_LEVEL           0
+#endif
+
+void aat31xx_set_backlight(uint32_t ul_level);
+void aat31xx_disable_backlight(void);
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* AAT31XX_H_INCLUDED */

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili9325_regs.h

@@ -0,0 +1,646 @@
+/**
+ * \file
+ *
+ * \brief registers definition for ili9325 TFT display component.
+ *
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ILI9325_REGS_H_INCLUDED
+#define ILI9325_REGS_H_INCLUDED
+
+/** @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/** @endcond */
+
+/** ili9325 LCD Registers */
+
+/** Driver Code Read */
+#define ILI9325_DEVICE_CODE_REG (0x00u)
+
+/** ILI9325_START_OSC_CTRL : (Offset: 0x00) Start Oscillator Control*/
+#define ILI9325_START_OSC_CTRL    (0x00u)
+#define ILI9325_START_OSC_CTRL_EN (0x1u << 0)
+
+/** ILI9325_DRIVER_OUTPUT_CTRL1 : (Offset: 0x01) Driver Output Control 1*/
+#define ILI9325_DRIVER_OUTPUT_CTRL1    (0x01u)
+#define ILI9325_DRIVER_OUTPUT_CTRL1_SS (0x1u << 8)
+#define ILI9325_DRIVER_OUTPUT_CTRL1_SM (0x1u << 10)
+
+/** ILI9325_LCD_DRIVING_CTRL : (Offset: 0x02) LCD Driving Control */
+#define ILI9325_LCD_DRIVING_CTRL       (0x02u)
+#define ILI9325_LCD_DRIVING_CTRL_EOR   (0x1u << 8)
+#define ILI9325_LCD_DRIVING_CTRL_BC0   (0x1u << 9)
+#define ILI9325_LCD_DRIVING_CTRL_BIT10 (0x1u << 10)
+
+/** ILI9325_ENTRY_MODE : (Offset: 0x03) Entry Mode*/
+#define ILI9325_ENTRY_MODE           (0x03u)
+#define ILI9325_ENTRY_MODE_AM        (0x1u << 3)
+#define ILI9325_ENTRY_MODE_ID_POS     4
+#define ILI9325_ENTRY_MODE_ID_MSK    (0x3u << ILI9325_ENTRY_MODE_ID_POS)
+#define ILI9325_ENTRY_MODE_ID(value) ((ILI9325_ENTRY_MODE_ID_MSK & \
+	((value) << ILI9325_ENTRY_MODE_ID_POS)))
+#define ILI9325_ENTRY_MODE_ORG       (0x1u << 7)
+#define ILI9325_ENTRY_MODE_HWM       (0x1u << 9)
+#define ILI9325_ENTRY_MODE_BGR       (0x1u << 12)
+#define ILI9325_ENTRY_MODE_DFM       (0x1u << 14)
+#define ILI9325_ENTRY_MODE_TRI       (0x1u << 15)
+
+/** ILI9325_RESIZE_CTRL : (Offset: 0x04) Resize Control */
+#define ILI9325_RESIZE_CTRL            (0x04u)
+#define ILI9325_RESIZE_CTRL_RSZ_POS     0
+#define ILI9325_RESIZE_CTRL_RSZ_MSK    (0x3u << ILI9325_RESIZE_CTRL_RSZ_POS)
+#define ILI9325_RESIZE_CTRL_RSZ(value) ((ILI9325_RESIZE_CTRL_RSZ_MSK & \
+	((value) << ILI9325_RESIZE_CTRL_RSZ_POS)))
+#define ILI9325_RESIZE_CTRL_RCH_POS     4
+#define ILI9325_RESIZE_CTRL_RCH_MSK    (0x3u << ILI9325_RESIZE_CTRL_RCH_POS)
+#define ILI9325_RESIZE_CTRL_RCH(value) ((ILI9325_RESIZE_CTRL_RCH_MSK & \
+	((value) << ILI9325_RESIZE_CTRL_RCH_POS)))
+#define ILI9325_RESIZE_CTRL_RCV_POS     8
+#define ILI9325_RESIZE_CTRL_RCV_MSK    (0x3u << ILI9325_RESIZE_CTRL_RCV_POS)
+#define ILI9325_RESIZE_CTRL_RCV(value) ((ILI9325_RESIZE_CTRL_RCV_MSK & \
+	((value) << ILI9325_RESIZE_CTRL_RCV_POS)))
+
+/** ILI9325_DISP_CTRL1 : (Offset: 0x07) Display Control 1 */
+#define ILI9325_DISP_CTRL1             (0x07u)
+#define ILI9325_DISP_CTRL1_D_POS        0
+#define ILI9325_DISP_CTRL1_D_MSK       (0x3u << ILI9325_DISP_CTRL1_D_POS)
+#define ILI9325_DISP_CTRL1_D(value)    ((ILI9325_DISP_CTRL1_D_MSK & \
+	((value) << ILI9325_DISP_CTRL1_D_POS)))
+#define ILI9325_DISP_CTRL1_CL          (0x1u << 3)
+#define ILI9325_DISP_CTRL1_DTE         (0x1u << 4)
+#define ILI9325_DISP_CTRL1_GON         (0x1u << 5)
+#define ILI9325_DISP_CTRL1_BASEE       (0x1u << 8)
+#define ILI9325_DISP_CTRL1_PTDE_POS     12
+#define ILI9325_DISP_CTRL1_PTDE_MSK    (0x3u << ILI9325_DISP_CTRL1_PTDE_POS)
+#define ILI9325_DISP_CTRL1_PTDE(value) ((ILI9325_DISP_CTRL1_PTDE_MSK & \
+	((value) << ILI9325_DISP_CTRL1_PTDE_POS)))
+
+/** ILI9325_DISP_CTRL2 : (Offset: 0x08) Display Control 2 */
+#define ILI9325_DISP_CTRL2           (0x08u)
+#define ILI9325_DISP_CTRL2_BP_POS     0
+#define ILI9325_DISP_CTRL2_BP_MSK    (0xfu << ILI9325_DISP_CTRL2_BP_POS)
+#define ILI9325_DISP_CTRL2_BP(value) ((ILI9325_DISP_CTRL2_BP_MSK & \
+	((value) << ILI9325_DISP_CTRL2_BP_POS)))
+#define ILI9325_DISP_CTRL2_FP_POS     8
+#define ILI9325_DISP_CTRL2_FP_MSK    (0xfu << ILI9325_DISP_CTRL2_FP_POS)
+#define ILI9325_DISP_CTRL2_FP(value) ((ILI9325_DISP_CTRL2_FP_MSK & \
+	((value) << ILI9325_DISP_CTRL2_FP_POS)))
+
+/** ILI9325_DISP_CTRL3 : (Offset: 0x09) Display Control 3 */
+#define ILI9325_DISP_CTRL3            (0x09u)
+#define ILI9325_DISP_CTRL3_ISC_POS     0
+#define ILI9325_DISP_CTRL3_ISC_MSK    (0xfu << ILI9325_DISP_CTRL3_ISC_POS)
+#define ILI9325_DISP_CTRL3_ISC(value) ((ILI9325_DISP_CTRL3_ISC_MSK & \
+	((value) << ILI9325_DISP_CTRL3_ISC_POS)))
+#define ILI9325_DISP_CTRL3_PTG_POS     4
+#define ILI9325_DISP_CTRL3_PTG_MSK    (0x3u << ILI9325_DISP_CTRL3_PTG_POS)
+#define ILI9325_DISP_CTRL3_PTG(value) ((ILI9325_DISP_CTRL3_PTG_MSK & \
+	((value) << ILI9325_DISP_CTRL3_PTG_POS)))
+#define ILI9325_DISP_CTRL3_PTS_POS     8
+#define ILI9325_DISP_CTRL3_PTS_MSK    (0x7u << ILI9325_DISP_CTRL3_PTS_POS)
+#define ILI9325_DISP_CTRL3_PTS(value) ((ILI9325_DISP_CTRL3_PTS_MSK & \
+	((value) << ILI9325_DISP_CTRL3_PTS_POS)))
+
+/** ILI9325_DISP_CTRL4 : (Offset: 0x0A) Display Control 4 */
+#define ILI9325_DISP_CTRL4            (0x0Au)
+#define ILI9325_DISP_CTRL4_FMI_POS     0
+#define ILI9325_DISP_CTRL4_FMI_MSK    (0x7u << ILI9325_DISP_CTRL4_FMI_POS)
+#define ILI9325_DISP_CTRL4_FMI(value) ((ILI9325_DISP_CTRL4_FMI_MSK & \
+	((value) << ILI9325_DISP_CTRL4_FMI_POS)))
+#define ILI9325_DISP_CTRL4_FMARKOE    (0x1u << 3)
+
+/** ILI9325_RGB_DISP_INTERFACE_CTRL1 : (Offset: 0x0C) RGB Display
+ *Interface Control 1 */
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1            (0x0Cu)
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM_POS     0
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM_MSK    (0x3u << \
+	ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM_POS)
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM(value) (( \
+		ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM_MSK & \
+		((value) << ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM_POS)))
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_DM0        (0x1u << 4)
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_DM1        (0x1u << 5)
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_DM_POS      4
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_DM_MSK     (0x3u << \
+	ILI9325_RGB_DISP_INTERFACE_CTRL1_DM_POS)
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_DM(value)  (( \
+		ILI9325_RGB_DISP_INTERFACE_CTRL1_DM_MSK & \
+		((value) << ILI9325_RGB_DISP_INTERFACE_CTRL1_DM_POS)))
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_RM         (0x1u << 8)
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC_POS     12
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC_MSK    (0x7u << \
+	ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC_POS)
+#define ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC(value) (( \
+		ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC_MSK & \
+		((value) < ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC_POS)))
+
+/** ILI9325_FRAME_MAKER_POS : (Offset: 0x0D) Frame Maker Position */
+#define ILI9325_FRAME_MAKER_POS            (0x0Du)
+#define ILI9325_FRAME_MAKER_POS_FMP_POS     0
+#define ILI9325_FRAME_MAKER_POS_FMP_MSK    (0x1ffu << \
+	ILI9325_FRAME_MAKER_POS_FMP_POS)
+#define ILI9325_FRAME_MAKER_POS_FMP(value) ((ILI9325_FRAME_MAKER_POS_FMP_MSK & \
+	((value) << ILI9325_FRAME_MAKER_POS_FMP_POS)))
+
+/** ILI9325_RGB_DISP_INTERFACE_CTRL2 : (Offset: 0x0F) RGB Display
+ * Interface Control 2 */
+#define ILI9325_RGB_DISP_INTERFACE_CTRL2      (0x0Fu)
+#define ILI9325_RGB_DISP_INTERFACE_CTRL2_EPL  (0x1u << 0)
+#define ILI9325_RGB_DISP_INTERFACE_CTRL2_DPL  (0x1u << 1)
+#define ILI9325_RGB_DISP_INTERFACE_CTRL2_HSPL (0x1u << 3)
+#define ILI9325_RGB_DISP_INTERFACE_CTRL2_VSPL (0x1u << 4)
+
+/** ILI9325_POWER_CTRL1 : (Offset: 0x10) Power Control 1 */
+#define ILI9325_POWER_CTRL1           (0x10u)
+#define ILI9325_POWER_CTRL1_STB       (0x1u << 0)
+#define ILI9325_POWER_CTRL1_SLP       (0x1u << 1)
+#define ILI9325_POWER_CTRL1_DSTB      (0x1u << 2)
+#define ILI9325_POWER_CTRL1_AP_POS     4
+#define ILI9325_POWER_CTRL1_AP_MSK    (0x7u << ILI9325_POWER_CTRL1_AP_POS)
+#define ILI9325_POWER_CTRL1_AP(value) ((ILI9325_POWER_CTRL1_AP_MSK & \
+	((value) << ILI9325_POWER_CTRL1_AP_POS)))
+#define ILI9325_POWER_CTRL1_APE       (0x1u << 7)
+#define ILI9325_POWER_CTRL1_BT_POS     8
+#define ILI9325_POWER_CTRL1_BT_MSK    (0x7u << ILI9325_POWER_CTRL1_BT_POS)
+#define ILI9325_POWER_CTRL1_BT(value) ((ILI9325_POWER_CTRL1_BT_MSK & \
+	((value) << ILI9325_POWER_CTRL1_BT_POS)))
+#define ILI9325_POWER_CTRL1_SAP       (0x1u << 12)
+
+/** ILI9325_POWER_CTRL2 : (Offset: 0x11) Power Control 2 */
+#define ILI9325_POWER_CTRL2            (0x11u)
+#define ILI9325_POWER_CTRL2_VC_POS      0
+#define ILI9325_POWER_CTRL2_VC_MSK     (0x7u << ILI9325_POWER_CTRL2_VC_POS)
+#define ILI9325_POWER_CTRL2_VC(value)  ((ILI9325_POWER_CTRL2_VC_MSK & \
+	((value) << ILI9325_POWER_CTRL2_VC_POS)))
+#define ILI9325_POWER_CTRL2_DC0_POS     4
+#define ILI9325_POWER_CTRL2_DC0_MSK    (0x7u << ILI9325_POWER_CTRL2_DC0_POS)
+#define ILI9325_POWER_CTRL2_DC0(value) ((ILI9325_POWER_CTRL2_DC0_MSK & \
+	((value) << ILI9325_POWER_CTRL2_DC0_POS)))
+#define ILI9325_POWER_CTRL2_DC1_POS     8
+#define ILI9325_POWER_CTRL2_DC1_MSK    (0x7u << ILI9325_POWER_CTRL2_DC1_POS)
+#define ILI9325_POWER_CTRL2_DC1(value) ((ILI9325_POWER_CTRL2_DC1_MSK & \
+	((value) << ILI9325_POWER_CTRL2_DC1_POS)))
+
+/** ILI9325_POWER_CTRL3 : (Offset: 0x12) Power Control 3 */
+#define ILI9325_POWER_CTRL3            (0x12u)
+#define ILI9325_POWER_CTRL3_VRH_POS     0
+#define ILI9325_POWER_CTRL3_VRH_MSK    (0xfu << ILI9325_POWER_CTRL3_VRH_POS)
+#define ILI9325_POWER_CTRL3_VRH(value) ((ILI9325_POWER_CTRL3_VRH_MSK & \
+	((value) << ILI9325_POWER_CTRL3_VRH_POS)))
+#define ILI9325_POWER_CTRL3_PON        (0x1u << 4)
+#define ILI9325_POWER_CTRL3_VCIRE      (0x1u << 7)
+
+/** ILI9325_POWER_CTRL4 : (Offset: 0x13) Power Control 4 */
+#define ILI9325_POWER_CTRL4            (0x13u)
+#define ILI9325_POWER_CTRL4_VDV_POS     8
+#define ILI9325_POWER_CTRL4_VDV_MSK    (0x1fu << ILI9325_POWER_CTRL4_VDV_POS)
+#define ILI9325_POWER_CTRL4_VDV(value) ((ILI9325_POWER_CTRL4_VDV_MSK & \
+	((value) << ILI9325_POWER_CTRL4_VDV_POS)))
+
+/** ILI9325_HORIZONTAL_GRAM_ADDR_SET : (Offset: 0x20) Horizontal GRAM
+ * Address Set */
+#define ILI9325_HORIZONTAL_GRAM_ADDR_SET           (0x20u)
+#define ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD_POS     0
+#define ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD_MSK    (0xffu << \
+	ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD_POS)
+#define ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD(value) (( \
+		ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD_MSK & \
+		((value) << ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD_POS)))
+
+/** ILI9325_VERTICAL_GRAM_ADDR_SET : (Offset: 0x21) Vertical  GRAM
+ * Address Set */
+#define ILI9325_VERTICAL_GRAM_ADDR_SET           (0x21u)
+#define ILI9325_VERTICAL_GRAM_ADDR_SET_AD_POS     0
+#define ILI9325_VERTICAL_GRAM_ADDR_SET_AD_MSK    (0xffu << \
+	ILI9325_VERTICAL_GRAM_ADDR_SET_AD_POS)
+#define ILI9325_VERTICAL_GRAM_ADDR_SET_AD(value) (( \
+		ILI9325_VERTICAL_GRAM_ADDR_SET_AD_MSK &	\
+		((value) << ILI9325_VERTICAL_GRAM_ADDR_SET_AD_POS)))
+
+/** ILI9325_GRAM_DATA_REG : (Offset: 0x22) GRAM Data Register */
+#define ILI9325_GRAM_DATA_REG (0x22u)
+
+/** ILI9325_POWER_CTRL7 : (Offset: 0x29) Power Control 7 */
+#define ILI9325_POWER_CTRL7            (0x29u)
+#define ILI9325_POWER_CTRL7_VCM_POS     0
+#define ILI9325_POWER_CTRL7_VCM_MSK    (0x3fu << ILI9325_POWER_CTRL7_VCM_POS)
+#define ILI9325_POWER_CTRL7_VCM(value) ((ILI9325_POWER_CTRL7_VCM_MSK & \
+	((value) << ILI9325_POWER_CTRL7_VCM_POS)))
+
+/** ILI9325_FRAME_RATE_AND_COLOR_CTRL : (Offset: 0x2B) Frame Rate and
+ * Color Control */
+#define ILI9325_FRAME_RATE_AND_COLOR_CTRL            (0x2Bu)
+#define ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS_POS     0
+#define ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS_MSK    (0xfu << \
+	ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS_POS)
+#define ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS(value) ((	\
+		ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS_MSK & \
+		((value) << ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS_POS)))
+
+/** ILI9325_GAMMA_CTL1 : (Offset: 0x30) Gamma Control 1 */
+#define ILI9325_GAMMA_CTL1            (0x30u)
+#define ILI9325_GAMMA_CTL1_KP0_POS     0
+#define ILI9325_GAMMA_CTL1_KP0_MSK    (0x7u << ILI9325_GAMMA_CTL1_KP0_POS)
+#define ILI9325_GAMMA_CTL1_KP0(value) ((ILI9325_GAMMA_CTL1_KP0_MSK & \
+	((value) << ILI9325_GAMMA_CTL1_KP0_POS)))
+#define ILI9325_GAMMA_CTL1_KP1_POS     8
+#define ILI9325_GAMMA_CTL1_KP1_MSK    (0x7u << ILI9325_GAMMA_CTL1_KP1_POS)
+#define ILI9325_GAMMA_CTL1_KP1(value) ((ILI9325_GAMMA_CTL1_KP1_MSK & \
+	((value) << ILI9325_GAMMA_CTL1_KP1_POS)))
+
+/** ILI9325_GAMMA_CTL2 : (Offset: 0x31) Gamma Control 2 */
+#define ILI9325_GAMMA_CTL2            (0x31u)
+#define ILI9325_GAMMA_CTL2_KP2_POS     0
+#define ILI9325_GAMMA_CTL2_KP2_MSK    (0x7u << ILI9325_GAMMA_CTL2_KP2_POS)
+#define ILI9325_GAMMA_CTL2_KP2(value) ((ILI9325_GAMMA_CTL2_KP2_MSK & \
+	((value) << ILI9325_GAMMA_CTL2_KP2_POS)))
+#define ILI9325_GAMMA_CTL2_KP3_POS     8
+#define ILI9325_GAMMA_CTL2_KP3_MSK    (0x7u << ILI9325_GAMMA_CTL2_KP3_POS)
+#define ILI9325_GAMMA_CTL2_KP3(value) ((ILI9325_GAMMA_CTL2_KP3_MSK & \
+	((value) << ILI9325_GAMMA_CTL2_KP3_POS)))
+
+/** ILI9325_GAMMA_CTL3 : (Offset: 0x32) Gamma Control 3 */
+#define ILI9325_GAMMA_CTL3            (0x32u)
+#define ILI9325_GAMMA_CTL3_KP4_POS     0
+#define ILI9325_GAMMA_CTL3_KP4_MSK    (0x7u << ILI9325_GAMMA_CTL3_KP4_POS)
+#define ILI9325_GAMMA_CTL3_KP4(value) ((ILI9325_GAMMA_CTL3_KP4_MSK & \
+	((value) << ILI9325_GAMMA_CTL3_KP4_POS)))
+#define ILI9325_GAMMA_CTL3_KP5_POS     8
+#define ILI9325_GAMMA_CTL3_KP5_MSK    (0x7u << ILI9325_GAMMA_CTL3_KP5_POS)
+#define ILI9325_GAMMA_CTL3_KP5(value) ((ILI9325_GAMMA_CTL3_KP5_MSK & \
+	((value) << ILI9325_GAMMA_CTL3_KP5_POS)))
+
+/** ILI9325_GAMMA_CTL4 : (Offset: 0x35) Gamma Control 4 */
+#define ILI9325_GAMMA_CTL4            (0x35u)
+#define ILI9325_GAMMA_CTL4_RP0_POS     0
+#define ILI9325_GAMMA_CTL4_RP0_MSK    (0x7u << ILI9325_GAMMA_CTL4_RP0_POS)
+#define ILI9325_GAMMA_CTL4_RP0(value) ((ILI9325_GAMMA_CTL4_RP0_MSK & \
+	((value) << ILI9325_GAMMA_CTL4_RP0_POS)))
+#define ILI9325_GAMMA_CTL4_RP1_POS     8
+#define ILI9325_GAMMA_CTL4_RP1_MSK    (0x7u << ILI9325_GAMMA_CTL4_RP1_POS)
+#define ILI9325_GAMMA_CTL4_RP1(value) ((ILI9325_GAMMA_CTL4_RP1_MSK & \
+	((value) << ILI9325_GAMMA_CTL4_RP1_POS)))
+
+/** ILI9325_GAMMA_CTL5 : (Offset: 0x36) Gamma Control 5 */
+#define ILI9325_GAMMA_CTL5             (0x36u)
+#define ILI9325_GAMMA_CTL5_VRP0_POS     0
+#define ILI9325_GAMMA_CTL5_VRP0_MSK    (0xfu << ILI9325_GAMMA_CTL5_VRP0_POS)
+#define ILI9325_GAMMA_CTL5_VRP0(value) ((ILI9325_GAMMA_CTL5_VRP0_MSK & \
+	((value) << ILI9325_GAMMA_CTL5_VRP0_POS)))
+#define ILI9325_GAMMA_CTL5_VRP1_POS     8
+#define ILI9325_GAMMA_CTL5_VRP1_MSK    (0x1fu << ILI9325_GAMMA_CTL5_VRP1_POS)
+#define ILI9325_GAMMA_CTL5_VRP1(value) ((ILI9325_GAMMA_CTL5_VRP1_MSK & \
+	((value) << ILI9325_GAMMA_CTL5_VRP1_POS)))
+
+/** ILI9325_GAMMA_CTL6 : (Offset: 0x37) Gamma Control 6*/
+#define ILI9325_GAMMA_CTL6            (0x37u)
+#define ILI9325_GAMMA_CTL6_KN0_POS     0
+#define ILI9325_GAMMA_CTL6_KN0_MSK    (0x7u << ILI9325_GAMMA_CTL6_KN0_POS)
+#define ILI9325_GAMMA_CTL6_KN0(value) ((ILI9325_GAMMA_CTL6_KN0_MSK & \
+	((value) << ILI9325_GAMMA_CTL6_KN0_POS)))
+#define ILI9325_GAMMA_CTL6_KN1_POS     8
+#define ILI9325_GAMMA_CTL6_KN1_MSK    (0x7u << ILI9325_GAMMA_CTL6_KN1_POS)
+#define ILI9325_GAMMA_CTL6_KN1(value) ((ILI9325_GAMMA_CTL6_KN1_MSK \
+	& ((value) << ILI9325_GAMMA_CTL6_KN1_POS)))
+
+/** ILI9325_GAMMA_CTL7 : (Offset: 0x38) Gamma Control 7*/
+#define ILI9325_GAMMA_CTL7            (0x38u)
+#define ILI9325_GAMMA_CTL7_KN2_POS     0
+#define ILI9325_GAMMA_CTL7_KN2_MSK    (0x7u << ILI9325_GAMMA_CTL7_KN2_POS)
+#define ILI9325_GAMMA_CTL7_KN2(value) ((ILI9325_GAMMA_CTL7_KN2_MSK & \
+	((value) << ILI9325_GAMMA_CTL7_KN2_POS)))
+#define ILI9325_GAMMA_CTL7_KN3_POS     8
+#define ILI9325_GAMMA_CTL7_KN3_MSK    (0x7u << ILI9325_GAMMA_CTL7_KN3_POS)
+#define ILI9325_GAMMA_CTL7_KN3(value) ((ILI9325_GAMMA_CTL7_KN3_MSK & \
+	((value) << ILI9325_GAMMA_CTL7_KN3_POS)))
+
+/** ILI9325_GAMMA_CTL8 : (Offset: 0x39) Gamma Control 8*/
+#define ILI9325_GAMMA_CTL8            (0x39u)
+#define ILI9325_GAMMA_CTL8_KN4_POS     0
+#define ILI9325_GAMMA_CTL8_KN4_MSK    (0x7u << ILI9325_GAMMA_CTL8_KN4_POS)
+#define ILI9325_GAMMA_CTL8_KN4(value) ((ILI9325_GAMMA_CTL8_KN4_MSK & \
+	((value) << ILI9325_GAMMA_CTL8_KN4_POS)))
+#define ILI9325_GAMMA_CTL8_KN5_POS     8
+#define ILI9325_GAMMA_CTL8_KN5_MSK    (0x7u << ILI9325_GAMMA_CTL8_KN5_POS)
+#define ILI9325_GAMMA_CTL8_KN5(value) ((ILI9325_GAMMA_CTL8_KN5_MSK & \
+	((value) << ILI9325_GAMMA_CTL8_KN5_POS)))
+
+/** ILI9325_GAMMA_CTL9 : (Offset: 0x3C) Gamma Control 9*/
+#define ILI9325_GAMMA_CTL9            (0x3Cu)
+#define ILI9325_GAMMA_CTL9_RN0_POS     0
+#define ILI9325_GAMMA_CTL9_RN0_MSK    (0x7u << ILI9325_GAMMA_CTL9_RN0_POS)
+#define ILI9325_GAMMA_CTL9_RN0(value) ((ILI9325_GAMMA_CTL9_RN0_MSK & \
+	((value) << ILI9325_GAMMA_CTL9_RN0_POS)))
+#define ILI9325_GAMMA_CTL9_RN1_POS     8
+#define ILI9325_GAMMA_CTL9_RN1_MSK    (0x7u << ILI9325_GAMMA_CTL9_RN1_POS)
+#define ILI9325_GAMMA_CTL9_RN1(value) ((ILI9325_GAMMA_CTL9_RN1_MSK & \
+	((value) << ILI9325_GAMMA_CTL9_RN1_POS)))
+
+/** ILI9325_GAMMA_CTL10 : (Offset: 0x3D) Gamma Control 10*/
+#define ILI9325_GAMMA_CTL10             (0x3Du)
+#define ILI9325_GAMMA_CTL10_VRN0_POS     0
+#define ILI9325_GAMMA_CTL10_VRN0_MSK    (0xfu << ILI9325_GAMMA_CTL10_VRN0_POS)
+#define ILI9325_GAMMA_CTL10_VRN0(value) ((ILI9325_GAMMA_CTL10_VRN0_MSK & \
+	((value) << ILI9325_GAMMA_CTL10_VRN0_POS)))
+#define ILI9325_GAMMA_CTL10_VRN1_POS     8
+#define ILI9325_GAMMA_CTL10_VRN1_MSK    (0x1fu << \
+	ILI9325_GAMMA_CTL10_VRN1_POS)
+#define ILI9325_GAMMA_CTL10_VRN1(value) ((ILI9325_GAMMA_CTL10_VRN1_MSK & \
+	((value) << ILI9325_GAMMA_CTL10_VRN1_POS)))
+
+/**
+ * ILI9325_HORIZONTAL_ADDR_START : (Offset: 0x50) Horizontal Address
+ * Start Position
+ */
+#define ILI9325_HORIZONTAL_ADDR_START            (0x50u)
+#define ILI9325_HORIZONTAL_ADDR_START_HSA_POS     0
+#define ILI9325_HORIZONTAL_ADDR_START_HSA_MSK    (0xffu << \
+	ILI9325_HORIZONTAL_ADDR_START_HSA_POS)
+#define ILI9325_HORIZONTAL_ADDR_START_HSA(value) (( \
+		ILI9325_HORIZONTAL_ADDR_START_HSA_MSK &	\
+		((value) << ILI9325_HORIZONTAL_ADDR_START_HSA_POS)))
+
+/**
+ * ILI9325_HORIZONTAL_ADDR_END : (Offset: 0x51) Horizontal Address End
+ * Position
+ */
+#define ILI9325_HORIZONTAL_ADDR_END            (0x51u)
+#define ILI9325_HORIZONTAL_ADDR_END_HEA_POS     0
+#define ILI9325_HORIZONTAL_ADDR_END_HEA_MSK    (0xffu << \
+	ILI9325_HORIZONTAL_ADDR_END_HEA_POS)
+#define ILI9325_HORIZONTAL_ADDR_END_HEA(value) (( \
+		ILI9325_HORIZONTAL_ADDR_END_HEA_MSK & \
+		((value) << ILI9325_HORIZONTAL_ADDR_END_HEA_POS)))
+
+/**
+ * ILI9325_VERTICAL_ADDR_START : (Offset: 0x52) Vertical Address Start
+ * Position
+ */
+#define ILI9325_VERTICAL_ADDR_START            (0x52u)
+#define ILI9325_VERTICAL_ADDR_START_VSA_POS     0
+#define ILI9325_VERTICAL_ADDR_START_VSA_MSK    (0x1ffu << \
+	ILI9325_VERTICAL_ADDR_START_VSA_POS)
+#define ILI9325_VERTICAL_ADDR_START_VSA(value) (( \
+		ILI9325_VERTICAL_ADDR_START_VSA_MSK & \
+		((value) << ILI9325_VERTICAL_ADDR_START_VSA_POS)))
+
+/**
+ * ILI9325_VERTICAL_ADDR_END : (Offset: 0x53) Vertical Address End
+ * Position
+ */
+#define ILI9325_VERTICAL_ADDR_END            (0x53u)
+#define ILI9325_VERTICAL_ADDR_END_VEA_POS     0
+#define ILI9325_VERTICAL_ADDR_END_VEA_MSK    (0x1ffu <<	\
+	ILI9325_VERTICAL_ADDR_END_VEA_POS)
+#define ILI9325_VERTICAL_ADDR_END_VEA(value) ((ILI9325_VERTICAL_ADDR_END_VEA_MSK \
+	& ((value) << ILI9325_VERTICAL_ADDR_END_VEA_POS)))
+
+/**
+ * ILI9325_DRIVER_OUTPUT_CTRL2 : (Offset: 0x60) Driver Output
+ * Control 2
+ */
+#define ILI9325_DRIVER_OUTPUT_CTRL2            (0x60u)
+#define ILI9325_DRIVER_OUTPUT_CTRL2_SCN_POS     0
+#define ILI9325_DRIVER_OUTPUT_CTRL2_SCN_MSK    (0x3fu << \
+	ILI9325_DRIVER_OUTPUT_CTRL2_SCN_POS)
+#define ILI9325_DRIVER_OUTPUT_CTRL2_SCN(value) (( \
+		ILI9325_DRIVER_OUTPUT_CTRL2_SCN_MSK & \
+		((value) << ILI9325_DRIVER_OUTPUT_CTRL2_SCN_POS)))
+#define ILI9325_DRIVER_OUTPUT_CTRL2_NL_POS      8
+#define ILI9325_DRIVER_OUTPUT_CTRL2_NL_MSK     (0x3fu << \
+	ILI9325_DRIVER_OUTPUT_CTRL2_NL_POS)
+#define ILI9325_DRIVER_OUTPUT_CTRL2_NL(value)  (( \
+		ILI9325_DRIVER_OUTPUT_CTRL2_NL_MSK & \
+		((value) << ILI9325_DRIVER_OUTPUT_CTRL2_NL_POS)))
+#define ILI9325_DRIVER_OUTPUT_CTRL2_GS         (0x1u << 15)
+
+/**
+ * ILI9325_BASE_IMG_DISP_CTRL : (Offset: 0x61) Base Image Display
+ * Control
+ */
+#define ILI9325_BASE_IMG_DISP_CTRL     (0x61u)
+#define ILI9325_BASE_IMG_DISP_CTRL_REV (0x1u << 0)
+#define ILI9325_BASE_IMG_DISP_CTRL_VLE (0x1u << 1)
+#define ILI9325_BASE_IMG_DISP_CTRL_NDL (0x1u << 2)
+
+/**
+ * ILI9325_VERTICAL_SCROLL_CTRL : (Offset: 0x6A) Vertical Scroll
+ * Control
+ */
+#define ILI9325_VERTICAL_SCROLL_CTRL           (0x6Au)
+#define ILI9325_VERTICAL_SCROLL_CTRL_VL_POS     0
+#define ILI9325_VERTICAL_SCROLL_CTRL_VL_MSK    (0x1ffu << \
+	ILI9325_VERTICAL_SCROLL_CTRL_VL_POS)
+#define ILI9325_VERTICAL_SCROLL_CTRL_VL(value) (( \
+		ILI9325_VERTICAL_SCROLL_CTRL_VL_MSK & \
+		((value) << ILI9325_VERTICAL_SCROLL_CTRL_VL_POS)))
+
+/**
+ * ILI9325_PARTIAL_IMG1_DISP_POS : (Offset: 0x80) Partial Image 1
+ * Display Position
+ */
+#define ILI9325_PARTIAL_IMG1_DISP_POS              (0x80u)
+#define ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0_POS     0
+#define ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0_MSK    (0x1ffu << \
+	ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0_POS)
+#define ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0(value) (( \
+		ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0_MSK & \
+		((value) << ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0_POS)))
+
+/**
+ * ILI9325_PARTIAL_IMG1_AREA_START_LINE : (Offset: 0x81) Partial Image
+ * 1 Area (Start Line)
+ */
+#define ILI9325_PARTIAL_IMG1_AREA_START_LINE              (0x81u)
+#define ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0_POS     0
+#define ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0_MSK    (0x1ffu << \
+	ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0_POS)
+#define ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0(value) (( \
+		ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0_MSK & \
+		((value) << \
+		ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0_POS)))
+
+/**
+ * ILI9325_PARTIAL_IMG1_AREA_END_LINE : (Offset: 0x82) Partial Image 1
+ * Area (End Line)
+ */
+#define ILI9325_PARTIAL_IMG1_AREA_END_LINE              (0x82u)
+#define ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0_POS     0
+#define ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0_MSK    (0x1ffu << \
+	ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0_POS)
+#define ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0(value) (( \
+		ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0_MSK & \
+		((value) << \
+		ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0_POS)))
+
+/**
+ * ILI9325_PARTIAL_IMG2_DISP_POS : (Offset: 0x83) Partial Image 2
+ * Display Position
+ */
+#define ILI9325_PARTIAL_IMG2_DISP_POS              (0x83u)
+#define ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1_POS     0
+#define ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1_MSK    (0x1ffu << \
+	ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1_POS)
+#define ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1(value) (( \
+		ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1_MSK & \
+		((value) << ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1_POS)))
+
+/**
+ * ILI9325_PARTIAL_IMG2_AREA_START_LINE : (Offset: 0x84) Partial Image
+ * 2 Area (Start Line)
+ */
+#define ILI9325_PARTIAL_IMG2_AREA_START_LINE              (0x84u)
+#define ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1_POS     0
+#define ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1_MSK    (0x1ffu << \
+	ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1_POS)
+#define ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1(value) (( \
+		ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1_MSK & \
+		((value) << \
+		ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1_POS)))
+
+/**
+ * ILI9325_PARTIAL_IMG2_AREA_END_LINE : (Offset: 0x85) Partial Image 2
+ * Area (End Line)
+ */
+#define ILI9325_PARTIAL_IMG2_AREA_END_LINE              (0x85u)
+#define ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1_POS     0
+#define ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1_MSK    (0x1ffu << \
+	ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1_POS)
+#define ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1(value) (( \
+		ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1_MSK & \
+		((value) << \
+		ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1_POS)))
+
+/**
+ * ILI9325_PANEL_INTERFACE_CTRL1 : (Offset: 0x90) Panel Interface
+ * Control 1
+ */
+#define ILI9325_PANEL_INTERFACE_CTRL1             (0x90u)
+#define ILI9325_PANEL_INTERFACE_CTRL1_RTNI_POS     0
+#define ILI9325_PANEL_INTERFACE_CTRL1_RTNI_MSK    (0x1fu << \
+	ILI9325_PANEL_INTERFACE_CTRL1_RTNI_POS)
+#define ILI9325_PANEL_INTERFACE_CTRL1_RTNI(value) (( \
+		ILI9325_PANEL_INTERFACE_CTRL1_RTNI_MSK & \
+		((value) << ILI9325_PANEL_INTERFACE_CTRL1_RTNI_POS)))
+#define ILI9325_PANEL_INTERFACE_CTRL1_DIVI_POS     8
+#define ILI9325_PANEL_INTERFACE_CTRL1_DIVI_MSK    (0x3u << \
+	ILI9325_PANEL_INTERFACE_CTRL1_DIVI_POS)
+#define ILI9325_PANEL_INTERFACE_CTRL1_DIVI(value) (( \
+		ILI9325_PANEL_INTERFACE_CTRL1_DIVI_MSK & \
+		((value) << ILI9325_PANEL_INTERFACE_CTRL1_DIVI_POS)))
+
+/**
+ * ILI9325_PANEL_INTERFACE_CTRL2 : (Offset: 0x92) Panel Interface
+ * Control 2
+ */
+#define ILI9325_PANEL_INTERFACE_CTRL2             (0x92u)
+#define ILI9325_PANEL_INTERFACE_CTRL2_NOWI_POS     8
+#define ILI9325_PANEL_INTERFACE_CTRL2_NOWI_MSK    (0x7u << \
+	ILI9325_PANEL_INTERFACE_CTRL2_NOWI_POS)
+#define ILI9325_PANEL_INTERFACE_CTRL2_NOWI(value) (( \
+		ILI9325_PANEL_INTERFACE_CTRL2_NOWI_MSK & \
+		((value) << ILI9325_PANEL_INTERFACE_CTRL2_NOWI_POS)))
+
+/**
+ * ILI9325_PANEL_INTERFACE_CTRL4 : (Offset: 0x95) Panel Interface
+ * Control 4
+ */
+#define ILI9325_PANEL_INTERFACE_CTRL4             (0x95u)
+#define ILI9325_PANEL_INTERFACE_CTRL4_RTNE_POS     0
+#define ILI9325_PANEL_INTERFACE_CTRL4_RTNE_MSK    (0x3fu << \
+	ILI9325_PANEL_INTERFACE_CTRL4_RTNE_POS)
+#define ILI9325_PANEL_INTERFACE_CTRL4_RTNE(value) (( \
+		ILI9325_PANEL_INTERFACE_CTRL4_RTNE_MSK & \
+		((value) << ILI9325_PANEL_INTERFACE_CTRL4_RTNE_POS)))
+#define ILI9325_PANEL_INTERFACE_CTRL4_DIVE_POS     8
+#define ILI9325_PANEL_INTERFACE_CTRL4_DIVE_MSK    (0x3u << \
+	ILI9325_PANEL_INTERFACE_CTRL4_DIVE_POS)
+#define ILI9325_PANEL_INTERFACE_CTRL4_DIVE(value) (( \
+		ILI9325_PANEL_INTERFACE_CTRL4_DIVE_MSK & \
+		((value) << ILI9325_PANEL_INTERFACE_CTRL4_DIVE_POS)))
+
+/** ILI9325_OTP_VCM_PROG_CTRL : (Offset: 0xA1) OTP VCM Programming Control */
+#define ILI9325_OTP_VCM_PROG_CTRL                (0xA1u)
+#define ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP_POS     0
+#define ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP_MSK    (0x3fu << \
+	ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP_POS)
+#define ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP(value) (( \
+		ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP_MSK &	\
+		((value) << ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP_POS)))
+#define ILI9325_OTP_VCM_PROG_CTRL_OTP_PGM_EN     (0x1u << 11)
+
+/** ILI9325_OTP_VCM_STATUS_AND_ENABLE : (Offset: 0xA2) OTP VCM Status
+ * and Enable   */
+#define ILI9325_OTP_VCM_STATUS_AND_ENABLE                (0xA2u)
+#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_EN         (0x1u << 0)
+#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D_POS       8
+#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D_MSK      (0x3fu << \
+	ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D_POS)
+#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D(value)   (( \
+		ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D_MSK & ((value) << \
+		ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D_POS)))
+#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT_POS     14
+#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT_MSK    (0x3u << \
+	ILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT_POS)
+#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT(value) (( \
+		ILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT_MSK &	\
+		((value) << \
+		IILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT_POS)))
+
+/** ILI9325_OTP_PROG_ID_KEY : (Offset: 0xA5) OTP Programming ID Key */
+#define ILI9325_OTP_PROG_ID_KEY            (0xA5u)
+#define ILI9325_OTP_PROG_ID_KEY_KEY_POS     0
+#define ILI9325_OTP_PROG_ID_KEY_KEY_MSK    (0xffffu << \
+	ILI9325_OTP_PROG_ID_KEY_KEY_POS)
+#define ILI9325_OTP_PROG_ID_KEY_KEY(value) ((ILI9325_OTP_PROG_ID_KEY_KEY_MSK & \
+	((value) << ILI9325_OTP_PROG_ID_KEY_KEY_POS)))
+
+/** @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/** @endcond */
+
+#endif /* ILI9325_REGS_H_INCLUDED */

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili9341_regs.h

@@ -0,0 +1,245 @@
+/**
+ * \file
+ *
+ * \brief registers definition for ili9341 TFT display component.
+ *
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ILI9341_REGS_H_INCLUDED
+#define ILI9341_REGS_H_INCLUDED
+
+/** @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/** @endcond */
+
+/** ili9341 LCD Registers */
+
+/** Level 1 Commands (from the display Datasheet) */
+/** Nop operation*/
+#define ILI9341_CMD_NOP                             0x00
+/** Software reset*/
+#define ILI9341_CMD_SOFTWARE_RESET                  0x01
+/** Read Display Identification information*/
+#define ILI9341_CMD_READ_DISP_ID                    0x04
+/** Read display status*/
+#define ILI9341_CMD_READ_DISP_STATUS                0x09
+/** Read display power mode*/
+#define ILI9341_CMD_READ_DISP_POWER_MODE            0x0A
+/** Read display MADCTL*/
+#define ILI9341_CMD_READ_DISP_MADCTRL               0x0B
+/** Read display pixel format*/
+#define ILI9341_CMD_READ_DISP_PIXEL_FORMAT          0x0C
+/** Read display image format*/
+#define ILI9341_CMD_READ_DISP_IMAGE_FORMAT          0x0D
+/** Read display signal mode*/
+#define ILI9341_CMD_READ_DISP_SIGNAL_MODE           0x0E
+/** read display self-diagnostic resutl*/
+#define ILI9341_CMD_READ_DISP_SELF_DIAGNOSTIC       0x0F
+/** Enter sleep mode*/
+#define ILI9341_CMD_ENTER_SLEEP_MODE                0x10
+/** Sleep out*/
+#define ILI9341_CMD_SLEEP_OUT                       0x11
+/** Partial mode on*/
+#define ILI9341_CMD_PARTIAL_MODE_ON                 0x12
+/** Normal display mode on*/
+#define ILI9341_CMD_NORMAL_DISP_MODE_ON             0x13
+/** Display inversion off*/
+#define ILI9341_CMD_DISP_INVERSION_OFF              0x20
+/** Display inversion on*/
+#define ILI9341_CMD_DISP_INVERSION_ON               0x21
+/** Gamma set*/
+#define ILI9341_CMD_GAMMA_SET                       0x26
+/** Display off*/
+#define ILI9341_CMD_DISPLAY_OFF                     0x28
+/** Display on*/
+#define ILI9341_CMD_DISPLAY_ON                      0x29
+/** Column address set*/
+#define ILI9341_CMD_COLUMN_ADDRESS_SET              0x2A
+/** Page address set*/
+#define ILI9341_CMD_PAGE_ADDRESS_SET                0x2B
+/** Memory write*/
+#define ILI9341_CMD_MEMORY_WRITE                    0x2C
+/** Color set*/
+#define ILI9341_CMD_COLOR_SET                       0x2D
+/** Memory read*/
+#define ILI9341_CMD_MEMORY_READ                     0x2E
+/** Partial area*/
+#define ILI9341_CMD_PARTIAL_AREA                    0x30
+/** Vertical scrolling definition*/
+#define ILI9341_CMD_VERT_SCROLL_DEFINITION          0x33
+/** Tearing effect line off*/
+#define ILI9341_CMD_TEARING_EFFECT_LINE_OFF         0x34
+/** Tearing effect line on*/
+#define ILI9341_CMD_TEARING_EFFECT_LINE_ON          0x35
+
+/** Memory Access control*/
+#define ILI9341_CMD_MEMORY_ACCESS_CONTROL           0x36
+#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_MY        (0x1u << 7)
+#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_MX        (0x1u << 6)
+#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_MV        (0x1u << 5)
+#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_ML        (0x1u << 4)
+#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_BGR       (0x1u << 3)
+#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_MH        (0x1u << 2)
+
+/** Vetical scrolling start address*/
+#define ILI9341_CMD_VERT_SCROLL_START_ADDRESS       0x37
+/** Idle mode off*/
+#define ILI9341_CMD_IDLE_MODE_OFF                   0x38
+/** Idle mode on*/
+#define ILI9341_CMD_IDLE_MODE_ON                    0x39
+/** Pixel Format set*/
+#define ILI9341_CMD_PIXEL_FORMAT_SET                0x3A
+/** write memory continue*/
+#define ILI9341_CMD_WRITE_MEMORY_CONTINUE           0x3C
+/** Read memory continue*/
+#define ILI9341_CMD_READ_MEMORY_CONTINUE            0x3E
+/** set tear scanline*/
+#define ILI9341_CMD_SET_TEAR_SCANLINE               0x44
+/** get scanline*/
+#define ILI9341_CMD_GET_SCANLINE                    0x45
+/** write display brightness*/
+#define ILI9341_CMD_WRITE_DISPLAY_BRIGHTNESS        0x51
+/** read display brightness*/
+#define ILI9341_CMD_READ_DISPLAY_BRIGHTNESS         0x52
+/** write control display*/
+#define ILI9341_CMD_WRITE_CTRL_DISPLAY              0x53
+/** read control display*/
+#define ILI9341_CMD_READ_CTRL_DISPLAY               0x54
+/** write content adaptive brightness control*/
+#define ILI9341_CMD_WRITE_CONTENT_ADAPT_BRIGHTNESS  0x55
+/** read content adaptive brightness control*/
+#define ILI9341_CMD_READ_CONTENT_ADAPT_BRIGHTNESS   0x56
+/** write CABC minimum brightness*/
+#define ILI9341_CMD_WRITE_MIN_CAB_LEVEL             0x5E
+/** read CABC minimum brightness*/
+#define ILI9341_CMD_READ_MIN_CAB_LEVEL              0x5F
+/** Read ID1*/
+#define ILI9341_CMD_READ_ID1                        0xDA
+/** Read ID2*/
+#define ILI9341_CMD_READ_ID2                        0xDB
+/** Read ID3*/
+#define ILI9341_CMD_READ_ID3                        0xDC
+
+/** Level 2 Commands (from the display Datasheet) */
+/** RGB interface signal control*/
+#define ILI9341_CMD_RGB_SIGNAL_CONTROL              0xB0
+/** frame control*/
+#define ILI9341_CMD_FRAME_RATE_CONTROL_NORMAL       0xB1
+/** frame control in idle mode*/
+#define ILI9341_CMD_FRAME_RATE_CONTROL_IDLE_8COLOR  0xB2
+/** frame control in partial mode*/
+#define ILI9341_CMD_FRAME_RATE_CONTROL_PARTIAL      0xB3
+/** display inversion control*/
+#define ILI9341_CMD_DISPLAY_INVERSION_CONTROL       0xB4
+/** blanking porch control*/
+#define ILI9341_CMD_BLANKING_PORCH_CONTROL          0xB5
+/** display function control*/
+#define ILI9341_CMD_DISPLAY_FUNCTION_CTL            0xB6
+#define ILI9341_DISP_FUNC_CTL_REV                   (0x1u << 7)
+#define ILI9341_DISP_FUNC_CTL_GS                    (0x1u << 6)
+#define ILI9341_DISP_FUNC_CTL_SS                    (0x1u << 5)
+#define ILI9341_DISP_FUNC_CTL_SM                    (0x1u << 4)
+#define ILI9341_DISP_FUNC_CTL_ISC_POS               0
+#define ILI9341_DISP_FUNC_CTL_ISC_MSK               (0x0F << 0)
+#define ILI9341_DISP_FUNC_CTL_ISC(value) \
+	(ILI9341_DISP_FUNC_CTL_ISC_MSK & \
+	(value << ILI9341_DISP_FUNC_CTL_ISC_POS))
+
+/** entry mode set*/
+#define ILI9341_CMD_ENTRY_MODE_SET                  0xB7
+/** backlight control1*/
+#define ILI9341_CMD_BACKLIGHT_CONTROL_1             0xB8
+/** backlight control2*/
+#define ILI9341_CMD_BACKLIGHT_CONTROL_2             0xB9
+/** backlight control3*/
+#define ILI9341_CMD_BACKLIGHT_CONTROL_3             0xBA
+/** backlight control 4*/
+#define ILI9341_CMD_BACKLIGHT_CONTROL_4             0xBB
+/** backlight control 5*/
+#define ILI9341_CMD_BACKLIGHT_CONTROL_5             0xBC
+/** backlight control 7*/
+#define ILI9341_CMD_BACKLIGHT_CONTROL_7             0xBE
+/** backlight control 8*/
+#define ILI9341_CMD_BACKLIGHT_CONTROL_8             0xBF
+/** power control 1*/
+#define ILI9341_CMD_POWER_CONTROL_1                 0xC0
+/** power control 2*/
+#define ILI9341_CMD_POWER_CONTROL_2                 0xC1
+/** VCOM control 1*/
+#define ILI9341_CMD_VCOM_CONTROL_1                  0xC5
+/** VCOM control 2*/
+#define ILI9341_CMD_VCOM_CONTROL_2                  0xC7
+/** Power control A*/
+#define ILI9341_CMD_POWER_CONTROL_A                 0xCB
+/** Power control B*/
+#define ILI9341_CMD_POWER_CONTROL_B                 0xCF
+/** NV memory write*/
+#define ILI9341_CMD_NVMEM_WRITE                     0xD0
+/** NV memory protection key*/
+#define ILI9341_CMD_NVMEM_PROTECTION_KEY            0xD1
+/** NV memory status read*/
+#define ILI9341_CMD_NVMEM_STATUS_READ               0xD2
+/** Read ID4*/
+#define ILI9341_CMD_READ_ID4                        0xD3
+/** positive gamma correction*/
+#define ILI9341_CMD_POSITIVE_GAMMA_CORRECTION       0xE0
+/** negative gamma correction*/
+#define ILI9341_CMD_NEGATIVE_GAMMA_CORRECTION       0xE1
+/** digital gamma control 1*/
+#define ILI9341_CMD_DIGITAL_GAMMA_CONTROL_1         0xE2
+/** digital gamma control 2*/
+#define ILI9341_CMD_DIGITAL_GAMMA_CONTROL_2         0xE3
+/** driver timing control A*/
+#define ILI9341_CMD_DRIVER_TIMING_CTL_A             0xE8
+/** driver timing control B*/
+#define ILI9341_CMD_DRIVER_TIMING_CTL_B             0xEA
+/** power-on sequence control*/
+#define ILI9341_CMD_POWER_ON_SEQUENCE_CONTROL       0xED
+/** enable 3g gamma control*/
+#define ILI9341_CMD_ENABLE_3_GAMMA_CONTROL          0xF2
+/** Interface control*/
+#define ILI9341_CMD_INTERFACE_CONTROL               0xF6
+/** pump ration control*/
+#define ILI9341_CMD_PUMP_RATIO_CONTROL              0xF7
+
+#endif /* ILI9341_REGS_H_INCLUDED */

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili93xx.h

@@ -0,0 +1,349 @@
+/**
+ * \file
+ *
+ * \brief API driver for ili93xx TFT display component.
+ *
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ILI93XX_H_INCLUDED
+#define ILI93XX_H_INCLUDED
+
+/**
+ * \defgroup ili93xx_display_group - LCD with ili93xx component driver
+ *
+ * This is a driver for LCD with ili93xx. Now this driver supports ili9325 and
+ * ili9341.This component is custom LCD used for SAM4E-EK.
+ * The driver provides functions for initializtion and control of the LCD.
+ *
+ * See \ref sam_component_ili93xx_quickstart.
+ *
+ * \{
+ */
+
+#include "compiler.h"
+#include "board.h"
+#include "conf_ili93xx.h"
+
+/** @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/** @endcond */
+
+/** Type define for an integer type large enough to store a pixel color. */
+typedef uint32_t ili93xx_color_t;
+
+/** Type define for an integer type large enough to store a pixel coordinate.
+ */
+typedef int16_t ili93xx_coord_t;
+
+/** This macro generates a 16-bit native color for the display from a
+ *  24-bit RGB value.
+ */
+#define ili93xx_COLOR(r, g, b) ((r << 16) | (g << 8) | b)
+
+typedef ili93xx_color_t gfx_color_t;
+typedef int16_t gfx_coord_t;
+
+/** ili93xx screen size */
+#define ILI93XX_LCD_WIDTH  240
+#define ILI93XX_LCD_HEIGHT 320
+
+/** ili93xx ID code */
+#define ILI9325_DEVICE_CODE (0x9325u)
+#define ILI9341_DEVICE_CODE (0x9341u)
+#define DEVICE_TYPE_ILI9325  1
+#define DEVICE_TYPE_ILI9341  2
+/** Define EBI access for ILI93xx 8-bit System Interface.*/
+#if defined(BOARD_ILI93XX_ADDR) && defined (BOARD_ILI93XX_RS)
+static inline void LCD_IR(uint8_t lcd_index)
+{
+	/** ILI9325 index register address */
+	*((volatile uint8_t *)(BOARD_ILI93XX_ADDR)) = lcd_index;
+}
+
+static inline void LCD_WD(uint8_t lcd_data)
+{
+	*((volatile uint8_t *)((BOARD_ILI93XX_ADDR) | (BOARD_ILI93XX_RS))) =
+																lcd_data;
+}
+
+static inline uint8_t LCD_RD(void)
+{
+	return *((volatile uint8_t *)((BOARD_ILI93XX_ADDR) |(BOARD_ILI93XX_RS)));
+}
+
+#else
+	#error "Missing module configuration for ILI93xx!"
+#endif
+
+/** RGB 24-bits color table definition (RGB888). */
+#define COLOR_BLACK          (0x000000u)
+#define COLOR_WHITE          (0xFFFFFFu)
+#define COLOR_BLUE           (0x0000FFu)
+#define COLOR_GREEN          (0x00FF00u)
+#define COLOR_RED            (0xFF0000u)
+#define COLOR_NAVY           (0x000080u)
+#define COLOR_DARKBLUE       (0x00008Bu)
+#define COLOR_DARKGREEN      (0x006400u)
+#define COLOR_DARKCYAN       (0x008B8Bu)
+#define COLOR_CYAN           (0x00FFFFu)
+#define COLOR_TURQUOISE      (0x40E0D0u)
+#define COLOR_INDIGO         (0x4B0082u)
+#define COLOR_DARKRED        (0x800000u)
+#define COLOR_OLIVE          (0x808000u)
+#define COLOR_GRAY           (0x808080u)
+#define COLOR_SKYBLUE        (0x87CEEBu)
+#define COLOR_BLUEVIOLET     (0x8A2BE2u)
+#define COLOR_LIGHTGREEN     (0x90EE90u)
+#define COLOR_DARKVIOLET     (0x9400D3u)
+#define COLOR_YELLOWGREEN    (0x9ACD32u)
+#define COLOR_BROWN          (0xA52A2Au)
+#define COLOR_DARKGRAY       (0xA9A9A9u)
+#define COLOR_SIENNA         (0xA0522Du)
+#define COLOR_LIGHTBLUE      (0xADD8E6u)
+#define COLOR_GREENYELLOW    (0xADFF2Fu)
+#define COLOR_SILVER         (0xC0C0C0u)
+#define COLOR_LIGHTGREY      (0xD3D3D3u)
+#define COLOR_LIGHTCYAN      (0xE0FFFFu)
+#define COLOR_VIOLET         (0xEE82EEu)
+#define COLOR_AZUR           (0xF0FFFFu)
+#define COLOR_BEIGE          (0xF5F5DCu)
+#define COLOR_MAGENTA        (0xFF00FFu)
+#define COLOR_TOMATO         (0xFF6347u)
+#define COLOR_GOLD           (0xFFD700u)
+#define COLOR_ORANGE         (0xFFA500u)
+#define COLOR_SNOW           (0xFFFAFAu)
+#define COLOR_YELLOW         (0xFFFF00u)
+
+/**
+ * Input parameters when initializing ili9325 driver.
+ */
+struct ili93xx_opt_t {
+	/** LCD width in pixel*/
+	uint32_t ul_width;
+	/** LCD height in pixel*/
+	uint32_t ul_height;
+	/** LCD foreground color*/
+	uint32_t foreground_color;
+	/** LCD background color*/
+	uint32_t background_color;
+};
+
+/**
+ * Font structure
+ */
+struct ili93xx_font {
+	/** Font width in pixels. */
+	uint8_t width;
+	/** Font height in pixels. */
+	uint8_t height;
+};
+
+/**
+ * Display direction option
+ */
+enum ili93xx_display_direction {
+	LANDSCAPE  = 0,
+	PORTRAIT   = 1
+};
+
+/**
+ * Shift direction option
+ */
+enum ili93xx_shift_direction {
+	H_INCREASE  = 0,
+	H_DECREASE  = 1
+};
+
+/**
+ * Scan direction option
+ */
+enum ili93xx_scan_direction {
+	V_INCREASE  = 0,
+	V_DEREASE   = 1
+};
+
+uint32_t ili93xx_init(struct ili93xx_opt_t *p_opt);
+void ili93xx_display_on(void);
+void ili93xx_display_off(void);
+void ili93xx_set_foreground_color(ili93xx_color_t ul_color);
+void ili93xx_fill(ili93xx_color_t ul_color);
+void ili93xx_set_window(uint32_t ul_x, uint32_t ul_y,
+		uint32_t ul_width, uint32_t ul_height);
+void ili93xx_set_cursor_position(uint16_t us_x, uint16_t us_y);
+void ili93xx_scroll(int32_t ul_lines);
+void ili93xx_enable_scroll(void);
+void ili93xx_disable_scroll(void);
+void ili93xx_set_display_direction(enum ili93xx_display_direction e_dd,
+		enum ili93xx_shift_direction e_shd,
+		enum ili93xx_scan_direction e_scd);
+uint32_t ili93xx_draw_pixel(uint32_t ul_x, uint32_t ul_y);
+ili93xx_color_t ili93xx_get_pixel(uint32_t ul_x, uint32_t ul_y);
+void ili93xx_draw_line(uint32_t ul_x1, uint32_t ul_y1,
+		uint32_t ul_x2, uint32_t ul_y2);
+void ili93xx_draw_rectangle(uint32_t ul_x1, uint32_t ul_y1,
+		uint32_t ul_x2, uint32_t ul_y2);
+void ili93xx_draw_filled_rectangle(uint32_t ul_x1, uint32_t ul_y1,
+		uint32_t ul_x2, uint32_t ul_y2);
+uint32_t ili93xx_draw_circle(uint32_t ul_x, uint32_t ul_y, uint32_t ul_r);
+uint32_t ili93xx_draw_filled_circle(uint32_t ul_x, uint32_t ul_y,
+		uint32_t ul_r);
+void ili93xx_draw_string(uint32_t ul_x, uint32_t ul_y, const uint8_t *p_str);
+void ili93xx_draw_pixmap(uint32_t ul_x, uint32_t ul_y, uint32_t ul_width,
+		uint32_t ul_height, const ili93xx_color_t *p_ul_pixmap);
+void ili93xx_set_top_left_limit(ili93xx_coord_t x, ili93xx_coord_t y);
+void ili93xx_set_bottom_right_limit(ili93xx_coord_t x, ili93xx_coord_t y);
+void ili93xx_set_limits(ili93xx_coord_t start_x, ili93xx_coord_t start_y,
+		ili93xx_coord_t end_x, ili93xx_coord_t end_y);
+ili93xx_color_t ili93xx_read_gram(void);
+void ili93xx_write_gram(ili93xx_color_t color);
+void ili93xx_copy_pixels_to_screen(const ili93xx_color_t *pixels,
+		uint32_t count);
+void ili93xx_copy_raw_pixel_24bits_to_screen(const uint8_t *raw_pixels,
+		uint32_t count);
+void ili93xx_duplicate_pixel(const ili93xx_color_t color, uint32_t count);
+void ili93xx_copy_pixels_from_screen(ili93xx_color_t *pixels, uint32_t count);
+uint8_t ili93xx_device_type(void);
+void ili93xx_vscroll_area_define(uint16_t us_tfa, uint16_t us_vsa,
+		uint16_t us_bfa);
+uint8_t ili93xx_device_type_identify(void);
+
+/** @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/** @endcond */
+
+/**
+ * \}
+ */
+
+/**
+ * \page sam_component_ili93xx_quickstart Quick Start Guide for the ILI93XX
+ * LCD Glass component.
+ *
+ * This is the quick start guide for the \ref ili93xx_display_group, with
+ * step-by-step instructions on how to configure and use the driver for
+ * a specific use case.The code examples can be copied into e.g the main
+ * application loop or any other function that will need to control the
+ * ili93xx LCD Glass component module. Now ili9325 and ili9341 are supported.
+ *
+ * \section ili93xx_qs_use_cases Use cases
+ * - \ref ili93xx_basic
+ *
+ * \section ili93xx_basic ili93xx LCD Glass basic usage
+ *
+ * This use case will demonstrate how to initialize the ili93xx LCD Glass
+ * module.
+ *
+ *
+ * \section ili93xx_basic_setup Setup steps
+ *
+ * \subsection ili93xx_basic_prereq Prerequisites
+ *
+ * This module requires the following driver
+ * - \ref smc_group
+ *
+ * \subsection ili93xx_basic_setup_code
+ *
+ * Add this to the main loop or a setup function:
+ * \code
+ * struct ili93xx_opt_t g_ili93xx_display_opt;
+ * g_ili93xx_display_opt.ul_width = ILI93XX_LCD_WIDTH;
+ * g_ili93xx_display_opt.ul_height = ILI93XX_LCD_HEIGHT;
+ * g_ili93xx_display_opt.foreground_color = COLOR_BLACK;
+ * g_ili93xx_display_opt.background_color = COLOR_WHITE;
+ * ili93xx_init(&g_ili93xx_display_opt);
+ * \endcode
+ *
+ * \subsection ili93xx_basic_setup_workflow
+ * -\ref ili93xx_basic_setup_code
+ *
+ * \section ili93xx_basic_usage Usage steps
+ *
+ * \subsection ili93xx_basic_usage_code
+ *
+ * -# Set display on
+ * \code
+ * ili93xx_display_on();
+ * \endcode
+ *
+ * -# Turn display off
+ * \code
+ * ili93xx_display_off();
+ * \endcode
+ *
+ * -# Draw a pixel
+ * \code
+ * ili93xx_set_foreground_color(COLOR_RED);
+ * ili93xx_draw_pixel(60, 60);
+ * \endcode
+ *
+ * -# Draw a line and circle
+ * \code
+ * ili93xx_set_foreground_color(COLOR_BLUE);
+ * ili93xx_draw_circle(180, 160, 40);
+ * ili93xx_set_foreground_color(COLOR_VIOLET);
+ * ili93xx_draw_line(0, 0, 240, 320);
+ * \endcode
+ *
+ * -# Draw a string of text
+ * \code
+ * ili93xx_set_foreground_color(COLOR_BLACK);
+ * ili93xx_draw_string(10, 20, (uint8_t *)"ili93xx_lcd example");
+ * \endcode
+ *
+ * -# Fill a rectangle with one certain color
+ * \code
+ * ili93xx_set_foreground_color(COLOR_BLUE);
+ * ili93xx_draw_filled_rectangle(0, 0, ILI93XX_LCD_WIDTH, ILI93XX_LCD_HEIGHT);
+ * \endcode
+ *
+ * -# Get device type
+ * \code
+ * ili93xx_device_type();
+ * \endcode
+ */
+
+#endif /* ILI93XX_H_INCLUDED */

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/ebi/smc/smc.c

@@ -0,0 +1,429 @@
+/**
+ * \file
+ *
+ * \brief Static Memory Controller (SMC) driver for SAM.
+ *
+ * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "smc.h"
+#include "board.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \defgroup sam_drivers_smc_group Static Memory Controller (SMC)
+ *
+ * Driver for the Static Memory Controller. It provides functions for configuring
+ * and using the on-chip SMC.
+ *
+ * @{
+ */
+
+#if ((SAM3S) || (SAM3U) || (SAM3XA) || (SAM4S) || (SAM4E))
+#define SMC_WPKEY_VALUE (0x534D43)
+/**
+ * \brief Configure the SMC Setup timing for the specified Chip Select.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_cs Chip Select number to be set.
+ * \param ul_setup_timing Setup timing for NWE, NCS, NRD.
+ */
+void smc_set_setup_timing(Smc *p_smc, uint32_t ul_cs,
+		uint32_t ul_setup_timing)
+{
+	p_smc->SMC_CS_NUMBER[ul_cs].SMC_SETUP = ul_setup_timing;
+}
+
+/**
+ * \brief Configure the SMC pulse timing for the specified Chip Select.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_cs Chip Select number to be set.
+ * \param ul_pulse_timing Pulse timing for NWE,NCS,NRD.
+ */
+void smc_set_pulse_timing(Smc *p_smc, uint32_t ul_cs,
+		uint32_t ul_pulse_timing)
+{
+	p_smc->SMC_CS_NUMBER[ul_cs].SMC_PULSE = ul_pulse_timing;
+}
+
+/**
+ * \brief Configure the SMC cycle timing for the specified Chip Select.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_cs Chip Select number to be set.
+ * \param ul_cycle_timing Cycle timing for NWE and NRD.
+ */
+void smc_set_cycle_timing(Smc *p_smc, uint32_t ul_cs,
+		uint32_t ul_cycle_timing)
+{
+	p_smc->SMC_CS_NUMBER[ul_cs].SMC_CYCLE = ul_cycle_timing;
+}
+
+/**
+ * \brief Configure the SMC mode for the specified Chip Select.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_cs Chip select number to be set.
+ * \param ul_mode SMC mode.
+ */
+void smc_set_mode(Smc *p_smc, uint32_t ul_cs, uint32_t ul_mode)
+{
+	p_smc->SMC_CS_NUMBER[ul_cs].SMC_MODE = ul_mode;
+}
+
+/**
+ * \brief Get the SMC mode of the specified Chip Select.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_cs Chip select number to be set.
+ *
+ * \return SMC mode.
+ */
+uint32_t smc_get_mode(Smc *p_smc, uint32_t ul_cs)
+{
+	return p_smc->SMC_CS_NUMBER[ul_cs].SMC_MODE;
+}
+
+/**
+ * \brief Set write protection of SMC registers.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_enable 1 to enable, 0 to disable.
+ */
+void smc_enable_writeprotect(Smc *p_smc, uint32_t ul_enable)
+{
+#if (SAM3S || SAM4S || SAM4E)
+	if (ul_enable)
+		p_smc->SMC_WPMR =
+				SMC_WPMR_WPKEY(SMC_WPKEY_VALUE) | SMC_WPMR_WPEN;
+	else
+		p_smc->SMC_WPMR = SMC_WPMR_WPKEY(SMC_WPKEY_VALUE);
+#else
+	if (ul_enable)
+		p_smc->SMC_WPCR =
+				SMC_WPCR_WP_KEY(SMC_WPKEY_VALUE) |
+				SMC_WPCR_WP_EN;
+	else
+		p_smc->SMC_WPCR = SMC_WPCR_WP_KEY(SMC_WPKEY_VALUE);
+#endif
+}
+
+/**
+ * \brief Get the status of SMC write protection register.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ *
+ * \return Write protect status.
+ */
+uint32_t smc_get_writeprotect_status(Smc *p_smc)
+{
+	return p_smc->SMC_WPSR;
+}
+#endif /* ((SAM3S) || (SAM3U) || (SAM3XA)) */
+
+#if ((SAM3U) || (SAM3XA))
+/**
+ * \brief Configure the SMC nand timing for the specified Chip Select.
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_cs Chip Select number to be set.
+ * \param ul_nand_timing nand timing for related signal.
+ */
+void smc_set_nand_timing(Smc *p_smc, uint32_t ul_cs,
+		uint32_t ul_nand_timing)
+{
+	p_smc->SMC_CS_NUMBER[ul_cs].SMC_TIMINGS= ul_nand_timing;
+}
+
+/**
+ * \brief Initialize NFC configuration.
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_config SMC NFC Configuration.
+ */
+void smc_nfc_init(Smc *p_smc, uint32_t ul_config)
+{
+	p_smc->SMC_CFG = ul_config;
+}
+
+/**
+ * \brief Set NFC page size.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_page_size Use pattern defined in the device header file.
+ */
+void smc_nfc_set_page_size(Smc *p_smc, uint32_t ul_page_size)
+{
+	p_smc->SMC_CFG &= (~SMC_CFG_PAGESIZE_Msk);
+	p_smc->SMC_CFG |= ul_page_size;
+}
+
+/**
+ * \brief Enable NFC controller to read both main and spare area in read mode.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ */
+void smc_nfc_enable_spare_read(Smc *p_smc)
+{
+	p_smc->SMC_CFG |= SMC_CFG_RSPARE;
+}
+
+/**
+ * \brief Prevent NFC controller from reading the spare area in read mode.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ */
+void smc_nfc_disable_spare_read(Smc *p_smc)
+{
+	p_smc->SMC_CFG &= (~SMC_CFG_RSPARE);
+}
+
+/**
+ * \brief Enable NFC controller to write both main and spare area in write mode.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ */
+void smc_nfc_enable_spare_write(Smc *p_smc)
+{
+	p_smc->SMC_CFG |= SMC_CFG_WSPARE;
+}
+
+/**
+ * \brief Prevent NFC controller from writing the spare area in read mode.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ */
+void smc_nfc_disable_spare_write(Smc *p_smc)
+{
+	p_smc->SMC_CFG &= (~SMC_CFG_WSPARE);
+}
+
+/**
+ * \brief Enable NFC controller.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ */
+void smc_nfc_enable(Smc *p_smc)
+{
+	p_smc->SMC_CTRL = SMC_CTRL_NFCEN;
+}
+
+/**
+ * \brief Disable NFC controller.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ */
+void smc_nfc_disable(Smc *p_smc)
+{
+	p_smc->SMC_CTRL = SMC_CTRL_NFCDIS;
+}
+
+/**
+ * \brief Get the NFC Status.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ *
+ * \return Returns the current status register of SMC NFC Status Register.
+ * This resets the internal value of the status register, so further
+ * read may yield different values.
+ */
+uint32_t smc_nfc_get_status(Smc *p_smc)
+{
+	return p_smc->SMC_SR;
+}
+
+/**
+ * \brief Enable SMC interrupts.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_sources Interrupt source bitmap.
+ */
+void smc_nfc_enable_interrupt(Smc *p_smc, uint32_t ul_sources)
+{
+	p_smc->SMC_IER = ul_sources;
+}
+
+/**
+ * \brief Disable SMC interrupts.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_sources Interrupt source bitmap.
+ */
+void smc_nfc_disable_interrupt(Smc *p_smc, uint32_t ul_sources)
+{
+	p_smc->SMC_IDR = ul_sources;
+}
+
+/**
+ * \brief Get the interrupt mask.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ *
+ * \return Interrupt mask bitmap.
+ */
+uint32_t smc_nfc_get_interrupt_mask(Smc *p_smc)
+{
+	return p_smc->SMC_IMR;
+}
+
+/**
+ * \brief Set flash cycle 0 address.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param uc_address0 Address cycle 0 in 5 address cycles.
+ */
+void smc_nfc_set_address0(Smc *p_smc, uint8_t uc_address0)
+{
+	p_smc->SMC_ADDR = uc_address0;
+}
+
+/**
+ * \brief Set NFC sram bank.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_bank NFC sram bank.
+ */
+void smc_nfc_set_bank(Smc *p_smc, uint32_t ul_bank)
+{
+	p_smc->SMC_BANK = SMC_BANK_BANK(ul_bank);
+}
+
+/**
+ * \brief Use the HOST nandflash controller to send a command.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_cmd Command to send.
+ * \param ul_address_cycle Address cycle when command access is decoded.
+ * \param ul_cycle0 Address at first cycle.
+ */
+void smc_nfc_send_command(Smc *p_smc, uint32_t ul_cmd,
+		uint32_t ul_address_cycle, uint32_t ul_cycle0)
+{
+	volatile uint32_t *p_command_address;
+
+	/* Wait until host controller is not busy. */
+	while (((*((volatile uint32_t *)(BOARD_NF_DATA_ADDR + NFCADDR_CMD_NFCCMD)))
+			& NFC_BUSY_FLAG) == NFC_BUSY_FLAG) {
+	}
+	/* Send the command plus the ADDR_CYCLE. */
+	p_command_address = (volatile uint32_t *)(ul_cmd + BOARD_NF_DATA_ADDR);
+	p_smc->SMC_ADDR = ul_cycle0;
+	*p_command_address = ul_address_cycle;
+	while (!((p_smc->SMC_SR & SMC_SR_CMDDONE) == SMC_SR_CMDDONE)) {
+	}
+}
+
+/**
+ * \brief Initialize ECC mode.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_type Type of correction, use pattern defined in the device header file.
+ * \param ul_pagesize Page size of NAND Flash device, use pattern defined in
+ * the device header file.
+ */
+void smc_ecc_init(Smc *p_smc, uint32_t ul_type, uint32_t ul_pagesize)
+{
+	/* Software Reset ECC. */
+	p_smc->SMC_ECC_CTRL = SMC_ECC_CTRL_SWRST;
+	p_smc->SMC_ECC_MD = ul_type | ul_pagesize;
+}
+
+/**
+ * \brief Get ECC status by giving ecc number.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param ul_parity_number ECC parity number from 0 to 15.
+ *
+ * \return ECC status by giving ECC number.
+ */
+uint32_t smc_ecc_get_status(Smc *p_smc, uint32_t ul_parity_number)
+{
+	uint32_t status;
+
+	if (ul_parity_number < 8) {
+		status = p_smc->SMC_ECC_SR1;
+	} else {
+		status = p_smc->SMC_ECC_SR2;
+		ul_parity_number -= 8;
+	}
+
+	return ((status >> (ul_parity_number * 4)) & ECC_STATUS_MASK);
+}
+
+/**
+ * \brief Get all ECC parity registers value.
+ *
+ * \param p_smc Pointer to an SMC instance.
+ * \param p_ecc Pointer to a parity buffer.
+ */
+void smc_ecc_get_value(Smc *p_smc, uint32_t *p_ecc)
+{
+	p_ecc[0] = p_smc->SMC_ECC_PR0;
+	p_ecc[1] = p_smc->SMC_ECC_PR1;
+	p_ecc[2] = p_smc->SMC_ECC_PR2;
+	p_ecc[3] = p_smc->SMC_ECC_PR3;
+	p_ecc[4] = p_smc->SMC_ECC_PR4;
+	p_ecc[5] = p_smc->SMC_ECC_PR5;
+	p_ecc[6] = p_smc->SMC_ECC_PR6;
+	p_ecc[7] = p_smc->SMC_ECC_PR7;
+	p_ecc[8] = p_smc->SMC_ECC_PR8;
+	p_ecc[9] = p_smc->SMC_ECC_PR9;
+	p_ecc[10] = p_smc->SMC_ECC_PR10;
+	p_ecc[11] = p_smc->SMC_ECC_PR11;
+	p_ecc[12] = p_smc->SMC_ECC_PR12;
+	p_ecc[13] = p_smc->SMC_ECC_PR13;
+	p_ecc[14] = p_smc->SMC_ECC_PR14;
+	p_ecc[15] = p_smc->SMC_ECC_PR15;
+}
+#endif /* ((SAM3U) || (SAM3XA)) */
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/ebi/smc/smc.h

@@ -0,0 +1,120 @@
+/**
+ * \file
+ *
+ * \brief Static Memory Controller (SMC) driver for SAM.
+ *
+ * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef SMC_H_INCLUDED
+#define SMC_H_INCLUDED
+
+#include "compiler.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#if ((SAM3S) || (SAM3U) || (SAM3XA) || (SAM4S) || (SAM4E))
+void smc_set_setup_timing(Smc *p_smc, uint32_t ul_cs, uint32_t ul_setup_timing);
+void smc_set_pulse_timing(Smc *p_smc, uint32_t ul_cs, uint32_t ul_pulse_timing);
+void smc_set_cycle_timing(Smc *p_smc, uint32_t ul_cs, uint32_t ul_cycle_timing);
+void smc_set_mode(Smc *p_smc, uint32_t ul_cs, uint32_t ul_mode);
+uint32_t smc_get_mode(Smc *p_smc, uint32_t ul_cs);
+void smc_enable_writeprotect(Smc *p_smc, uint32_t ul_enable);
+uint32_t smc_get_writeprotect_status(Smc *p_smc);
+#endif	/* ((SAM3S) || (SAM3U) || (SAM3XA)) */
+
+#if ((SAM3U) || (SAM3XA))
+/* NFCADDR_CMD : NFC Address Command */
+#define NFCADDR_CMD_CMD1      (0xFFu <<  2) /* Command Register Value for Cycle 1 */
+#define NFCADDR_CMD_CMD2      (0xFFu << 10) /* Command Register Value for Cycle 2 */
+#define NFCADDR_CMD_VCMD2     (0x1u << 18)  /* Valid Cycle 2 Command */
+#define NFCADDR_CMD_ACYCLE    (0x7u << 19)  /* Number of Address required for the current command */
+#define   NFCADDR_CMD_ACYCLE_NONE    (0x0u << 19) /* No address cycle */
+#define   NFCADDR_CMD_ACYCLE_ONE     (0x1u << 19) /* One address cycle */
+#define   NFCADDR_CMD_ACYCLE_TWO     (0x2u << 19) /* Two address cycles */
+#define   NFCADDR_CMD_ACYCLE_THREE   (0x3u << 19) /* Three address cycles */
+#define   NFCADDR_CMD_ACYCLE_FOUR    (0x4u << 19) /* Four address cycles */
+#define   NFCADDR_CMD_ACYCLE_FIVE    (0x5u << 19) /* Five address cycles */
+#define NFCADDR_CMD_CSID_Pos 22
+#define NFCADDR_CMD_CSID_Msk (0x7u << NFCADDR_CMD_CSID_Pos) /* Chip Select Identifier */
+#define NFCADDR_CMD_CSID(value) ((NFCADDR_CMD_CSID_Msk & ((value) << NFCADDR_CMD_CSID_Pos)))
+#define NFCADDR_CMD_NFCEN     (0x1u << 25)  /* NFC Enable */
+#define NFCADDR_CMD_NFC_READ     (0x0u << 26)  /* NFC Write Enable */
+#define NFCADDR_CMD_NFC_WIRTE    (0x1u << 26)  /* NFC Write Enable */
+#define NFCADDR_CMD_NFCCMD    (0x1u << 27)  /* NFC Command Enable */
+
+#define NFC_BUSY_FLAG    0x8000000
+#define ECC_STATUS_MASK   0x07
+
+void smc_set_nand_timing(Smc * p_smc, uint32_t ul_cs,
+		uint32_t ul_nand_timing);
+void smc_nfc_init(Smc *p_smc, uint32_t ul_config);
+void smc_nfc_set_page_size(Smc *p_smc, uint32_t ul_page_size);
+void smc_nfc_enable_spare_read(Smc *p_smc);
+void smc_nfc_disable_spare_read(Smc *p_smc);
+void smc_nfc_enable_spare_write(Smc *p_smc);
+void smc_nfc_disable_spare_write(Smc *p_smc);
+void smc_nfc_enable(Smc *p_smc);
+void smc_nfc_disable(Smc *p_smc);
+uint32_t smc_nfc_get_status(Smc * p_smc);
+void smc_nfc_enable_interrupt(Smc *p_smc, uint32_t ul_sources);
+void smc_nfc_disable_interrupt(Smc *p_smc, uint32_t ul_sources);
+uint32_t smc_nfc_get_interrupt_mask(Smc *p_smc);
+void smc_nfc_set_address0(Smc *p_smc, uint8_t uc_address0);
+void smc_nfc_set_bank(Smc *p_smc, uint32_t ul_bank);
+void smc_nfc_send_command(Smc *p_smc, uint32_t ul_cmd, uint32_t ul_address_cycle, uint32_t ul_cycle0);
+void smc_ecc_init(Smc *p_smc, uint32_t ul_type, uint32_t ul_pagesize);
+uint32_t smc_ecc_get_status(Smc *p_smc, uint32_t ul_parity_number);
+void smc_ecc_get_value(Smc *p_smc, uint32_t *p_ecc);
+#endif  /* ((SAM3U) || (SAM3XA)) */
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* SMC_H_INCLUDED */

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/LCDUtils.c

@@ -0,0 +1,174 @@
+/**
+ * gfx_draw_bmpfile() is provided by and copyright to Atmel Corporation with the
+ * following usage restrictions:
+ *
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Library includes. */
+#include <asf.h>
+
+/* Bitmap. */
+#include "logo_atmel.h"
+
+/* Chip select number to be set for LCD. */
+#define ILI93XX_LCD_CS  1
+
+/*
+ * Initialise the LCD and output a bitmap.
+ */
+void vInitialiseLCD( void );
+
+/*
+ * Output a bitmap to the LCD.
+ */
+static void gfx_draw_bmpfile( const uint8_t *bmpImage );
+
+/*-----------------------------------------------------------*/
+
+COMPILER_PACK_SET( 1 )
+struct bmpfile_header {
+	/** signature, must be 4D42 hex */
+	uint16_t type;
+	/** size of BMP file in bytes (unreliable) */
+	uint32_t file_size;
+	/** reserved, must be zero */
+	uint16_t reserved1;
+	/** reserved, must be zero */
+	uint16_t reserved2;
+	/** offset to start of image data in bytes */
+	uint32_t offset;
+	/** size of BITMAPINFOHEADER structure, must be 40 */
+	uint32_t header_size;
+	/** image width in pixels */
+	uint32_t width;
+	/** image height in pixels */
+	uint32_t height;
+	/** number of planes in the image, must be 1 */
+	uint16_t planes;
+	/** number of bits per pixel (1, 4, 8, 16, 24, 32) */
+	uint16_t bits;
+	/** compression type (0=none, 1=RLE-8, 2=RLE-4) */
+	uint32_t compression;
+	/** size of image data in bytes (including padding) */
+	uint32_t inage_size;
+	/** horizontal resolution in pixels per meter */
+	uint32_t h_resolution;
+	/** vertical resolution in pixels per meter */
+	uint32_t v_resolution;
+	/** number of colors in image, or zero */
+	uint32_t colours;
+	/** number of important colors, or zero */
+	uint32_t important_colors;
+};
+COMPILER_PACK_RESET()
+
+void vInitialiseLCD( void )
+{
+struct ili93xx_opt_t g_ili93xx_display_opt;
+
+	/* Configure SMC interface for Lcd */
+	smc_set_setup_timing( SMC, ILI93XX_LCD_CS, SMC_SETUP_NWE_SETUP( 2 ) | SMC_SETUP_NCS_WR_SETUP( 2 ) | SMC_SETUP_NRD_SETUP( 2 ) | SMC_SETUP_NCS_RD_SETUP( 2 ) );
+	smc_set_pulse_timing( SMC, ILI93XX_LCD_CS, SMC_PULSE_NWE_PULSE( 4 )	| SMC_PULSE_NCS_WR_PULSE( 4 ) | SMC_PULSE_NRD_PULSE( 10 )| SMC_PULSE_NCS_RD_PULSE( 10 ) );
+	smc_set_cycle_timing( SMC, ILI93XX_LCD_CS, SMC_CYCLE_NWE_CYCLE( 10 )| SMC_CYCLE_NRD_CYCLE( 22 ) );
+	smc_set_mode( SMC, ILI93XX_LCD_CS, SMC_MODE_READ_MODE | SMC_MODE_WRITE_MODE );
+	
+	/* Initialise the LCD. */
+	g_ili93xx_display_opt.ul_width = ILI93XX_LCD_WIDTH;
+	g_ili93xx_display_opt.ul_height = ILI93XX_LCD_HEIGHT;
+	g_ili93xx_display_opt.foreground_color = COLOR_BLACK;
+	g_ili93xx_display_opt.background_color = COLOR_WHITE;
+	ili93xx_init( &g_ili93xx_display_opt );
+
+	/* Set backlight level */
+	aat31xx_set_backlight(AAT31XX_AVG_BACKLIGHT_LEVEL);
+
+	/* Turn on LCD */
+	ili93xx_display_on();
+	
+	/* Clear. */
+	ili93xx_set_foreground_color( COLOR_WHITE );
+	ili93xx_draw_filled_rectangle( 0, 0, ILI93XX_LCD_WIDTH, ILI93XX_LCD_HEIGHT );
+	
+	/* Draw logos. */
+	ili93xx_set_cursor_position( 0,0 );
+	gfx_draw_bmpfile( logo_atmel_bmp );
+	
+	/* Set foreground colour ready to write text. */
+	ili93xx_set_foreground_color( COLOR_BLACK );
+}
+/*-----------------------------------------------------------*/
+
+static void gfx_draw_bmpfile( const uint8_t *bmpImage )
+{
+	struct bmpfile_header *bmp_header;
+	uint32_t length;
+	uint32_t i = 0;
+	uint32_t offset;
+	uint16_t j;
+
+	bmp_header = (struct bmpfile_header*) bmpImage;
+	length = bmp_header->height * bmp_header->width * 3;
+	offset = sizeof(struct bmpfile_header);
+
+	if (ili93xx_device_type() == DEVICE_TYPE_ILI9325) {
+
+		ili93xx_set_cursor_position(0, 0);
+
+		/** Prepare to write in GRAM */
+		LCD_IR(0);
+		LCD_IR(ILI9325_GRAM_DATA_REG);
+		for (i = offset; i < length; i += 3) {
+			/** Invert red and blue. */
+			LCD_WD(bmpImage[i + 2]);
+			LCD_WD(bmpImage[i + 1]);
+			LCD_WD(bmpImage[i]);
+		}
+		} else if (ili93xx_device_type() == DEVICE_TYPE_ILI9341) {
+		ili93xx_set_window(0, 0, bmp_header->width - 15, bmp_header->height);
+		/** memory write command (R2Ch)*/
+		LCD_IR(ILI9341_CMD_MEMORY_WRITE);
+		LCD_IR(ILI9341_CMD_WRITE_MEMORY_CONTINUE);
+
+		/** the original image is mirrored */
+		for (i= bmp_header->height - 1; i * bmp_header->width * 3 > offset;
+		i -=1) {
+			for (j = 45; j < bmp_header->width * 3; j += 3) {
+				LCD_WD(bmpImage[i * bmp_header->width * 3 + j + 2]);
+				LCD_WD(bmpImage[i * bmp_header->width * 3 + j + 1]);
+				LCD_WD(bmpImage[i * bmp_header->width * 3 + j]);
+			}
+		}
+	}
+}

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/asf.h

@@ -56,6 +56,14 @@
 #include <compiler.h>
 #include <status_codes.h>
 
+// From module: Display - AAT31XX Backlight Controller
+#include <aat31xx.h>
+
+// From module: Display - ILI93xx LCD Controller
+#include <ili9325_regs.h>
+#include <ili9341_regs.h>
+#include <ili93xx.h>
+
 // From module: Ethernet MAC (GMAC)
 #include <gmac.h>
 
@@ -87,6 +95,9 @@
 // From module: SAM4E startup code
 #include <exceptions.h>
 
+// From module: SMC - Static Memory Controller
+#include <smc.h>
+
 // From module: System Clock Control - SAM4E implementation
 #include <sysclk.h>
 

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/config/FreeRTOSConfig.h

@@ -91,7 +91,7 @@
 #define configTICK_RATE_HZ						( 1000 )
 #define configMAX_PRIORITIES					( 5 )
 #define configMINIMAL_STACK_SIZE				( ( unsigned short ) 130 )
-#define configTOTAL_HEAP_SIZE					( ( size_t ) ( 34 * 1024 ) )
+#define configTOTAL_HEAP_SIZE					( ( size_t ) ( 46 * 1024 ) )
 #define configMAX_TASK_NAME_LEN					( 10 )
 #define configUSE_TRACE_FACILITY				1
 #define configUSE_16_BIT_TICKS					0
@@ -212,6 +212,16 @@ ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
 #define configNET_MASK2		255
 #define configNET_MASK3		0
 
+/* The address of the echo server.  Used when the demo is build to include the
+UDP echo tasks (when mainINCLUDE_ECHO_CLIENT_TASKS is set to 1 in 
+FreeRTOSConfig.h.
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */
+#define configECHO_SERVER_ADDR0	192
+#define configECHO_SERVER_ADDR1 168
+#define configECHO_SERVER_ADDR2 0
+#define configECHO_SERVER_ADDR3 2
+
+
 /* The priority used by the Ethernet MAC driver interrupt. */
 #define configMAC_INTERRUPT_PRIORITY	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY )
 

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/config/FreeRTOSIPConfig.h

@@ -111,7 +111,7 @@ stack will revert to using the static IP address even when ipconfigUSE_DHCP is
 set to 1 if a valid configuration cannot be obtained from a DHCP server for any
 reason.  The static configuration used is that passed into the stack by the
 FreeRTOS_IPInit() function call. */
-#define ipconfigUSE_DHCP	0
+#define ipconfigUSE_DHCP	1
 
 /* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at
 increasing time intervals until either a reply is received from a DHCP server
@@ -205,7 +205,7 @@ contain.  For normal Ethernet V2 frames the maximum MTU is 1500.  Setting a
 lower value can save RAM, depending on the buffer management scheme used.  If
 ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must
 be divisible by 8. */
-#define ipconfigNETWORK_MTU 1200
+#define ipconfigNETWORK_MTU 1000
 
 /* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver.  DNS is used
 through the FreeRTOS_gethostbyname() API function. */

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/config/conf_aat31xx.h

@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief AAT31XX configuration.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+//! Configuration of the AAT31XX Backlight driver
+
+#ifndef CONF_AAT31XX_H_INCLUDED
+#define CONF_AAT31XX_H_INCLUDED
+
+#include "board.h"
+
+#if !defined(BOARD_AAT31XX_SET_GPIO)
+
+	#warning The AAT31XX PIN configuration does not exist in the board definition file. Using default settings.
+
+	#define BOARD_AAT31XX_SET_GPIO     PIO_PC13_IDX /* Should use the PIN index of which pin is connected with EN/SET of AAT31XX device */
+
+#endif
+
+#endif /* CONF_AAT31XX_H_INCLUDED */

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/config/conf_board.h

@@ -49,6 +49,13 @@
 
 /* Enable ETH PHY: KSZ8051MNL feature */
 #define CONF_BOARD_KSZ8051MNL
+
+/** Configure LCD EBI pins */
+#define CONF_BOARD_ILI93XX
+
+/** Configure Backlight control pin */
+#define CONF_BOARD_AAT3155
+
 /*
  * LED pins are not configured for PWM function here.
  * Because those LED pins are enabled for PIO function by default.

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/config/conf_ili93xx.h

@@ -0,0 +1,62 @@
+/**
+ * \file
+ *
+ * \brief ILI93XX configuration.
+ *
+ * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+//! Configuration of the ILI93XX (ILI9325 or ILI9341) LCD display driver
+
+#ifndef CONF_ILI93XX_H_INCLUDED
+#define CONF_ILI93XX_H_INCLUDED
+
+#include "board.h"
+
+#if !defined(BOARD_ILI93XX_ADDR) || !defined(BOARD_ILI93XX_RS)
+
+	#warning The ILI93XX EBI configuration does not exist in the board definition file. Using default settings.
+
+	 /** The base address, depends on which SMC chip select is used by ILI9325. */
+	#define BOARD_ILI93XX_ADDR     0x61000000
+	/** Register select (1 << 1) */
+	#define BOARD_ILI93XX_RS       1 << 1
+
+#endif
+
+#endif /* CONF_ILI93XX_H_INCLUDED */

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/main.c

@@ -131,6 +131,7 @@ static void prvSetupHardware( void )
 	board_init();
 	sysclk_init();
 	pmc_enable_periph_clk( ID_GMAC );
+	pmc_enable_periph_clk( ID_SMC );
 	vParTestInitialise();
 }
 /*-----------------------------------------------------------*/
@@ -233,14 +234,22 @@ void _exit_( int status )
 	vAssertCalled( __LINE__, __FILE__ );
 	for( ;; );
 }
+/*-----------------------------------------------------------*/
 
+/* Provided to keep the linker happy. */
 int _read( void )
 {
 	return 0;
 }
+/*-----------------------------------------------------------*/
 
+/* Provided to keep the linker happy. */
 int _write( int x )
 {
 	( void ) x;
 	return 0;
-}
+}
+/*-----------------------------------------------------------*/
+
+
+

FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/main_full.c

@@ -70,9 +70,13 @@
 
 /* FreeRTOS+UDP includes. */
 #include "FreeRTOS_UDP_IP.h"
+#include "FreeRTOS_Sockets.h"
 
-/* Demo application includes. */
+/* UDP demo includes. */
 #include "UDPCommandInterpreter.h"
+#include "TwoEchoClients.h"
+
+/* Standard demo includes. */
 #include "partest.h"
 #include "blocktim.h"
 #include "flash_timer.h"
@@ -128,9 +132,12 @@ passed into the network event hook is eNetworkUp). */
 #define mainDISCONNECTED_IP_TASK_PRIORITY	( tskIDLE_PRIORITY )
 
 /* UDP command server task parameters. */
-#define mainUDP_CLI_TASK_PRIORITY					( tskIDLE_PRIORITY )
+#define mainUDP_CLI_TASK_PRIORITY			( tskIDLE_PRIORITY )
-#define mainUDP_CLI_PORT_NUMBER						( 5001UL )
+#define mainUDP_CLI_PORT_NUMBER				( 5001UL )
-#define mainUDP_CLI_TASK_STACK_SIZE					( configMINIMAL_STACK_SIZE * 2U )
+#define mainUDP_CLI_TASK_STACK_SIZE			( configMINIMAL_STACK_SIZE * 2U )
+
+/* Set to 1 to include the UDP echo client tasks. */
+#define mainINCLUDE_ECHO_CLIENT_TASKS		1
 
 /*-----------------------------------------------------------*/
 
@@ -159,6 +166,11 @@ extern void vRegisterFileSystemCLICommands( void );
  */
 extern void vRegisterUDPCLICommands( void );
 
+/*
+ * Initialise the LCD and output a bitmap.
+ */
+extern void vInitialiseLCD( void );
+
 /*-----------------------------------------------------------*/
 
 /* The default IP and MAC address used by the demo.  The address configuration
@@ -180,6 +192,9 @@ int main_full( void )
 {
 xTimerHandle xTimer = NULL;
 
+	/* Initialise the LCD and output the bitmap. */
+	vInitialiseLCD();
+
 	/* If the file system is only going to be accessed from one task then
 	F_FS_THREAD_AWARE can be set to 0 and the set of example files are created
 	before the RTOS scheduler is started.  If the file system is going to be
@@ -319,6 +334,9 @@ unsigned long ulErrorOccurred = pdFALSE;
 void vApplicationIPNetworkEventHook( eIPCallbackEvent_t eNetworkEvent )
 {
 static long lTasksAlreadyCreated = pdFALSE;
+const unsigned long ulXCoord = 3, ulYCoord = 3, ulIPAddressOffset = 45;
+unsigned long ulIPAddress;
+char cIPAddress[ 20 ];
 
 	/* Note:  If the application is started without the network cable plugged in
 	then ipconfigUDP_TASK_PRIORITY should be set to 0 in FreeRTOSIPConfig.h to
@@ -330,14 +348,27 @@ static long lTasksAlreadyCreated = pdFALSE;
 	passed into the network event hook is eNetworkUp). */
 	if( eNetworkEvent == eNetworkUp )
 	{
-		vTaskPrioritySet( NULL, mainCONNECTED_IP_TASK_PRIORITY );
-
 		if( lTasksAlreadyCreated == pdFALSE )
 		{		
 			/* Create the task that handles the CLI on a UDP port.  The port number
 			is set using the configUDP_CLI_PORT_NUMBER setting in FreeRTOSConfig.h. */
 			vStartUDPCommandInterpreterTask( mainUDP_CLI_TASK_STACK_SIZE, mainUDP_CLI_PORT_NUMBER, mainUDP_CLI_TASK_PRIORITY );
+			
+			#if( mainINCLUDE_ECHO_CLIENT_TASKS == 1 )
+			{
+				vStartEchoClientTasks( configMINIMAL_STACK_SIZE, tskIDLE_PRIORITY );
+			}
+			#endif
 		}
+		
+		/* Obtain the IP address, convert it to a string, then display. */
+		FreeRTOS_GetAddressConfiguration( &ulIPAddress, NULL, NULL, NULL );
+		FreeRTOS_inet_ntoa( ulIPAddress, cIPAddress );
+		ili93xx_draw_string( ulXCoord, ulYCoord, ( uint8_t * ) "IP: " );
+		ili93xx_draw_string( ulXCoord + ulIPAddressOffset, ulYCoord, ( uint8_t * ) cIPAddress );
+		
+		/* Set the IP task up to the desired priority now it has connected. */
+		vTaskPrioritySet( NULL, mainCONNECTED_IP_TASK_PRIORITY );
 	}
 
 	if( eNetworkEvent == eNetworkDown )
@@ -387,25 +418,7 @@ void vApplicationPingReplyHook( ePingReplyStatus_t eStatus, uint16_t usIdentifie
 {
 	/* This demo has nowhere to output any information so does nothing. */
 	( void ) usIdentifier;
-	
+	( void ) eStatus;
-	switch( eStatus )
-	{
-		case eSuccess	:
-			break;
-
-		case eInvalidChecksum :
-			break;
-
-		case eInvalidData :
-			break;
-
-		default :
-			/* It is not possible to get here as all enums have their own
-			case. */
-			break;
-	}
 }
-
+/*-----------------------------------------------------------*/
-
-