Aidan MacDonald 777f63d529 Move MIPS cache management functions to IRAM ... Previously these were placed in DRAM, which is overwritten by RoLo when it loads a new image, but RoLo must call commit_discard_idcache() after loading the image. Change-Id: I5dcc4ca711b774166f83c668695edbcabfab2604		2021-03-09 20:04:30 +00:00
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ingenic_jz47xx	jz4740: Fix incorrect dcache flush in the USB RX DMA code.	2021-03-03 21:44:28 -05:00
mmu-mips.c	Fix typo in MIPS cache discard	2021-03-04 19:39:28 +00:00
mmu-mips.h	Move MIPS cache management functions to IRAM	2021-03-09 20:04:30 +00:00