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Fix typo in MIPS cache discard

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Change-Id: I6a06e5f3098324d985bd59322755cd68122ec0bf
This commit is contained in:
Aidan MacDonald 2021-03-04 19:38:14 +00:00
parent cbace906c6
commit fb99d890a8
1 changed files with 1 additions and 1 deletions
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2
firmware/target/mips/mmu-mips.c
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@ -234,7 +234,7 @@ void discard_dcache_range(const void *base, unsigned int size)
cacheline and shrink down the region to discard. */
if (ptr != end && (end !=((char*)base + size))) {
end -= CACHEALIGN_SIZE;
__CACHE_OP(DCHitWBInv, ptr);
__CACHE_OP(DCHitWBInv, end);
}
/* Finally, discard whatever is left */