forked from len0rd/rockbox
74 lines
2.8 KiB
C
74 lines
2.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* cortex_m7 version: 1.0
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* cortex_m7 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __ARM_CORTEX_M_CACHE_H__
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#define __ARM_CORTEX_M_CACHE_H__
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#include "macro.h"
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#define REG_CACHE_ICIALLU cm_reg(CACHE_ICIALLU)
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#define CMA_CACHE_ICIALLU (0xe000e000 + 0xf50)
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#define CMT_CACHE_ICIALLU CMIO_32_RW
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#define CMN_CACHE_ICIALLU CACHE_ICIALLU
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#define REG_CACHE_ICIMVAU cm_reg(CACHE_ICIMVAU)
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#define CMA_CACHE_ICIMVAU (0xe000e000 + 0xf58)
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#define CMT_CACHE_ICIMVAU CMIO_32_RW
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#define CMN_CACHE_ICIMVAU CACHE_ICIMVAU
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#define REG_CACHE_DCIMVAC cm_reg(CACHE_DCIMVAC)
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#define CMA_CACHE_DCIMVAC (0xe000e000 + 0xf5c)
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#define CMT_CACHE_DCIMVAC CMIO_32_RW
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#define CMN_CACHE_DCIMVAC CACHE_DCIMVAC
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#define REG_CACHE_DCISW cm_reg(CACHE_DCISW)
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#define CMA_CACHE_DCISW (0xe000e000 + 0xf60)
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#define CMT_CACHE_DCISW CMIO_32_RW
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#define CMN_CACHE_DCISW CACHE_DCISW
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#define REG_CACHE_DCCMVAU cm_reg(CACHE_DCCMVAU)
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#define CMA_CACHE_DCCMVAU (0xe000e000 + 0xf64)
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#define CMT_CACHE_DCCMVAU CMIO_32_RW
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#define CMN_CACHE_DCCMVAU CACHE_DCCMVAU
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#define REG_CACHE_DCCMVAC cm_reg(CACHE_DCCMVAC)
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#define CMA_CACHE_DCCMVAC (0xe000e000 + 0xf68)
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#define CMT_CACHE_DCCMVAC CMIO_32_RW
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#define CMN_CACHE_DCCMVAC CACHE_DCCMVAC
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#define REG_CACHE_DCCSW cm_reg(CACHE_DCCSW)
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#define CMA_CACHE_DCCSW (0xe000e000 + 0xf6c)
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#define CMT_CACHE_DCCSW CMIO_32_RW
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#define CMN_CACHE_DCCSW CACHE_DCCSW
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#define REG_CACHE_DCCIMVAC cm_reg(CACHE_DCCIMVAC)
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#define CMA_CACHE_DCCIMVAC (0xe000e000 + 0xf70)
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#define CMT_CACHE_DCCIMVAC CMIO_32_RW
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#define CMN_CACHE_DCCIMVAC CACHE_DCCIMVAC
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#define REG_CACHE_DCCISW cm_reg(CACHE_DCCISW)
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#define CMA_CACHE_DCCISW (0xe000e000 + 0xf74)
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#define CMT_CACHE_DCCISW CMIO_32_RW
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#define CMN_CACHE_DCCISW CACHE_DCCISW
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#endif /* __ARM_CORTEX_M_CACHE_H__*/
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